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authorCorey Schuhen <[email protected]>2024-03-16 19:24:47 +1000
committerCorey Schuhen <[email protected]>2024-03-16 19:32:38 +1000
commit3f5c8784afe2174fd1df8446bd21240608c558e0 (patch)
treeb7b676e5f7baf9dec46195e7e509dc88fc9c8996 /tests/stm32/src/bin/fdcan.rs
parentc580d4c490239762b6e68ee9e25599bfe86ed926 (diff)
FDCAN: Fix offset issue preventing CAN2 and CAN3 from working.
Fix for not H7
Diffstat (limited to 'tests/stm32/src/bin/fdcan.rs')
-rw-r--r--tests/stm32/src/bin/fdcan.rs53
1 files changed, 51 insertions, 2 deletions
diff --git a/tests/stm32/src/bin/fdcan.rs b/tests/stm32/src/bin/fdcan.rs
index dd78d7fb3..c7373e294 100644
--- a/tests/stm32/src/bin/fdcan.rs
+++ b/tests/stm32/src/bin/fdcan.rs
@@ -13,7 +13,11 @@ use embassy_stm32::{bind_interrupts, can, Config};
13use embassy_time::{Duration, Instant}; 13use embassy_time::{Duration, Instant};
14use {defmt_rtt as _, panic_probe as _}; 14use {defmt_rtt as _, panic_probe as _};
15 15
16bind_interrupts!(struct Irqs { 16bind_interrupts!(struct Irqs2 {
17 FDCAN2_IT0 => can::IT0InterruptHandler<FDCAN2>;
18 FDCAN2_IT1 => can::IT1InterruptHandler<FDCAN2>;
19});
20bind_interrupts!(struct Irqs1 {
17 FDCAN1_IT0 => can::IT0InterruptHandler<FDCAN1>; 21 FDCAN1_IT0 => can::IT0InterruptHandler<FDCAN1>;
18 FDCAN1_IT1 => can::IT1InterruptHandler<FDCAN1>; 22 FDCAN1_IT1 => can::IT1InterruptHandler<FDCAN1>;
19}); 23});
@@ -75,17 +79,24 @@ async fn main(_spawner: Spawner) {
75 let options = options(); 79 let options = options();
76 let peripherals = embassy_stm32::init(options.config); 80 let peripherals = embassy_stm32::init(options.config);
77 81
78 let mut can = can::FdcanConfigurator::new(peripherals.FDCAN1, peripherals.PB8, peripherals.PB9, Irqs); 82 let mut can = can::FdcanConfigurator::new(peripherals.FDCAN1, peripherals.PB8, peripherals.PB9, Irqs1);
83 let mut can2 = can::FdcanConfigurator::new(peripherals.FDCAN2, peripherals.PB12, peripherals.PB13, Irqs2);
79 84
80 // 250k bps 85 // 250k bps
81 can.set_bitrate(250_000); 86 can.set_bitrate(250_000);
87 can2.set_bitrate(250_000);
82 88
83 can.set_extended_filter( 89 can.set_extended_filter(
84 can::filter::ExtendedFilterSlot::_0, 90 can::filter::ExtendedFilterSlot::_0,
85 can::filter::ExtendedFilter::accept_all_into_fifo1(), 91 can::filter::ExtendedFilter::accept_all_into_fifo1(),
86 ); 92 );
93 can2.set_extended_filter(
94 can::filter::ExtendedFilterSlot::_0,
95 can::filter::ExtendedFilter::accept_all_into_fifo1(),
96 );
87 97
88 let mut can = can.into_internal_loopback_mode(); 98 let mut can = can.into_internal_loopback_mode();
99 let mut can2 = can2.into_internal_loopback_mode();
89 100
90 info!("CAN Configured"); 101 info!("CAN Configured");
91 102
@@ -126,6 +137,44 @@ async fn main(_spawner: Spawner) {
126 } 137 }
127 } 138 }
128 139
140 let mut i: u8 = 0;
141 loop {
142 let tx_frame = can::frame::ClassicFrame::new_standard(0x123, &[i; 1]).unwrap();
143
144 info!("Transmitting frame...");
145 let tx_ts = Instant::now();
146 can2.write(&tx_frame).await;
147
148 let (frame, timestamp) = can2.read().await.unwrap();
149 info!("Frame received!");
150
151 //print_regs().await;
152 // Check data.
153 assert!(i == frame.data()[0], "{} == {}", i, frame.data()[0]);
154
155 info!("loopback time {}", timestamp);
156 info!("loopback frame {=u8}", frame.data()[0]);
157 let latency = timestamp.saturating_duration_since(tx_ts);
158 info!("loopback latency {} us", latency.as_micros());
159
160 // Theoretical minimum latency is 55us, actual is usually ~80us
161 const MIN_LATENCY: Duration = Duration::from_micros(50);
162 // Was failing at 150 but we are not getting a real time stamp. I'm not
163 // sure if there are other delays
164 assert!(
165 MIN_LATENCY <= latency && latency <= options.max_latency,
166 "{} <= {} <= {}",
167 MIN_LATENCY,
168 latency,
169 options.max_latency
170 );
171
172 i += 1;
173 if i > 10 {
174 break;
175 }
176 }
177
129 let max_buffered = if options.second_fifo_working { 6 } else { 3 }; 178 let max_buffered = if options.second_fifo_working { 6 } else { 3 };
130 179
131 // Below here, check that we can receive from both FIFO0 and FIFO0 180 // Below here, check that we can receive from both FIFO0 and FIFO0