aboutsummaryrefslogtreecommitdiff
path: root/tests/stm32/src/bin
diff options
context:
space:
mode:
authorxoviat <[email protected]>2023-05-30 21:14:25 -0500
committerxoviat <[email protected]>2023-05-30 21:14:25 -0500
commit16bfbd4e99dbc765c93610557a7857a9013ff756 (patch)
tree3103c09168aa1c672daa47b97eb86e663333e057 /tests/stm32/src/bin
parentf8d35806dc773a6310a60115fbf90f48fe409207 (diff)
stm32/can: add hw test and cleanup
Diffstat (limited to 'tests/stm32/src/bin')
-rw-r--r--tests/stm32/src/bin/can.rs78
1 files changed, 78 insertions, 0 deletions
diff --git a/tests/stm32/src/bin/can.rs b/tests/stm32/src/bin/can.rs
new file mode 100644
index 000000000..f39f83e82
--- /dev/null
+++ b/tests/stm32/src/bin/can.rs
@@ -0,0 +1,78 @@
1#![no_std]
2#![no_main]
3#![feature(type_alias_impl_trait)]
4
5// required-features: can
6
7#[path = "../example_common.rs"]
8mod example_common;
9use embassy_executor::Spawner;
10use embassy_stm32::bind_interrupts;
11use embassy_stm32::can::bxcan::filter::Mask32;
12use embassy_stm32::can::bxcan::{Fifo, Frame, StandardId};
13use embassy_stm32::can::{Can, Rx0InterruptHandler, Rx1InterruptHandler, SceInterruptHandler, TxInterruptHandler};
14use embassy_stm32::gpio::{Input, Pull};
15use embassy_stm32::peripherals::CAN1;
16use example_common::*;
17use {defmt_rtt as _, panic_probe as _};
18
19bind_interrupts!(struct Irqs {
20 CAN1_RX0 => Rx0InterruptHandler<CAN1>;
21 CAN1_RX1 => Rx1InterruptHandler<CAN1>;
22 CAN1_SCE => SceInterruptHandler<CAN1>;
23 CAN1_TX => TxInterruptHandler<CAN1>;
24});
25
26#[embassy_executor::main]
27async fn main(_spawner: Spawner) {
28 let mut p = embassy_stm32::init(config());
29 info!("Hello World!");
30
31 // HW is connected as follows:
32 // PB13 -> PD0
33 // PB12 -> PD1
34
35 // The next two lines are a workaround for testing without transceiver.
36 // To synchronise to the bus the RX input needs to see a high level.
37 // Use `mem::forget()` to release the borrow on the pin but keep the
38 // pull-up resistor enabled.
39 let rx_pin = Input::new(&mut p.PD0, Pull::Up);
40 core::mem::forget(rx_pin);
41
42 let mut can = Can::new(p.CAN1, p.PD0, p.PD1, Irqs);
43
44 info!("Configuring can...");
45
46 can.modify_filters().enable_bank(0, Fifo::Fifo0, Mask32::accept_all());
47
48 can.set_bitrate(1_000_000);
49 can.modify_config()
50 .set_loopback(true) // Receive own frames
51 .set_silent(true)
52 // .set_bit_timing(0x001c0003)
53 .enable();
54
55 info!("Can configured");
56
57 let mut i: u8 = 0;
58 loop {
59 let tx_frame = Frame::new_data(unwrap!(StandardId::new(i as _)), [i]);
60
61 info!("Transmitting frame...");
62 can.write(&tx_frame).await;
63
64 info!("Receiving frame...");
65 let (time, rx_frame) = can.read().await.unwrap();
66
67 info!("loopback time {}", time);
68 info!("loopback frame {=u8}", rx_frame.data().unwrap()[0]);
69
70 i += 1;
71 if i > 10 {
72 break;
73 }
74 }
75
76 info!("Test OK");
77 cortex_m::asm::bkpt();
78}