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authorDario Nieuwenhuis <[email protected]>2024-05-01 02:21:06 +0200
committerDario Nieuwenhuis <[email protected]>2024-05-01 02:24:45 +0200
commitfb67fe0a6c155191534955f1230dccaea0e11a94 (patch)
treeac01b69047aeee08983a5149409080d137f19cb1 /tests/stm32/src/bin
parentecc910b76dbfa2064f42e6917a7b5654a89b81ed (diff)
stm32: add support for STM32H7[RS] "bootflash line", add HIL tests.
Diffstat (limited to 'tests/stm32/src/bin')
-rw-r--r--tests/stm32/src/bin/cordic.rs7
-rw-r--r--tests/stm32/src/bin/fdcan.rs14
-rw-r--r--tests/stm32/src/bin/gpio.rs7
-rw-r--r--tests/stm32/src/bin/hash.rs3
4 files changed, 28 insertions, 3 deletions
diff --git a/tests/stm32/src/bin/cordic.rs b/tests/stm32/src/bin/cordic.rs
index 400e10207..e09226de8 100644
--- a/tests/stm32/src/bin/cordic.rs
+++ b/tests/stm32/src/bin/cordic.rs
@@ -67,7 +67,12 @@ async fn main(_spawner: Spawner) {
67 #[cfg(feature = "stm32g491re")] 67 #[cfg(feature = "stm32g491re")]
68 let (mut write_dma, mut read_dma) = (dp.DMA1_CH4, dp.DMA1_CH5); 68 let (mut write_dma, mut read_dma) = (dp.DMA1_CH4, dp.DMA1_CH5);
69 69
70 #[cfg(any(feature = "stm32h563zi", feature = "stm32u585ai", feature = "stm32u5a5zj"))] 70 #[cfg(any(
71 feature = "stm32h563zi",
72 feature = "stm32u585ai",
73 feature = "stm32u5a5zj",
74 feature = "stm32h7s3l8"
75 ))]
71 let (mut write_dma, mut read_dma) = (dp.GPDMA1_CH0, dp.GPDMA1_CH1); 76 let (mut write_dma, mut read_dma) = (dp.GPDMA1_CH0, dp.GPDMA1_CH1);
72 77
73 // calculate first result using blocking mode 78 // calculate first result using blocking mode
diff --git a/tests/stm32/src/bin/fdcan.rs b/tests/stm32/src/bin/fdcan.rs
index b0c0cd82e..20bd3f7e3 100644
--- a/tests/stm32/src/bin/fdcan.rs
+++ b/tests/stm32/src/bin/fdcan.rs
@@ -74,6 +74,20 @@ fn options() -> (Config, TestOptions) {
74 ) 74 )
75} 75}
76 76
77#[cfg(any(feature = "stm32h7s3l8"))]
78fn options() -> (Config, TestOptions) {
79 use embassy_stm32::rcc;
80 let mut c = config();
81 c.rcc.mux.fdcansel = rcc::mux::Fdcansel::HSE;
82 (
83 c,
84 TestOptions {
85 max_latency: Duration::from_micros(1200),
86 max_buffered: 3,
87 },
88 )
89}
90
77#[cfg(any(feature = "stm32g491re", feature = "stm32g431cb"))] 91#[cfg(any(feature = "stm32g491re", feature = "stm32g431cb"))]
78fn options() -> (Config, TestOptions) { 92fn options() -> (Config, TestOptions) {
79 info!("G4 config"); 93 info!("G4 config");
diff --git a/tests/stm32/src/bin/gpio.rs b/tests/stm32/src/bin/gpio.rs
index c4e2fe161..dfa299ab5 100644
--- a/tests/stm32/src/bin/gpio.rs
+++ b/tests/stm32/src/bin/gpio.rs
@@ -216,7 +216,12 @@ async fn main(_spawner: Spawner) {
216} 216}
217 217
218fn delay() { 218fn delay() {
219 #[cfg(any(feature = "stm32h755zi", feature = "stm32h753zi", feature = "stm32h7a3zi"))] 219 #[cfg(any(
220 feature = "stm32h755zi",
221 feature = "stm32h753zi",
222 feature = "stm32h7a3zi",
223 feature = "stm32h7s3l8"
224 ))]
220 cortex_m::asm::delay(9000); 225 cortex_m::asm::delay(9000);
221 cortex_m::asm::delay(1000); 226 cortex_m::asm::delay(1000);
222} 227}
diff --git a/tests/stm32/src/bin/hash.rs b/tests/stm32/src/bin/hash.rs
index 8cc5d593f..5f54ea435 100644
--- a/tests/stm32/src/bin/hash.rs
+++ b/tests/stm32/src/bin/hash.rs
@@ -26,7 +26,8 @@ bind_interrupts!(struct Irqs {
26 feature = "stm32h563zi", 26 feature = "stm32h563zi",
27 feature = "stm32h503rb", 27 feature = "stm32h503rb",
28 feature = "stm32u5a5zj", 28 feature = "stm32u5a5zj",
29 feature = "stm32u585ai" 29 feature = "stm32u585ai",
30 feature = "stm32h7s3l8"
30))] 31))]
31bind_interrupts!(struct Irqs { 32bind_interrupts!(struct Irqs {
32 HASH => hash::InterruptHandler<peripherals::HASH>; 33 HASH => hash::InterruptHandler<peripherals::HASH>;