Added STM32 hash test.

2 files changed, 73 insertions, 0 deletions

diff --git a/tests/stm32/src/bin/hash.rs b/tests/stm32/src/bin/hash.rs
new file mode 100644
index 000000000..60a60b0f1
--- /dev/null
+++ b/tests/stm32/src/bin/hash.rs
@@ -0,0 +1,66 @@
+// required-features: hash
+#![no_std]
+#![no_main]
+
+#[path = "../common.rs"]
+mod common;
+use common::*;
+use embassy_executor::Spawner;
+use embassy_stm32::hash::*;
+use embassy_stm32::{bind_interrupts, peripherals, hash};
+use sha2::{Digest, Sha224, Sha256};
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+   HASH_RNG => hash::InterruptHandler<peripherals::HASH>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p: embassy_stm32::Peripherals = embassy_stm32::init(config());
+    let dma = peri!(p, HASH_DMA);
+    let mut hw_hasher = Hash::new(p.HASH, dma);
+
+    let test_1: &[u8] = b"as;dfhaslfhas;oifvnasd;nifvnhasd;nifvhndlkfghsd;nvfnahssdfgsdafgsasdfasdfasdfasdfasdfghjklmnbvcalskdjghalskdjgfbaslkdjfgbalskdjgbalskdjbdfhsdfhsfghsfghfgh";
+    let test_2: &[u8] = b"fdhalksdjfhlasdjkfhalskdjfhgal;skdjfgalskdhfjgalskdjfglafgadfgdfgdafgaadsfgfgdfgadrgsyfthxfgjfhklhjkfgukhulkvhlvhukgfhfsrghzdhxyfufynufyuszeradrtydyytserr";
+    let test_3: &[u8] = b"a.ewtkluGWEBR.KAJRBTA,RMNRBG,FDMGB.kger.tkasjrbt.akrjtba.krjtba.ktmyna,nmbvtyliasd;gdrtba,sfvs.kgjzshd.gkbsr.tksejb.SDkfBSE.gkfgb>ESkfbSE>gkJSBESE>kbSE>fk";
+
+    // Start an SHA-256 digest.
+    let mut sha256context = hw_hasher.start(Algorithm::SHA256, DataType::Width8).await;
+    hw_hasher.update(&mut sha256context, test_1).await;
+
+    // Interrupt the SHA-256 digest to compute an SHA-224 digest.
+    let mut sha224context = hw_hasher.start(Algorithm::SHA224, DataType::Width8).await;
+    hw_hasher.update(&mut sha224context, test_3).await;
+    let mut sha224_digest_buffer: [u8; 64] = [0; 64];
+    let sha224_digest = hw_hasher.finish(sha224context, &mut sha224_digest_buffer).await;
+
+    // Finish the SHA-256 digest.
+    hw_hasher.update(&mut sha256context, test_2).await;
+    let mut sha_256_digest_buffer: [u8; 64] = [0; 64];
+    let sha256_digest = hw_hasher.finish(sha256context, &mut sha_256_digest_buffer).await;
+    
+    // Compute the SHA-256 digest in software.
+    let mut sw_sha256_hasher = Sha256::new();
+    sw_sha256_hasher.update(test_1);
+    sw_sha256_hasher.update(test_2);
+    let sw_sha256_digest = sw_sha256_hasher.finalize();
+
+    //Compute the SHA-224 digest in software.
+    let mut sw_sha224_hasher = Sha224::new();
+    sw_sha224_hasher.update(test_3);
+    let sw_sha224_digest = sw_sha224_hasher.finalize();
+
+    // Compare the SHA-256 digests.
+    info!("Hardware SHA-256 Digest: {:?}", sha256_digest);
+    info!("Software SHA-256 Digest: {:?}", sw_sha256_digest[..]);
+    defmt::assert!(*sha256_digest == sw_sha256_digest[..]);
+
+    // Compare the SHA-224 digests.
+    info!("Hardware SHA-256 Digest: {:?}", sha224_digest);
+    info!("Software SHA-256 Digest: {:?}", sw_sha224_digest[..]);
+    defmt::assert!(*sha224_digest == sw_sha224_digest[..]);
+
+    info!("Test OK");
+    cortex_m::asm::bkpt();
+}
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index fefe72c86..7e7915b2e 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -128,6 +128,7 @@ define_peris!(
 );
 #[cfg(any(feature = "stm32h755zi", feature = "stm32h753zi"))]
 define_peris!(
+    HASH_DMA = DMA1_CH0,
     UART = USART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = DMA1_CH0, UART_RX_DMA = DMA1_CH1,
     SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PB5, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH0, SPI_RX_DMA = DMA1_CH1,
     ADC = ADC1, DAC = DAC1, DAC_PIN = PA4,
@@ -141,18 +142,21 @@ define_peris!(
 );
 #[cfg(feature = "stm32u585ai")]
 define_peris!(
+    HASH_DMA = GPDMA1_CH0,
     UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
     SPI = SPI1, SPI_SCK = PE13, SPI_MOSI = PE15, SPI_MISO = PE14, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
     @irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
 );
 #[cfg(feature = "stm32u5a5zj")]
 define_peris!(
+    HASH_DMA = GPDMA1_CH0,
     UART = LPUART1, UART_TX = PG7, UART_RX = PG8, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
     SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
     @irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
 );
 #[cfg(feature = "stm32h563zi")]
 define_peris!(
+    HASH_DMA = GPDMA1_CH0,
     UART = LPUART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
     SPI = SPI4, SPI_SCK = PE12, SPI_MOSI = PE14, SPI_MISO = PE13, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
     @irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
@@ -171,6 +175,7 @@ define_peris!(
 );
 #[cfg(feature = "stm32l4a6zg")]
 define_peris!(
+    HASH_DMA = DMA2_CH7,
     UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = DMA1_CH2, UART_RX_DMA = DMA1_CH3,
     SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2,
     @irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
@@ -196,6 +201,7 @@ define_peris!(
 );
 #[cfg(feature = "stm32l552ze")]
 define_peris!(
+    HASH_DMA = DMA1_CH0,
     UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2,
     SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
     @irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
@@ -226,6 +232,7 @@ define_peris!(
 );
 #[cfg(feature = "stm32wba52cg")]
 define_peris!(
+    HASH_DMA = GPDMA1_CH0,
     UART = LPUART1, UART_TX = PB5, UART_RX = PA10, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
     SPI = SPI1, SPI_SCK = PB4, SPI_MOSI = PA15, SPI_MISO = PB3, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
     @irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},