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authorChris Storah <[email protected]>2025-07-23 12:38:58 +1000
committerChris Storah <[email protected]>2025-07-23 12:38:58 +1000
commite64c23076d2c003efe60419eab6b86630d7886b4 (patch)
tree96458b028c508e4b22f6094c6213bea0a82e54b7 /tests/stm32/src
parent26232778e69bdfddcd1df0747b7414ef936e3ea2 (diff)
Updated version of stm32-data and added c071 and c051 into ci.sh
Diffstat (limited to 'tests/stm32/src')
-rw-r--r--tests/stm32/src/common.rs10
1 files changed, 9 insertions, 1 deletions
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 829f2cff0..a4d8048ce 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -34,6 +34,8 @@ teleprobe_meta::target!(b"nucleo-stm32u5a5zj");
34teleprobe_meta::target!(b"nucleo-stm32h563zi"); 34teleprobe_meta::target!(b"nucleo-stm32h563zi");
35#[cfg(feature = "stm32c031c6")] 35#[cfg(feature = "stm32c031c6")]
36teleprobe_meta::target!(b"nucleo-stm32c031c6"); 36teleprobe_meta::target!(b"nucleo-stm32c031c6");
37#[cfg(feature = "stm32c071rb")]
38teleprobe_meta::target!(b"nucleo-stm32c071rb");
37#[cfg(feature = "stm32l073rz")] 39#[cfg(feature = "stm32l073rz")]
38teleprobe_meta::target!(b"nucleo-stm32l073rz"); 40teleprobe_meta::target!(b"nucleo-stm32l073rz");
39#[cfg(feature = "stm32l152re")] 41#[cfg(feature = "stm32l152re")]
@@ -186,6 +188,12 @@ define_peris!(
186 SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2, 188 SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
187 @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;}, 189 @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
188); 190);
191#[cfg(feature = "stm32c071rb")]
192define_peris!(
193 UART = USART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2,
194 SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
195 @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
196);
189#[cfg(feature = "stm32l496zg")] 197#[cfg(feature = "stm32l496zg")]
190define_peris!( 198define_peris!(
191 UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = DMA1_CH2, UART_RX_DMA = DMA1_CH3, 199 UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = DMA1_CH2, UART_RX_DMA = DMA1_CH3,
@@ -271,7 +279,7 @@ pub fn config() -> Config {
271 #[allow(unused_mut)] 279 #[allow(unused_mut)]
272 let mut config = Config::default(); 280 let mut config = Config::default();
273 281
274 #[cfg(feature = "stm32c031c6")] 282 #[cfg(any(feature = "stm32c031c6", feature = "stm32c071rb"))]
275 { 283 {
276 config.rcc.hsi = Some(Hsi { 284 config.rcc.hsi = Some(Hsi {
277 sys_div: HsiSysDiv::DIV1, // 48Mhz 285 sys_div: HsiSysDiv::DIV1, // 48Mhz