aboutsummaryrefslogtreecommitdiff
path: root/tests/stm32
diff options
context:
space:
mode:
authorleftger <[email protected]>2025-07-27 09:38:38 -0700
committerGitHub <[email protected]>2025-07-27 09:38:38 -0700
commitb9e643d5c2d7192143e91db83b9e8377f0fbcacc (patch)
tree86a695a05ccb70be67613ea742b14094a7aca362 /tests/stm32
parent1b3674b30ac2b7deb8e19b132d5ba15351cb8ebd (diff)
parent77a8bc27e9c34e363f321132ebb9e8d8ff684a9f (diff)
Merge branch 'main' into feat/stm32wba-rcc-pll-support
Diffstat (limited to 'tests/stm32')
-rw-r--r--tests/stm32/src/common.rs2
1 files changed, 2 insertions, 0 deletions
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index a4d8048ce..cb63b3374 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -681,6 +681,8 @@ pub fn config() -> Config {
681 divp: Some(PllDiv::DIV2), // 600Mhz 681 divp: Some(PllDiv::DIV2), // 600Mhz
682 divq: Some(PllDiv::DIV25), // 48Mhz 682 divq: Some(PllDiv::DIV25), // 48Mhz
683 divr: None, 683 divr: None,
684 divs: None,
685 divt: None,
684 }); 686 });
685 config.rcc.sys = Sysclk::PLL1_P; // 600 Mhz 687 config.rcc.sys = Sysclk::PLL1_P; // 600 Mhz
686 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 300 Mhz 688 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 300 Mhz