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authorDario Nieuwenhuis <[email protected]>2024-02-23 01:22:11 +0100
committerDario Nieuwenhuis <[email protected]>2024-02-23 01:24:05 +0100
commit0665e0d452627b5fe3c0b52981c7f4ef380de83f (patch)
treec29ad9f8e51b8b91c22309b58f965021607cd973 /tests
parent4481c5f3ccf29da071538ef4f1e48fc5372a72a5 (diff)
stm32/rcc: port U5 to new API, add all PLLs, all HSE modes.
Diffstat (limited to 'tests')
-rw-r--r--tests/stm32/src/common.rs13
1 files changed, 12 insertions, 1 deletions
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 50a7f9bae..1e6b1cce9 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -577,7 +577,18 @@ pub fn config() -> Config {
577 #[cfg(any(feature = "stm32u585ai", feature = "stm32u5a5zj"))] 577 #[cfg(any(feature = "stm32u585ai", feature = "stm32u5a5zj"))]
578 { 578 {
579 use embassy_stm32::rcc::*; 579 use embassy_stm32::rcc::*;
580 config.rcc.mux = ClockSrc::MSI(Msirange::RANGE_48MHZ); 580 config.rcc.hsi = true;
581 config.rcc.pll1 = Some(Pll {
582 source: PllSource::HSI, // 16 MHz
583 prediv: PllPreDiv::DIV1,
584 mul: PllMul::MUL10,
585 divp: None,
586 divq: None,
587 divr: Some(PllDiv::DIV1), // 160 MHz
588 });
589 config.rcc.mux = ClockSrc::PLL1_R;
590 config.rcc.voltage_range = VoltageScale::RANGE1;
591 config.rcc.hsi48 = Some(Hsi48Config { sync_from_usb: true }); // needed for USB
581 } 592 }
582 593
583 #[cfg(feature = "stm32wba52cg")] 594 #[cfg(feature = "stm32wba52cg")]