diff options
| author | Caleb Garrett <[email protected]> | 2024-02-05 14:44:50 -0500 |
|---|---|---|
| committer | Caleb Garrett <[email protected]> | 2024-02-05 14:44:50 -0500 |
| commit | 09973ad4827222251a46cb7b1f48841245b54709 (patch) | |
| tree | 1d3f567e64c9aabe181588bfdafab22fcf3d9ad2 /tests | |
| parent | 079bb7b4901b3fa6787c2ca5d8c022de3533ad8c (diff) | |
Corrected hash CI build issues.
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/stm32/src/bin/hash.rs | 4 | ||||
| -rw-r--r-- | tests/stm32/src/common.rs | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/tests/stm32/src/bin/hash.rs b/tests/stm32/src/bin/hash.rs index 60a60b0f1..05b61a10c 100644 --- a/tests/stm32/src/bin/hash.rs +++ b/tests/stm32/src/bin/hash.rs | |||
| @@ -7,7 +7,7 @@ mod common; | |||
| 7 | use common::*; | 7 | use common::*; |
| 8 | use embassy_executor::Spawner; | 8 | use embassy_executor::Spawner; |
| 9 | use embassy_stm32::hash::*; | 9 | use embassy_stm32::hash::*; |
| 10 | use embassy_stm32::{bind_interrupts, peripherals, hash}; | 10 | use embassy_stm32::{bind_interrupts, hash, peripherals}; |
| 11 | use sha2::{Digest, Sha224, Sha256}; | 11 | use sha2::{Digest, Sha224, Sha256}; |
| 12 | use {defmt_rtt as _, panic_probe as _}; | 12 | use {defmt_rtt as _, panic_probe as _}; |
| 13 | 13 | ||
| @@ -39,7 +39,7 @@ async fn main(_spawner: Spawner) { | |||
| 39 | hw_hasher.update(&mut sha256context, test_2).await; | 39 | hw_hasher.update(&mut sha256context, test_2).await; |
| 40 | let mut sha_256_digest_buffer: [u8; 64] = [0; 64]; | 40 | let mut sha_256_digest_buffer: [u8; 64] = [0; 64]; |
| 41 | let sha256_digest = hw_hasher.finish(sha256context, &mut sha_256_digest_buffer).await; | 41 | let sha256_digest = hw_hasher.finish(sha256context, &mut sha_256_digest_buffer).await; |
| 42 | 42 | ||
| 43 | // Compute the SHA-256 digest in software. | 43 | // Compute the SHA-256 digest in software. |
| 44 | let mut sw_sha256_hasher = Sha256::new(); | 44 | let mut sw_sha256_hasher = Sha256::new(); |
| 45 | sw_sha256_hasher.update(test_1); | 45 | sw_sha256_hasher.update(test_1); |
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs index 7e7915b2e..14d5b6d7b 100644 --- a/tests/stm32/src/common.rs +++ b/tests/stm32/src/common.rs | |||
| @@ -201,7 +201,7 @@ define_peris!( | |||
| 201 | ); | 201 | ); |
| 202 | #[cfg(feature = "stm32l552ze")] | 202 | #[cfg(feature = "stm32l552ze")] |
| 203 | define_peris!( | 203 | define_peris!( |
| 204 | HASH_DMA = DMA1_CH0, | 204 | HASH_DMA = DMA1_CH1, |
| 205 | UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2, | 205 | UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2, |
| 206 | SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2, | 206 | SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2, |
| 207 | @irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;}, | 207 | @irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;}, |
