diff options
| author | Dario Nieuwenhuis <[email protected]> | 2023-10-18 03:16:36 +0200 |
|---|---|---|
| committer | Dario Nieuwenhuis <[email protected]> | 2023-10-18 05:01:11 +0200 |
| commit | 67010d123c874383f48ccd5c1b2287907677e460 (patch) | |
| tree | 806c4259519c3883e697c1327cf1231b92ea1005 /tests | |
| parent | 361fde35cf37e5c8171ab470449e85ad44da4e52 (diff) | |
stm32/rcc: refactor f7.
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/stm32/src/common.rs | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs index 9f1307ce5..7bc741416 100644 --- a/tests/stm32/src/common.rs +++ b/tests/stm32/src/common.rs | |||
| @@ -233,7 +233,23 @@ pub fn config() -> Config { | |||
| 233 | 233 | ||
| 234 | #[cfg(feature = "stm32f767zi")] | 234 | #[cfg(feature = "stm32f767zi")] |
| 235 | { | 235 | { |
| 236 | config.rcc.sys_ck = Some(Hertz(200_000_000)); | 236 | use embassy_stm32::rcc::*; |
| 237 | config.rcc.hse = Some(Hse { | ||
| 238 | freq: Hertz(8_000_000), | ||
| 239 | mode: HseMode::Bypass, | ||
| 240 | }); | ||
| 241 | config.rcc.pll_src = PllSource::HSE; | ||
| 242 | config.rcc.pll = Some(Pll { | ||
| 243 | prediv: PllPreDiv::DIV4, | ||
| 244 | mul: PllMul::MUL216, | ||
| 245 | divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz. | ||
| 246 | divq: None, | ||
| 247 | divr: None, | ||
| 248 | }); | ||
| 249 | config.rcc.ahb_pre = AHBPrescaler::DIV1; | ||
| 250 | config.rcc.apb1_pre = APBPrescaler::DIV4; | ||
| 251 | config.rcc.apb2_pre = APBPrescaler::DIV2; | ||
| 252 | config.rcc.sys = Sysclk::PLL1_P; | ||
| 237 | } | 253 | } |
| 238 | 254 | ||
| 239 | #[cfg(feature = "stm32h563zi")] | 255 | #[cfg(feature = "stm32h563zi")] |
