aboutsummaryrefslogtreecommitdiff
path: root/tests
diff options
context:
space:
mode:
authorDario Nieuwenhuis <[email protected]>2024-04-29 20:52:27 +0200
committerDario Nieuwenhuis <[email protected]>2024-04-29 20:52:27 +0200
commit6f44d7a9dfbb1dfe503c978e2277cfc5b1b6d486 (patch)
tree0850613ec1eef6397d853c8b04a1ae86c12f9d8a /tests
parent679160a1c573709ccf2c54755e69ea9e1b5a209e (diff)
stm32: update metapac. Adds U5 LPDMA, fixes ADC_COMMONs.
Diffstat (limited to 'tests')
-rw-r--r--tests/stm32/src/bin/dac_l1.rs2
-rw-r--r--tests/stm32/src/common.rs6
2 files changed, 4 insertions, 4 deletions
diff --git a/tests/stm32/src/bin/dac_l1.rs b/tests/stm32/src/bin/dac_l1.rs
index f8b00aaef..d5e9c9722 100644
--- a/tests/stm32/src/bin/dac_l1.rs
+++ b/tests/stm32/src/bin/dac_l1.rs
@@ -19,7 +19,7 @@ use micromath::F32Ext;
19use {defmt_rtt as _, panic_probe as _}; 19use {defmt_rtt as _, panic_probe as _};
20 20
21bind_interrupts!(struct Irqs { 21bind_interrupts!(struct Irqs {
22 ADC1 => embassy_stm32::adc::InterruptHandler<peripherals::ADC>; 22 ADC1 => embassy_stm32::adc::InterruptHandler<peripherals::ADC1>;
23}); 23});
24 24
25#[embassy_executor::main] 25#[embassy_executor::main]
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 0e555efc8..24d33dc3b 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -120,7 +120,7 @@ define_peris!(
120define_peris!( 120define_peris!(
121 UART = USART6, UART_TX = PG14, UART_RX = PG9, UART_TX_DMA = DMA2_CH6, UART_RX_DMA = DMA2_CH1, 121 UART = USART6, UART_TX = PG14, UART_RX = PG9, UART_TX_DMA = DMA2_CH6, UART_RX_DMA = DMA2_CH1,
122 SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA2_CH3, SPI_RX_DMA = DMA2_CH2, 122 SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA2_CH3, SPI_RX_DMA = DMA2_CH2,
123 ADC = ADC1, DAC = DAC, DAC_PIN = PA4, 123 ADC = ADC1, DAC = DAC1, DAC_PIN = PA4,
124 CAN = CAN1, CAN_RX = PD0, CAN_TX = PD1, 124 CAN = CAN1, CAN_RX = PD0, CAN_TX = PD1,
125 @irq UART = {USART6 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART6>;}, 125 @irq UART = {USART6 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART6>;},
126); 126);
@@ -128,7 +128,7 @@ define_peris!(
128define_peris!( 128define_peris!(
129 UART = USART1, UART_TX = PA9, UART_RX = PA10, UART_TX_DMA = DMA2_CH7, UART_RX_DMA = DMA2_CH5, 129 UART = USART1, UART_TX = PA9, UART_RX = PA10, UART_TX_DMA = DMA2_CH7, UART_RX_DMA = DMA2_CH5,
130 SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA2_CH3, SPI_RX_DMA = DMA2_CH2, 130 SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA2_CH3, SPI_RX_DMA = DMA2_CH2,
131 ADC = ADC1, DAC = DAC, DAC_PIN = PA4, 131 ADC = ADC1, DAC = DAC1, DAC_PIN = PA4,
132 CAN = CAN1, CAN_RX = PA11, CAN_TX = PA12, 132 CAN = CAN1, CAN_RX = PA11, CAN_TX = PA12,
133 @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;}, 133 @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
134); 134);
@@ -210,7 +210,7 @@ define_peris!(
210define_peris!( 210define_peris!(
211 UART = USART3, UART_TX = PB10, UART_RX = PB11, UART_TX_DMA = DMA1_CH2, UART_RX_DMA = DMA1_CH3, 211 UART = USART3, UART_TX = PB10, UART_RX = PB11, UART_TX_DMA = DMA1_CH2, UART_RX_DMA = DMA1_CH3,
212 SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2, 212 SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2,
213 ADC = ADC, DAC = DAC, DAC_PIN = PA4, 213 ADC = ADC1, DAC = DAC1, DAC_PIN = PA4,
214 @irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;}, 214 @irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
215); 215);
216#[cfg(feature = "stm32l552ze")] 216#[cfg(feature = "stm32l552ze")]