diff options
| author | Dario Nieuwenhuis <[email protected]> | 2023-10-15 03:08:14 +0200 |
|---|---|---|
| committer | Dario Nieuwenhuis <[email protected]> | 2023-10-15 03:08:49 +0200 |
| commit | 8a10948ce97fa3b3c29cf55c91585789dd0f360c (patch) | |
| tree | 4ad52bcc18d35459e4431b4f65c66c243a152efb /tests | |
| parent | 7045c5317091c8e81b0dbe64c9788bb2667472b1 (diff) | |
stm32/rcc: port L4 to the "flattened" API like h5/h7.
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/stm32/src/common.rs | 20 |
1 files changed, 11 insertions, 9 deletions
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs index 2bf500798..e1d7855fc 100644 --- a/tests/stm32/src/common.rs +++ b/tests/stm32/src/common.rs | |||
| @@ -284,17 +284,19 @@ pub fn config() -> Config { | |||
| 284 | config.rcc.adc_clock_source = AdcClockSource::PLL2_P; | 284 | config.rcc.adc_clock_source = AdcClockSource::PLL2_P; |
| 285 | } | 285 | } |
| 286 | 286 | ||
| 287 | #[cfg(any(feature = "stm32l4a6zg", feature = "stm32l4r5zi"))] | 287 | #[cfg(any(feature = "stm32l496zg", feature = "stm32l4a6zg", feature = "stm32l4r5zi"))] |
| 288 | { | 288 | { |
| 289 | use embassy_stm32::rcc::*; | 289 | use embassy_stm32::rcc::*; |
| 290 | config.rcc.mux = ClockSrc::PLL( | 290 | config.rcc.mux = ClockSrc::PLL; |
| 291 | // 72Mhz clock (16 / 1 * 18 / 4) | 291 | config.rcc.hsi16 = true; |
| 292 | PLLSource::HSI16, | 292 | config.rcc.pll_src = PLLSource::HSI16; |
| 293 | PllRDiv::DIV4, | 293 | config.rcc.pll = Some(Pll { |
| 294 | PllPreDiv::DIV1, | 294 | prediv: PllPreDiv::DIV1, |
| 295 | PllMul::MUL18, | 295 | mul: PllMul::MUL18, |
| 296 | Some(PllQDiv::DIV6), // 48Mhz (16 / 1 * 18 / 6) | 296 | divp: None, |
| 297 | ); | 297 | divq: Some(PllQDiv::DIV6), // 48Mhz (16 / 1 * 18 / 6) |
| 298 | divr: Some(PllRDiv::DIV4), // sysclk 72Mhz clock (16 / 1 * 18 / 4) | ||
| 299 | }); | ||
| 298 | } | 300 | } |
| 299 | 301 | ||
| 300 | #[cfg(any(feature = "stm32l552ze"))] | 302 | #[cfg(any(feature = "stm32l552ze"))] |