diff options
| author | xoviat <[email protected]> | 2023-10-17 20:31:44 -0500 |
|---|---|---|
| committer | xoviat <[email protected]> | 2023-10-17 20:31:44 -0500 |
| commit | bbd12c9372049e3d586b1738642c768849d42471 (patch) | |
| tree | 80124a4757982e2239dc3767cb07977bcc66342d /tests | |
| parent | d94b9fe6fb6adee82c1427e72450f77a0d0973c3 (diff) | |
stm32: update metapac
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/stm32/src/common.rs | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs index 52edae3ac..9f1307ce5 100644 --- a/tests/stm32/src/common.rs +++ b/tests/stm32/src/common.rs | |||
| @@ -295,7 +295,14 @@ pub fn config() -> Config { | |||
| 295 | #[cfg(any(feature = "stm32l496zg", feature = "stm32l4a6zg", feature = "stm32l4r5zi"))] | 295 | #[cfg(any(feature = "stm32l496zg", feature = "stm32l4a6zg", feature = "stm32l4r5zi"))] |
| 296 | { | 296 | { |
| 297 | use embassy_stm32::rcc::*; | 297 | use embassy_stm32::rcc::*; |
| 298 | config.rcc.mux = ClockSrc::PLL; | 298 | #[cfg(feature = "stm32l4r5zi")] |
| 299 | { | ||
| 300 | config.rcc.mux = ClockSrc::PLL1_R; | ||
| 301 | } | ||
| 302 | #[cfg(not(feature = "stm32l4r5zi"))] | ||
| 303 | { | ||
| 304 | config.rcc.mux = ClockSrc::PLL1_P; | ||
| 305 | } | ||
| 299 | config.rcc.hsi16 = true; | 306 | config.rcc.hsi16 = true; |
| 300 | config.rcc.pll = Some(Pll { | 307 | config.rcc.pll = Some(Pll { |
| 301 | source: PLLSource::HSI, | 308 | source: PLLSource::HSI, |
| @@ -320,10 +327,10 @@ pub fn config() -> Config { | |||
| 320 | { | 327 | { |
| 321 | use embassy_stm32::rcc::*; | 328 | use embassy_stm32::rcc::*; |
| 322 | config.rcc.hsi16 = true; | 329 | config.rcc.hsi16 = true; |
| 323 | config.rcc.mux = ClockSrc::PLL; | 330 | config.rcc.mux = ClockSrc::PLL1_R; |
| 324 | config.rcc.pll = Some(Pll { | 331 | config.rcc.pll = Some(Pll { |
| 325 | // 110Mhz clock (16 / 4 * 55 / 2) | 332 | // 110Mhz clock (16 / 4 * 55 / 2) |
| 326 | source: PLLSource::HSI16, | 333 | source: PLLSource::HSI, |
| 327 | prediv: PllPreDiv::DIV4, | 334 | prediv: PllPreDiv::DIV4, |
| 328 | mul: PllMul::MUL55, | 335 | mul: PllMul::MUL55, |
| 329 | divp: None, | 336 | divp: None, |
