stm32/hil: add f2, f3, f7, l49

4 files changed, 87 insertions, 7 deletions

diff --git a/tests/perf-client/src/lib.rs b/tests/perf-client/src/lib.rs
index a36147dbb..d709c7bd0 100644
--- a/tests/perf-client/src/lib.rs
+++ b/tests/perf-client/src/lib.rs
@@ -30,6 +30,7 @@ pub async fn run<D: Driver>(stack: &Stack<D>, expected: Expected) {
 }
 
 const TEST_DURATION: usize = 10;
+const IO_BUFFER_SIZE: usize = 1024;
 const RX_BUFFER_SIZE: usize = 4096;
 const TX_BUFFER_SIZE: usize = 4096;
 const SERVER_ADDRESS: Ipv4Address = Ipv4Address::new(192, 168, 2, 2);
@@ -52,7 +53,7 @@ async fn test_download<D: Driver>(stack: &Stack<D>) -> usize {
     }
     info!("connected, testing...");
 
-    let mut rx_buf = [0; 4096];
+    let mut rx_buf = [0; IO_BUFFER_SIZE];
     let mut total: usize = 0;
     with_timeout(Duration::from_secs(TEST_DURATION as _), async {
         loop {
@@ -92,7 +93,7 @@ async fn test_upload<D: Driver>(stack: &Stack<D>) -> usize {
     }
     info!("connected, testing...");
 
-    let buf = [0; 4096];
+    let buf = [0; IO_BUFFER_SIZE];
     let mut total: usize = 0;
     with_timeout(Duration::from_secs(TEST_DURATION as _), async {
         loop {
@@ -134,8 +135,8 @@ async fn test_upload_download<D: Driver>(stack: &Stack<D>) -> usize {
 
     let (mut reader, mut writer) = socket.split();
 
-    let tx_buf = [0; 4096];
-    let mut rx_buf = [0; 4096];
+    let tx_buf = [0; IO_BUFFER_SIZE];
+    let mut rx_buf = [0; IO_BUFFER_SIZE];
     let mut total: usize = 0;
     let tx_fut = async {
         loop {
diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml
index 2b01def5c..c1addcd99 100644
--- a/tests/stm32/Cargo.toml
+++ b/tests/stm32/Cargo.toml
@@ -20,6 +20,10 @@ stm32l152re = ["embassy-stm32/stm32l152re", "not-gpdma"]     # Nucleo
 stm32l4a6zg = ["embassy-stm32/stm32l4a6zg", "not-gpdma"]     # Nucleo
 stm32l4r5zi = ["embassy-stm32/stm32l4r5zi", "not-gpdma"]     # Nucleo
 stm32l552ze = ["embassy-stm32/stm32l552ze", "not-gpdma"]     # Nucleo
+stm32f767zi = ["embassy-stm32/stm32f767zi", "not-gpdma", "eth"]     # Nucleo
+stm32f207zg = ["embassy-stm32/stm32f207zg", "not-gpdma", "eth"]     # Nucleo
+stm32f303ze = ["embassy-stm32/stm32f303ze", "not-gpdma"]     # Nucleo
+stm32l496zg = ["embassy-stm32/stm32l496zg", "not-gpdma"]     # Nucleo
 
 eth = []
 sdmmc = []
diff --git a/tests/stm32/src/bin/eth.rs b/tests/stm32/src/bin/eth.rs
index 0b32b60b3..139192381 100644
--- a/tests/stm32/src/bin/eth.rs
+++ b/tests/stm32/src/bin/eth.rs
@@ -19,12 +19,12 @@ use {defmt_rtt as _, panic_probe as _};
 
 teleprobe_meta::timeout!(120);
 
-#[cfg(not(feature = "stm32h563zi"))]
+#[cfg(not(any(feature = "stm32h563zi", feature = "stm32f767zi", feature = "stm32f207zg")))]
 bind_interrupts!(struct Irqs {
     ETH => eth::InterruptHandler;
     HASH_RNG => rng::InterruptHandler<peripherals::RNG>;
 });
-#[cfg(feature = "stm32h563zi")]
+#[cfg(any(feature = "stm32h563zi", feature = "stm32f767zi", feature = "stm32f207zg"))]
 bind_interrupts!(struct Irqs {
     ETH => eth::InterruptHandler;
     RNG => rng::InterruptHandler<peripherals::RNG>;
@@ -56,11 +56,21 @@ async fn main(spawner: Spawner) {
     let n = 2;
     #[cfg(feature = "stm32h563zi")]
     let n = 3;
+    #[cfg(feature = "stm32f767zi")]
+    let n = 4;
+    #[cfg(feature = "stm32f207zg")]
+    let n = 5;
 
     let mac_addr = [0x00, n, 0xDE, 0xAD, 0xBE, 0xEF];
 
+    // F2 runs out of RAM
+    #[cfg(feature = "stm32f207zg")]
+    const PACKET_QUEUE_SIZE: usize = 2;
+    #[cfg(not(feature = "stm32f207zg"))]
+    const PACKET_QUEUE_SIZE: usize = 4;
+
     let device = Ethernet::new(
-        make_static!(PacketQueue::<4, 4>::new()),
+        make_static!(PacketQueue::<PACKET_QUEUE_SIZE, PACKET_QUEUE_SIZE>::new()),
         p.ETH,
         Irqs,
         p.PA1,
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 6bf5c36ef..32ba03e4f 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -34,6 +34,14 @@ teleprobe_meta::target!(b"nucleo-stm32l4a6zg");
 teleprobe_meta::target!(b"nucleo-stm32l4r5zi");
 #[cfg(feature = "stm32l552ze")]
 teleprobe_meta::target!(b"nucleo-stm32l552ze");
+#[cfg(feature = "stm32f767zi")]
+teleprobe_meta::target!(b"nucleo-stm32f767zi");
+#[cfg(feature = "stm32f207zg")]
+teleprobe_meta::target!(b"nucleo-stm32f207zg");
+#[cfg(feature = "stm32f303ze")]
+teleprobe_meta::target!(b"nucleo-stm32f303ze");
+#[cfg(feature = "stm32l496zg")]
+teleprobe_meta::target!(b"nucleo-stm32l496zg");
 
 macro_rules! define_peris {
     ($($name:ident = $peri:ident,)* $(@irq $irq_name:ident = $irq_code:tt,)*) => {
@@ -119,6 +127,12 @@ define_peris!(
     SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
     @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
 );
+#[cfg(feature = "stm32l496zg")]
+define_peris!(
+    UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = DMA1_CH2, UART_RX_DMA = DMA1_CH3,
+    SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2,
+    @irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
+);
 #[cfg(feature = "stm32l4a6zg")]
 define_peris!(
     UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = DMA1_CH2, UART_RX_DMA = DMA1_CH3,
@@ -149,11 +163,57 @@ define_peris!(
     SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
     @irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
 );
+#[cfg(feature = "stm32f767zi")]
+define_peris!(
+    UART = USART6, UART_TX = PG14, UART_RX = PG9, UART_TX_DMA = DMA2_CH6, UART_RX_DMA = DMA2_CH1,
+    SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA2_CH3, SPI_RX_DMA = DMA2_CH2,
+    @irq UART = {USART6 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART6>;},
+);
+#[cfg(feature = "stm32f207zg")]
+define_peris!(
+    UART = USART6, UART_TX = PG14, UART_RX = PG9, UART_TX_DMA = DMA2_CH6, UART_RX_DMA = DMA2_CH1,
+    SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA2_CH3, SPI_RX_DMA = DMA2_CH2,
+    @irq UART = {USART6 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART6>;},
+);
+#[cfg(feature = "stm32f303ze")]
+define_peris!(
+    UART = USART1, UART_TX = PC4, UART_RX = PC5, UART_TX_DMA = DMA1_CH4, UART_RX_DMA = DMA1_CH5,
+    SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2,
+    @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
+);
 
 pub fn config() -> Config {
     #[allow(unused_mut)]
     let mut config = Config::default();
 
+    #[cfg(feature = "stm32f207zg")]
+    {
+        use embassy_stm32::rcc::*;
+        // By default, HSE on the board comes from a 8 MHz clock signal (not a crystal)
+        config.rcc.hse = Some(HSEConfig {
+            frequency: Hertz(8_000_000),
+            source: HSESrc::Bypass,
+        });
+        // PLL uses HSE as the clock source
+        config.rcc.pll_mux = PLLSrc::HSE;
+        config.rcc.pll = PLLConfig {
+            // 8 MHz clock source / 8 = 1 MHz PLL input
+            pre_div: unwrap!(PLLPreDiv::try_from(8)),
+            // 1 MHz PLL input * 240 = 240 MHz PLL VCO
+            mul: unwrap!(PLLMul::try_from(240)),
+            // 240 MHz PLL VCO / 2 = 120 MHz main PLL output
+            main_div: PLLMainDiv::Div2,
+            // 240 MHz PLL VCO / 5 = 48 MHz PLL48 output
+            pll48_div: unwrap!(PLL48Div::try_from(5)),
+        };
+        // System clock comes from PLL (= the 120 MHz main PLL output)
+        config.rcc.mux = ClockSrc::PLL;
+        // 120 MHz / 4 = 30 MHz APB1 frequency
+        config.rcc.apb1_pre = APBPrescaler::DIV4;
+        // 120 MHz / 2 = 60 MHz APB2 frequency
+        config.rcc.apb2_pre = APBPrescaler::DIV2;
+    }
+
     #[cfg(feature = "stm32f429zi")]
     {
         // TODO: stm32f429zi can do up to 180mhz, but that makes tests fail.
@@ -163,6 +223,11 @@ pub fn config() -> Config {
         config.rcc.pclk2 = Some(Hertz(84_000_000));
     }
 
+    #[cfg(feature = "stm32f767zi")]
+    {
+        config.rcc.sys_ck = Some(Hertz(200_000_000));
+    }
+
     #[cfg(feature = "stm32h563zi")]
     {
         use embassy_stm32::rcc::*;