Merge #664

664: stm32: more spi fixes r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <[email protected]>

2 files changed, 42 insertions, 0 deletions

diff --git a/tests/stm32/src/bin/spi.rs b/tests/stm32/src/bin/spi.rs
index 47d0017ac..b079472d5 100644
--- a/tests/stm32/src/bin/spi.rs
+++ b/tests/stm32/src/bin/spi.rs
@@ -37,9 +37,30 @@ async fn main(_spawner: Spawner, p: Peripherals) {
     // Arduino pins D11 and D12 (MOSI-MISO) are connected together with a 1K resistor.
     // so we should get the data we sent back.
     let mut buf = data;
+    spi.blocking_transfer(&mut buf, &data).unwrap();
+    assert_eq!(buf, data);
+
     spi.blocking_transfer_in_place(&mut buf).unwrap();
     assert_eq!(buf, data);
 
+    // Check read/write don't hang. We can't check they transfer the right data
+    // without fancier test mechanisms.
+    spi.blocking_write(&buf).unwrap();
+    spi.blocking_read(&mut buf).unwrap();
+    spi.blocking_write(&buf).unwrap();
+    spi.blocking_read(&mut buf).unwrap();
+    spi.blocking_write(&buf).unwrap();
+
+    // Check transfer doesn't break after having done a write, due to garbage in the FIFO
+    spi.blocking_transfer(&mut buf, &data).unwrap();
+    assert_eq!(buf, data);
+
+    // Check zero-length operations, these should be noops.
+    spi.blocking_transfer::<u8>(&mut [], &[]).unwrap();
+    spi.blocking_transfer_in_place::<u8>(&mut []).unwrap();
+    spi.blocking_read::<u8>(&mut []).unwrap();
+    spi.blocking_write::<u8>(&[]).unwrap();
+
     info!("Test OK");
     cortex_m::asm::bkpt();
 }
diff --git a/tests/stm32/src/bin/spi_dma.rs b/tests/stm32/src/bin/spi_dma.rs
index 59a5bcd0c..3e9521ae7 100644
--- a/tests/stm32/src/bin/spi_dma.rs
+++ b/tests/stm32/src/bin/spi_dma.rs
@@ -47,6 +47,27 @@ async fn main(_spawner: Spawner, p: Peripherals) {
     spi.transfer(&mut buf, &data).await.unwrap();
     assert_eq!(buf, data);
 
+    spi.transfer_in_place(&mut buf).await.unwrap();
+    assert_eq!(buf, data);
+
+    // Check read/write don't hang. We can't check they transfer the right data
+    // without fancier test mechanisms.
+    spi.write(&buf).await.unwrap();
+    spi.read(&mut buf).await.unwrap();
+    spi.write(&buf).await.unwrap();
+    spi.read(&mut buf).await.unwrap();
+    spi.write(&buf).await.unwrap();
+
+    // Check transfer doesn't break after having done a write, due to garbage in the FIFO
+    spi.transfer(&mut buf, &data).await.unwrap();
+    assert_eq!(buf, data);
+
+    // Check zero-length operations, these should be noops.
+    spi.transfer::<u8>(&mut [], &[]).await.unwrap();
+    spi.transfer_in_place::<u8>(&mut []).await.unwrap();
+    spi.read::<u8>(&mut []).await.unwrap();
+    spi.write::<u8>(&[]).await.unwrap();
+
     info!("Test OK");
     cortex_m::asm::bkpt();
 }