5 files changed, 128 insertions, 120 deletions

diff --git a/embassy-net-adin1110/src/crc32.rs b/embassy-net-adin1110/src/crc32.rs
index 75a7d65b7..906c9aad7 100644
--- a/embassy-net-adin1110/src/crc32.rs
+++ b/embassy-net-adin1110/src/crc32.rs
@@ -1,33 +1,33 @@
 pub const CRC32R_LOOKUP_TABLE: [u32; 256] = [
-    0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3, 0x0EDB8832,
-    0x79DCB8A4, 0xE0D5E91E, 0x97D2D988, 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91, 0x1DB71064, 0x6AB020F2,
-    0xF3B97148, 0x84BE41DE, 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7, 0x136C9856, 0x646BA8C0, 0xFD62F97A,
-    0x8A65C9EC, 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5, 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
-    0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B, 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940, 0x32D86CE3,
-    0x45DF5C75, 0xDCD60DCF, 0xABD13D59, 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116, 0x21B4F4B5, 0x56B3C423,
-    0xCFBA9599, 0xB8BDA50F, 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924, 0x2F6F7C87, 0x58684C11, 0xC1611DAB,
-    0xB6662D3D, 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A, 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
-    0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818, 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01, 0x6B6B51F4,
-    0x1C6C6162, 0x856530D8, 0xF262004E, 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457, 0x65B0D9C6, 0x12B7E950,
-    0x8BBEB8EA, 0xFCB9887C, 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65, 0x4DB26158, 0x3AB551CE, 0xA3BC0074,
-    0xD4BB30E2, 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB, 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
-    0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9, 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086, 0x5768B525,
-    0x206F85B3, 0xB966D409, 0xCE61E49F, 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4, 0x59B33D17, 0x2EB40D81,
-    0xB7BD5C3B, 0xC0BA6CAD, 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A, 0xEAD54739, 0x9DD277AF, 0x04DB2615,
-    0x73DC1683, 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8, 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
-    0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE, 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7, 0xFED41B76,
-    0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC, 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5, 0xD6D6A3E8, 0xA1D1937E,
-    0x38D8C2C4, 0x4FDFF252, 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B, 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6,
-    0x41047A60, 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79, 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
-    0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F, 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04, 0xC2D7FFA7,
-    0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D, 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A, 0x9C0906A9, 0xEB0E363F,
-    0x72076785, 0x05005713, 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38, 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7,
-    0x0BDBDF21, 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E, 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
-    0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C, 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45, 0xA00AE278,
-    0xD70DD2EE, 0x4E048354, 0x3903B3C2, 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB, 0xAED16A4A, 0xD9D65ADC,
-    0x40DF0B66, 0x37D83BF0, 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9, 0xBDBDF21C, 0xCABAC28A, 0x53B39330,
-    0x24B4A3A6, 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF, 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
-    0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D,
+    0x0000_0000, 0x7707_3096, 0xEE0E_612C, 0x9909_51BA, 0x076D_C419, 0x706A_F48F, 0xE963_A535, 0x9E64_95A3, 0x0EDB_8832,
+    0x79DC_B8A4, 0xE0D5_E91E, 0x97D2_D988, 0x09B6_4C2B, 0x7EB1_7CBD, 0xE7B8_2D07, 0x90BF_1D91, 0x1DB7_1064, 0x6AB0_20F2,
+    0xF3B9_7148, 0x84BE_41DE, 0x1ADA_D47D, 0x6DDD_E4EB, 0xF4D4_B551, 0x83D3_85C7, 0x136C_9856, 0x646B_A8C0, 0xFD62_F97A,
+    0x8A65_C9EC, 0x1401_5C4F, 0x6306_6CD9, 0xFA0F_3D63, 0x8D08_0DF5, 0x3B6E_20C8, 0x4C69_105E, 0xD560_41E4, 0xA267_7172,
+    0x3C03_E4D1, 0x4B04_D447, 0xD20D_85FD, 0xA50A_B56B, 0x35B5_A8FA, 0x42B2_986C, 0xDBBB_C9D6, 0xACBC_F940, 0x32D8_6CE3,
+    0x45DF_5C75, 0xDCD6_0DCF, 0xABD1_3D59, 0x26D9_30AC, 0x51DE_003A, 0xC8D7_5180, 0xBFD0_6116, 0x21B4_F4B5, 0x56B3_C423,
+    0xCFBA_9599, 0xB8BD_A50F, 0x2802_B89E, 0x5F05_8808, 0xC60C_D9B2, 0xB10B_E924, 0x2F6F_7C87, 0x5868_4C11, 0xC161_1DAB,
+    0xB666_2D3D, 0x76DC_4190, 0x01DB_7106, 0x98D2_20BC, 0xEFD5_102A, 0x71B1_8589, 0x06B6_B51F, 0x9FBF_E4A5, 0xE8B8_D433,
+    0x7807_C9A2, 0x0F00_F934, 0x9609_A88E, 0xE10E_9818, 0x7F6A_0DBB, 0x086D_3D2D, 0x9164_6C97, 0xE663_5C01, 0x6B6B_51F4,
+    0x1C6C_6162, 0x8565_30D8, 0xF262_004E, 0x6C06_95ED, 0x1B01_A57B, 0x8208_F4C1, 0xF50F_C457, 0x65B0_D9C6, 0x12B7_E950,
+    0x8BBE_B8EA, 0xFCB9_887C, 0x62DD_1DDF, 0x15DA_2D49, 0x8CD3_7CF3, 0xFBD4_4C65, 0x4DB2_6158, 0x3AB5_51CE, 0xA3BC_0074,
+    0xD4BB_30E2, 0x4ADF_A541, 0x3DD8_95D7, 0xA4D1_C46D, 0xD3D6_F4FB, 0x4369_E96A, 0x346E_D9FC, 0xAD67_8846, 0xDA60_B8D0,
+    0x4404_2D73, 0x3303_1DE5, 0xAA0A_4C5F, 0xDD0D_7CC9, 0x5005_713C, 0x2702_41AA, 0xBE0B_1010, 0xC90C_2086, 0x5768_B525,
+    0x206F_85B3, 0xB966_D409, 0xCE61_E49F, 0x5EDE_F90E, 0x29D9_C998, 0xB0D0_9822, 0xC7D7_A8B4, 0x59B3_3D17, 0x2EB4_0D81,
+    0xB7BD_5C3B, 0xC0BA_6CAD, 0xEDB8_8320, 0x9ABF_B3B6, 0x03B6_E20C, 0x74B1_D29A, 0xEAD5_4739, 0x9DD2_77AF, 0x04DB_2615,
+    0x73DC_1683, 0xE363_0B12, 0x9464_3B84, 0x0D6D_6A3E, 0x7A6A_5AA8, 0xE40E_CF0B, 0x9309_FF9D, 0x0A00_AE27, 0x7D07_9EB1,
+    0xF00F_9344, 0x8708_A3D2, 0x1E01_F268, 0x6906_C2FE, 0xF762_575D, 0x8065_67CB, 0x196C_3671, 0x6E6B_06E7, 0xFED4_1B76,
+    0x89D3_2BE0, 0x10DA_7A5A, 0x67DD_4ACC, 0xF9B9_DF6F, 0x8EBE_EFF9, 0x17B7_BE43, 0x60B0_8ED5, 0xD6D6_A3E8, 0xA1D1_937E,
+    0x38D8_C2C4, 0x4FDF_F252, 0xD1BB_67F1, 0xA6BC_5767, 0x3FB5_06DD, 0x48B2_364B, 0xD80D_2BDA, 0xAF0A_1B4C, 0x3603_4AF6,
+    0x4104_7A60, 0xDF60_EFC3, 0xA867_DF55, 0x316E_8EEF, 0x4669_BE79, 0xCB61_B38C, 0xBC66_831A, 0x256F_D2A0, 0x5268_E236,
+    0xCC0C_7795, 0xBB0B_4703, 0x2202_16B9, 0x5505_262F, 0xC5BA_3BBE, 0xB2BD_0B28, 0x2BB4_5A92, 0x5CB3_6A04, 0xC2D7_FFA7,
+    0xB5D0_CF31, 0x2CD9_9E8B, 0x5BDE_AE1D, 0x9B64_C2B0, 0xEC63_F226, 0x756A_A39C, 0x026D_930A, 0x9C09_06A9, 0xEB0E_363F,
+    0x7207_6785, 0x0500_5713, 0x95BF_4A82, 0xE2B8_7A14, 0x7BB1_2BAE, 0x0CB6_1B38, 0x92D2_8E9B, 0xE5D5_BE0D, 0x7CDC_EFB7,
+    0x0BDB_DF21, 0x86D3_D2D4, 0xF1D4_E242, 0x68DD_B3F8, 0x1FDA_836E, 0x81BE_16CD, 0xF6B9_265B, 0x6FB0_77E1, 0x18B7_4777,
+    0x8808_5AE6, 0xFF0F_6A70, 0x6606_3BCA, 0x1101_0B5C, 0x8F65_9EFF, 0xF862_AE69, 0x616B_FFD3, 0x166C_CF45, 0xA00A_E278,
+    0xD70D_D2EE, 0x4E04_8354, 0x3903_B3C2, 0xA767_2661, 0xD060_16F7, 0x4969_474D, 0x3E6E_77DB, 0xAED1_6A4A, 0xD9D6_5ADC,
+    0x40DF_0B66, 0x37D8_3BF0, 0xA9BC_AE53, 0xDEBB_9EC5, 0x47B2_CF7F, 0x30B5_FFE9, 0xBDBD_F21C, 0xCABA_C28A, 0x53B3_9330,
+    0x24B4_A3A6, 0xBAD0_3605, 0xCDD7_0693, 0x54DE_5729, 0x23D9_67BF, 0xB366_7A2E, 0xC461_4AB8, 0x5D68_1B02, 0x2A6F_2B94,
+    0xB40B_BE37, 0xC30C_8EA1, 0x5A05_DF1B, 0x2D02_EF8D,
 ];
 
 #[allow(non_camel_case_types)]
@@ -35,9 +35,9 @@ pub const CRC32R_LOOKUP_TABLE: [u32; 256] = [
 pub struct ETH_FSC(pub u32);
 
 impl ETH_FSC {
-    pub const CRC32_OK: u32 = 0x2144df1c;
+    pub const CRC32_OK: u32 = 0x2144_df1c;
 
-    pub fn new(data: &[u8]) -> Self {
+    #[must_use] pub fn new(data: &[u8]) -> Self {
         let fsc = data.iter().fold(u32::MAX, |crc, byte| {
             let idx = u8::try_from(crc & 0xFF).unwrap() ^ byte;
             CRC32R_LOOKUP_TABLE[usize::from(idx)] ^ (crc >> 8)
@@ -45,15 +45,15 @@ impl ETH_FSC {
         Self(fsc)
     }
 
-    pub fn crc_ok(&self) -> bool {
+    #[must_use] pub fn crc_ok(&self) -> bool {
         self.0 == Self::CRC32_OK
     }
 
-    pub fn hton_bytes(&self) -> [u8; 4] {
+    #[must_use] pub fn hton_bytes(&self) -> [u8; 4] {
         self.0.to_le_bytes()
     }
 
-    pub fn hton(&self) -> u32 {
+    #[must_use] pub fn hton(&self) -> u32 {
         self.0.to_le()
     }
 }
diff --git a/embassy-net-adin1110/src/lib.rs b/embassy-net-adin1110/src/lib.rs
index 4ce8a1895..c74648936 100644
--- a/embassy-net-adin1110/src/lib.rs
+++ b/embassy-net-adin1110/src/lib.rs
@@ -1,16 +1,10 @@
-#![allow(clippy::pedantic)]
+#![deny(clippy::pedantic)]
 #![feature(type_alias_impl_trait)]
 #![feature(async_fn_in_trait)]
 #![cfg_attr(not(any(test, feature = "std")), no_std)]
-
-use ch::driver::LinkState;
-use embassy_futures::select::{select, Either};
-use embassy_net_driver_channel as ch;
-use embassy_time::{Duration, Timer};
-use embedded_hal_1::digital::OutputPin;
-use embedded_hal_async::digital::Wait;
-use embedded_hal_async::spi::{Operation, SpiDevice};
-use heapless::Vec;
+#![allow(clippy::module_name_repetitions)]
+#![allow(clippy::missing_errors_doc)]
+#![allow(clippy::missing_panics_doc)]
 
 mod crc32;
 mod crc8;
@@ -18,15 +12,23 @@ mod mdio;
 mod phy;
 mod regs;
 
+use ch::driver::LinkState;
 pub use crc32::ETH_FSC;
 use crc8::crc8;
+use embassy_futures::select::{select, Either};
+use embassy_net_driver_channel as ch;
+use embassy_time::{Duration, Timer};
+use embedded_hal_1::digital::OutputPin;
+use embedded_hal_async::digital::Wait;
+use embedded_hal_async::spi::{Operation, SpiDevice};
+use heapless::Vec;
 pub use mdio::MdioBus;
 pub use phy::{Phy10BaseT1x, RegsC22, RegsC45};
 pub use regs::{Config0, Config2, SpiRegisters as sr, Status0, Status1};
 
 use crate::regs::{LedCntrl, LedFunc, LedPol, LedPolarity, SpiHeader};
 
-pub const PHYID: u32 = 0x0283BC91;
+pub const PHYID: u32 = 0x0283_BC91;
 
 /// Error values ADIN1110
 #[derive(Debug)]
@@ -44,21 +46,28 @@ pub enum AdinError<E> {
 
 pub type AEResult<T, SPIE> = core::result::Result<T, AdinError<SPIE>>;
 pub const MDIO_PHY_ADDR: u8 = 0x01;
-pub const MTU: usize = 1500;
+
+/// Maximum Transmission Unit
+pub const MTU: usize = 1514;
+
 /// Max SPI/Frame buffer size
 pub const MAX_BUFF: usize = 2048;
 
 const DONT_CARE_BYTE: u8 = 0x00;
 const TURN_AROUND_BYTE: u8 = 0x00;
 
-const FEC_LEN: usize = 4;
+/// Packet minimal frame/packet length
+const ETH_MIN_LEN: usize = 64;
+
+/// Ethernet `Frame Check Sequence` length
+const FSC_LEN: usize = 4;
 const FRAME_HEADER_LEN: usize = 2;
 const WR_HEADER_LEN: usize = 2;
 
 // P1 = 0x00, P2 = 0x01
 const PORT_ID_BYTE: u8 = 0x00;
 
-pub type Packet = Vec<u8, { MTU + FEC_LEN + WR_HEADER_LEN }>;
+pub type Packet = Vec<u8, { MTU + FSC_LEN + WR_HEADER_LEN }>;
 
 /// Type alias for the embassy-net driver for ADIN1110
 pub type Device<'d> = embassy_net_driver_channel::Device<'d, MTU>;
@@ -69,6 +78,7 @@ pub struct State<const N_RX: usize, const N_TX: usize> {
 }
 impl<const N_RX: usize, const N_TX: usize> State<N_RX, N_TX> {
     /// Create a new `State`.
+    #[must_use]
     pub const fn new() -> Self {
         Self {
             ch_state: ch::State::new(),
@@ -81,11 +91,11 @@ pub struct ADIN1110<SPI> {
     /// SPI bus
     spi: SPI,
     /// Enable CRC on SPI transfer.
-    /// This must match with the hardware pin SPI_CFG0 were 0 = CRC enable, 1 CRC disabled.
+    /// This must match with the hardware pin `SPI_CFG0` were low = CRC enable, high = CRC disabled.
     crc: bool,
 }
 
-// Round size up the N u32;
+/// Round size up the N u32;
 pub(crate) fn size_align_u32(size: u32) -> u32 {
     (size + 3) & 0xFFFF_FFFC
 }
@@ -166,7 +176,7 @@ where
         self.spi.write(&tx_buf).await.map_err(AdinError::Spi)
     }
 
-    // helper function for write to MDIO_ACC register and wait for ready!
+    /// helper function for write to `MDIO_ACC` register and wait for ready!
     async fn write_mdio_acc_reg(&mut self, mdio_acc_val: u32) -> AEResult<u32, SpiE> {
         self.write_reg(sr::MDIO_ACC, mdio_acc_val).await?;
 
@@ -181,6 +191,7 @@ where
         Err(AdinError::MDIO_ACC_TIMEOUT)
     }
 
+    /// Read out fifo ethernet packet memory received via the wire.
     pub async fn read_fifo(&mut self, packet: &mut [u8]) -> AEResult<usize, SpiE> {
         let mut tx_buf = Vec::<u8, 16>::new();
 
@@ -190,7 +201,7 @@ where
         // Packet read of write to the MAC packet buffer must be a multipul of 4!
         let read_size = size_align_u32(packet_size);
 
-        if packet_size < u32::try_from(FRAME_HEADER_LEN + FEC_LEN).unwrap()
+        if packet_size < u32::try_from(FRAME_HEADER_LEN + FSC_LEN).unwrap()
             || read_size > u32::try_from(packet.len()).unwrap()
         {
             return Err(AdinError::PACKET_TOO_BIG);
@@ -226,11 +237,9 @@ where
         Ok(packet_size as usize)
     }
 
+    /// Write to fifo ethernet packet memory send over the wire.
     pub async fn write_fifo(&mut self, frame: &[u8]) -> AEResult<(), SpiE> {
         let header_len = self.header_write_len();
-        // if packet.len() < header_len {
-        //     return Err(AdinError::PACKET_TOO_SMALL);
-        // }
 
         let mut packet = Packet::new();
 
@@ -244,37 +253,33 @@ where
             .map_err(|_| AdinError::PACKET_TOO_BIG)?;
 
         if self.crc {
-            assert_eq!(header_len, 5);
             // Add CRC for header data
             packet
                 .push(crc8(&packet[0..2]))
                 .map_err(|_| AdinError::PACKET_TOO_BIG)?;
         }
 
-        // Add port number
-        // packet[header_len - FRAME_HEADER_LEN..header_len]
-        //     .copy_from_slice(u16::from(PORT_ID_BYTE).to_be_bytes().as_slice());
+        // Add port number, ADIN1110 its fixed to zero/P1, but for ADIN2111 has two ports.
         packet
             .extend_from_slice(u16::from(PORT_ID_BYTE).to_be_bytes().as_slice())
             .map_err(|_| AdinError::PACKET_TOO_BIG)?;
 
+        // Copy packet data to spi buffer.
         packet.extend_from_slice(frame).map_err(|_| AdinError::PACKET_TOO_BIG)?;
 
-        // Pad data up to 64
-        for _ in packet.len()..(64 - FEC_LEN + header_len) {
+        // Pad data up to ETH_MIN_LEN - FCS_LEN
+        for _ in packet.len()..(ETH_MIN_LEN - FSC_LEN + header_len) {
             let _ = packet.push(0x00);
         }
 
-        // // add ethernet crc32
+        // add ethernet FCS only over the ethernet packet.
         let crc = ETH_FSC::new(&packet[header_len..]);
         let _ = packet.extend_from_slice(crc.hton_bytes().as_slice());
 
-        let crc = ETH_FSC::new(&packet[header_len..]);
-        assert!(crc.crc_ok());
-
-        let send_len = packet.len() - header_len + FRAME_HEADER_LEN;
+        let send_len =
+            u32::try_from(packet.len() - header_len + FRAME_HEADER_LEN).map_err(|_| AdinError::PACKET_TOO_BIG)?;
 
-        // Packet read of write to the MAC packet buffer must be a multipul of 4!
+        // Packet read of write to the MAC packet buffer must be a multipul of 4 bytes!
         while packet.len() & 0x3 != 0 {
             let _ = packet.push(DONT_CARE_BYTE);
         }
@@ -288,7 +293,7 @@ where
             send_len,
         );
 
-        self.write_reg(sr::TX_FSIZE, send_len as u32).await?;
+        self.write_reg(sr::TX_FSIZE, send_len).await?;
 
         // Spi packet must be half word / even length
         if send_len & 1 != 0 {
@@ -346,17 +351,21 @@ where
         let mdio_acc_val: u32 =
             (0x1 << 28) | u32::from(phy_id & 0x1F) << 21 | u32::from(reg & 0x1F) << 16 | (0x3 << 26);
 
+        // Result is in the lower half of the answer.
+        #[allow(clippy::cast_possible_truncation)]
         self.write_mdio_acc_reg(mdio_acc_val).await.map(|val| val as u16)
     }
 
     /// Read from the PHY Registers as Clause 45.
     async fn read_cl45(&mut self, phy_id: u8, regc45: (u8, u16)) -> Result<u16, Self::Error> {
-        let mdio_acc_val: u32 = u32::from(phy_id & 0x1F) << 21 | u32::from(regc45.0 & 0x1F) << 16 | u32::from(regc45.1);
+        let mdio_acc_val = u32::from(phy_id & 0x1F) << 21 | u32::from(regc45.0 & 0x1F) << 16 | u32::from(regc45.1);
 
         self.write_mdio_acc_reg(mdio_acc_val).await?;
 
-        let mdio_acc_val: u32 = u32::from(phy_id & 0x1F) << 21 | u32::from(regc45.0 & 0x1F) << 16 | (0x03 << 26);
+        let mdio_acc_val = u32::from(phy_id & 0x1F) << 21 | u32::from(regc45.0 & 0x1F) << 16 | (0x03 << 26);
 
+        // Result is in the lower half of the answer.
+        #[allow(clippy::cast_possible_truncation)]
         self.write_mdio_acc_reg(mdio_acc_val).await.map(|val| val as u16)
     }
 
@@ -394,6 +403,7 @@ pub struct Runner<'d, SPI, INT, RST> {
 }
 
 impl<'d, SPI: SpiDevice, INT: Wait, RST: OutputPin> Runner<'d, SPI, INT, RST> {
+    #[allow(clippy::too_many_lines)]
     pub async fn run(mut self) -> ! {
         loop {
             let (state_chan, mut rx_chan, mut tx_chan) = self.ch.split();
@@ -566,6 +576,7 @@ pub async fn new<const N_RX: usize, const N_TX: usize, SPI: SpiDevice, INT: Wait
 
     // Reset sequence
     reset.set_low().unwrap();
+
     // Wait t1: 20-43mS
     Timer::after(Duration::from_millis(30)).await;
 
@@ -604,7 +615,7 @@ pub async fn new<const N_RX: usize, const N_TX: usize, SPI: SpiDevice, INT: Wait
     }
 
     // Config2: CRC_APPEND
-    let mut config2 = Config2(0x00000800);
+    let mut config2 = Config2(0x0000_0800);
     config2.set_crc_append(true);
     mac.write_reg(sr::CONFIG2, config2.0).await.unwrap();
 
@@ -677,6 +688,7 @@ pub async fn new<const N_RX: usize, const N_TX: usize, SPI: SpiDevice, INT: Wait
     )
 }
 
+#[allow(clippy::similar_names)]
 #[cfg(test)]
 mod tests {
     use core::convert::Infallible;
@@ -743,16 +755,12 @@ mod tests {
         let mut spe = ADIN1110::new(spi_dev, false);
 
         // Read PHIID
-        match spe.read_reg(sr::PHYID).await {
-            Ok(val) => assert_eq!(val, 0x0283BC91),
-            Err(_e) => panic!("Error:"),
-        };
+        let val = spe.read_reg(sr::PHYID).await.expect("Error");
+        assert_eq!(val, 0x0283_BC91);
 
         // Read CAPAVILITY
-        match spe.read_reg(sr::CAPABILITY).await {
-            Ok(val) => assert_eq!(val, 0x000006C3),
-            Err(_e) => panic!("Error:"),
-        };
+        let val = spe.read_reg(sr::CAPABILITY).await.expect("Error");
+        assert_eq!(val, 0x0000_06C3);
 
         spi.done();
     }
@@ -778,20 +786,16 @@ mod tests {
 
         let mut spe = ADIN1110::new(spi_dev, true);
 
-        assert_eq!(crc8(0x0283BC91_u32.to_be_bytes().as_slice()), 215);
-        assert_eq!(crc8(0x000006C3_u32.to_be_bytes().as_slice()), 57);
+        assert_eq!(crc8(0x0283_BC91_u32.to_be_bytes().as_slice()), 215);
+        assert_eq!(crc8(0x0000_06C3_u32.to_be_bytes().as_slice()), 57);
 
         // Read PHIID
-        match spe.read_reg(sr::PHYID).await {
-            Ok(val) => assert_eq!(val, 0x0283BC91),
-            Err(e) => panic!("Error: {e:?}"),
-        };
+        let val = spe.read_reg(sr::PHYID).await.expect("Error");
+        assert_eq!(val, 0x0283_BC91);
 
         // Read CAPAVILITY
-        match spe.read_reg(sr::CAPABILITY).await {
-            Ok(val) => assert_eq!(val, 0x000006C3),
-            Err(_e) => panic!("Error:"),
-        };
+        let val = spe.read_reg(sr::CAPABILITY).await.expect("Error");
+        assert_eq!(val, 0x0000_06C3);
 
         spi.done();
     }
@@ -885,7 +889,7 @@ mod tests {
     //         ];
 
     //         let mut packet = Packet::new();
-    //         packet.resize(64, 0).unwrap();
+    //         packet.resize(ETH_MIN_LEN, 0).unwrap();
 
     //         for &byte in &packet[4..] {
     //             expectations.push(SpiTransaction::send(byte));
@@ -893,7 +897,7 @@ mod tests {
     //         }
 
     //         // padding
-    //         for _ in packet.len() as u32..65 {
+    //         for _ in packet.len()..65 {
     //             expectations.push(SpiTransaction::send(0x00));
     //             expectations.push(SpiTransaction::read(DONT_CARE_BYTE));
     //         }
@@ -943,7 +947,7 @@ mod tests {
     //         ];
 
     //         let mut packet = Packet::new();
-    //         packet.resize(64, 0).unwrap();
+    //         packet.resize(ETH_MIN_LEN, 0).unwrap();
 
     //         for &byte in &packet[4..] {
     //             expectations.push(SpiTransaction::send(byte));
@@ -951,7 +955,7 @@ mod tests {
     //         }
 
     //         // padding
-    //         for _ in packet.len() as u32..64 {
+    //         for _ in packet.len() as u32..ETH_MIN_LEN {
     //             expectations.push(SpiTransaction::send(0x00));
     //             expectations.push(SpiTransaction::read(DONT_CARE_BYTE));
     //         }
@@ -1061,7 +1065,7 @@ mod tests {
     //         }
 
     //         // padding
-    //         for _ in packet.len() as u32..64 {
+    //         for _ in packet.len()..ETH_MIN_LEN {
     //             expectations.push(SpiTransaction::send(0x00));
     //             expectations.push(SpiTransaction::read(DONT_CARE_BYTE));
     //         }
@@ -1119,7 +1123,7 @@ mod tests {
     //         }
 
     //         // padding
-    //         for _ in packet.len() as u32..64 {
+    //         for _ in packet.len()..ETH_MIN_LEN {
     //             expectations.push(SpiTransaction::send(0x00));
     //             expectations.push(SpiTransaction::read(DONT_CARE_BYTE));
     //         }
@@ -1176,7 +1180,7 @@ mod tests {
     //         }
 
     //         // padding
-    //         for _ in packet.len() as u32..64 {
+    //         for _ in packet.len()..ETH_MIN_LEN {
     //             expectations.push(SpiTransaction::send(0x00));
     //             expectations.push(SpiTransaction::read(DONT_CARE_BYTE));
     //         }
@@ -1219,15 +1223,17 @@ mod tests {
         spi_packet.extend_from_slice(&[160, 49, 143, 0, 0]).unwrap();
         // Packet data
         spi_packet.extend_from_slice(&packet).unwrap();
-        // Packet padding up to 60 (64 - FCS)
-        for _ in packet.len() as u32..60 {
+        // Packet padding up to 60 (ETH_MIN_LEN - FCS)
+        for _ in packet.len()..(ETH_MIN_LEN - FSC_LEN) {
             spi_packet.push(0x00).unwrap();
         }
         // Packet FCS
         spi_packet.extend_from_slice(&[147, 149, 213, 68]).unwrap();
 
+        let spi_packet_len = u32::try_from(spi_packet.len()).unwrap();
+
         // SPI HEADER Padding of u32
-        for _ in spi_packet.len() as u32..size_align_u32(spi_packet.len() as u32) {
+        for _ in spi_packet_len..size_align_u32(spi_packet_len) {
             spi_packet.push(0x00).unwrap();
         }
 
@@ -1242,7 +1248,7 @@ mod tests {
 
         let mut spe = ADIN1110::new(spi_dev, true);
 
-        assert!(spe.write_fifo(&mut packet).await.is_ok());
+        assert!(spe.write_fifo(&packet).await.is_ok());
 
         spi.done();
     }
diff --git a/embassy-net-adin1110/src/mdio.rs b/embassy-net-adin1110/src/mdio.rs
index ab7629d3d..68477006a 100644
--- a/embassy-net-adin1110/src/mdio.rs
+++ b/embassy-net-adin1110/src/mdio.rs
@@ -32,11 +32,11 @@ enum Reg13Op {
     PostReadIncAddr = 0b10 << 14,
     Read = 0b11 << 14,
 }
-/// MdioBus trait
-/// Driver needs to implemnt the Claus 22
+/// `MdioBus` trait
+/// Driver needs to implement the Clause 22
 /// Optional Clause 45 is the device supports this.
 ///
-/// Claus 45 methodes are bases on https://www.ieee802.org/3/efm/public/nov02/oam/pannell_oam_1_1102.pdf
+/// Claus 45 methodes are bases on <https://www.ieee802.org/3/efm/public/nov02/oam/pannell_oam_1_1102.pdf>
 pub trait MdioBus {
     type Error;
 
@@ -52,13 +52,14 @@ pub trait MdioBus {
     /// Implement this function when your hardware supports it.
     async fn read_cl45(&mut self, phy_id: PhyAddr, regc45: (u8, RegC45)) -> Result<RegVal, Self::Error> {
         // Write FN
-        let val = (Reg13Op::Addr as RegVal) | (regc45.0 & DEV_MASK) as RegVal;
+        let val = (Reg13Op::Addr as RegVal) | RegVal::from(regc45.0 & DEV_MASK);
+
         self.write_cl22(phy_id, REG13, val).await?;
         // Write Addr
         self.write_cl22(phy_id, REG14, regc45.1).await?;
 
         // Write FN
-        let val = (Reg13Op::Read as RegVal) | (regc45.0 & DEV_MASK) as RegVal;
+        let val = (Reg13Op::Read as RegVal) | RegVal::from(regc45.0 & DEV_MASK);
         self.write_cl22(phy_id, REG13, val).await?;
         // Write Addr
         self.read_cl22(phy_id, REG14).await
@@ -69,7 +70,7 @@ pub trait MdioBus {
     /// Many hardware these days support direct Clause 45 operations.
     /// Implement this function when your hardware supports it.
     async fn write_cl45(&mut self, phy_id: PhyAddr, regc45: (u8, RegC45), reg_val: RegVal) -> Result<(), Self::Error> {
-        let dev_addr = (regc45.0 & DEV_MASK) as RegVal;
+        let dev_addr = RegVal::from(regc45.0 & DEV_MASK);
         let reg = regc45.1;
 
         // Write FN
diff --git a/embassy-net-adin1110/src/phy.rs b/embassy-net-adin1110/src/phy.rs
index 78d3fdf77..70060a0c3 100644
--- a/embassy-net-adin1110/src/phy.rs
+++ b/embassy-net-adin1110/src/phy.rs
@@ -30,7 +30,7 @@ pub mod RegsC45 {
     }
 
     impl DA1 {
-        pub fn into(self) -> (u8, u16) {
+        #[must_use] pub fn into(self) -> (u8, u16) {
             (0x01, self as u16)
         }
     }
@@ -48,7 +48,7 @@ pub mod RegsC45 {
     }
 
     impl DA3 {
-        pub fn into(self) -> (u8, u16) {
+        #[must_use] pub fn into(self) -> (u8, u16) {
             (0x03, self as u16)
         }
     }
@@ -62,7 +62,7 @@ pub mod RegsC45 {
     }
 
     impl DA7 {
-        pub fn into(self) -> (u8, u16) {
+        #[must_use] pub fn into(self) -> (u8, u16) {
             (0x07, self as u16)
         }
     }
@@ -84,7 +84,7 @@ pub mod RegsC45 {
     }
 
     impl DA1E {
-        pub fn into(self) -> (u8, u16) {
+        #[must_use] pub fn into(self) -> (u8, u16) {
             (0x1e, self as u16)
         }
     }
@@ -100,7 +100,7 @@ pub mod RegsC45 {
     }
 
     impl DA1F {
-        pub fn into(self) -> (u8, u16) {
+        #[must_use] pub fn into(self) -> (u8, u16) {
             (0x1f, self as u16)
         }
     }
@@ -121,8 +121,8 @@ impl Phy10BaseT1x {
         MDIOBUS: MdioBus<Error = MDE>,
         MDE: core::fmt::Debug,
     {
-        let mut phyid = (mdiobus.read_cl22(self.0, RegsC22::PHY_ID1 as u8).await? as u32) << 16;
-        phyid |= mdiobus.read_cl22(self.0, RegsC22::PHY_ID2 as u8).await? as u32;
+        let mut phyid = u32::from(mdiobus.read_cl22(self.0, RegsC22::PHY_ID1 as u8).await?) << 16;
+        phyid |= u32::from(mdiobus.read_cl22(self.0, RegsC22::PHY_ID2 as u8).await?);
         Ok(phyid)
     }
 
diff --git a/embassy-net-adin1110/src/regs.rs b/embassy-net-adin1110/src/regs.rs
index 93ce812db..4557929f0 100644
--- a/embassy-net-adin1110/src/regs.rs
+++ b/embassy-net-adin1110/src/regs.rs
@@ -74,7 +74,6 @@ impl From<u16> for SpiRegisters {
 }
 
 // Register definitions
-
 bitfield! {
     /// Status0 Register bits
     pub struct Status0(u32);
@@ -242,6 +241,7 @@ bitfield! {
     pub link_change_mask, set_link_change_mask : 1;
 }
 
+/// LED Functions
 #[repr(u8)]
 pub enum LedFunc {
     LinkupTxRxActicity = 0,
@@ -326,7 +326,7 @@ bitfield_bitrange! {struct LedCntrl(u16)}
 impl LedCntrl {
     bitfield_fields! {
         u8;
-        /// LED_0 Pin Function
+        /// LED 0 Pin Function
         pub from into LedFunc, led0_function, set_led0_function: 4, 0;
         /// LED 0 Mode Selection
         pub led0_mode, set_led0_mode: 5;
@@ -334,7 +334,7 @@ impl LedCntrl {
         pub led0_link_st_qualify, set_led0_link_st_qualify: 6;
         /// LED 0 Enable
         pub led0_en, set_led0_en: 7;
-        /// LED_1 Pin Function
+        /// LED 1 Pin Function
         pub from into LedFunc, led1_function, set_led1_function: 12, 8;
         /// /// LED 1 Mode Selection
         pub led1_mode, set_led1_mode: 13;
@@ -349,7 +349,7 @@ impl LedCntrl {
     }
 }
 
-// #[allow(dead_code)]
+// LED Polarity
 #[repr(u8)]
 pub enum LedPol {
     AutoSense = 0,
@@ -384,12 +384,12 @@ impl LedPolarity {
         u8;
         /// LED 1 Polarity
         pub from into LedPol, led1_polarity, set_led1_polarity: 3, 2;
-        /// LED_0 Polarity
+        /// LED 0 Polarity
         pub from into LedPol, led0_polarity, set_led0_polarity: 1, 0;
     }
 }
 
-/// LED Control Register
+/// SPI Header
 #[derive(Copy, Clone, PartialEq, Eq, Hash)]
 pub struct SpiHeader(pub u16);
 bitfield_bitrange! {struct SpiHeader(u16)}
@@ -400,8 +400,9 @@ impl SpiHeader {
         /// Mask Bit for TXF_ECC_ERR
         pub control, set_control : 15;
         pub full_duplex, set_full_duplex : 14;
+        /// Read or Write to register
         pub write, set_write : 13;
-        /// LED_0 Polarity
+        /// Registers ID/addr
         pub from into SpiRegisters, addr, set_addr: 11, 0;
     }
 }