178 files changed, 9129 insertions, 3316 deletions

diff --git a/.gitattributes b/.gitattributes
index a51376f0d..2850eb3b1 100644
--- a/.gitattributes
+++ b/.gitattributes
@@ -17,6 +17,13 @@
 
 .vscode/*.json linguist-language=JSON-with-Comments
 
+# Configure changelog files to use union merge strategy
+# This prevents merge conflicts by automatically combining changes from both branches
+CHANGELOG.md merge=union
+changelog.md merge=union
+CHANGELOG.txt merge=union
+changelog.txt merge=union
+
 *.raw    binary
 *.bin    binary
 *.png    binary
diff --git a/.github/ci/build-nightly.sh b/.github/ci/build-nightly.sh
index 95cb4100c..2d7c4db3f 100755
--- a/.github/ci/build-nightly.sh
+++ b/.github/ci/build-nightly.sh
@@ -7,6 +7,7 @@ set -euo pipefail
 export RUSTUP_HOME=/ci/cache/rustup
 export CARGO_HOME=/ci/cache/cargo
 export CARGO_TARGET_DIR=/ci/cache/target
+export PATH=$CARGO_HOME/bin:$PATH
 mv rust-toolchain-nightly.toml rust-toolchain.toml
 
 # needed for "dumb HTTP" transport support
@@ -22,6 +23,8 @@ fi
 hashtime restore /ci/cache/filetime.json || true
 hashtime save /ci/cache/filetime.json
 
+cargo install --git https://github.com/embassy-rs/cargo-embassy-devtool --locked --rev 280829ad163f1444999468a57d28fb7c412babbe
+
 ./ci-nightly.sh
 
 # Save lockfiles
diff --git a/.github/ci/build-xtensa.sh b/.github/ci/build-xtensa.sh
index 103575bc9..b6626639d 100755
--- a/.github/ci/build-xtensa.sh
+++ b/.github/ci/build-xtensa.sh
@@ -7,13 +7,14 @@ set -euo pipefail
 export RUSTUP_HOME=/ci/cache/rustup
 export CARGO_HOME=/ci/cache/cargo
 export CARGO_TARGET_DIR=/ci/cache/target
+export PATH=$CARGO_HOME/bin:$PATH
 
 # needed for "dumb HTTP" transport support
 # used when pointing stm32-metapac to a CI-built one.
 export CARGO_NET_GIT_FETCH_WITH_CLI=true
 
-cargo install espup
-/ci/cache/cargo/bin/espup install --toolchain-version 1.84.0.0
+cargo install espup --locked
+espup install --toolchain-version 1.88.0.0
 
 # Restore lockfiles
 if [ -f /ci/cache/lockfiles.tar ]; then
@@ -24,11 +25,7 @@ fi
 hashtime restore /ci/cache/filetime.json || true
 hashtime save /ci/cache/filetime.json
 
-mkdir .cargo
-cat > .cargo/config.toml<< EOF
-[unstable]
-build-std = ["alloc", "core"]
-EOF
+cargo install --git https://github.com/embassy-rs/cargo-embassy-devtool --locked --rev 280829ad163f1444999468a57d28fb7c412babbe
 
 ./ci-xtensa.sh
 
diff --git a/.github/ci/build.sh b/.github/ci/build.sh
index 68a7c0c34..59bcefed6 100755
--- a/.github/ci/build.sh
+++ b/.github/ci/build.sh
@@ -7,6 +7,7 @@ set -euo pipefail
 export RUSTUP_HOME=/ci/cache/rustup
 export CARGO_HOME=/ci/cache/cargo
 export CARGO_TARGET_DIR=/ci/cache/target
+export PATH=$CARGO_HOME/bin:$PATH
 if [ -f /ci/secrets/teleprobe-token.txt ]; then
     echo Got teleprobe token!
     export TELEPROBE_HOST=https://teleprobe.embassy.dev
@@ -27,6 +28,8 @@ fi
 hashtime restore /ci/cache/filetime.json || true
 hashtime save /ci/cache/filetime.json
 
+cargo install --git https://github.com/embassy-rs/cargo-embassy-devtool --locked --rev 280829ad163f1444999468a57d28fb7c412babbe
+
 ./ci.sh
 
 # Save lockfiles
diff --git a/.github/ci/doc.sh b/.github/ci/doc.sh
index ac96008d8..876c261a1 100755
--- a/.github/ci/doc.sh
+++ b/.github/ci/doc.sh
@@ -19,42 +19,42 @@ mv rust-toolchain-nightly.toml rust-toolchain.toml
 # which makes rustup very sad
 rustc --version > /dev/null
 
-docserver-builder -i ./embassy-boot -o webroot/crates/embassy-boot/git.zup
-docserver-builder -i ./embassy-boot-nrf -o webroot/crates/embassy-boot-nrf/git.zup
-docserver-builder -i ./embassy-boot-rp -o webroot/crates/embassy-boot-rp/git.zup
-docserver-builder -i ./embassy-boot-stm32 -o webroot/crates/embassy-boot-stm32/git.zup
-docserver-builder -i ./embassy-embedded-hal -o webroot/crates/embassy-embedded-hal/git.zup
-docserver-builder -i ./embassy-executor -o webroot/crates/embassy-executor/git.zup
-docserver-builder -i ./embassy-futures -o webroot/crates/embassy-futures/git.zup
-docserver-builder -i ./embassy-nrf -o webroot/crates/embassy-nrf/git.zup
-docserver-builder -i ./embassy-rp -o webroot/crates/embassy-rp/git.zup
-docserver-builder -i ./embassy-mspm0 -o webroot/crates/embassy-mspm0/git.zup
-docserver-builder -i ./embassy-nxp -o webroot/crates/embassy-nxp/git.zup
-docserver-builder -i ./embassy-sync -o webroot/crates/embassy-sync/git.zup
-docserver-builder -i ./cyw43 -o webroot/crates/cyw43/git.zup
-docserver-builder -i ./cyw43-pio -o webroot/crates/cyw43-pio/git.zup
-docserver-builder -i ./embassy-stm32-wpan -o webroot/crates/embassy-stm32-wpan/git.zup --output-static webroot/static
+docserver build -i ./embassy-boot -o webroot/crates/embassy-boot/git.zup
+docserver build -i ./embassy-boot-nrf -o webroot/crates/embassy-boot-nrf/git.zup
+docserver build -i ./embassy-boot-rp -o webroot/crates/embassy-boot-rp/git.zup
+docserver build -i ./embassy-boot-stm32 -o webroot/crates/embassy-boot-stm32/git.zup
+docserver build -i ./embassy-embedded-hal -o webroot/crates/embassy-embedded-hal/git.zup
+docserver build -i ./embassy-executor -o webroot/crates/embassy-executor/git.zup
+docserver build -i ./embassy-futures -o webroot/crates/embassy-futures/git.zup
+docserver build -i ./embassy-nrf -o webroot/crates/embassy-nrf/git.zup
+docserver build -i ./embassy-rp -o webroot/crates/embassy-rp/git.zup
+docserver build -i ./embassy-mspm0 -o webroot/crates/embassy-mspm0/git.zup
+docserver build -i ./embassy-nxp -o webroot/crates/embassy-nxp/git.zup
+docserver build -i ./embassy-sync -o webroot/crates/embassy-sync/git.zup
+docserver build -i ./cyw43 -o webroot/crates/cyw43/git.zup
+docserver build -i ./cyw43-pio -o webroot/crates/cyw43-pio/git.zup
+docserver build -i ./embassy-stm32-wpan -o webroot/crates/embassy-stm32-wpan/git.zup --output-static webroot/static
 
-docserver-builder -i ./embassy-time -o webroot/crates/embassy-time/git.zup
-docserver-builder -i ./embassy-time-driver -o webroot/crates/embassy-time-driver/git.zup
-docserver-builder -i ./embassy-time-queue-utils -o webroot/crates/embassy-time-queue-utils/git.zup
+docserver build -i ./embassy-time -o webroot/crates/embassy-time/git.zup
+docserver build -i ./embassy-time-driver -o webroot/crates/embassy-time-driver/git.zup
+docserver build -i ./embassy-time-queue-utils -o webroot/crates/embassy-time-queue-utils/git.zup
 
-docserver-builder -i ./embassy-usb -o webroot/crates/embassy-usb/git.zup
-docserver-builder -i ./embassy-usb-dfu -o webroot/crates/embassy-usb-dfu/git.zup
-docserver-builder -i ./embassy-usb-driver -o webroot/crates/embassy-usb-driver/git.zup
-docserver-builder -i ./embassy-usb-logger -o webroot/crates/embassy-usb-logger/git.zup
-docserver-builder -i ./embassy-usb-synopsys-otg -o webroot/crates/embassy-usb-synopsys-otg/git.zup
+docserver build -i ./embassy-usb -o webroot/crates/embassy-usb/git.zup
+docserver build -i ./embassy-usb-dfu -o webroot/crates/embassy-usb-dfu/git.zup
+docserver build -i ./embassy-usb-driver -o webroot/crates/embassy-usb-driver/git.zup
+docserver build -i ./embassy-usb-logger -o webroot/crates/embassy-usb-logger/git.zup
+docserver build -i ./embassy-usb-synopsys-otg -o webroot/crates/embassy-usb-synopsys-otg/git.zup
 
-docserver-builder -i ./embassy-net -o webroot/crates/embassy-net/git.zup
-docserver-builder -i ./embassy-net-nrf91 -o webroot/crates/embassy-net-nrf91/git.zup
-docserver-builder -i ./embassy-net-driver -o webroot/crates/embassy-net-driver/git.zup
-docserver-builder -i ./embassy-net-driver-channel -o webroot/crates/embassy-net-driver-channel/git.zup
-docserver-builder -i ./embassy-net-wiznet -o webroot/crates/embassy-net-wiznet/git.zup
-docserver-builder -i ./embassy-net-ppp -o webroot/crates/embassy-net-ppp/git.zup
-docserver-builder -i ./embassy-net-tuntap -o webroot/crates/embassy-net-tuntap/git.zup
-docserver-builder -i ./embassy-net-enc28j60 -o webroot/crates/embassy-net-enc28j60/git.zup
-docserver-builder -i ./embassy-net-esp-hosted -o webroot/crates/embassy-net-esp-hosted/git.zup
-docserver-builder -i ./embassy-net-adin1110 -o webroot/crates/embassy-net-adin1110/git.zup
+docserver build -i ./embassy-net -o webroot/crates/embassy-net/git.zup
+docserver build -i ./embassy-net-nrf91 -o webroot/crates/embassy-net-nrf91/git.zup
+docserver build -i ./embassy-net-driver -o webroot/crates/embassy-net-driver/git.zup
+docserver build -i ./embassy-net-driver-channel -o webroot/crates/embassy-net-driver-channel/git.zup
+docserver build -i ./embassy-net-wiznet -o webroot/crates/embassy-net-wiznet/git.zup
+docserver build -i ./embassy-net-ppp -o webroot/crates/embassy-net-ppp/git.zup
+docserver build -i ./embassy-net-tuntap -o webroot/crates/embassy-net-tuntap/git.zup
+docserver build -i ./embassy-net-enc28j60 -o webroot/crates/embassy-net-enc28j60/git.zup
+docserver build -i ./embassy-net-esp-hosted -o webroot/crates/embassy-net-esp-hosted/git.zup
+docserver build -i ./embassy-net-adin1110 -o webroot/crates/embassy-net-adin1110/git.zup
 
 export KUBECONFIG=/ci/secrets/kubeconfig.yml
 POD=$(kubectl -n embassy get po -l app=docserver -o jsonpath={.items[0].metadata.name})
@@ -65,6 +65,6 @@ kubectl cp webroot/static $POD:/data
 # so that it doesn't prevent other crates from getting docs updates when it breaks.
 
 rm -rf webroot
-docserver-builder -i ./embassy-stm32 -o webroot/crates/embassy-stm32/git.zup
+docserver build -i ./embassy-stm32 -o webroot/crates/embassy-stm32/git.zup
 POD=$(kubectl -n embassy get po -l app=docserver -o jsonpath={.items[0].metadata.name})
 kubectl cp webroot/crates $POD:/data
diff --git a/.vscode/settings.json b/.vscode/settings.json
index 6edd9312a..c504f3ccd 100644
--- a/.vscode/settings.json
+++ b/.vscode/settings.json
@@ -17,7 +17,7 @@
   //"rust-analyzer.cargo.target": "thumbv8m.main-none-eabihf",
   "rust-analyzer.cargo.features": [
     // Comment out these features when working on the examples. Most example crates do not have any cargo features.
-    "stm32f446re",
+    "stm32f107rb",
     "time-driver-any",
     "unstable-pac",
     "exti",
diff --git a/ci-nightly.sh b/ci-nightly.sh
index d486d442c..afe9f534c 100755
--- a/ci-nightly.sh
+++ b/ci-nightly.sh
@@ -8,19 +8,4 @@ if [[ -z "${CARGO_TARGET_DIR}" ]]; then
     export CARGO_TARGET_DIR=target_ci
 fi
 
-cargo batch  \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features nightly \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features nightly,log \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features nightly,defmt \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv6m-none-eabi --features nightly,defmt \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv6m-none-eabi --features nightly,defmt,arch-cortex-m,executor-thread,executor-interrupt \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features nightly,arch-cortex-m \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features nightly,arch-cortex-m,executor-thread \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features nightly,arch-cortex-m,executor-interrupt \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features nightly,arch-cortex-m,executor-thread,executor-interrupt \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target riscv32imac-unknown-none-elf --features nightly,arch-riscv32 \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target riscv32imac-unknown-none-elf --features nightly,arch-riscv32,executor-thread \
-    --- build --release --manifest-path examples/nrf52840-rtic/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/nrf52840-rtic \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target armv7a-none-eabi --features nightly,arch-cortex-ar,executor-thread \
-
-RUSTFLAGS="$RUSTFLAGS -C target-cpu=atmega328p" cargo build --release --manifest-path embassy-executor/Cargo.toml --target avr-none -Z build-std=core,alloc --features nightly,arch-avr,avr-device/atmega328p
+cargo embassy-devtool build --group nightly
diff --git a/ci-xtensa.sh b/ci-xtensa.sh
index 6c9807e98..0dd41a9ce 100755
--- a/ci-xtensa.sh
+++ b/ci-xtensa.sh
@@ -9,30 +9,4 @@ if [[ -z "${CARGO_TARGET_DIR}" ]]; then
     export CARGO_TARGET_DIR=target_ci
 fi
 
-cargo batch \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target xtensa-esp32-none-elf \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target xtensa-esp32-none-elf --features log \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target xtensa-esp32-none-elf --features defmt \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target xtensa-esp32s2-none-elf --features defmt \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target xtensa-esp32-none-elf --features defmt,arch-spin,executor-thread \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target xtensa-esp32s2-none-elf --features defmt,arch-spin,executor-thread \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target xtensa-esp32s3-none-elf --features defmt,arch-spin,executor-thread \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target xtensa-esp32-none-elf --features arch-spin \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target xtensa-esp32-none-elf --features arch-spin,rtos-trace \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target xtensa-esp32-none-elf --features arch-spin,executor-thread \
-    --- build --release --manifest-path embassy-sync/Cargo.toml --target xtensa-esp32s2-none-elf --features defmt \
-    --- build --release --manifest-path embassy-time/Cargo.toml --target xtensa-esp32s2-none-elf --features defmt,defmt-timestamp-uptime,mock-driver \
-    --- build --release --manifest-path embassy-time-queue-utils/Cargo.toml --target xtensa-esp32s2-none-elf \
-    --- build --release --manifest-path embassy-time-queue-utils/Cargo.toml --target xtensa-esp32s2-none-elf --features generic-queue-8 \
-    --- build --release --manifest-path embassy-net/Cargo.toml --target xtensa-esp32-none-elf --features defmt,tcp,udp,dns,proto-ipv4,medium-ethernet,packet-trace \
-    --- build --release --manifest-path embassy-net/Cargo.toml --target xtensa-esp32-none-elf --features defmt,tcp,udp,dns,proto-ipv4,multicast,medium-ethernet \
-    --- build --release --manifest-path embassy-net/Cargo.toml --target xtensa-esp32-none-elf --features defmt,tcp,udp,dns,dhcpv4,medium-ethernet \
-    --- build --release --manifest-path embassy-net/Cargo.toml --target xtensa-esp32-none-elf --features defmt,tcp,udp,dns,dhcpv4,medium-ethernet,dhcpv4-hostname \
-    --- build --release --manifest-path embassy-net/Cargo.toml --target xtensa-esp32-none-elf --features defmt,tcp,udp,dns,proto-ipv6,medium-ethernet \
-    --- build --release --manifest-path embassy-net/Cargo.toml --target xtensa-esp32-none-elf --features defmt,tcp,udp,dns,proto-ipv6,medium-ieee802154 \
-    --- build --release --manifest-path embassy-net/Cargo.toml --target xtensa-esp32-none-elf --features defmt,tcp,udp,dns,proto-ipv6,medium-ethernet,medium-ieee802154 \
-    --- build --release --manifest-path embassy-net/Cargo.toml --target xtensa-esp32-none-elf --features defmt,tcp,udp,dns,proto-ipv6,medium-ethernet \
-    --- build --release --manifest-path embassy-net/Cargo.toml --target xtensa-esp32-none-elf --features defmt,tcp,udp,dns,proto-ipv4,proto-ipv6,medium-ethernet \
-    --- build --release --manifest-path embassy-net/Cargo.toml --target xtensa-esp32-none-elf --features defmt,tcp,udp,dns,proto-ipv4,proto-ipv6,medium-ip \
-    --- build --release --manifest-path embassy-net/Cargo.toml --target xtensa-esp32-none-elf --features defmt,tcp,udp,dns,proto-ipv4,proto-ipv6,medium-ip,medium-ethernet \
-    --- build --release --manifest-path embassy-net/Cargo.toml --target xtensa-esp32-none-elf --features defmt,tcp,udp,dns,proto-ipv4,proto-ipv6,medium-ip,medium-ethernet,medium-ieee802154 \
+cargo embassy-devtool build --group xtensa
diff --git a/ci.sh b/ci.sh
index a585a3ab8..6cc2a031d 100755
--- a/ci.sh
+++ b/ci.sh
@@ -10,352 +10,21 @@ if ! command -v cargo-batch &> /dev/null; then
     exit 1
 fi
 
+if ! command -v cargo-embassy-devtool &> /dev/null; then
+    echo "cargo-embassy-devtool could not be found. Install it with the following command:"
+    echo ""
+    echo "    cargo install --git https://github.com/embassy-rs/cargo-embassy-devtool --locked"
+    echo ""
+    exit 1
+fi
+
 export RUSTFLAGS=-Dwarnings
 export DEFMT_LOG=trace,embassy_hal_internal=debug,embassy_net_esp_hosted=debug,cyw43=info,cyw43_pio=info,smoltcp=info
 if [[ -z "${CARGO_TARGET_DIR}" ]]; then
     export CARGO_TARGET_DIR=target_ci
 fi
 
-TARGET=$(rustc -vV | sed -n 's|host: ||p')
-
-BUILD_EXTRA=""
-if [ $TARGET = "x86_64-unknown-linux-gnu" ] || [ $TARGET = "aarch64-unknown-linux-gnu" ]; then
-    BUILD_EXTRA="--- build --release --manifest-path examples/std/Cargo.toml --target $TARGET --artifact-dir out/examples/std"
-fi
-
-# CI intentionally does not use -eabihf on thumbv7em to minimize dep compile time.
-cargo batch \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features log \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features defmt \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv6m-none-eabi --features defmt \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv6m-none-eabi --features defmt,arch-cortex-m,executor-thread,executor-interrupt \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features arch-cortex-m \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features arch-cortex-m,metadata-name \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features arch-cortex-m,trace \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features arch-cortex-m,rtos-trace \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features arch-cortex-m,trace,rtos-trace \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features arch-cortex-m,executor-thread \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features arch-cortex-m,executor-interrupt \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features arch-cortex-m,executor-thread,executor-interrupt \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target armv7a-none-eabi --features arch-cortex-ar,executor-thread \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target armv7r-none-eabi --features arch-cortex-ar,executor-thread \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target armv7r-none-eabihf --features arch-cortex-ar,executor-thread \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target riscv32imac-unknown-none-elf --features arch-riscv32 \
-    --- build --release --manifest-path embassy-executor/Cargo.toml --target riscv32imac-unknown-none-elf --features arch-riscv32,executor-thread \
-    --- build --release --manifest-path embassy-embedded-hal/Cargo.toml --target thumbv7em-none-eabi \
-    --- build --release --manifest-path embassy-embedded-hal/Cargo.toml --target thumbv7em-none-eabi --features time \
-    --- build --release --manifest-path embassy-sync/Cargo.toml --target thumbv6m-none-eabi --features defmt \
-    --- build --release --manifest-path embassy-time/Cargo.toml --target thumbv6m-none-eabi --features defmt,defmt-timestamp-uptime,mock-driver \
-    --- build --release --manifest-path embassy-time/Cargo.toml --features defmt,std \
-    --- build --release --manifest-path embassy-time-queue-utils/Cargo.toml --target thumbv6m-none-eabi \
-    --- build --release --manifest-path embassy-time-queue-utils/Cargo.toml --target thumbv6m-none-eabi --features generic-queue-8 \
-    --- build --release --manifest-path embassy-net/Cargo.toml --target thumbv7em-none-eabi --features defmt,tcp,udp,dns,proto-ipv4,medium-ethernet,packet-trace \
-    --- build --release --manifest-path embassy-net/Cargo.toml --target thumbv7em-none-eabi --features defmt,tcp,udp,dns,proto-ipv4,multicast,medium-ethernet \
-    --- build --release --manifest-path embassy-net/Cargo.toml --target thumbv7em-none-eabi --features defmt,tcp,udp,dns,dhcpv4,medium-ethernet \
-    --- build --release --manifest-path embassy-net/Cargo.toml --target thumbv7em-none-eabi --features defmt,tcp,udp,dns,dhcpv4,medium-ethernet,dhcpv4-hostname \
-    --- build --release --manifest-path embassy-net/Cargo.toml --target thumbv7em-none-eabi --features defmt,tcp,udp,dns,proto-ipv6,medium-ethernet \
-    --- build --release --manifest-path embassy-net/Cargo.toml --target thumbv7em-none-eabi --features defmt,tcp,udp,dns,proto-ipv6,medium-ieee802154 \
-    --- build --release --manifest-path embassy-net/Cargo.toml --target thumbv7em-none-eabi --features defmt,tcp,udp,dns,proto-ipv6,medium-ethernet,medium-ieee802154 \
-    --- build --release --manifest-path embassy-net/Cargo.toml --target thumbv7em-none-eabi --features defmt,tcp,udp,dns,proto-ipv6,medium-ethernet \
-    --- build --release --manifest-path embassy-net/Cargo.toml --target thumbv7em-none-eabi --features defmt,tcp,udp,dns,proto-ipv4,proto-ipv6,medium-ethernet \
-    --- build --release --manifest-path embassy-net/Cargo.toml --target thumbv7em-none-eabi --features defmt,tcp,udp,dns,proto-ipv4,proto-ipv6,medium-ip \
-    --- build --release --manifest-path embassy-net/Cargo.toml --target thumbv7em-none-eabi --features defmt,tcp,udp,dns,proto-ipv4,proto-ipv6,medium-ip,medium-ethernet \
-    --- build --release --manifest-path embassy-net/Cargo.toml --target thumbv7em-none-eabi --features defmt,tcp,udp,dns,proto-ipv4,proto-ipv6,medium-ip,medium-ethernet,medium-ieee802154 \
-    --- build --release --manifest-path embassy-imxrt/Cargo.toml --target thumbv8m.main-none-eabihf --features mimxrt633s,defmt,unstable-pac,time,time-driver-rtc \
-    --- build --release --manifest-path embassy-imxrt/Cargo.toml --target thumbv8m.main-none-eabihf --features mimxrt685s,defmt,unstable-pac,time,time-driver-rtc \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv6m-none-eabi --features nrf51,gpiote,time,time-driver-rtc1 \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52805,gpiote,time,time-driver-rtc1 \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52810,gpiote,time,time-driver-rtc1 \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52811,gpiote,time,time-driver-rtc1 \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52820,gpiote,time,time-driver-rtc1 \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52832,gpiote,time,time-driver-rtc1,reset-pin-as-gpio \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52833,gpiote,time,time-driver-rtc1,nfc-pins-as-gpio \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features nrf9160-s,gpiote,time,time-driver-rtc1 \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features nrf9160-ns,gpiote,time,time-driver-rtc1 \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features nrf5340-app-s,gpiote,time,time-driver-rtc1 \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features nrf5340-app-ns,gpiote,time,time-driver-rtc1 \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features nrf5340-net,gpiote,time,time-driver-rtc1 \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features nrf54l15-app-s,gpiote,time,time-driver-rtc1 \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features nrf54l15-app-ns,gpiote,time,time-driver-rtc1 \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52840,gpiote,time \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52840,gpiote,time-driver-rtc1 \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52840,gpiote,time,time-driver-rtc1 \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52840,gpiote,log,time \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52840,gpiote,log,time-driver-rtc1 \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52840,gpiote,log,time,time-driver-rtc1 \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52840,gpiote,defmt,time \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52840,gpiote,defmt,time-driver-rtc1 \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52840,gpiote,defmt,time,time-driver-rtc1 \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv6m-none-eabi --features nrf51,defmt,time,time-driver-rtc1 \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv6m-none-eabi --features nrf51,defmt,time \
-    --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv6m-none-eabi --features nrf51,time \
-    --- build --release --manifest-path embassy-rp/Cargo.toml --target thumbv6m-none-eabi --features time-driver,defmt,rp2040 \
-    --- build --release --manifest-path embassy-rp/Cargo.toml --target thumbv6m-none-eabi --features time-driver,log,rp2040 \
-    --- build --release --manifest-path embassy-rp/Cargo.toml --target thumbv6m-none-eabi --features time-driver,intrinsics,rp2040 \
-    --- build --release --manifest-path embassy-rp/Cargo.toml --target thumbv6m-none-eabi --features time-driver,qspi-as-gpio,rp2040 \
-    --- build --release --manifest-path embassy-rp/Cargo.toml --target thumbv8m.main-none-eabihf --features time-driver,defmt,rp235xa \
-    --- build --release --manifest-path embassy-rp/Cargo.toml --target thumbv8m.main-none-eabihf --features time-driver,log,rp235xa \
-    --- build --release --manifest-path embassy-rp/Cargo.toml --target thumbv8m.main-none-eabihf --features time-driver,rp235xa,binary-info \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,dual-bank,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,dual-bank,defmt,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,dual-bank,defmt,exti,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,dual-bank,defmt,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,dual-bank,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,dual-bank,defmt,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,dual-bank,defmt,exti,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,dual-bank,defmt,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,dual-bank,defmt,exti \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,dual-bank,defmt \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,single-bank,defmt \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32c071rb,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32c051f6,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32c091gb,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32c092rc,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32f038f6,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32f030c6,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32f058t8,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32f030r8,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32f031k6,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32f030rc,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32f070f6,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32f078vb,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32f042g4,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32f072c8,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f401ve,defmt,exti,time-driver-any \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f405zg,defmt,exti,time-driver-any \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f407zg,defmt,exti,time-driver-any \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f401ve,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f405zg,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f407zg,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f410tb,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f411ce,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f412zg,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f413vh,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f415zg,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f417zg,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f423zh,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f427zi,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f429zi,log,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f437zi,log,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f439zi,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f446ze,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f469zi,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f479zi,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f730i8,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h753zi,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h735zg,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h755zi-cm7,defmt,exti,time-driver-any,time,split-pc2,split-pc3 \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h725re,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h7b3ai,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h7b3ai,defmt,exti,time-driver-tim1,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h7r3z8,defmt,exti,time-driver-tim1,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h7r7a8,defmt,exti,time-driver-tim1,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h7s3a8,defmt,exti,time-driver-tim1,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h7s7z8,defmt,exti,time-driver-tim1,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32l431cb,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32l476vg,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32l422cb,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32wb15cc,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32l072cz,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32l041f6,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32l051k8,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32l073cz,defmt,exti,time-driver-any,low-power,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32l151cb-a,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f303c8,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f398ve,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f378cc,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32g0b0ce,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32g0c1ve,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32f217zg,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,dual-bank,defmt,exti,time-driver-any,low-power,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32wl54jc-cm0p,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32wle5jb,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32g431kb,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32g474pe,dual-bank,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32f107vc,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32f103re,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32f100c4,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32h503rb,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32h523cc,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32h562ag,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32wba50ke,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32wba55ug,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32wba62cg,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32wba65ri,defmt,exti,time-driver-any,low-power,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32u5f9zj,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32u5g9nj,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32wb35ce,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32wb55rg,defmt,exti,time-driver-any,low-power,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32u031r8,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32u073mb,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32u083rc,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-nxp/Cargo.toml --target thumbv8m.main-none-eabihf --features lpc55,defmt \
-    --- build --release --manifest-path embassy-nxp/Cargo.toml --target thumbv7em-none-eabihf --features mimxrt1011,rt,defmt,time-driver-pit \
-    --- build --release --manifest-path embassy-nxp/Cargo.toml --target thumbv7em-none-eabihf --features mimxrt1062,rt,defmt,time-driver-pit \
-    --- build --release --manifest-path embassy-mspm0/Cargo.toml --target thumbv6m-none-eabi --features mspm0c1104dgs20,defmt,time-driver-any \
-    --- build --release --manifest-path embassy-mspm0/Cargo.toml --target thumbv6m-none-eabi --features mspm0g3507pm,defmt,time-driver-any \
-    --- build --release --manifest-path embassy-mspm0/Cargo.toml --target thumbv6m-none-eabi --features mspm0g3519pz,defmt,time-driver-any \
-    --- build --release --manifest-path embassy-mspm0/Cargo.toml --target thumbv6m-none-eabi --features mspm0l1306rhb,defmt,time-driver-any \
-    --- build --release --manifest-path embassy-mspm0/Cargo.toml --target thumbv6m-none-eabi --features mspm0l2228pn,defmt,time-driver-any \
-    --- build --release --manifest-path embassy-mspm0/Cargo.toml --target thumbv6m-none-eabi --features mspm0l1345dgs28,defmt,time-driver-any \
-    --- build --release --manifest-path embassy-mspm0/Cargo.toml --target thumbv6m-none-eabi --features mspm0l1106dgs28,defmt,time-driver-any \
-    --- build --release --manifest-path embassy-mspm0/Cargo.toml --target thumbv6m-none-eabi --features mspm0l1228pm,defmt,time-driver-any \
-    --- build --release --manifest-path embassy-mspm0/Cargo.toml --target thumbv6m-none-eabi --features mspm0g1107ycj,defmt,time-driver-any \
-    --- build --release --manifest-path embassy-mspm0/Cargo.toml --target thumbv6m-none-eabi --features mspm0g3105rhb,defmt,time-driver-any \
-    --- build --release --manifest-path embassy-mspm0/Cargo.toml --target thumbv6m-none-eabi --features mspm0g1505pt,defmt,time-driver-any \
-    --- build --release --manifest-path embassy-mspm0/Cargo.toml --target thumbv6m-none-eabi --features mspm0g1519rhb,defmt,time-driver-any \
-    --- build --release --manifest-path cyw43/Cargo.toml --target thumbv6m-none-eabi --features ''\
-    --- build --release --manifest-path cyw43/Cargo.toml --target thumbv6m-none-eabi --features 'log' \
-    --- build --release --manifest-path cyw43/Cargo.toml --target thumbv6m-none-eabi --features 'defmt' \
-    --- build --release --manifest-path cyw43/Cargo.toml --target thumbv6m-none-eabi --features 'log,firmware-logs' \
-    --- build --release --manifest-path cyw43/Cargo.toml --target thumbv6m-none-eabi --features 'defmt,firmware-logs' \
-    --- build --release --manifest-path cyw43/Cargo.toml --target thumbv6m-none-eabi --features 'log,firmware-logs,bluetooth' \
-    --- build --release --manifest-path cyw43/Cargo.toml --target thumbv6m-none-eabi --features 'defmt,firmware-logs,bluetooth' \
-    --- build --release --manifest-path cyw43-pio/Cargo.toml --target thumbv6m-none-eabi --features 'embassy-rp/rp2040' \
-    --- build --release --manifest-path cyw43-pio/Cargo.toml --target thumbv6m-none-eabi --features 'embassy-rp/rp2040' \
-    --- build --release --manifest-path embassy-boot-nrf/Cargo.toml --target thumbv7em-none-eabi --features embassy-nrf/nrf52840 \
-    --- build --release --manifest-path embassy-boot-nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features embassy-nrf/nrf5340-app-s \
-    --- build --release --manifest-path embassy-boot-nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features embassy-nrf/nrf9160-ns \
-    --- build --release --manifest-path embassy-boot-nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features embassy-nrf/nrf9120-ns \
-    --- build --release --manifest-path embassy-boot-nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features embassy-nrf/nrf9151-ns \
-    --- build --release --manifest-path embassy-boot-nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features embassy-nrf/nrf9161-ns \
-    --- build --release --manifest-path embassy-boot-rp/Cargo.toml --target thumbv6m-none-eabi --features embassy-rp/rp2040 \
-    --- build --release --manifest-path embassy-boot-stm32/Cargo.toml --target thumbv7em-none-eabi --features embassy-stm32/stm32l496zg \
-    --- build --release --manifest-path embassy-usb/Cargo.toml --target thumbv6m-none-eabi --no-default-features \
-    --- build --release --manifest-path embassy-usb/Cargo.toml --target thumbv6m-none-eabi \
-    --- build --release --manifest-path embassy-usb/Cargo.toml --target thumbv6m-none-eabi --features log \
-    --- build --release --manifest-path embassy-usb/Cargo.toml --target thumbv6m-none-eabi --features defmt \
-    --- build --release --manifest-path embassy-usb/Cargo.toml --target thumbv6m-none-eabi --features usbd-hid \
-    --- build --release --manifest-path embassy-usb/Cargo.toml --target thumbv6m-none-eabi --features max-interface-count-1 \
-    --- build --release --manifest-path embassy-usb/Cargo.toml --target thumbv6m-none-eabi --features max-interface-count-8 \
-    --- build --release --manifest-path embassy-usb/Cargo.toml --target thumbv6m-none-eabi --features max-handler-count-8 \
-    --- build --release --manifest-path embassy-usb/Cargo.toml --target thumbv6m-none-eabi --features max-handler-count-8 \
-    --- build --release --manifest-path docs/examples/basic/Cargo.toml --target thumbv7em-none-eabi \
-    --- build --release --manifest-path docs/examples/layer-by-layer/blinky-pac/Cargo.toml --target thumbv7em-none-eabi \
-    --- build --release --manifest-path docs/examples/layer-by-layer/blinky-hal/Cargo.toml --target thumbv7em-none-eabi \
-    --- build --release --manifest-path docs/examples/layer-by-layer/blinky-irq/Cargo.toml --target thumbv7em-none-eabi \
-    --- build --release --manifest-path docs/examples/layer-by-layer/blinky-async/Cargo.toml --target thumbv7em-none-eabi \
-    --- build --release --manifest-path examples/nrf52810/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/nrf52810 \
-    --- build --release --manifest-path examples/nrf52840/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/nrf52840 \
-    --- build --release --manifest-path examples/nrf5340/Cargo.toml --target thumbv8m.main-none-eabihf --artifact-dir out/examples/nrf5340 \
-    --- build --release --manifest-path examples/nrf54l15/Cargo.toml --target thumbv8m.main-none-eabihf --artifact-dir out/examples/nrf54l15 \
-    --- build --release --manifest-path examples/nrf9160/Cargo.toml --target thumbv8m.main-none-eabihf --artifact-dir out/examples/nrf9160 \
-    --- build --release --manifest-path examples/nrf9151/s/Cargo.toml --target thumbv8m.main-none-eabihf --artifact-dir out/examples/nrf9151/s \
-    --- build --release --manifest-path examples/nrf9151/ns/Cargo.toml --target thumbv8m.main-none-eabihf --artifact-dir out/examples/nrf9151/ns \
-    --- build --release --manifest-path examples/nrf51/Cargo.toml --target thumbv6m-none-eabi --artifact-dir out/examples/nrf51 \
-    --- build --release --manifest-path examples/rp/Cargo.toml --target thumbv6m-none-eabi --artifact-dir out/examples/rp \
-    --- build --release --manifest-path examples/rp235x/Cargo.toml --target thumbv8m.main-none-eabihf --artifact-dir out/examples/rp235x \
-    --- build --release --manifest-path examples/stm32f0/Cargo.toml --target thumbv6m-none-eabi --artifact-dir out/examples/stm32f0 \
-    --- build --release --manifest-path examples/stm32f1/Cargo.toml --target thumbv7m-none-eabi --artifact-dir out/examples/stm32f1 \
-    --- build --release --manifest-path examples/stm32f2/Cargo.toml --target thumbv7m-none-eabi --artifact-dir out/examples/stm32f2 \
-    --- build --release --manifest-path examples/stm32f3/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/stm32f3 \
-    --- build --release --manifest-path examples/stm32f334/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/stm32f334 \
-    --- build --release --manifest-path examples/stm32f4/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/stm32f4 \
-    --- build --release --manifest-path examples/stm32f469/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/stm32f469 \
-    --- build --release --manifest-path examples/stm32f7/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/stm32f7 \
-    --- build --release --manifest-path examples/stm32c0/Cargo.toml --target thumbv6m-none-eabi --artifact-dir out/examples/stm32c0 \
-    --- build --release --manifest-path examples/stm32g0/Cargo.toml --target thumbv6m-none-eabi --artifact-dir out/examples/stm32g0 \
-    --- build --release --manifest-path examples/stm32g4/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/stm32g4 \
-    --- build --release --manifest-path examples/stm32h5/Cargo.toml --target thumbv8m.main-none-eabihf --artifact-dir out/examples/stm32h5 \
-    --- build --release --manifest-path examples/stm32h7/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/stm32h7 \
-    --- build --release --manifest-path examples/stm32h7b0/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/stm32h7b0 \
-    --- build --release --manifest-path examples/stm32h723/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/stm32h723 \
-    --- build --release --manifest-path examples/stm32h735/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/stm32h735 \
-    --- build --release --manifest-path examples/stm32h755cm4/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/stm32h755cm4 \
-    --- build --release --manifest-path examples/stm32h755cm7/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/stm32h755cm7 \
-    --- build --release --manifest-path examples/stm32h7rs/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/stm32h7rs \
-    --- build --release --manifest-path examples/stm32l0/Cargo.toml --target thumbv6m-none-eabi --artifact-dir out/examples/stm32l0 \
-    --- build --release --manifest-path examples/stm32l1/Cargo.toml --target thumbv7m-none-eabi --artifact-dir out/examples/stm32l1 \
-    --- build --release --manifest-path examples/stm32l4/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/stm32l4 \
-    --- build --release --manifest-path examples/stm32l432/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/stm32l432 \
-    --- build --release --manifest-path examples/stm32l5/Cargo.toml --target thumbv8m.main-none-eabihf --artifact-dir out/examples/stm32l5 \
-    --- build --release --manifest-path examples/stm32u0/Cargo.toml --target thumbv6m-none-eabi --artifact-dir out/examples/stm32u0 \
-    --- build --release --manifest-path examples/stm32u5/Cargo.toml --target thumbv8m.main-none-eabihf --artifact-dir out/examples/stm32u5 \
-    --- build --release --manifest-path examples/stm32wb/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/stm32wb \
-    --- build --release --manifest-path examples/stm32wba/Cargo.toml --target thumbv8m.main-none-eabihf --artifact-dir out/examples/stm32wba \
-    --- build --release --manifest-path examples/stm32wba6/Cargo.toml --target thumbv8m.main-none-eabihf --artifact-dir out/examples/stm32wba6 \
-    --- build --release --manifest-path examples/stm32wl/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/stm32wl \
-    --- build --release --manifest-path examples/lpc55s69/Cargo.toml --target thumbv8m.main-none-eabihf --artifact-dir out/examples/lpc55s69 \
-    --- build --release --manifest-path examples/mimxrt1011/Cargo.toml --target thumbv7em-none-eabihf --artifact-dir out/examples/mimxrt1011 \
-    --- build --release --manifest-path examples/mimxrt1062-evk/Cargo.toml --target thumbv7em-none-eabihf --artifact-dir out/examples/mimxrt1062-evk \
-    --- build --release --manifest-path examples/mspm0g3507/Cargo.toml --target thumbv6m-none-eabi --artifact-dir out/examples/mspm0g3507 \
-    --- build --release --manifest-path examples/mspm0g3519/Cargo.toml --target thumbv6m-none-eabi --artifact-dir out/examples/mspm0g3519 \
-    --- build --release --manifest-path examples/mspm0l1306/Cargo.toml --target thumbv6m-none-eabi --artifact-dir out/examples/mspm0l1306 \
-    --- build --release --manifest-path examples/mspm0l2228/Cargo.toml --target thumbv6m-none-eabi --artifact-dir out/examples/mspm0l2228 \
-    --- build --release --manifest-path examples/boot/application/nrf/Cargo.toml --target thumbv7em-none-eabi --features embassy-nrf/nrf52840,skip-include --artifact-dir out/examples/boot/nrf52840 \
-    --- build --release --manifest-path examples/boot/application/nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features embassy-nrf/nrf9160-ns,skip-include --artifact-dir out/examples/boot/nrf9160 \
-    --- build --release --manifest-path examples/boot/application/nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features embassy-nrf/nrf9120-ns,skip-include --artifact-dir out/examples/boot/nrf9120 \
-    --- build --release --manifest-path examples/boot/application/nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features embassy-nrf/nrf9151-ns,skip-include --artifact-dir out/examples/boot/nrf9151 \
-    --- build --release --manifest-path examples/boot/application/nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features embassy-nrf/nrf9161-ns,skip-include --artifact-dir out/examples/boot/nrf9161 \
-    --- build --release --manifest-path examples/boot/application/rp/Cargo.toml --target thumbv6m-none-eabi --features skip-include --artifact-dir out/examples/boot/rp \
-    --- build --release --manifest-path examples/boot/application/stm32f3/Cargo.toml --target thumbv7em-none-eabi --features skip-include --artifact-dir out/examples/boot/stm32f3 \
-    --- build --release --manifest-path examples/boot/application/stm32f7/Cargo.toml --target thumbv7em-none-eabi --features skip-include --artifact-dir out/examples/boot/stm32f7 \
-    --- build --release --manifest-path examples/boot/application/stm32h7/Cargo.toml --target thumbv7em-none-eabi --features skip-include --artifact-dir out/examples/boot/stm32h7 \
-    --- build --release --manifest-path examples/boot/application/stm32l0/Cargo.toml --target thumbv6m-none-eabi --features skip-include --artifact-dir out/examples/boot/stm32l0 \
-    --- build --release --manifest-path examples/boot/application/stm32l1/Cargo.toml --target thumbv7m-none-eabi --features skip-include --artifact-dir out/examples/boot/stm32l1 \
-    --- build --release --manifest-path examples/boot/application/stm32l4/Cargo.toml --target thumbv7em-none-eabi --features skip-include --artifact-dir out/examples/boot/stm32l4 \
-    --- build --release --manifest-path examples/boot/application/stm32wl/Cargo.toml --target thumbv7em-none-eabi --features skip-include --artifact-dir out/examples/boot/stm32wl \
-    --- build --release --manifest-path examples/boot/application/stm32wb-dfu/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/boot/stm32wb-dfu \
-    --- build --release --manifest-path examples/boot/application/stm32wba-dfu/Cargo.toml --target thumbv8m.main-none-eabihf --artifact-dir out/examples/boot/stm32wba-dfu \
-    --- build --release --manifest-path examples/boot/bootloader/nrf/Cargo.toml --target thumbv7em-none-eabi --features embassy-nrf/nrf52840 \
-    --- build --release --manifest-path examples/boot/bootloader/nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features embassy-nrf/nrf9160-ns \
-    --- build --release --manifest-path examples/boot/bootloader/nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features embassy-nrf/nrf9120-ns \
-    --- build --release --manifest-path examples/boot/bootloader/nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features embassy-nrf/nrf9151-ns \
-    --- build --release --manifest-path examples/boot/bootloader/nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features embassy-nrf/nrf9161-ns \
-    --- build --release --manifest-path examples/boot/bootloader/rp/Cargo.toml --target thumbv6m-none-eabi \
-    --- build --release --manifest-path examples/boot/bootloader/stm32/Cargo.toml --target thumbv7em-none-eabi --features embassy-stm32/stm32l496zg \
-    --- build --release --manifest-path examples/boot/bootloader/stm32wb-dfu/Cargo.toml --target thumbv7em-none-eabi --features embassy-stm32/stm32wb55rg \
-    --- build --release --manifest-path examples/boot/bootloader/stm32wb-dfu/Cargo.toml --target thumbv7em-none-eabi --features embassy-stm32/stm32wb55rg,verify \
-    --- build --release --manifest-path examples/boot/bootloader/stm32wba-dfu/Cargo.toml --target thumbv8m.main-none-eabihf --features embassy-stm32/stm32wba65ri,verify \
-    --- build --release --manifest-path examples/boot/bootloader/stm32-dual-bank/Cargo.toml --target thumbv7em-none-eabi --features embassy-stm32/stm32h743zi \
-    --- build --release --manifest-path examples/wasm/Cargo.toml --target wasm32-unknown-unknown --artifact-dir out/examples/wasm \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32f103c8 --artifact-dir out/tests/stm32f103c8 \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f429zi --artifact-dir out/tests/stm32f429zi \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f446re --artifact-dir out/tests/stm32f446re \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32g491re --artifact-dir out/tests/stm32g491re \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32g071rb --artifact-dir out/tests/stm32g071rb \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32c031c6 --artifact-dir out/tests/stm32c031c6 \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32c071rb --artifact-dir out/tests/stm32c071rb \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h755zi --artifact-dir out/tests/stm32h755zi \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h753zi --artifact-dir out/tests/stm32h753zi \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h7a3zi --artifact-dir out/tests/stm32h7a3zi \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32wb55rg --artifact-dir out/tests/stm32wb55rg \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32h563zi --artifact-dir out/tests/stm32h563zi \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32u585ai --artifact-dir out/tests/stm32u585ai \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32u5a5zj --artifact-dir out/tests/stm32u5a5zj \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32wba52cg --artifact-dir out/tests/stm32wba52cg \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32l073rz --artifact-dir out/tests/stm32l073rz \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32l152re --artifact-dir out/tests/stm32l152re \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32l4a6zg --artifact-dir out/tests/stm32l4a6zg \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32l4r5zi --artifact-dir out/tests/stm32l4r5zi \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze --artifact-dir out/tests/stm32l552ze \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f767zi --artifact-dir out/tests/stm32f767zi \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32f207zg --artifact-dir out/tests/stm32f207zg \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f303ze --artifact-dir out/tests/stm32f303ze \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32l496zg --artifact-dir out/tests/stm32l496zg \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32wl55jc --artifact-dir out/tests/stm32wl55jc \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h7s3l8 --artifact-dir out/tests/stm32h7s3l8 \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32f091rc --artifact-dir out/tests/stm32f091rc \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32h503rb --artifact-dir out/tests/stm32h503rb \
-    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32u083rc --artifact-dir out/tests/stm32u083rc \
-    --- build --release --manifest-path tests/rp/Cargo.toml --target thumbv6m-none-eabi --features rp2040 --artifact-dir out/tests/rpi-pico \
-    --- build --release --manifest-path tests/rp/Cargo.toml --target thumbv8m.main-none-eabihf --features rp235xb --artifact-dir out/tests/pimoroni-pico-plus-2 \
-    --- build --release --manifest-path tests/nrf/Cargo.toml --target thumbv6m-none-eabi --features nrf51422 --artifact-dir out/tests/nrf51422-dk \
-    --- build --release --manifest-path tests/nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52832 --artifact-dir out/tests/nrf52832-dk \
-    --- build --release --manifest-path tests/nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52833 --artifact-dir out/tests/nrf52833-dk \
-    --- build --release --manifest-path tests/nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52840 --artifact-dir out/tests/nrf52840-dk \
-    --- build --release --manifest-path tests/nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features nrf5340 --artifact-dir out/tests/nrf5340-dk \
-    --- build --release --manifest-path tests/nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features nrf9160 --artifact-dir out/tests/nrf9160-dk \
-    --- build --release --manifest-path tests/mspm0/Cargo.toml --target thumbv6m-none-eabi --features mspm0g3507 --artifact-dir out/tests/mspm0g3507 \
-    --- build --release --manifest-path tests/riscv32/Cargo.toml --target riscv32imac-unknown-none-elf \
-    $BUILD_EXTRA
-
-
-# MSPM0C1104 must be built seperately since cargo batch does not consider env vars set in `.cargo/config.toml`.
-# Since the target has 1KB of ram, we need to limit defmt's buffer size.
-DEFMT_RTT_BUFFER_SIZE="72" cargo batch \
-    --- build --release --manifest-path examples/mspm0c1104/Cargo.toml --target thumbv6m-none-eabi --artifact-dir out/examples/mspm0c1104 \
+cargo embassy-devtool build
 
 # temporarily disabled, these boards are dead.
 rm -rf out/tests/stm32f103c8
@@ -397,8 +66,10 @@ rm out/tests/pimoroni-pico-plus-2/pwm
 rm out/tests/rpi-pico/pwm
 rm out/tests/rpi-pico/cyw43-perf
 
-# tests are implemented but the HIL test farm doesn't actually have this board yet
+# tests are implemented but the HIL test farm doesn't actually have these boards, yet
 rm -rf out/tests/stm32c071rb
+rm -rf out/tests/stm32f100rd
+rm -rf out/tests/stm32f107vc
 
 if [[ -z "${TELEPROBE_TOKEN-}" ]]; then
     echo No teleprobe token found, skipping running HIL tests
diff --git a/docs/pages/embassy_in_the_wild.adoc b/docs/pages/embassy_in_the_wild.adoc
index 620794c31..cedbedada 100644
--- a/docs/pages/embassy_in_the_wild.adoc
+++ b/docs/pages/embassy_in_the_wild.adoc
@@ -2,6 +2,10 @@
 
 Here are known examples of real-world projects which make use of Embassy. Feel free to link:https://github.com/embassy-rs/embassy/blob/main/docs/pages/embassy_in_the_wild.adoc[add more]!
 
+_newer entries at the top_
+
+* link:https://github.com/CarlKCarlK/clock[Embassy Clock: Layered, modular bare-metal clock with emulation]
+** A `no_std` Raspberry Pi Pico clock demonstrating layered Embassy tasks (Display->Blinker->Clock) for clean separation of multiplexing, blinking, and UI logic. Features single-button HH:MM/MM:SS time-set UI, heapless data structures, and a Renode emulator for hardware-free testing. See link:https://medium.com/@carlmkadie/how-rust-embassy-shine-on-embedded-devices-part-2-aad1adfccf72[this article] for details.
 * link:https://github.com/1-rafael-1/simple-robot[A simple tracked robot based on Raspberry Pi Pico 2]
 ** A hobbyist project building a tracked robot with basic autonomous and manual drive mode.
 * link:https://github.com/1-rafael-1/pi-pico-alarmclock-rust[A Raspberry Pi Pico W Alarmclock]
diff --git a/embassy-executor-macros/Cargo.toml b/embassy-executor-macros/Cargo.toml
index f803e6644..9c2b40d03 100644
--- a/embassy-executor-macros/Cargo.toml
+++ b/embassy-executor-macros/Cargo.toml
@@ -23,3 +23,4 @@ proc-macro = true
 
 [features]
 nightly = []
+metadata-name = []
diff --git a/embassy-executor-macros/src/macros/main.rs b/embassy-executor-macros/src/macros/main.rs
index f043ff7f6..dc470e51c 100644
--- a/embassy-executor-macros/src/macros/main.rs
+++ b/embassy-executor-macros/src/macros/main.rs
@@ -170,7 +170,7 @@ For example: `#[embassy_executor::main(entry = ..., executor = \"some_crate::Exe
     let f_body = f.body;
     let out = &f.sig.output;
 
-    let name_main_task = if cfg!(feature = "rtos-trace") {
+    let name_main_task = if cfg!(feature = "metadata-name") {
         quote!(
             main_task.metadata().set_name("main\0");
         )
diff --git a/embassy-executor/CHANGELOG.md b/embassy-executor/CHANGELOG.md
index 3e6c180c6..6f079a11a 100644
--- a/embassy-executor/CHANGELOG.md
+++ b/embassy-executor/CHANGELOG.md
@@ -8,9 +8,11 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 <!-- next-header -->
 ## Unreleased - ReleaseDate
 
-- Added new metadata API for tasks
-- Named main task when rtos-trace feature is enabled.
+- Added new metadata API for tasks.
+- Main task automatically gets a name of `main` when the `metadata-name` feature is enabled.
 - Upgraded rtos-trace
+- Added optional "highest priority" scheduling
+- Added optional "earliest deadline first" EDF scheduling
 
 ## 0.9.1 - 2025-08-31
 
@@ -20,8 +22,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 - Added `extern "Rust" fn __embassy_time_queue_item_from_waker`
 - Removed `TaskRef::dangling`
-- Added `embassy_time_queue_utils` as a dependency
-- Moved the `TimeQueueItem` struct and `timer-item-payload-size-*` features into embassy-time-queue-utils
+- Added `embassy-executor-timer-queue` as a dependency
+- Moved the `TimeQueueItem` struct and `timer-item-payload-size-*` features (as `timer-item-size-X-words`) into `embassy-executor-timer-queue`
 
 ## 0.8.0 - 2025-07-31
 
diff --git a/embassy-executor/Cargo.toml b/embassy-executor/Cargo.toml
index dc423aba2..f6dce5c0e 100644
--- a/embassy-executor/Cargo.toml
+++ b/embassy-executor/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "embassy-executor"
-version = "0.9.0"
+version = "0.9.1"
 edition = "2021"
 license = "MIT OR Apache-2.0"
 description = "async/await executor designed for embedded usage"
@@ -24,18 +24,49 @@ build = [
     {target = "thumbv7em-none-eabi", features = ["arch-cortex-m", "executor-thread"]},
     {target = "thumbv7em-none-eabi", features = ["arch-cortex-m", "executor-interrupt"]},
     {target = "thumbv7em-none-eabi", features = ["arch-cortex-m", "executor-interrupt", "executor-thread"]},
+    {target = "thumbv7em-none-eabi", features = ["arch-cortex-m", "executor-interrupt", "executor-thread", "embassy-time-driver"]},
+    {target = "thumbv7em-none-eabi", features = ["arch-cortex-m", "executor-interrupt", "executor-thread", "embassy-time-driver", "scheduler-priority"]},
+    {target = "thumbv7em-none-eabi", features = ["arch-cortex-m", "executor-interrupt", "executor-thread", "embassy-time-driver", "scheduler-priority", "scheduler-deadline"]},
+    {target = "thumbv7em-none-eabi", features = ["arch-cortex-m", "executor-interrupt", "executor-thread", "embassy-time-driver", "scheduler-deadline"]},
+    {target = "thumbv7em-none-eabi", features = ["arch-cortex-m", "executor-interrupt", "executor-thread", "scheduler-priority", "scheduler-deadline"]},
+    {target = "thumbv7em-none-eabi", features = ["arch-cortex-m", "executor-interrupt", "executor-thread", "scheduler-deadline"]},
     {target = "armv7a-none-eabi", features = ["arch-cortex-ar", "executor-thread"]},
     {target = "armv7r-none-eabi", features = ["arch-cortex-ar", "executor-thread"]},
     {target = "armv7r-none-eabihf", features = ["arch-cortex-ar", "executor-thread"]},
     {target = "riscv32imac-unknown-none-elf", features = ["arch-riscv32"]},
     {target = "riscv32imac-unknown-none-elf", features = ["arch-riscv32", "executor-thread"]},
+    # Nightly builds
+    {group = "nightly", target = "thumbv7em-none-eabi", features = ["nightly"]},
+    {group = "nightly", target = "thumbv7em-none-eabi", features = ["nightly", "log"]},
+    {group = "nightly", target = "thumbv7em-none-eabi", features = ["nightly", "defmt"]},
+    {group = "nightly", target = "thumbv6m-none-eabi", features = ["nightly", "defmt"]},
+    {group = "nightly", target = "thumbv6m-none-eabi", features = ["nightly", "defmt", "arch-cortex-m", "executor-thread", "executor-interrupt"]},
+    {group = "nightly", target = "thumbv7em-none-eabi", features = ["nightly", "arch-cortex-m"]},
+    {group = "nightly", target = "thumbv7em-none-eabi", features = ["nightly", "arch-cortex-m", "executor-thread"]},
+    {group = "nightly", target = "thumbv7em-none-eabi", features = ["nightly", "arch-cortex-m", "executor-interrupt"]},
+    {group = "nightly", target = "thumbv7em-none-eabi", features = ["nightly", "arch-cortex-m", "executor-thread", "executor-interrupt"]},
+    {group = "nightly", target = "riscv32imac-unknown-none-elf", features = ["nightly", "arch-riscv32"]},
+    {group = "nightly", target = "riscv32imac-unknown-none-elf", features = ["nightly", "arch-riscv32", "executor-thread"]},
+    {group = "nightly", target = "armv7a-none-eabi", features = ["nightly", "arch-cortex-ar", "executor-thread"]},
+    {group = "nightly", target = "avr-none", features = ["nightly", "arch-avr", "avr-device/atmega328p"], build-std = ["core", "alloc"], env = { RUSTFLAGS = "-Ctarget-cpu=atmega328p" }},
+    # Xtensa builds
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32-none-elf", features = []},
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32-none-elf", features = ["log"]},
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32-none-elf", features = ["defmt"]},
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32s2-none-elf", features = ["defmt"]},
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32-none-elf", features = ["defmt", "arch-spin", "executor-thread"]},
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32s2-none-elf", features = ["defmt", "arch-spin", "executor-thread"]},
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32s3-none-elf", features = ["defmt", "arch-spin", "executor-thread"]},
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32-none-elf", features = ["arch-spin"]},
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32-none-elf", features = ["arch-spin", "rtos-trace"]},
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32-none-elf", features = ["arch-spin", "executor-thread"]},
 ]
 
 
 [package.metadata.embassy_docs]
 src_base = "https://github.com/embassy-rs/embassy/blob/embassy-executor-v$VERSION/embassy-executor/src/"
 src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-executor/src/"
-features = ["defmt"]
+features = ["defmt", "scheduler-deadline", "scheduler-priority"]
 flavors = [
     { name = "std",             target = "x86_64-unknown-linux-gnu",     features = ["arch-std", "executor-thread"] },
     { name = "wasm",            target = "wasm32-unknown-unknown",       features = ["arch-wasm", "executor-thread"] },
@@ -46,7 +77,7 @@ flavors = [
 [package.metadata.docs.rs]
 default-target = "thumbv7em-none-eabi"
 targets = ["thumbv7em-none-eabi"]
-features = ["defmt", "arch-cortex-m", "executor-thread", "executor-interrupt"]
+features = ["defmt", "arch-cortex-m", "executor-thread", "executor-interrupt", "scheduler-deadline", "scheduler-priority", "embassy-time-driver"]
 
 [dependencies]
 defmt = { version = "1.0.1", optional = true }
@@ -76,6 +107,11 @@ js-sys = { version = "0.3", optional = true }
 # arch-avr dependencies
 avr-device = { version = "0.7.0", optional = true }
 
+
+[dependencies.cordyceps]
+version = "0.3.4"
+features = ["no-cache-pad"]
+
 [dev-dependencies]
 critical-section = { version = "1.1", features = ["std"] }
 trybuild = "1.0"
@@ -112,7 +148,7 @@ arch-spin = ["_arch"]
 #! ### Metadata
 
 ## Enable the `name` field in task metadata.
-metadata-name = []
+metadata-name = ["embassy-executor-macros/metadata-name"]
 
 #! ### Executor
 
@@ -123,21 +159,16 @@ executor-interrupt = []
 ## Enable tracing hooks
 trace = ["_any_trace"]
 ## Enable support for rtos-trace framework
-rtos-trace = ["_any_trace", "metadata-name", "dep:rtos-trace", "dep:embassy-time-driver"]
+rtos-trace = ["_any_trace", "metadata-name", "dep:rtos-trace", "embassy-time-driver"]
 _any_trace = []
 
-#! ### Timer Item Payload Size
-#! Sets the size of the payload for timer items, allowing integrated timer implementors to store
-#! additional data in the timer item. The payload field will be aligned to this value as well.
-#! If these features are not defined, the timer item will contain no payload field.
-
-_timer-item-payload = [] # A size was picked
-
-## 1 bytes
-timer-item-payload-size-1 = ["_timer-item-payload"]
-## 2 bytes
-timer-item-payload-size-2 = ["_timer-item-payload"]
-## 4 bytes
-timer-item-payload-size-4 = ["_timer-item-payload"]
-## 8 bytes
-timer-item-payload-size-8 = ["_timer-item-payload"]
+## Enable "Earliest Deadline First" Scheduler, using soft-realtime "deadlines" to prioritize
+## tasks based on the remaining time before their deadline. Adds some overhead.
+scheduler-deadline = []
+
+## Enable "Highest Priority First" Scheduler. Adds some overhead.
+scheduler-priority = []
+
+## Enable the embassy_time_driver dependency.
+## This can unlock extra APIs, for example for the `sheduler-deadline`
+embassy-time-driver = ["dep:embassy-time-driver"]
diff --git a/embassy-executor/src/metadata.rs b/embassy-executor/src/metadata.rs
index f92c9b37c..bc0df0f83 100644
--- a/embassy-executor/src/metadata.rs
+++ b/embassy-executor/src/metadata.rs
@@ -1,17 +1,25 @@
 #[cfg(feature = "metadata-name")]
 use core::cell::Cell;
 use core::future::{poll_fn, Future};
+#[cfg(feature = "scheduler-priority")]
+use core::sync::atomic::{AtomicU8, Ordering};
 use core::task::Poll;
 
 #[cfg(feature = "metadata-name")]
 use critical_section::Mutex;
 
 use crate::raw;
+#[cfg(feature = "scheduler-deadline")]
+use crate::raw::Deadline;
 
 /// Metadata associated with a task.
 pub struct Metadata {
     #[cfg(feature = "metadata-name")]
     name: Mutex<Cell<Option<&'static str>>>,
+    #[cfg(feature = "scheduler-priority")]
+    priority: AtomicU8,
+    #[cfg(feature = "scheduler-deadline")]
+    deadline: raw::Deadline,
 }
 
 impl Metadata {
@@ -19,12 +27,26 @@ impl Metadata {
         Self {
             #[cfg(feature = "metadata-name")]
             name: Mutex::new(Cell::new(None)),
+            #[cfg(feature = "scheduler-priority")]
+            priority: AtomicU8::new(0),
+            // NOTE: The deadline is set to zero to allow the initializer to reside in `.bss`. This
+            // will be lazily initalized in `initialize_impl`
+            #[cfg(feature = "scheduler-deadline")]
+            deadline: raw::Deadline::new_unset(),
         }
     }
 
     pub(crate) fn reset(&self) {
         #[cfg(feature = "metadata-name")]
         critical_section::with(|cs| self.name.borrow(cs).set(None));
+
+        #[cfg(feature = "scheduler-priority")]
+        self.set_priority(0);
+
+        // By default, deadlines are set to the maximum value, so that any task WITH
+        // a set deadline will ALWAYS be scheduled BEFORE a task WITHOUT a set deadline
+        #[cfg(feature = "scheduler-deadline")]
+        self.unset_deadline();
     }
 
     /// Get the metadata for the current task.
@@ -52,4 +74,75 @@ impl Metadata {
     pub fn set_name(&self, name: &'static str) {
         critical_section::with(|cs| self.name.borrow(cs).set(Some(name)))
     }
+
+    /// Get this task's priority.
+    #[cfg(feature = "scheduler-priority")]
+    pub fn priority(&self) -> u8 {
+        self.priority.load(Ordering::Relaxed)
+    }
+
+    /// Set this task's priority.
+    #[cfg(feature = "scheduler-priority")]
+    pub fn set_priority(&self, priority: u8) {
+        self.priority.store(priority, Ordering::Relaxed)
+    }
+
+    /// Get this task's deadline.
+    #[cfg(feature = "scheduler-deadline")]
+    pub fn deadline(&self) -> u64 {
+        self.deadline.instant_ticks()
+    }
+
+    /// Set this task's deadline.
+    ///
+    /// This method does NOT check whether the deadline has already passed.
+    #[cfg(feature = "scheduler-deadline")]
+    pub fn set_deadline(&self, instant_ticks: u64) {
+        self.deadline.set(instant_ticks);
+    }
+
+    /// Remove this task's deadline.
+    /// This brings it back to the defaul where it's not scheduled ahead of other tasks.
+    #[cfg(feature = "scheduler-deadline")]
+    pub fn unset_deadline(&self) {
+        self.deadline.set(Deadline::UNSET_TICKS);
+    }
+
+    /// Set this task's deadline `duration_ticks` in the future from when
+    /// this future is polled. This deadline is saturated to the max tick value.
+    ///
+    /// Analogous to `Timer::after`.
+    #[cfg(all(feature = "scheduler-deadline", feature = "embassy-time-driver"))]
+    pub fn set_deadline_after(&self, duration_ticks: u64) {
+        let now = embassy_time_driver::now();
+
+        // Since ticks is a u64, saturating add is PROBABLY overly cautious, leave
+        // it for now, we can probably make this wrapping_add for performance
+        // reasons later.
+        let deadline = now.saturating_add(duration_ticks);
+
+        self.set_deadline(deadline);
+    }
+
+    /// Set the this task's deadline `increment_ticks` from the previous deadline.
+    ///
+    /// This deadline is saturated to the max tick value.
+    ///
+    /// Note that by default (unless otherwise set), tasks start life with the deadline
+    /// not set, which means this method will have no effect.
+    ///
+    /// Analogous to one increment of `Ticker::every().next()`.
+    ///
+    /// Returns the deadline that was set.
+    #[cfg(feature = "scheduler-deadline")]
+    pub fn increment_deadline(&self, duration_ticks: u64) {
+        let last = self.deadline();
+
+        // Since ticks is a u64, saturating add is PROBABLY overly cautious, leave
+        // it for now, we can probably make this wrapping_add for performance
+        // reasons later.
+        let deadline = last.saturating_add(duration_ticks);
+
+        self.set_deadline(deadline);
+    }
 }
diff --git a/embassy-executor/src/raw/deadline.rs b/embassy-executor/src/raw/deadline.rs
new file mode 100644
index 000000000..cc89fadb0
--- /dev/null
+++ b/embassy-executor/src/raw/deadline.rs
@@ -0,0 +1,44 @@
+use core::sync::atomic::{AtomicU32, Ordering};
+
+/// A type for interacting with the deadline of the current task
+///
+/// Requires the `scheduler-deadline` feature.
+///
+/// Note: Interacting with the deadline should be done locally in a task.
+/// In theory you could try to set or read the deadline from another task,
+/// but that will result in weird (though not unsound) behavior.
+pub(crate) struct Deadline {
+    instant_ticks_hi: AtomicU32,
+    instant_ticks_lo: AtomicU32,
+}
+
+impl Deadline {
+    pub(crate) const fn new(instant_ticks: u64) -> Self {
+        Self {
+            instant_ticks_hi: AtomicU32::new((instant_ticks >> 32) as u32),
+            instant_ticks_lo: AtomicU32::new(instant_ticks as u32),
+        }
+    }
+
+    pub(crate) const fn new_unset() -> Self {
+        Self::new(Self::UNSET_TICKS)
+    }
+
+    pub(crate) fn set(&self, instant_ticks: u64) {
+        self.instant_ticks_hi
+            .store((instant_ticks >> 32) as u32, Ordering::Relaxed);
+        self.instant_ticks_lo.store(instant_ticks as u32, Ordering::Relaxed);
+    }
+
+    /// Deadline value in ticks, same time base and ticks as `embassy-time`
+    pub(crate) fn instant_ticks(&self) -> u64 {
+        let hi = self.instant_ticks_hi.load(Ordering::Relaxed) as u64;
+        let lo = self.instant_ticks_lo.load(Ordering::Relaxed) as u64;
+
+        (hi << 32) | lo
+    }
+
+    /// Sentinel value representing an "unset" deadline, which has lower priority
+    /// than any other set deadline value
+    pub(crate) const UNSET_TICKS: u64 = u64::MAX;
+}
diff --git a/embassy-executor/src/raw/mod.rs b/embassy-executor/src/raw/mod.rs
index 4280c5750..9f36c60bc 100644
--- a/embassy-executor/src/raw/mod.rs
+++ b/embassy-executor/src/raw/mod.rs
@@ -7,8 +7,6 @@
 //! Using this module requires respecting subtle safety contracts. If you can, prefer using the safe
 //! [executor wrappers](crate::Executor) and the [`embassy_executor::task`](embassy_executor_macros::task) macro, which are fully safe.
 
-#[cfg_attr(target_has_atomic = "ptr", path = "run_queue_atomics.rs")]
-#[cfg_attr(not(target_has_atomic = "ptr"), path = "run_queue_critical_section.rs")]
 mod run_queue;
 
 #[cfg_attr(all(cortex_m, target_has_atomic = "32"), path = "state_atomics_arm.rs")]
@@ -28,6 +26,9 @@ pub(crate) mod util;
 #[cfg_attr(feature = "turbowakers", path = "waker_turbo.rs")]
 mod waker;
 
+#[cfg(feature = "scheduler-deadline")]
+mod deadline;
+
 use core::future::Future;
 use core::marker::PhantomData;
 use core::mem;
@@ -38,6 +39,8 @@ use core::sync::atomic::AtomicPtr;
 use core::sync::atomic::Ordering;
 use core::task::{Context, Poll, Waker};
 
+#[cfg(feature = "scheduler-deadline")]
+pub(crate) use deadline::Deadline;
 use embassy_executor_timer_queue::TimerQueueItem;
 #[cfg(feature = "arch-avr")]
 use portable_atomic::AtomicPtr;
@@ -96,6 +99,7 @@ extern "Rust" fn __embassy_time_queue_item_from_waker(waker: &Waker) -> &'static
 pub(crate) struct TaskHeader {
     pub(crate) state: State,
     pub(crate) run_queue_item: RunQueueItem,
+
     pub(crate) executor: AtomicPtr<SyncExecutor>,
     poll_fn: SyncUnsafeCell<Option<unsafe fn(TaskRef)>>,
 
diff --git a/embassy-executor/src/raw/run_queue.rs b/embassy-executor/src/raw/run_queue.rs
new file mode 100644
index 000000000..b8b052310
--- /dev/null
+++ b/embassy-executor/src/raw/run_queue.rs
@@ -0,0 +1,213 @@
+use core::ptr::{addr_of_mut, NonNull};
+
+use cordyceps::sorted_list::Links;
+use cordyceps::Linked;
+#[cfg(any(feature = "scheduler-priority", feature = "scheduler-deadline"))]
+use cordyceps::SortedList;
+
+#[cfg(target_has_atomic = "ptr")]
+type TransferStack<T> = cordyceps::TransferStack<T>;
+
+#[cfg(not(target_has_atomic = "ptr"))]
+type TransferStack<T> = MutexTransferStack<T>;
+
+use super::{TaskHeader, TaskRef};
+
+/// Use `cordyceps::sorted_list::Links` as the singly linked list
+/// for RunQueueItems.
+pub(crate) type RunQueueItem = Links<TaskHeader>;
+
+/// Implements the `Linked` trait, allowing for singly linked list usage
+/// of any of cordyceps' `TransferStack` (used for the atomic runqueue),
+/// `SortedList` (used with the DRS scheduler), or `Stack`, which is
+/// popped atomically from the `TransferStack`.
+unsafe impl Linked<Links<TaskHeader>> for TaskHeader {
+    type Handle = TaskRef;
+
+    // Convert a TaskRef into a TaskHeader ptr
+    fn into_ptr(r: TaskRef) -> NonNull<TaskHeader> {
+        r.ptr
+    }
+
+    // Convert a TaskHeader into a TaskRef
+    unsafe fn from_ptr(ptr: NonNull<TaskHeader>) -> TaskRef {
+        TaskRef { ptr }
+    }
+
+    // Given a pointer to a TaskHeader, obtain a pointer to the Links structure,
+    // which can be used to traverse to other TaskHeader nodes in the linked list
+    unsafe fn links(ptr: NonNull<TaskHeader>) -> NonNull<Links<TaskHeader>> {
+        let ptr: *mut TaskHeader = ptr.as_ptr();
+        NonNull::new_unchecked(addr_of_mut!((*ptr).run_queue_item))
+    }
+}
+
+/// Atomic task queue using a very, very simple lock-free linked-list queue:
+///
+/// To enqueue a task, task.next is set to the old head, and head is atomically set to task.
+///
+/// Dequeuing is done in batches: the queue is emptied by atomically replacing head with
+/// null. Then the batch is iterated following the next pointers until null is reached.
+///
+/// Note that batches will be iterated in the reverse order as they were enqueued. This is OK
+/// for our purposes: it can't create fairness problems since the next batch won't run until the
+/// current batch is completely processed, so even if a task enqueues itself instantly (for example
+/// by waking its own waker) can't prevent other tasks from running.
+pub(crate) struct RunQueue {
+    stack: TransferStack<TaskHeader>,
+}
+
+impl RunQueue {
+    pub const fn new() -> Self {
+        Self {
+            stack: TransferStack::new(),
+        }
+    }
+
+    /// Enqueues an item. Returns true if the queue was empty.
+    ///
+    /// # Safety
+    ///
+    /// `item` must NOT be already enqueued in any queue.
+    #[inline(always)]
+    pub(crate) unsafe fn enqueue(&self, task: TaskRef, _tok: super::state::Token) -> bool {
+        self.stack.push_was_empty(
+            task,
+            #[cfg(not(target_has_atomic = "ptr"))]
+            _tok,
+        )
+    }
+
+    /// # Standard atomic runqueue
+    ///
+    /// Empty the queue, then call `on_task` for each task that was in the queue.
+    /// NOTE: It is OK for `on_task` to enqueue more tasks. In this case they're left in the queue
+    /// and will be processed by the *next* call to `dequeue_all`, *not* the current one.
+    #[cfg(not(any(feature = "scheduler-priority", feature = "scheduler-deadline")))]
+    pub(crate) fn dequeue_all(&self, on_task: impl Fn(TaskRef)) {
+        let taken = self.stack.take_all();
+        for taskref in taken {
+            run_dequeue(&taskref);
+            on_task(taskref);
+        }
+    }
+
+    /// # Earliest Deadline First Scheduler
+    ///
+    /// This algorithm will loop until all enqueued tasks are processed.
+    ///
+    /// Before polling a task, all currently enqueued tasks will be popped from the
+    /// runqueue, and will be added to the working `sorted` list, a linked-list that
+    /// sorts tasks by their deadline, with nearest deadline items in the front, and
+    /// furthest deadline items in the back.
+    ///
+    /// After popping and sorting all pending tasks, the SOONEST task will be popped
+    /// from the front of the queue, and polled by calling `on_task` on it.
+    ///
+    /// This process will repeat until the local `sorted` queue AND the global
+    /// runqueue are both empty, at which point this function will return.
+    #[cfg(any(feature = "scheduler-priority", feature = "scheduler-deadline"))]
+    pub(crate) fn dequeue_all(&self, on_task: impl Fn(TaskRef)) {
+        let mut sorted = SortedList::<TaskHeader>::new_with_cmp(|lhs, rhs| {
+            // compare by priority first
+            #[cfg(feature = "scheduler-priority")]
+            {
+                let lp = lhs.metadata.priority();
+                let rp = rhs.metadata.priority();
+                if lp != rp {
+                    return lp.cmp(&rp).reverse();
+                }
+            }
+            // compare deadlines in case of tie.
+            #[cfg(feature = "scheduler-deadline")]
+            {
+                let ld = lhs.metadata.deadline();
+                let rd = rhs.metadata.deadline();
+                if ld != rd {
+                    return ld.cmp(&rd);
+                }
+            }
+            core::cmp::Ordering::Equal
+        });
+
+        loop {
+            // For each loop, grab any newly pended items
+            let taken = self.stack.take_all();
+
+            // Sort these into the list - this is potentially expensive! We do an
+            // insertion sort of new items, which iterates the linked list.
+            //
+            // Something on the order of `O(n * m)`, where `n` is the number
+            // of new tasks, and `m` is the number of already pending tasks.
+            sorted.extend(taken);
+
+            // Pop the task with the SOONEST deadline. If there are no tasks
+            // pending, then we are done.
+            let Some(taskref) = sorted.pop_front() else {
+                return;
+            };
+
+            // We got one task, mark it as dequeued, and process the task.
+            run_dequeue(&taskref);
+            on_task(taskref);
+        }
+    }
+}
+
+/// atomic state does not require a cs...
+#[cfg(target_has_atomic = "ptr")]
+#[inline(always)]
+fn run_dequeue(taskref: &TaskRef) {
+    taskref.header().state.run_dequeue();
+}
+
+/// ...while non-atomic state does
+#[cfg(not(target_has_atomic = "ptr"))]
+#[inline(always)]
+fn run_dequeue(taskref: &TaskRef) {
+    critical_section::with(|cs| {
+        taskref.header().state.run_dequeue(cs);
+    })
+}
+
+/// A wrapper type that acts like TransferStack by wrapping a normal Stack in a CS mutex
+#[cfg(not(target_has_atomic = "ptr"))]
+struct MutexTransferStack<T: Linked<cordyceps::stack::Links<T>>> {
+    inner: critical_section::Mutex<core::cell::UnsafeCell<cordyceps::Stack<T>>>,
+}
+
+#[cfg(not(target_has_atomic = "ptr"))]
+impl<T: Linked<cordyceps::stack::Links<T>>> MutexTransferStack<T> {
+    const fn new() -> Self {
+        Self {
+            inner: critical_section::Mutex::new(core::cell::UnsafeCell::new(cordyceps::Stack::new())),
+        }
+    }
+
+    /// Push an item to the transfer stack, returning whether the stack was previously empty
+    fn push_was_empty(&self, item: T::Handle, token: super::state::Token) -> bool {
+        // SAFETY: The critical-section mutex guarantees that there is no *concurrent* access
+        // for the lifetime of the token, but does NOT protect against re-entrant access.
+        // However, we never *return* the reference, nor do we recurse (or call another method
+        // like `take_all`) that could ever allow for re-entrant aliasing. Therefore, the
+        // presence of the critical section is sufficient to guarantee exclusive access to
+        // the `inner` field for the purposes of this function.
+        let inner = unsafe { &mut *self.inner.borrow(token).get() };
+        let is_empty = inner.is_empty();
+        inner.push(item);
+        is_empty
+    }
+
+    fn take_all(&self) -> cordyceps::Stack<T> {
+        critical_section::with(|cs| {
+            // SAFETY: The critical-section mutex guarantees that there is no *concurrent* access
+            // for the lifetime of the token, but does NOT protect against re-entrant access.
+            // However, we never *return* the reference, nor do we recurse (or call another method
+            // like `push_was_empty`) that could ever allow for re-entrant aliasing. Therefore, the
+            // presence of the critical section is sufficient to guarantee exclusive access to
+            // the `inner` field for the purposes of this function.
+            let inner = unsafe { &mut *self.inner.borrow(cs).get() };
+            inner.take_all()
+        })
+    }
+}
diff --git a/embassy-executor/src/raw/run_queue_atomics.rs b/embassy-executor/src/raw/run_queue_atomics.rs
deleted file mode 100644
index ce511d79a..000000000
--- a/embassy-executor/src/raw/run_queue_atomics.rs
+++ /dev/null
@@ -1,88 +0,0 @@
-use core::ptr;
-use core::ptr::NonNull;
-use core::sync::atomic::{AtomicPtr, Ordering};
-
-use super::{TaskHeader, TaskRef};
-use crate::raw::util::SyncUnsafeCell;
-
-pub(crate) struct RunQueueItem {
-    next: SyncUnsafeCell<Option<TaskRef>>,
-}
-
-impl RunQueueItem {
-    pub const fn new() -> Self {
-        Self {
-            next: SyncUnsafeCell::new(None),
-        }
-    }
-}
-
-/// Atomic task queue using a very, very simple lock-free linked-list queue:
-///
-/// To enqueue a task, task.next is set to the old head, and head is atomically set to task.
-///
-/// Dequeuing is done in batches: the queue is emptied by atomically replacing head with
-/// null. Then the batch is iterated following the next pointers until null is reached.
-///
-/// Note that batches will be iterated in the reverse order as they were enqueued. This is OK
-/// for our purposes: it can't create fairness problems since the next batch won't run until the
-/// current batch is completely processed, so even if a task enqueues itself instantly (for example
-/// by waking its own waker) can't prevent other tasks from running.
-pub(crate) struct RunQueue {
-    head: AtomicPtr<TaskHeader>,
-}
-
-impl RunQueue {
-    pub const fn new() -> Self {
-        Self {
-            head: AtomicPtr::new(ptr::null_mut()),
-        }
-    }
-
-    /// Enqueues an item. Returns true if the queue was empty.
-    ///
-    /// # Safety
-    ///
-    /// `item` must NOT be already enqueued in any queue.
-    #[inline(always)]
-    pub(crate) unsafe fn enqueue(&self, task: TaskRef, _: super::state::Token) -> bool {
-        let mut was_empty = false;
-
-        self.head
-            .fetch_update(Ordering::SeqCst, Ordering::SeqCst, |prev| {
-                was_empty = prev.is_null();
-                unsafe {
-                    // safety: the pointer is either null or valid
-                    let prev = NonNull::new(prev).map(|ptr| TaskRef::from_ptr(ptr.as_ptr()));
-                    // safety: there are no concurrent accesses to `next`
-                    task.header().run_queue_item.next.set(prev);
-                }
-                Some(task.as_ptr() as *mut _)
-            })
-            .ok();
-
-        was_empty
-    }
-
-    /// Empty the queue, then call `on_task` for each task that was in the queue.
-    /// NOTE: It is OK for `on_task` to enqueue more tasks. In this case they're left in the queue
-    /// and will be processed by the *next* call to `dequeue_all`, *not* the current one.
-    pub(crate) fn dequeue_all(&self, on_task: impl Fn(TaskRef)) {
-        // Atomically empty the queue.
-        let ptr = self.head.swap(ptr::null_mut(), Ordering::AcqRel);
-
-        // safety: the pointer is either null or valid
-        let mut next = unsafe { NonNull::new(ptr).map(|ptr| TaskRef::from_ptr(ptr.as_ptr())) };
-
-        // Iterate the linked list of tasks that were previously in the queue.
-        while let Some(task) = next {
-            // If the task re-enqueues itself, the `next` pointer will get overwritten.
-            // Therefore, first read the next pointer, and only then process the task.
-            // safety: there are no concurrent accesses to `next`
-            next = unsafe { task.header().run_queue_item.next.get() };
-
-            task.header().state.run_dequeue();
-            on_task(task);
-        }
-    }
-}
diff --git a/embassy-executor/src/raw/run_queue_critical_section.rs b/embassy-executor/src/raw/run_queue_critical_section.rs
deleted file mode 100644
index 86c4085ed..000000000
--- a/embassy-executor/src/raw/run_queue_critical_section.rs
+++ /dev/null
@@ -1,74 +0,0 @@
-use core::cell::Cell;
-
-use critical_section::{CriticalSection, Mutex};
-
-use super::TaskRef;
-
-pub(crate) struct RunQueueItem {
-    next: Mutex<Cell<Option<TaskRef>>>,
-}
-
-impl RunQueueItem {
-    pub const fn new() -> Self {
-        Self {
-            next: Mutex::new(Cell::new(None)),
-        }
-    }
-}
-
-/// Atomic task queue using a very, very simple lock-free linked-list queue:
-///
-/// To enqueue a task, task.next is set to the old head, and head is atomically set to task.
-///
-/// Dequeuing is done in batches: the queue is emptied by atomically replacing head with
-/// null. Then the batch is iterated following the next pointers until null is reached.
-///
-/// Note that batches will be iterated in the reverse order as they were enqueued. This is OK
-/// for our purposes: it can't create fairness problems since the next batch won't run until the
-/// current batch is completely processed, so even if a task enqueues itself instantly (for example
-/// by waking its own waker) can't prevent other tasks from running.
-pub(crate) struct RunQueue {
-    head: Mutex<Cell<Option<TaskRef>>>,
-}
-
-impl RunQueue {
-    pub const fn new() -> Self {
-        Self {
-            head: Mutex::new(Cell::new(None)),
-        }
-    }
-
-    /// Enqueues an item. Returns true if the queue was empty.
-    ///
-    /// # Safety
-    ///
-    /// `item` must NOT be already enqueued in any queue.
-    #[inline(always)]
-    pub(crate) unsafe fn enqueue(&self, task: TaskRef, cs: CriticalSection<'_>) -> bool {
-        let prev = self.head.borrow(cs).replace(Some(task));
-        task.header().run_queue_item.next.borrow(cs).set(prev);
-
-        prev.is_none()
-    }
-
-    /// Empty the queue, then call `on_task` for each task that was in the queue.
-    /// NOTE: It is OK for `on_task` to enqueue more tasks. In this case they're left in the queue
-    /// and will be processed by the *next* call to `dequeue_all`, *not* the current one.
-    pub(crate) fn dequeue_all(&self, on_task: impl Fn(TaskRef)) {
-        // Atomically empty the queue.
-        let mut next = critical_section::with(|cs| self.head.borrow(cs).take());
-
-        // Iterate the linked list of tasks that were previously in the queue.
-        while let Some(task) = next {
-            // If the task re-enqueues itself, the `next` pointer will get overwritten.
-            // Therefore, first read the next pointer, and only then process the task.
-
-            critical_section::with(|cs| {
-                next = task.header().run_queue_item.next.borrow(cs).get();
-                task.header().state.run_dequeue(cs);
-            });
-
-            on_task(task);
-        }
-    }
-}
diff --git a/embassy-mspm0/CHANGELOG.md b/embassy-mspm0/CHANGELOG.md
index eca0defd7..b846f21b1 100644
--- a/embassy-mspm0/CHANGELOG.md
+++ b/embassy-mspm0/CHANGELOG.md
@@ -7,7 +7,9 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 <!-- next-header -->
 ## Unreleased - ReleaseDate
-
+ 
 - feat: Add I2C Controller (blocking & async) + examples for mspm0l1306, mspm0g3507 (tested MCUs) (#4435)
 - fix gpio interrupt not being set for mspm0l110x
 - feat: Add window watchdog implementation based on WWDT0, WWDT1 peripherals (#4574)
+- feat: Add MSPM0C1105/C1106 support
+- feat: Add adc implementation (#4646)
diff --git a/embassy-mspm0/Cargo.toml b/embassy-mspm0/Cargo.toml
index 92f7a2655..1b32c4d43 100644
--- a/embassy-mspm0/Cargo.toml
+++ b/embassy-mspm0/Cargo.toml
@@ -69,7 +69,7 @@ cortex-m = "0.7.6"
 critical-section = "1.2.0"
 
 # mspm0-metapac = { version = "" }
-mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-fe17d879548757ca29821da66a1bebf2debd4846" }
+mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-d7bf3d01ac0780e716a45b0474234d39443dc5cf" }
 
 [build-dependencies]
 proc-macro2 = "1.0.94"
@@ -77,7 +77,7 @@ quote = "1.0.40"
 cfg_aliases = "0.2.1"
 
 # mspm0-metapac = { version = "", default-features = false, features = ["metadata"] }
-mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-fe17d879548757ca29821da66a1bebf2debd4846", default-features = false, features = ["metadata"] }
+mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-d7bf3d01ac0780e716a45b0474234d39443dc5cf", default-features = false, features = ["metadata"] }
 
 [features]
 default = ["rt"]
@@ -159,6 +159,24 @@ mspm0c1104dsg = ["mspm0-metapac/mspm0c1104dsg"]
 mspm0c1104dyy = ["mspm0-metapac/mspm0c1104dyy"]
 mspm0c1104ruk = ["mspm0-metapac/mspm0c1104ruk"]
 mspm0c1104ycj = ["mspm0-metapac/mspm0c1104ycj"]
+mspm0c1105pt = ["mspm0-metapac/mspm0c1105pt"]
+mspm0c1105rgz = ["mspm0-metapac/mspm0c1105rgz"]
+mspm0c1105rhb = ["mspm0-metapac/mspm0c1105rhb"]
+mspm0c1105dgs32 = ["mspm0-metapac/mspm0c1105dgs32"]
+mspm0c1105dgs28 = ["mspm0-metapac/mspm0c1105dgs28"]
+mspm0c1105rge = ["mspm0-metapac/mspm0c1105rge"]
+mspm0c1105dgs20 = ["mspm0-metapac/mspm0c1105dgs20"]
+mspm0c1105ruk = ["mspm0-metapac/mspm0c1105ruk"]
+mspm0c1105zcm = ["mspm0-metapac/mspm0c1105zcm"]
+mspm0c1106pt = ["mspm0-metapac/mspm0c1106pt"]
+mspm0c1106rgz = ["mspm0-metapac/mspm0c1106rgz"]
+mspm0c1106rhb = ["mspm0-metapac/mspm0c1106rhb"]
+mspm0c1106dgs32 = ["mspm0-metapac/mspm0c1106dgs32"]
+mspm0c1106dgs28 = ["mspm0-metapac/mspm0c1106dgs28"]
+mspm0c1106rge = ["mspm0-metapac/mspm0c1106rge"]
+mspm0c1106dgs20 = ["mspm0-metapac/mspm0c1106dgs20"]
+mspm0c1106ruk = ["mspm0-metapac/mspm0c1106ruk"]
+mspm0c1106zcm = ["mspm0-metapac/mspm0c1106zcm"]
 mspm0g1105dgs28 = ["mspm0-metapac/mspm0g1105dgs28"]
 mspm0g1105pm = ["mspm0-metapac/mspm0g1105pm"]
 mspm0g1105pt = ["mspm0-metapac/mspm0g1105pt"]
diff --git a/embassy-mspm0/build.rs b/embassy-mspm0/build.rs
index 256192f8b..d294bc422 100644
--- a/embassy-mspm0/build.rs
+++ b/embassy-mspm0/build.rs
@@ -68,6 +68,7 @@ fn generate_code() {
     g.extend(generate_pin_trait_impls());
     g.extend(generate_groups());
     g.extend(generate_dma_channel_count());
+    g.extend(generate_adc_constants(&mut cfgs));
 
     let out_dir = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
     let out_file = out_dir.join("_generated.rs").to_string_lossy().to_string();
@@ -79,10 +80,14 @@ fn get_chip_cfgs(chip_name: &str) -> Vec<String> {
     let mut cfgs = Vec::new();
 
     // GPIO on C110x is special as it does not belong to an interrupt group.
-    if chip_name.starts_with("mspm0c110") || chip_name.starts_with("msps003f") {
+    if chip_name.starts_with("mspm0c1103") || chip_name.starts_with("mspm0c1104") || chip_name.starts_with("msps003f") {
         cfgs.push("mspm0c110x".to_string());
     }
 
+    if chip_name.starts_with("mspm0c1105") || chip_name.starts_with("mspm0c1106") {
+        cfgs.push("mspm0c1105_c1106".to_string());
+    }
+
     // Family ranges (temporary until int groups are generated)
     //
     // TODO: Remove this once int group stuff is generated.
@@ -216,6 +221,22 @@ fn generate_dma_channel_count() -> TokenStream {
     quote! { pub const DMA_CHANNELS: usize = #count; }
 }
 
+fn generate_adc_constants(cfgs: &mut CfgSet) -> TokenStream {
+    let vrsel = METADATA.adc_vrsel;
+    let memctl = METADATA.adc_memctl;
+
+    cfgs.declare("adc_neg_vref");
+    match vrsel {
+        3 => (),
+        5 => cfgs.enable("adc_neg_vref"),
+        _ => panic!("Unsupported ADC VRSEL value: {vrsel}"),
+    }
+    quote! {
+        pub const ADC_VRSEL: u8 = #vrsel;
+        pub const ADC_MEMCTL: u8 = #memctl;
+    }
+}
+
 #[derive(Debug, Clone)]
 struct Singleton {
     name: String,
@@ -537,6 +558,8 @@ fn generate_interrupts() -> TokenStream {
         pub fn enable_group_interrupts(_cs: critical_section::CriticalSection) {
             use crate::interrupt::typelevel::Interrupt;
 
+            // This is empty for C1105/6
+            #[allow(unused_unsafe)]
             unsafe {
                 #(#group_interrupt_enables)*
             }
@@ -555,6 +578,7 @@ fn generate_peripheral_instances() -> TokenStream {
             "uart" => Some(quote! { impl_uart_instance!(#peri); }),
             "i2c" => Some(quote! { impl_i2c_instance!(#peri, #fifo_size); }),
             "wwdt" => Some(quote! { impl_wwdt_instance!(#peri); }),
+            "adc" => Some(quote! { impl_adc_instance!(#peri); }),
             _ => None,
         };
 
@@ -603,6 +627,10 @@ fn generate_pin_trait_impls() -> TokenStream {
                 ("uart", "RTS") => Some(quote! { impl_uart_rts_pin!(#peri, #pin_name, #pf); }),
                 ("i2c", "SDA") => Some(quote! { impl_i2c_sda_pin!(#peri, #pin_name, #pf); }),
                 ("i2c", "SCL") => Some(quote! { impl_i2c_scl_pin!(#peri, #pin_name, #pf); }),
+                ("adc", s) => {
+                    let signal = s.parse::<u8>().unwrap();
+                    Some(quote! { impl_adc_pin!(#peri, #pin_name, #signal); })
+                }
 
                 _ => None,
             };
diff --git a/embassy-mspm0/src/adc.rs b/embassy-mspm0/src/adc.rs
new file mode 100644
index 000000000..5b93e9a6e
--- /dev/null
+++ b/embassy-mspm0/src/adc.rs
@@ -0,0 +1,510 @@
+#![macro_use]
+
+use core::future::poll_fn;
+use core::marker::PhantomData;
+use core::task::Poll;
+
+use embassy_hal_internal::{impl_peripheral, PeripheralType};
+use embassy_sync::waitqueue::AtomicWaker;
+
+use crate::interrupt::{Interrupt, InterruptExt};
+use crate::mode::{Async, Blocking, Mode};
+use crate::pac::adc::{vals, Adc as Regs};
+use crate::{interrupt, Peri};
+
+/// Interrupt handler.
+pub struct InterruptHandler<T: Instance> {
+    _phantom: PhantomData<T>,
+}
+
+impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
+    unsafe fn on_interrupt() {
+        // Mis is cleared upon reading iidx
+        let iidx = T::info().regs.cpu_int(0).iidx().read().stat();
+        // TODO: Running in sequence mode, we get an interrupt per finished result. It would be
+        // nice to wake up only after all results are finished.
+        if vals::CpuIntIidxStat::MEMRESIFG0 <= iidx && iidx <= vals::CpuIntIidxStat::MEMRESIFG23 {
+            T::state().waker.wake();
+        }
+    }
+}
+
+// Constants from the metapac crate
+const ADC_VRSEL: u8 = crate::_generated::ADC_VRSEL;
+const ADC_MEMCTL: u8 = crate::_generated::ADC_MEMCTL;
+
+#[derive(Clone, Copy, PartialEq, Eq, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// Conversion resolution of the ADC results.
+pub enum Resolution {
+    /// 12-bits resolution
+    BIT12,
+
+    /// 10-bits resolution
+    BIT10,
+
+    /// 8-bits resolution
+    BIT8,
+}
+
+impl Resolution {
+    /// Number of bits of the resolution.
+    pub fn bits(&self) -> u8 {
+        match self {
+            Resolution::BIT12 => 12,
+            Resolution::BIT10 => 10,
+            Resolution::BIT8 => 8,
+        }
+    }
+}
+
+#[derive(Clone, Copy, PartialEq, Eq, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// Reference voltage (Vref) selection for the ADC channels.
+pub enum Vrsel {
+    /// VDDA reference
+    VddaVssa = 0,
+
+    /// External reference from pin
+    ExtrefVrefm = 1,
+
+    /// Internal reference
+    IntrefVssa = 2,
+
+    /// VDDA and VREFM connected to VREF+ and VREF- of ADC
+    #[cfg(adc_neg_vref)]
+    VddaVrefm = 3,
+
+    /// INTREF and VREFM connected to VREF+ and VREF- of ADC
+    #[cfg(adc_neg_vref)]
+    IntrefVrefm = 4,
+}
+
+/// ADC configuration.
+#[derive(Copy, Clone)]
+#[non_exhaustive]
+pub struct Config {
+    /// Resolution of the ADC conversion. The number of bits used to represent an ADC measurement.
+    pub resolution: Resolution,
+    /// ADC voltage reference selection.
+    ///
+    /// This value is used when reading a single channel. When reading a sequence
+    /// the vr_select is provided per channel.
+    pub vr_select: Vrsel,
+    /// The sample time in number of ADC sample clock cycles.
+    pub sample_time: u16,
+}
+
+impl Default for Config {
+    fn default() -> Self {
+        Self {
+            resolution: Resolution::BIT12,
+            vr_select: Vrsel::VddaVssa,
+            sample_time: 50,
+        }
+    }
+}
+
+/// ADC (Analog to Digial Converter) Driver.
+pub struct Adc<'d, T: Instance, M: Mode> {
+    #[allow(unused)]
+    adc: crate::Peri<'d, T>,
+    info: &'static Info,
+    state: &'static State,
+    config: Config,
+    _phantom: PhantomData<M>,
+}
+
+impl<'d, T: Instance> Adc<'d, T, Blocking> {
+    /// A new blocking ADC driver instance.
+    pub fn new_blocking(peri: Peri<'d, T>, config: Config) -> Self {
+        let mut this = Self {
+            adc: peri,
+            info: T::info(),
+            state: T::state(),
+            config,
+            _phantom: PhantomData,
+        };
+        this.setup();
+        this
+    }
+}
+
+impl<'d, T: Instance> Adc<'d, T, Async> {
+    /// A new asynchronous ADC driver instance.
+    pub fn new_async(
+        peri: Peri<'d, T>,
+        config: Config,
+        _irqs: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
+    ) -> Self {
+        let mut this = Self {
+            adc: peri,
+            info: T::info(),
+            state: T::state(),
+            config,
+            _phantom: PhantomData,
+        };
+        this.setup();
+        unsafe {
+            this.info.interrupt.enable();
+        }
+        this
+    }
+}
+
+impl<'d, T: Instance, M: Mode> Adc<'d, T, M> {
+    const SINGLE_CHANNEL: u8 = 0;
+
+    fn setup(&mut self) {
+        let config = &self.config;
+        assert!(
+            (config.vr_select as u8) < ADC_VRSEL,
+            "Reference voltage selection out of bounds"
+        );
+        // Reset adc
+        self.info.regs.gprcm(0).rstctl().write(|reg| {
+            reg.set_resetstkyclr(true);
+            reg.set_resetassert(true);
+            reg.set_key(vals::ResetKey::KEY);
+        });
+
+        // Power up adc
+        self.info.regs.gprcm(0).pwren().modify(|reg| {
+            reg.set_enable(true);
+            reg.set_key(vals::PwrenKey::KEY);
+        });
+
+        // Wait for cycles similar to TI power setup
+        cortex_m::asm::delay(16);
+
+        // Set clock config
+        self.info.regs.gprcm(0).clkcfg().modify(|reg| {
+            reg.set_key(vals::ClkcfgKey::KEY);
+            reg.set_sampclk(vals::Sampclk::SYSOSC);
+        });
+        self.info.regs.ctl0().modify(|reg| {
+            reg.set_sclkdiv(vals::Sclkdiv::DIV_BY_4);
+        });
+        self.info.regs.clkfreq().modify(|reg| {
+            reg.set_frange(vals::Frange::RANGE24TO32);
+        });
+
+        // Init single conversion with software trigger and auto sampling
+        //
+        // We use sequence to support sequence operation in the future, but only set up a single
+        // channel
+        self.info.regs.ctl1().modify(|reg| {
+            reg.set_conseq(vals::Conseq::SEQUENCE);
+            reg.set_sampmode(vals::Sampmode::AUTO);
+            reg.set_trigsrc(vals::Trigsrc::SOFTWARE);
+        });
+        let res = match config.resolution {
+            Resolution::BIT12 => vals::Res::BIT_12,
+            Resolution::BIT10 => vals::Res::BIT_10,
+            Resolution::BIT8 => vals::Res::BIT_8,
+        };
+        self.info.regs.ctl2().modify(|reg| {
+            // Startadd detemines the channel used in single mode.
+            reg.set_startadd(Self::SINGLE_CHANNEL);
+            reg.set_endadd(Self::SINGLE_CHANNEL);
+            reg.set_res(res);
+            reg.set_df(false);
+        });
+
+        // Set the sample time used by all channels for now
+        self.info.regs.scomp0().modify(|reg| {
+            reg.set_val(config.sample_time);
+        });
+    }
+
+    fn setup_blocking_channel(&mut self, channel: &Peri<'d, impl AdcChannel<T>>) {
+        channel.setup();
+
+        // CTL0.ENC must be 0 to write the MEMCTL register
+        while self.info.regs.ctl0().read().enc() {
+            // Wait until the ADC is not in conversion mode
+        }
+
+        // Conversion mem config
+        let vrsel = vals::Vrsel::from_bits(self.config.vr_select as u8);
+        self.info.regs.memctl(Self::SINGLE_CHANNEL as usize).modify(|reg| {
+            reg.set_chansel(channel.channel());
+            reg.set_vrsel(vrsel);
+            reg.set_stime(vals::Stime::SEL_SCOMP0);
+            reg.set_avgen(false);
+            reg.set_bcsen(false);
+            reg.set_trig(vals::Trig::AUTO_NEXT);
+            reg.set_wincomp(false);
+        });
+        self.info.regs.ctl2().modify(|reg| {
+            // Set end address to the number of used channels
+            reg.set_endadd(Self::SINGLE_CHANNEL);
+        });
+    }
+
+    fn enable_conversion(&mut self) {
+        // Enable conversion
+        self.info.regs.ctl0().modify(|reg| {
+            reg.set_enc(true);
+        });
+    }
+
+    fn start_conversion(&mut self) {
+        // Start conversion
+        self.info.regs.ctl1().modify(|reg| {
+            reg.set_sc(vals::Sc::START);
+        });
+    }
+
+    fn conversion_result(&mut self, channel_id: usize) -> u16 {
+        // Read result
+        self.info.regs.memres(channel_id).read().data()
+    }
+
+    /// Read one ADC channel in blocking mode using the config provided at initialization.
+    pub fn blocking_read(&mut self, channel: &Peri<'d, impl AdcChannel<T>>) -> u16 {
+        self.setup_blocking_channel(channel);
+        self.enable_conversion();
+        self.start_conversion();
+
+        while self.info.regs.ctl0().read().enc() {}
+
+        self.conversion_result(Self::SINGLE_CHANNEL as usize)
+    }
+}
+
+impl<'d, T: Instance> Adc<'d, T, Async> {
+    /// Maximum length allowed for [`Self::read_sequence`].
+    pub const MAX_SEQUENCE_LEN: usize = ADC_MEMCTL as usize;
+
+    async fn wait_for_conversion(&self) {
+        let info = self.info;
+        let state = self.state;
+        poll_fn(move |cx| {
+            state.waker.register(cx.waker());
+
+            if !info.regs.ctl0().read().enc() {
+                Poll::Ready(())
+            } else {
+                Poll::Pending
+            }
+        })
+        .await;
+    }
+
+    fn setup_async_channel(&self, id: usize, channel: &Peri<'d, impl AdcChannel<T>>, vrsel: Vrsel) {
+        let vrsel = vals::Vrsel::from_bits(vrsel as u8);
+        // Conversion mem config
+        self.info.regs.memctl(id).modify(|reg| {
+            reg.set_chansel(channel.channel());
+            reg.set_vrsel(vrsel);
+            reg.set_stime(vals::Stime::SEL_SCOMP0);
+            reg.set_avgen(false);
+            reg.set_bcsen(false);
+            reg.set_trig(vals::Trig::AUTO_NEXT);
+            reg.set_wincomp(false);
+        });
+
+        // Clear interrupt status
+        self.info.regs.cpu_int(0).iclr().write(|reg| {
+            reg.set_memresifg(id, true);
+        });
+        // Enable interrupt
+        self.info.regs.cpu_int(0).imask().modify(|reg| {
+            reg.set_memresifg(id, true);
+        });
+    }
+
+    /// Read one ADC channel asynchronously using the config provided at initialization.
+    pub async fn read_channel(&mut self, channel: &Peri<'d, impl AdcChannel<T>>) -> u16 {
+        channel.setup();
+
+        // CTL0.ENC must be 0 to write the MEMCTL register
+        self.wait_for_conversion().await;
+
+        self.info.regs.ctl2().modify(|reg| {
+            // Set end address to the number of used channels
+            reg.set_endadd(Self::SINGLE_CHANNEL);
+        });
+
+        self.setup_async_channel(Self::SINGLE_CHANNEL as usize, channel, self.config.vr_select);
+
+        self.enable_conversion();
+        self.start_conversion();
+        self.wait_for_conversion().await;
+
+        self.conversion_result(Self::SINGLE_CHANNEL as usize)
+    }
+
+    /// Read one or multiple ADC channels using the Vrsel provided per channel.
+    ///
+    /// `sequence` iterator and `readings` must have the same length.
+    ///
+    /// Example
+    /// ```rust,ignore
+    /// use embassy_mspm0::adc::{Adc, AdcChannel, Vrsel};
+    ///
+    /// let mut adc = Adc::new_async(p.ADC0, adc_config, Irqs);
+    /// let sequence = [(&p.PA22.into(), Vrsel::VddaVssa), (&p.PA20.into(), Vrsel::VddaVssa)];
+    /// let mut readings = [0u16; 2];
+    ///
+    /// adc.read_sequence(sequence.into_iter(), &mut readings).await;
+    /// defmt::info!("Measurements: {}", readings);
+    /// ```
+    pub async fn read_sequence<'a>(
+        &mut self,
+        sequence: impl ExactSizeIterator<Item = (&'a Peri<'d, AnyAdcChannel<T>>, Vrsel)>,
+        readings: &mut [u16],
+    ) where
+        'd: 'a,
+    {
+        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
+        assert!(
+            sequence.len() == readings.len(),
+            "Sequence length must be equal to readings length"
+        );
+        assert!(
+            sequence.len() <= Self::MAX_SEQUENCE_LEN,
+            "Asynchronous read sequence cannot be more than {} in length",
+            Self::MAX_SEQUENCE_LEN
+        );
+
+        // CTL0.ENC must be 0 to write the MEMCTL register
+        self.wait_for_conversion().await;
+
+        self.info.regs.ctl2().modify(|reg| {
+            // Set end address to the number of used channels
+            reg.set_endadd((sequence.len() - 1) as u8);
+        });
+
+        for (i, (channel, vrsel)) in sequence.enumerate() {
+            self.setup_async_channel(i, channel, vrsel);
+        }
+        self.enable_conversion();
+        self.start_conversion();
+        self.wait_for_conversion().await;
+
+        for (i, r) in readings.iter_mut().enumerate() {
+            *r = self.conversion_result(i);
+        }
+    }
+}
+
+/// Peripheral instance trait.
+#[allow(private_bounds)]
+pub trait Instance: PeripheralType + SealedInstance {
+    type Interrupt: crate::interrupt::typelevel::Interrupt;
+}
+
+/// Peripheral state.
+pub(crate) struct State {
+    waker: AtomicWaker,
+}
+
+impl State {
+    pub const fn new() -> Self {
+        Self {
+            waker: AtomicWaker::new(),
+        }
+    }
+}
+
+/// Peripheral information.
+pub(crate) struct Info {
+    pub(crate) regs: Regs,
+    pub(crate) interrupt: Interrupt,
+}
+
+/// Peripheral instance trait.
+pub(crate) trait SealedInstance {
+    fn info() -> &'static Info;
+    fn state() -> &'static State;
+}
+
+macro_rules! impl_adc_instance {
+    ($instance: ident) => {
+        impl crate::adc::SealedInstance for crate::peripherals::$instance {
+            fn info() -> &'static crate::adc::Info {
+                use crate::adc::Info;
+                use crate::interrupt::typelevel::Interrupt;
+
+                static INFO: Info = Info {
+                    regs: crate::pac::$instance,
+                    interrupt: crate::interrupt::typelevel::$instance::IRQ,
+                };
+                &INFO
+            }
+
+            fn state() -> &'static crate::adc::State {
+                use crate::adc::State;
+
+                static STATE: State = State::new();
+                &STATE
+            }
+        }
+
+        impl crate::adc::Instance for crate::peripherals::$instance {
+            type Interrupt = crate::interrupt::typelevel::$instance;
+        }
+    };
+}
+
+/// A type-erased channel for a given ADC instance.
+///
+/// This is useful in scenarios where you need the ADC channels to have the same type, such as
+/// storing them in an array.
+pub struct AnyAdcChannel<T> {
+    pub(crate) channel: u8,
+    pub(crate) _phantom: PhantomData<T>,
+}
+
+impl_peripheral!(AnyAdcChannel<T: Instance>);
+impl<T: Instance> AdcChannel<T> for AnyAdcChannel<T> {}
+impl<T: Instance> SealedAdcChannel<T> for AnyAdcChannel<T> {
+    fn channel(&self) -> u8 {
+        self.channel
+    }
+}
+
+impl<T> AnyAdcChannel<T> {
+    #[allow(unused)]
+    pub(crate) fn get_hw_channel(&self) -> u8 {
+        self.channel
+    }
+}
+
+/// ADC channel.
+#[allow(private_bounds)]
+pub trait AdcChannel<T>: PeripheralType + Into<AnyAdcChannel<T>> + SealedAdcChannel<T> + Sized {}
+
+pub(crate) trait SealedAdcChannel<T> {
+    fn setup(&self) {}
+
+    fn channel(&self) -> u8;
+}
+
+macro_rules! impl_adc_pin {
+    ($inst: ident, $pin: ident, $ch: expr) => {
+        impl crate::adc::AdcChannel<peripherals::$inst> for crate::peripherals::$pin {}
+        impl crate::adc::SealedAdcChannel<peripherals::$inst> for crate::peripherals::$pin {
+            fn setup(&self) {
+                crate::gpio::SealedPin::set_as_analog(self);
+            }
+
+            fn channel(&self) -> u8 {
+                $ch
+            }
+        }
+
+        impl From<crate::peripherals::$pin> for crate::adc::AnyAdcChannel<peripherals::$inst> {
+            fn from(val: crate::peripherals::$pin) -> Self {
+                crate::adc::SealedAdcChannel::<peripherals::$inst>::setup(&val);
+
+                Self {
+                    channel: crate::adc::SealedAdcChannel::<peripherals::$inst>::channel(&val),
+                    _phantom: core::marker::PhantomData,
+                }
+            }
+        }
+    };
+}
diff --git a/embassy-mspm0/src/gpio.rs b/embassy-mspm0/src/gpio.rs
index f77848888..d5fd36dbf 100644
--- a/embassy-mspm0/src/gpio.rs
+++ b/embassy-mspm0/src/gpio.rs
@@ -10,7 +10,7 @@ use embassy_sync::waitqueue::AtomicWaker;
 
 use crate::pac::gpio::vals::*;
 use crate::pac::gpio::{self};
-#[cfg(all(feature = "rt", any(mspm0c110x, mspm0l110x)))]
+#[cfg(all(feature = "rt", any(mspm0c110x, mspm0c1105_c1106, mspm0l110x)))]
 use crate::pac::interrupt;
 use crate::pac::{self};
 
@@ -1108,24 +1108,30 @@ fn irq_handler(gpio: gpio::Gpio, wakers: &[AtomicWaker; 32]) {
 // C110x and L110x have a dedicated interrupts just for GPIOA.
 //
 // These chips do not have a GROUP1 interrupt.
-#[cfg(all(feature = "rt", any(mspm0c110x, mspm0l110x)))]
+#[cfg(all(feature = "rt", any(mspm0c110x, mspm0c1105_c1106, mspm0l110x)))]
 #[interrupt]
 fn GPIOA() {
     irq_handler(pac::GPIOA, &PORTA_WAKERS);
 }
 
+#[cfg(all(feature = "rt", mspm0c1105_c1106))]
+#[interrupt]
+fn GPIOB() {
+    irq_handler(pac::GPIOB, &PORTB_WAKERS);
+}
+
 // These symbols are weakly defined as DefaultHandler and are called by the interrupt group implementation.
 //
 // Defining these as no_mangle is required so that the linker will pick these over the default handler.
 
-#[cfg(all(feature = "rt", not(any(mspm0c110x, mspm0l110x))))]
+#[cfg(all(feature = "rt", not(any(mspm0c110x, mspm0c1105_c1106, mspm0l110x))))]
 #[no_mangle]
 #[allow(non_snake_case)]
 fn GPIOA() {
     irq_handler(pac::GPIOA, &PORTA_WAKERS);
 }
 
-#[cfg(all(feature = "rt", gpio_pb))]
+#[cfg(all(feature = "rt", gpio_pb, not(mspm0c1105_c1106)))]
 #[no_mangle]
 #[allow(non_snake_case)]
 fn GPIOB() {
diff --git a/embassy-mspm0/src/i2c.rs b/embassy-mspm0/src/i2c.rs
index 7e22bb724..1906e37ba 100644
--- a/embassy-mspm0/src/i2c.rs
+++ b/embassy-mspm0/src/i2c.rs
@@ -195,7 +195,7 @@ impl Config {
             .unwrap();
     }
 
-    #[cfg(any(mspm0c110x))]
+    #[cfg(any(mspm0c110x, mspm0c1105_c1106))]
     fn calculate_clock_source(&self) -> u32 {
         // Assume that BusClk has default value.
         // TODO: calculate BusClk more precisely.
diff --git a/embassy-mspm0/src/lib.rs b/embassy-mspm0/src/lib.rs
index 0cb19a379..13f0ce662 100644
--- a/embassy-mspm0/src/lib.rs
+++ b/embassy-mspm0/src/lib.rs
@@ -13,6 +13,7 @@ pub(crate) mod fmt;
 // This must be declared early as well for
 mod macros;
 
+pub mod adc;
 pub mod dma;
 pub mod gpio;
 pub mod i2c;
diff --git a/embassy-net-wiznet/CHANGELOG.md b/embassy-net-wiznet/CHANGELOG.md
index e464efa69..a74dc3125 100644
--- a/embassy-net-wiznet/CHANGELOG.md
+++ b/embassy-net-wiznet/CHANGELOG.md
@@ -8,6 +8,9 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 <!-- next-header -->
 ## Unreleased - ReleaseDate
 
+- Added experimental W6100 driver with disabled MAC filter (does not currently work with it enabled)
+- Introduced `SOCKET_INTR_CLR` register which is needed on W6100 and later models (on W5100/W5500 this is shared with `SOCKET_INTR` and the address is the same)
+
 ## 0.2.1 - 2025-08-26
 
 ## 0.1.1 - 2025-08-14
diff --git a/embassy-net-wiznet/src/chip/mod.rs b/embassy-net-wiznet/src/chip/mod.rs
index 2e7a9ed6c..47d7c5dc3 100644
--- a/embassy-net-wiznet/src/chip/mod.rs
+++ b/embassy-net-wiznet/src/chip/mod.rs
@@ -4,6 +4,8 @@ pub use w5500::W5500;
 mod w5100s;
 use embedded_hal_async::spi::SpiDevice;
 pub use w5100s::W5100S;
+mod w6100;
+pub use w6100::W6100;
 
 pub(crate) trait SealedChip {
     type Address;
@@ -28,7 +30,9 @@ pub(crate) trait SealedChip {
     const SOCKET_RECVD_SIZE: Self::Address;
     const SOCKET_RX_DATA_READ_PTR: Self::Address;
     const SOCKET_INTR_MASK: Self::Address;
+    #[allow(dead_code)]
     const SOCKET_INTR: Self::Address;
+    const SOCKET_INTR_CLR: Self::Address;
 
     const SOCKET_MODE_VALUE: u8;
 
diff --git a/embassy-net-wiznet/src/chip/w5100s.rs b/embassy-net-wiznet/src/chip/w5100s.rs
index 4c4b7ab16..1eef2369e 100644
--- a/embassy-net-wiznet/src/chip/w5100s.rs
+++ b/embassy-net-wiznet/src/chip/w5100s.rs
@@ -29,6 +29,7 @@ impl super::SealedChip for W5100S {
     const SOCKET_RX_DATA_READ_PTR: Self::Address = SOCKET_BASE + 0x28;
     const SOCKET_INTR_MASK: Self::Address = SOCKET_BASE + 0x2C;
     const SOCKET_INTR: Self::Address = SOCKET_BASE + 0x02;
+    const SOCKET_INTR_CLR: Self::Address = SOCKET_BASE + 0x02;
 
     const SOCKET_MODE_VALUE: u8 = (1 << 2) | (1 << 6);
 
diff --git a/embassy-net-wiznet/src/chip/w5500.rs b/embassy-net-wiznet/src/chip/w5500.rs
index 5cfcb94e4..198ba3226 100644
--- a/embassy-net-wiznet/src/chip/w5500.rs
+++ b/embassy-net-wiznet/src/chip/w5500.rs
@@ -33,6 +33,7 @@ impl super::SealedChip for W5500 {
     const SOCKET_RX_DATA_READ_PTR: Self::Address = (RegisterBlock::Socket0, 0x28);
     const SOCKET_INTR_MASK: Self::Address = (RegisterBlock::Socket0, 0x2C);
     const SOCKET_INTR: Self::Address = (RegisterBlock::Socket0, 0x02);
+    const SOCKET_INTR_CLR: Self::Address = (RegisterBlock::Socket0, 0x02);
 
     const SOCKET_MODE_VALUE: u8 = (1 << 2) | (1 << 7);
 
diff --git a/embassy-net-wiznet/src/chip/w6100.rs b/embassy-net-wiznet/src/chip/w6100.rs
new file mode 100644
index 000000000..740b0edaf
--- /dev/null
+++ b/embassy-net-wiznet/src/chip/w6100.rs
@@ -0,0 +1,83 @@
+use embedded_hal_async::spi::{Operation, SpiDevice};
+
+#[repr(u8)]
+pub enum RegisterBlock {
+    Common = 0x00,
+    Socket0 = 0x01,
+    TxBuf = 0x02,
+    RxBuf = 0x03,
+}
+
+/// Wiznet W6100 chip.
+pub enum W6100 {}
+
+impl super::Chip for W6100 {}
+impl super::SealedChip for W6100 {
+    type Address = (RegisterBlock, u16);
+
+    const CHIP_VERSION: u8 = 0x46;
+
+    const COMMON_MODE: Self::Address = (RegisterBlock::Common, 0x2004);
+    const COMMON_MAC: Self::Address = (RegisterBlock::Common, 0x4120);
+    // SIMR (SOCKET Interrupt Mask Register)
+    const COMMON_SOCKET_INTR: Self::Address = (RegisterBlock::Common, 0x2114);
+    const COMMON_PHY_CFG: Self::Address = (RegisterBlock::Common, 0x3000);
+    const COMMON_VERSION: Self::Address = (RegisterBlock::Common, 0x0002);
+
+    const SOCKET_MODE: Self::Address = (RegisterBlock::Socket0, 0x0000);
+    const SOCKET_COMMAND: Self::Address = (RegisterBlock::Socket0, 0x0010);
+    const SOCKET_RXBUF_SIZE: Self::Address = (RegisterBlock::Socket0, 0x0220);
+    const SOCKET_TXBUF_SIZE: Self::Address = (RegisterBlock::Socket0, 0x0200);
+    const SOCKET_TX_FREE_SIZE: Self::Address = (RegisterBlock::Socket0, 0x0204);
+    const SOCKET_TX_DATA_WRITE_PTR: Self::Address = (RegisterBlock::Socket0, 0x020C);
+    const SOCKET_RECVD_SIZE: Self::Address = (RegisterBlock::Socket0, 0x0224);
+    const SOCKET_RX_DATA_READ_PTR: Self::Address = (RegisterBlock::Socket0, 0x0228);
+    // Sn_IMR (SOCKET n Interrupt Mask Register)
+    const SOCKET_INTR_MASK: Self::Address = (RegisterBlock::Socket0, 0x0024);
+    // Sn_IR (SOCKET n Interrupt Register)
+    const SOCKET_INTR: Self::Address = (RegisterBlock::Socket0, 0x0020);
+    // Sn_IRCLR (Sn_IR Clear Register)
+    const SOCKET_INTR_CLR: Self::Address = (RegisterBlock::Socket0, 0x0028);
+
+    // MACRAW mode. See Page 57 of https://docs.wiznet.io/img/products/w6100/w6100_ds_v105e.pdf
+    // Note: Bit 7 is MAC filter. On the W5500 this is normally turned ON however the W6100 will not successfully retrieve an IP address with this enabled. Disabling for now and will have live with the extra noise.
+    const SOCKET_MODE_VALUE: u8 = 0b0000_0111;
+
+    const BUF_SIZE: u16 = 0x1000;
+    const AUTO_WRAP: bool = true;
+
+    fn rx_addr(addr: u16) -> Self::Address {
+        (RegisterBlock::RxBuf, addr)
+    }
+
+    fn tx_addr(addr: u16) -> Self::Address {
+        (RegisterBlock::TxBuf, addr)
+    }
+
+    async fn bus_read<SPI: SpiDevice>(
+        spi: &mut SPI,
+        address: Self::Address,
+        data: &mut [u8],
+    ) -> Result<(), SPI::Error> {
+        let address_phase = address.1.to_be_bytes();
+        let control_phase = [(address.0 as u8) << 3];
+        let operations = &mut [
+            Operation::Write(&address_phase),
+            Operation::Write(&control_phase),
+            Operation::TransferInPlace(data),
+        ];
+        spi.transaction(operations).await
+    }
+
+    async fn bus_write<SPI: SpiDevice>(spi: &mut SPI, address: Self::Address, data: &[u8]) -> Result<(), SPI::Error> {
+        let address_phase = address.1.to_be_bytes();
+        let control_phase = [(address.0 as u8) << 3 | 0b0000_0100];
+        let data_phase = data;
+        let operations = &mut [
+            Operation::Write(&address_phase[..]),
+            Operation::Write(&control_phase),
+            Operation::Write(&data_phase),
+        ];
+        spi.transaction(operations).await
+    }
+}
diff --git a/embassy-net-wiznet/src/device.rs b/embassy-net-wiznet/src/device.rs
index d2b6bb0c3..8ef92b022 100644
--- a/embassy-net-wiznet/src/device.rs
+++ b/embassy-net-wiznet/src/device.rs
@@ -125,7 +125,7 @@ impl<C: Chip, SPI: SpiDevice> WiznetDevice<C, SPI> {
 
     async fn reset_interrupt(&mut self, code: Interrupt) -> Result<(), SPI::Error> {
         let data = [code as u8];
-        self.bus_write(C::SOCKET_INTR, &data).await
+        self.bus_write(C::SOCKET_INTR_CLR, &data).await
     }
 
     async fn get_tx_write_ptr(&mut self) -> Result<u16, SPI::Error> {
diff --git a/embassy-net/Cargo.toml b/embassy-net/Cargo.toml
index 245626c14..61a2c858a 100644
--- a/embassy-net/Cargo.toml
+++ b/embassy-net/Cargo.toml
@@ -26,6 +26,19 @@ build = [
     {target = "thumbv7em-none-eabi", features = ["defmt", "dns", "medium-ip", "proto-ipv4", "proto-ipv6", "tcp", "udp"]},
     {target = "thumbv7em-none-eabi", features = ["defmt", "dns", "medium-ethernet", "medium-ip", "proto-ipv4", "proto-ipv6", "tcp", "udp"]},
     {target = "thumbv7em-none-eabi", features = ["defmt", "dns", "medium-ethernet", "medium-ieee802154", "medium-ip", "proto-ipv4", "proto-ipv6", "tcp", "udp"]},
+    # Xtensa builds
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32-none-elf", features = ["defmt", "tcp", "udp", "dns", "proto-ipv4", "medium-ethernet", "packet-trace"]},
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32-none-elf", features = ["defmt", "tcp", "udp", "dns", "proto-ipv4", "multicast", "medium-ethernet"]},
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32-none-elf", features = ["defmt", "tcp", "udp", "dns", "dhcpv4", "medium-ethernet"]},
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32-none-elf", features = ["defmt", "tcp", "udp", "dns", "dhcpv4", "medium-ethernet", "dhcpv4-hostname"]},
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32-none-elf", features = ["defmt", "tcp", "udp", "dns", "proto-ipv6", "medium-ethernet"]},
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32-none-elf", features = ["defmt", "tcp", "udp", "dns", "proto-ipv6", "medium-ieee802154"]},
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32-none-elf", features = ["defmt", "tcp", "udp", "dns", "proto-ipv6", "medium-ethernet", "medium-ieee802154"]},
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32-none-elf", features = ["defmt", "tcp", "udp", "dns", "proto-ipv6", "medium-ethernet"]},
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32-none-elf", features = ["defmt", "tcp", "udp", "dns", "proto-ipv4", "proto-ipv6", "medium-ethernet"]},
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32-none-elf", features = ["defmt", "tcp", "udp", "dns", "proto-ipv4", "proto-ipv6", "medium-ip"]},
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32-none-elf", features = ["defmt", "tcp", "udp", "dns", "proto-ipv4", "proto-ipv6", "medium-ip", "medium-ethernet"]},
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32-none-elf", features = ["defmt", "tcp", "udp", "dns", "proto-ipv4", "proto-ipv6", "medium-ip", "medium-ethernet", "medium-ieee802154"]},
 ]
 
 [package.metadata.embassy_docs]
diff --git a/embassy-net/README.md b/embassy-net/README.md
index 1722ffc7b..1c5b30a9c 100644
--- a/embassy-net/README.md
+++ b/embassy-net/README.md
@@ -25,6 +25,7 @@ unimplemented features of the network protocols.
 - [`embassy-stm32`](https://github.com/embassy-rs/embassy/tree/main/embassy-stm32) for the builtin Ethernet MAC in all STM32 chips (STM32F1, STM32F2, STM32F4, STM32F7, STM32H7, STM32H5).
 - [`embassy-net-wiznet`](https://github.com/embassy-rs/embassy/tree/main/embassy-net-wiznet) for Wiznet SPI Ethernet MAC+PHY chips (W5100S, W5500)
 - [`embassy-net-esp-hosted`](https://github.com/embassy-rs/embassy/tree/main/embassy-net-esp-hosted) for using ESP32 chips with the [`esp-hosted`](https://github.com/espressif/esp-hosted) firmware as WiFi adapters for another non-ESP32 MCU.
+- [`embassy-nrf`](https://github.com/embassy-rs/embassy/tree/main/embassy-nrf) for IEEE 802.15.4 support on nrf chips.
 
 ## Examples
 
diff --git a/embassy-nrf/CHANGELOG.md b/embassy-nrf/CHANGELOG.md
index 5dc941b25..befa34ecf 100644
--- a/embassy-nrf/CHANGELOG.md
+++ b/embassy-nrf/CHANGELOG.md
@@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ## Unreleased - ReleaseDate
 
 - changed: nrf54l: Disable glitch detection and enable DC/DC in init.
+- changed: Add embassy-net-driver-channel implementation for IEEE 802.15.4
 
 ## 0.7.0 - 2025-08-26
 
diff --git a/embassy-nrf/Cargo.toml b/embassy-nrf/Cargo.toml
index 2ce75cfac..4afd28fbd 100644
--- a/embassy-nrf/Cargo.toml
+++ b/embassy-nrf/Cargo.toml
@@ -79,6 +79,9 @@ gpiote = []
 ## Use RTC1 as the time driver for `embassy-time`, with a tick rate of 32.768khz
 time-driver-rtc1 = ["_time-driver"]
 
+## Enable embassy-net 802.15.4 driver
+net-driver = ["_net-driver"]
+
 ## Allow using the NFC pins as regular GPIO pins (P0_09/P0_10 on nRF52, P0_02/P0_03 on nRF53)
 nfc-pins-as-gpio = []
 
@@ -154,6 +157,8 @@ _nrf91 = []
 
 _time-driver = ["dep:embassy-time-driver", "embassy-time-driver?/tick-hz-32_768", "dep:embassy-time-queue-utils", "embassy-embedded-hal/time"]
 
+_net-driver = ["dep:embassy-net-driver-channel","dep:embassy-futures"]
+
 # trustzone state.
 _s = []
 _ns = []
@@ -177,6 +182,8 @@ embassy-sync = { version = "0.7.2", path = "../embassy-sync" }
 embassy-hal-internal = { version = "0.3.0", path = "../embassy-hal-internal", features = ["cortex-m", "prio-bits-3"] }
 embassy-embedded-hal = { version = "0.5.0", path = "../embassy-embedded-hal", default-features = false }
 embassy-usb-driver = { version = "0.2.0", path = "../embassy-usb-driver" }
+embassy-net-driver-channel = { version = "0.3.2", path = "../embassy-net-driver-channel", optional = true}
+embassy-futures = { version = "0.1.2", path = "../embassy-futures", optional = true}
 
 embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
 embedded-hal-1 = { package = "embedded-hal", version = "1.0" }
diff --git a/embassy-nrf/README.md b/embassy-nrf/README.md
index 3df5f1fa5..26b1fa5ea 100644
--- a/embassy-nrf/README.md
+++ b/embassy-nrf/README.md
@@ -28,6 +28,10 @@ allows running Rust code without a SPM or TF-M binary, saving flash space and si
 
 If the `time-driver-rtc1` feature is enabled, the HAL uses the RTC peripheral as a global time driver for [embassy-time](https://crates.io/crates/embassy-time), with a tick rate of 32768 Hz.
 
+## Embassy-net-driver
+
+If the board supports IEEE 802.15.4 (see `src/radio/mod.rs`) the corresponding [embassy-net-driver](https://crates.io/crates/embassy-net-driver) implementation can be enabled with the feature `net-driver`.
+
 ## Embedded-hal
 
 The `embassy-nrf` HAL implements the traits from [embedded-hal](https://crates.io/crates/embedded-hal) (v0.2 and 1.0) and [embedded-hal-async](https://crates.io/crates/embedded-hal-async), as well as [embedded-io](https://crates.io/crates/embedded-io) and [embedded-io-async](https://crates.io/crates/embedded-io-async).
diff --git a/embassy-nrf/src/embassy_net_802154_driver.rs b/embassy-nrf/src/embassy_net_802154_driver.rs
new file mode 100644
index 000000000..8662be787
--- /dev/null
+++ b/embassy-nrf/src/embassy_net_802154_driver.rs
@@ -0,0 +1,96 @@
+//! embassy-net IEEE 802.15.4 driver
+
+use embassy_futures::select::{select3, Either3};
+use embassy_net_driver_channel::driver::LinkState;
+use embassy_net_driver_channel::{self as ch};
+use embassy_time::{Duration, Ticker};
+
+use crate::radio::ieee802154::{Packet, Radio};
+use crate::radio::InterruptHandler;
+use crate::{self as nrf, interrupt};
+
+/// MTU for the nrf radio.
+pub const MTU: usize = Packet::CAPACITY as usize;
+
+/// embassy-net device for the driver.
+pub type Device<'d> = embassy_net_driver_channel::Device<'d, MTU>;
+
+/// Internal state for the embassy-net driver.
+pub struct State<const N_RX: usize, const N_TX: usize> {
+    ch_state: ch::State<MTU, N_RX, N_TX>,
+}
+
+impl<const N_RX: usize, const N_TX: usize> State<N_RX, N_TX> {
+    /// Create a new `State`.
+    pub const fn new() -> Self {
+        Self {
+            ch_state: ch::State::new(),
+        }
+    }
+}
+
+/// Background runner for the driver.
+///
+/// You must call `.run()` in a background task for the driver to operate.
+pub struct Runner<'d, T: nrf::radio::Instance> {
+    radio: nrf::radio::ieee802154::Radio<'d, T>,
+    ch: ch::Runner<'d, MTU>,
+}
+
+impl<'d, T: nrf::radio::Instance> Runner<'d, T> {
+    /// Drives the radio. Needs to run to use the driver.
+    pub async fn run(mut self) -> ! {
+        let (state_chan, mut rx_chan, mut tx_chan) = self.ch.split();
+        let mut tick = Ticker::every(Duration::from_millis(500));
+        let mut packet = Packet::new();
+        state_chan.set_link_state(LinkState::Up);
+        loop {
+            match select3(
+                async {
+                    let rx_buf = rx_chan.rx_buf().await;
+                    self.radio.receive(&mut packet).await.ok().map(|_| rx_buf)
+                },
+                tx_chan.tx_buf(),
+                tick.next(),
+            )
+            .await
+            {
+                Either3::First(Some(rx_buf)) => {
+                    let len = rx_buf.len().min(packet.len() as usize);
+                    (&mut rx_buf[..len]).copy_from_slice(&*packet);
+                    rx_chan.rx_done(len);
+                }
+                Either3::Second(tx_buf) => {
+                    let len = tx_buf.len().min(Packet::CAPACITY as usize);
+                    packet.copy_from_slice(&tx_buf[..len]);
+                    self.radio.try_send(&mut packet).await.ok().unwrap();
+                    tx_chan.tx_done();
+                }
+                _ => {}
+            }
+        }
+    }
+}
+
+/// Make sure to use `HfclkSource::ExternalXtal` as the `hfclk_source`
+/// to use the radio (nrf52840 product spec v1.11 5.4.1)
+/// ```
+/// # use embassy_nrf::config::*;
+/// let mut config = Config::default();
+/// config.hfclk_source = HfclkSource::ExternalXtal;
+/// ```
+pub async fn new<'a, const N_RX: usize, const N_TX: usize, T: nrf::radio::Instance, Irq>(
+    mac_addr: [u8; 8],
+    radio: nrf::Peri<'a, T>,
+    irq: Irq,
+    state: &'a mut State<N_RX, N_TX>,
+) -> Result<(Device<'a>, Runner<'a, T>), ()>
+where
+    Irq: interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'a,
+{
+    let radio = Radio::new(radio, irq);
+
+    let (runner, device) = ch::new(&mut state.ch_state, ch::driver::HardwareAddress::Ieee802154(mac_addr));
+
+    Ok((device, Runner { ch: runner, radio }))
+}
diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index aa4801897..897e660b8 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -137,6 +137,17 @@ pub mod qspi;
 #[cfg(not(feature = "_nrf54l"))] // TODO
 #[cfg(not(any(feature = "_nrf91", feature = "_nrf5340-app")))]
 pub mod radio;
+
+#[cfg(any(
+    feature = "nrf52811",
+    feature = "nrf52820",
+    feature = "nrf52833",
+    feature = "nrf52840",
+    feature = "_nrf5340-net"
+))]
+#[cfg(feature = "_net-driver")]
+pub mod embassy_net_802154_driver;
+
 #[cfg(not(feature = "_nrf54l"))] // TODO
 #[cfg(feature = "_nrf5340")]
 pub mod reset;
diff --git a/embassy-nxp/CHANGELOG.md b/embassy-nxp/CHANGELOG.md
index 7042ad14c..ab97c4185 100644
--- a/embassy-nxp/CHANGELOG.md
+++ b/embassy-nxp/CHANGELOG.md
@@ -7,5 +7,5 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 <!-- next-header -->
 ## Unreleased - ReleaseDate
-
+- Moved NXP LPC55S69 from `lpc55-pac` to `nxp-pac`
 - First release with changelog.
diff --git a/embassy-nxp/Cargo.toml b/embassy-nxp/Cargo.toml
index ab0bfbfd7..455915f29 100644
--- a/embassy-nxp/Cargo.toml
+++ b/embassy-nxp/Cargo.toml
@@ -7,7 +7,7 @@ publish = false
 
 [package.metadata.embassy]
 build = [
-    {target = "thumbv8m.main-none-eabihf", features = ["defmt", "lpc55"]},
+    {target = "thumbv8m.main-none-eabihf", features = ["defmt", "lpc55-core0"]},
     {target = "thumbv7em-none-eabihf", features = ["defmt", "mimxrt1011", "rt", "time-driver-pit"]},
     {target = "thumbv7em-none-eabihf", features = ["defmt", "mimxrt1062", "rt", "time-driver-pit"]},
 ]
@@ -18,7 +18,7 @@ src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-nxp/s
 features = ["defmt", "unstable-pac" ] # TODO: Add time-driver-any, as both lpc55 and mimxrt1xxx use different drivers.
 
 flavors = [
-    { regex_feature = "lpc55", target = "thumbv8m.main-none-eabihf" },
+    { regex_feature = "lpc55-core0", target = "thumbv8m.main-none-eabihf" },
     { regex_feature = "mimxrt.*", target = "thumbv7em-none-eabihf" },
 ]
 
@@ -36,21 +36,20 @@ embassy-time-queue-utils = { version = "0.3.0", path = "../embassy-time-queue-ut
 embedded-io = "0.6.1"
 embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
 ## Chip dependencies
-lpc55-pac = { version = "0.5.0", optional = true }
-nxp-pac = { version = "0.1.0", optional = true, git = "https://github.com/i509VCB/nxp-pac", rev = "be4dd0936c20d5897364a381b1d95a99514c1e7e" }
+nxp-pac = { version = "0.1.0", optional = true, git = "https://github.com/i509VCB/nxp-pac", rev = "b736e3038254d593024aaa1a5a7b1f95a5728538"}
 
 imxrt-rt = { version = "0.1.7", optional = true, features = ["device"] }
 
 [build-dependencies]
 cfg_aliases = "0.2.1"
-nxp-pac = { version = "0.1.0", git = "https://github.com/i509VCB/nxp-pac", rev = "be4dd0936c20d5897364a381b1d95a99514c1e7e", features = ["metadata"], optional = true }
+nxp-pac = { version = "0.1.0", git = "https://github.com/i509VCB/nxp-pac", rev = "b736e3038254d593024aaa1a5a7b1f95a5728538", features = ["metadata"], optional = true }
 proc-macro2 = "1.0.95"
 quote = "1.0.15"
 
 [features]
 default = ["rt"]
 # Enable PACs as optional dependencies, since some chip families will use different pac crates (temporarily).
-rt = ["lpc55-pac?/rt", "nxp-pac?/rt"]
+rt = ["nxp-pac?/rt"]
 
 ## Enable [defmt support](https://docs.rs/defmt) and enables `defmt` debug-log messages and formatting in embassy drivers.
 defmt = ["dep:defmt", "embassy-hal-internal/defmt", "embassy-sync/defmt"]
@@ -79,6 +78,6 @@ _rt1xxx = []
 _time_driver = ["dep:embassy-time-driver", "dep:embassy-time-queue-utils"]
 
 #! ### Chip selection features
-lpc55 = ["dep:lpc55-pac"]
+lpc55-core0 = ["nxp-pac/lpc55s69_cm33_core0"]
 mimxrt1011 = ["nxp-pac/mimxrt1011", "_rt1xxx", "dep:imxrt-rt"]
 mimxrt1062 = ["nxp-pac/mimxrt1062", "_rt1xxx", "dep:imxrt-rt"]
diff --git a/embassy-nxp/src/chips/lpc55.rs b/embassy-nxp/src/chips/lpc55.rs
index e168ced00..711bff3e7 100644
--- a/embassy-nxp/src/chips/lpc55.rs
+++ b/embassy-nxp/src/chips/lpc55.rs
@@ -1,4 +1,4 @@
-pub use lpc55_pac as pac;
+pub use nxp_pac as pac;
 
 embassy_hal_internal::peripherals! {
     // External pins. These are not only GPIOs, they are multi-purpose pins and can be used by other
diff --git a/embassy-nxp/src/gpio.rs b/embassy-nxp/src/gpio.rs
index 3049cc12d..717b38d96 100644
--- a/embassy-nxp/src/gpio.rs
+++ b/embassy-nxp/src/gpio.rs
@@ -1,7 +1,7 @@
 //! General purpose input/output (GPIO) driver.
 #![macro_use]
 
-#[cfg_attr(feature = "lpc55", path = "./gpio/lpc55.rs")]
+#[cfg_attr(feature = "lpc55-core0", path = "./gpio/lpc55.rs")]
 #[cfg_attr(rt1xxx, path = "./gpio/rt1xxx.rs")]
 mod inner;
 pub use inner::*;
diff --git a/embassy-nxp/src/gpio/lpc55.rs b/embassy-nxp/src/gpio/lpc55.rs
index 8f407bb3a..36ea99d21 100644
--- a/embassy-nxp/src/gpio/lpc55.rs
+++ b/embassy-nxp/src/gpio/lpc55.rs
@@ -1,12 +1,17 @@
 use embassy_hal_internal::{impl_peripheral, PeripheralType};
 
+use crate::pac::iocon::vals::{PioDigimode, PioMode};
+use crate::pac::{GPIO, IOCON, SYSCON};
 use crate::{peripherals, Peri};
 
 pub(crate) fn init() {
     // Enable clocks for GPIO, PINT, and IOCON
-    syscon_reg()
-        .ahbclkctrl0
-        .modify(|_, w| w.gpio0().enable().gpio1().enable().mux().enable().iocon().enable());
+    SYSCON.ahbclkctrl0().modify(|w| {
+        w.set_gpio0(true);
+        w.set_gpio1(true);
+        w.set_mux(true);
+        w.set_iocon(true);
+    });
     info!("GPIO initialized");
 }
 
@@ -59,21 +64,24 @@ impl<'d> Output<'d> {
     }
 
     pub fn set_high(&mut self) {
-        gpio_reg().set[self.pin.pin_bank() as usize].write(|w| unsafe { w.bits(self.pin.bit()) })
+        GPIO.set(self.pin.pin_bank() as usize)
+            .write(|w| w.set_setp(self.pin.bit()));
     }
 
     pub fn set_low(&mut self) {
-        gpio_reg().clr[self.pin.pin_bank() as usize].write(|w| unsafe { w.bits(self.pin.bit()) })
+        GPIO.clr(self.pin.pin_bank() as usize)
+            .write(|w| w.set_clrp(self.pin.bit()));
     }
 
     pub fn toggle(&mut self) {
-        gpio_reg().not[self.pin.pin_bank() as usize].write(|w| unsafe { w.bits(self.pin.bit()) })
+        GPIO.not(self.pin.pin_bank() as usize)
+            .write(|w| w.set_notp(self.pin.bit()));
     }
 
     /// Get the current output level of the pin. Note that the value returned by this function is
     /// the voltage level reported by the pin, not the value set by the output driver.
     pub fn level(&self) -> Level {
-        let bits = gpio_reg().pin[self.pin.pin_bank() as usize].read().bits();
+        let bits = GPIO.pin(self.pin.pin_bank() as usize).read().port();
         if bits & self.pin.bit() != 0 {
             Level::High
         } else {
@@ -101,18 +109,18 @@ impl<'d> Input<'d> {
 
     /// Set the pull configuration for the pin. To disable the pull, use [Pull::None].
     pub fn set_pull(&mut self, pull: Pull) {
-        match_iocon!(register, iocon_reg(), self.pin.pin_bank(), self.pin.pin_number(), {
-            register.modify(|_, w| match pull {
-                Pull::None => w.mode().inactive(),
-                Pull::Up => w.mode().pull_up(),
-                Pull::Down => w.mode().pull_down(),
+        match_iocon!(register, self.pin.pin_bank(), self.pin.pin_number(), {
+            register.modify(|w| match pull {
+                Pull::None => w.set_mode(PioMode::INACTIVE),
+                Pull::Up => w.set_mode(PioMode::PULL_UP),
+                Pull::Down => w.set_mode(PioMode::PULL_DOWN),
             });
         });
     }
 
     /// Get the current input level of the pin.
     pub fn read(&self) -> Level {
-        let bits = gpio_reg().pin[self.pin.pin_bank() as usize].read().bits();
+        let bits = GPIO.pin(self.pin.pin_bank() as usize).read().port();
         if bits & self.pin.bit() != 0 {
             Level::High
         } else {
@@ -188,8 +196,8 @@ impl<'d> Flex<'d> {
     /// Set the pin to digital mode. This is required for using a pin as a GPIO pin. The default
     /// setting for pins is (usually) non-digital.
     fn set_as_digital(&mut self) {
-        match_iocon!(register, iocon_reg(), self.pin_bank(), self.pin_number(), {
-            register.modify(|_, w| w.digimode().digital());
+        match_iocon!(register, self.pin_bank(), self.pin_number(), {
+            register.modify(|w| w.set_digimode(PioDigimode::DIGITAL));
         });
     }
 
@@ -197,12 +205,14 @@ impl<'d> Flex<'d> {
     /// function handles itself.
     pub fn set_as_output(&mut self) {
         self.set_as_digital();
-        gpio_reg().dirset[self.pin.pin_bank() as usize].write(|w| unsafe { w.dirsetp().bits(self.bit()) })
+        GPIO.dirset(self.pin.pin_bank() as usize)
+            .write(|w| w.set_dirsetp(self.bit()))
     }
 
     pub fn set_as_input(&mut self) {
         self.set_as_digital();
-        gpio_reg().dirclr[self.pin.pin_bank() as usize].write(|w| unsafe { w.dirclrp().bits(self.bit()) })
+        GPIO.dirclr(self.pin.pin_bank() as usize)
+            .write(|w| w.set_dirclrp(self.bit()))
     }
 }
 
@@ -262,52 +272,6 @@ impl SealedPin for AnyPin {
     }
 }
 
-/// Get the GPIO register block. This is used to configure all GPIO pins.
-///
-/// # Safety
-/// Due to the type system of peripherals, access to the settings of a single pin is possible only
-/// by a single thread at a time. Read/Write operations on a single registers are NOT atomic. You
-/// must ensure that the GPIO registers are not accessed concurrently by multiple threads.
-pub(crate) fn gpio_reg() -> &'static lpc55_pac::gpio::RegisterBlock {
-    unsafe { &*lpc55_pac::GPIO::ptr() }
-}
-
-/// Get the IOCON register block.
-///
-/// # Safety
-/// Read/Write operations on a single registers are NOT atomic. You must ensure that the GPIO
-/// registers are not accessed concurrently by multiple threads.
-pub(crate) fn iocon_reg() -> &'static lpc55_pac::iocon::RegisterBlock {
-    unsafe { &*lpc55_pac::IOCON::ptr() }
-}
-
-/// Get the INPUTMUX register block.
-///
-/// # Safety
-/// Read/Write operations on a single registers are NOT atomic. You must ensure that the GPIO
-/// registers are not accessed concurrently by multiple threads.
-pub(crate) fn inputmux_reg() -> &'static lpc55_pac::inputmux::RegisterBlock {
-    unsafe { &*lpc55_pac::INPUTMUX::ptr() }
-}
-
-/// Get the SYSCON register block.
-///
-/// # Safety
-/// Read/Write operations on a single registers are NOT atomic. You must ensure that the GPIO
-/// registers are not accessed concurrently by multiple threads.
-pub(crate) fn syscon_reg() -> &'static lpc55_pac::syscon::RegisterBlock {
-    unsafe { &*lpc55_pac::SYSCON::ptr() }
-}
-
-/// Get the PINT register block.
-///
-/// # Safety
-/// Read/Write operations on a single registers are NOT atomic. You must ensure that the GPIO
-/// registers are not accessed concurrently by multiple threads.
-pub(crate) fn pint_reg() -> &'static lpc55_pac::pint::RegisterBlock {
-    unsafe { &*lpc55_pac::PINT::ptr() }
-}
-
 /// Match the pin bank and number of a pin to the corresponding IOCON register.
 ///
 /// # Example
@@ -316,270 +280,26 @@ pub(crate) fn pint_reg() -> &'static lpc55_pac::pint::RegisterBlock {
 /// use embassy_nxp::pac_utils::{iocon_reg, match_iocon};
 ///
 /// // Make pin PIO1_6 digital and set it to pull-down mode.
-/// match_iocon!(register, iocon_reg(), Bank::Bank1, 6, {
-///     register.modify(|_, w| w.mode().pull_down().digimode().digital());
+/// match_iocon!(register, Bank::Bank1, 6, {
+///     register.modify(|w|{
+///         w.set_mode(PioMode::PULL_DOWN);
+///         w.set_digimode(PioDigimode::DIGITAL);
+///
+///     }
 /// });
 /// ```
 macro_rules! match_iocon {
-    ($register:ident, $iocon_register:expr, $pin_bank:expr, $pin_number:expr, $action:expr) => {
-        match ($pin_bank, $pin_number) {
-            (Bank::Bank0, 0) => {
-                let $register = &($iocon_register).pio0_0;
-                $action;
-            }
-            (Bank::Bank0, 1) => {
-                let $register = &($iocon_register).pio0_1;
-                $action;
-            }
-            (Bank::Bank0, 2) => {
-                let $register = &($iocon_register).pio0_2;
-                $action;
-            }
-            (Bank::Bank0, 3) => {
-                let $register = &($iocon_register).pio0_3;
-                $action;
-            }
-            (Bank::Bank0, 4) => {
-                let $register = &($iocon_register).pio0_4;
-                $action;
-            }
-            (Bank::Bank0, 5) => {
-                let $register = &($iocon_register).pio0_5;
-                $action;
-            }
-            (Bank::Bank0, 6) => {
-                let $register = &($iocon_register).pio0_6;
-                $action;
-            }
-            (Bank::Bank0, 7) => {
-                let $register = &($iocon_register).pio0_7;
-                $action;
-            }
-            (Bank::Bank0, 8) => {
-                let $register = &($iocon_register).pio0_8;
-                $action;
-            }
-            (Bank::Bank0, 9) => {
-                let $register = &($iocon_register).pio0_9;
-                $action;
-            }
-            (Bank::Bank0, 10) => {
-                let $register = &($iocon_register).pio0_10;
+    ($register:ident, $pin_bank:expr, $pin_number:expr, $action:expr) => {
+        match $pin_bank {
+            Bank::Bank0 => {
+                let $register = IOCON.pio0($pin_number as usize);
                 $action;
             }
-            (Bank::Bank0, 11) => {
-                let $register = &($iocon_register).pio0_11;
-                $action;
-            }
-            (Bank::Bank0, 12) => {
-                let $register = &($iocon_register).pio0_12;
-                $action;
-            }
-            (Bank::Bank0, 13) => {
-                let $register = &($iocon_register).pio0_13;
-                $action;
-            }
-            (Bank::Bank0, 14) => {
-                let $register = &($iocon_register).pio0_14;
-                $action;
-            }
-            (Bank::Bank0, 15) => {
-                let $register = &($iocon_register).pio0_15;
-                $action;
-            }
-            (Bank::Bank0, 16) => {
-                let $register = &($iocon_register).pio0_16;
-                $action;
-            }
-            (Bank::Bank0, 17) => {
-                let $register = &($iocon_register).pio0_17;
-                $action;
-            }
-            (Bank::Bank0, 18) => {
-                let $register = &($iocon_register).pio0_18;
-                $action;
-            }
-            (Bank::Bank0, 19) => {
-                let $register = &($iocon_register).pio0_19;
-                $action;
-            }
-            (Bank::Bank0, 20) => {
-                let $register = &($iocon_register).pio0_20;
-                $action;
-            }
-            (Bank::Bank0, 21) => {
-                let $register = &($iocon_register).pio0_21;
-                $action;
-            }
-            (Bank::Bank0, 22) => {
-                let $register = &($iocon_register).pio0_22;
-                $action;
-            }
-            (Bank::Bank0, 23) => {
-                let $register = &($iocon_register).pio0_23;
-                $action;
-            }
-            (Bank::Bank0, 24) => {
-                let $register = &($iocon_register).pio0_24;
-                $action;
-            }
-            (Bank::Bank0, 25) => {
-                let $register = &($iocon_register).pio0_25;
-                $action;
-            }
-            (Bank::Bank0, 26) => {
-                let $register = &($iocon_register).pio0_26;
-                $action;
-            }
-            (Bank::Bank0, 27) => {
-                let $register = &($iocon_register).pio0_27;
-                $action;
-            }
-            (Bank::Bank0, 28) => {
-                let $register = &($iocon_register).pio0_28;
-                $action;
-            }
-            (Bank::Bank0, 29) => {
-                let $register = &($iocon_register).pio0_29;
-                $action;
-            }
-            (Bank::Bank0, 30) => {
-                let $register = &($iocon_register).pio0_30;
-                $action;
-            }
-            (Bank::Bank0, 31) => {
-                let $register = &($iocon_register).pio0_31;
-                $action;
-            }
-            (Bank::Bank1, 0) => {
-                let $register = &($iocon_register).pio1_0;
-                $action;
-            }
-            (Bank::Bank1, 1) => {
-                let $register = &($iocon_register).pio1_1;
-                $action;
-            }
-            (Bank::Bank1, 2) => {
-                let $register = &($iocon_register).pio1_2;
-                $action;
-            }
-            (Bank::Bank1, 3) => {
-                let $register = &($iocon_register).pio1_3;
-                $action;
-            }
-            (Bank::Bank1, 4) => {
-                let $register = &($iocon_register).pio1_4;
-                $action;
-            }
-            (Bank::Bank1, 5) => {
-                let $register = &($iocon_register).pio1_5;
-                $action;
-            }
-            (Bank::Bank1, 6) => {
-                let $register = &($iocon_register).pio1_6;
-                $action;
-            }
-            (Bank::Bank1, 7) => {
-                let $register = &($iocon_register).pio1_7;
-                $action;
-            }
-            (Bank::Bank1, 8) => {
-                let $register = &($iocon_register).pio1_8;
-                $action;
-            }
-            (Bank::Bank1, 9) => {
-                let $register = &($iocon_register).pio1_9;
-                $action;
-            }
-            (Bank::Bank1, 10) => {
-                let $register = &($iocon_register).pio1_10;
-                $action;
-            }
-            (Bank::Bank1, 11) => {
-                let $register = &($iocon_register).pio1_11;
-                $action;
-            }
-            (Bank::Bank1, 12) => {
-                let $register = &($iocon_register).pio1_12;
-                $action;
-            }
-            (Bank::Bank1, 13) => {
-                let $register = &($iocon_register).pio1_13;
-                $action;
-            }
-            (Bank::Bank1, 14) => {
-                let $register = &($iocon_register).pio1_14;
-                $action;
-            }
-            (Bank::Bank1, 15) => {
-                let $register = &($iocon_register).pio1_15;
-                $action;
-            }
-            (Bank::Bank1, 16) => {
-                let $register = &($iocon_register).pio1_16;
-                $action;
-            }
-            (Bank::Bank1, 17) => {
-                let $register = &($iocon_register).pio1_17;
-                $action;
-            }
-            (Bank::Bank1, 18) => {
-                let $register = &($iocon_register).pio1_18;
-                $action;
-            }
-            (Bank::Bank1, 19) => {
-                let $register = &($iocon_register).pio1_19;
-                $action;
-            }
-            (Bank::Bank1, 20) => {
-                let $register = &($iocon_register).pio1_20;
-                $action;
-            }
-            (Bank::Bank1, 21) => {
-                let $register = &($iocon_register).pio1_21;
-                $action;
-            }
-            (Bank::Bank1, 22) => {
-                let $register = &($iocon_register).pio1_22;
-                $action;
-            }
-            (Bank::Bank1, 23) => {
-                let $register = &($iocon_register).pio1_23;
-                $action;
-            }
-            (Bank::Bank1, 24) => {
-                let $register = &($iocon_register).pio1_24;
-                $action;
-            }
-            (Bank::Bank1, 25) => {
-                let $register = &($iocon_register).pio1_25;
-                $action;
-            }
-            (Bank::Bank1, 26) => {
-                let $register = &($iocon_register).pio1_26;
-                $action;
-            }
-            (Bank::Bank1, 27) => {
-                let $register = &($iocon_register).pio1_27;
-                $action;
-            }
-            (Bank::Bank1, 28) => {
-                let $register = &($iocon_register).pio1_28;
-                $action;
-            }
-            (Bank::Bank1, 29) => {
-                let $register = &($iocon_register).pio1_29;
-                $action;
-            }
-            (Bank::Bank1, 30) => {
-                let $register = &($iocon_register).pio1_30;
-                $action;
-            }
-            (Bank::Bank1, 31) => {
-                let $register = &($iocon_register).pio1_31;
+
+            Bank::Bank1 => {
+                let $register = IOCON.pio1($pin_number as usize);
                 $action;
             }
-            _ => unreachable!(),
         }
     };
 }
diff --git a/embassy-nxp/src/lib.rs b/embassy-nxp/src/lib.rs
index 3fcb14b7e..74142a10b 100644
--- a/embassy-nxp/src/lib.rs
+++ b/embassy-nxp/src/lib.rs
@@ -4,9 +4,9 @@
 pub(crate) mod fmt;
 
 pub mod gpio;
-#[cfg(feature = "lpc55")]
+#[cfg(feature = "lpc55-core0")]
 pub mod pint;
-#[cfg(feature = "lpc55")]
+#[cfg(feature = "lpc55-core0")]
 pub mod usart;
 
 #[cfg(feature = "_time_driver")]
@@ -15,7 +15,7 @@ pub mod usart;
 mod time_driver;
 
 // This mod MUST go last, so that it sees all the `impl_foo!` macros
-#[cfg_attr(feature = "lpc55", path = "chips/lpc55.rs")]
+#[cfg_attr(feature = "lpc55-core0", path = "chips/lpc55.rs")]
 #[cfg_attr(feature = "mimxrt1011", path = "chips/mimxrt1011.rs")]
 #[cfg_attr(feature = "mimxrt1062", path = "chips/mimxrt1062.rs")]
 mod chip;
@@ -83,10 +83,10 @@ pub fn init(_config: config::Config) -> Peripherals {
         pac::CCM.ccgr6().modify(|v| v.set_cg0(1));
     }
 
-    #[cfg(any(feature = "lpc55", rt1xxx))]
+    #[cfg(any(feature = "lpc55-core0", rt1xxx))]
     gpio::init();
 
-    #[cfg(feature = "lpc55")]
+    #[cfg(feature = "lpc55-core0")]
     pint::init();
 
     #[cfg(feature = "_time_driver")]
diff --git a/embassy-nxp/src/pint.rs b/embassy-nxp/src/pint.rs
index ff414b4e6..e594aaa6a 100644
--- a/embassy-nxp/src/pint.rs
+++ b/embassy-nxp/src/pint.rs
@@ -5,10 +5,11 @@ use core::pin::Pin as FuturePin;
 use core::task::{Context, Poll};
 
 use critical_section::Mutex;
+use embassy_hal_internal::interrupt::InterruptExt;
 use embassy_sync::waitqueue::AtomicWaker;
 
-use crate::gpio::{self, inputmux_reg, pint_reg, syscon_reg, AnyPin, Level, SealedPin};
-use crate::pac::interrupt;
+use crate::gpio::{self, AnyPin, Level, SealedPin};
+use crate::pac::{interrupt, INPUTMUX, PINT, SYSCON};
 use crate::Peri;
 
 struct PinInterrupt {
@@ -88,18 +89,18 @@ enum InterruptOn {
 }
 
 pub(crate) fn init() {
-    syscon_reg().ahbclkctrl0.modify(|_, w| w.pint().enable());
+    SYSCON.ahbclkctrl0().modify(|w| w.set_pint(true));
 
     // Enable interrupts
     unsafe {
-        crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT0);
-        crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT1);
-        crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT2);
-        crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT3);
-        crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT4);
-        crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT5);
-        crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT6);
-        crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT7);
+        interrupt::PIN_INT0.enable();
+        interrupt::PIN_INT1.enable();
+        interrupt::PIN_INT2.enable();
+        interrupt::PIN_INT3.enable();
+        interrupt::PIN_INT4.enable();
+        interrupt::PIN_INT5.enable();
+        interrupt::PIN_INT6.enable();
+        interrupt::PIN_INT7.enable();
     };
 
     info!("Pin interrupts initialized");
@@ -119,24 +120,19 @@ impl<'d> InputFuture<'d> {
         let interrupt_number = next_available_interrupt()?;
 
         // Clear interrupt, just in case
-        pint_reg()
-            .rise
-            .write(|w| unsafe { w.rdet().bits(1 << interrupt_number) });
-        pint_reg()
-            .fall
-            .write(|w| unsafe { w.fdet().bits(1 << interrupt_number) });
+        PINT.rise().write(|w| w.set_rdet(1 << interrupt_number));
+        PINT.fall().write(|w| w.set_fdet(1 << interrupt_number));
 
         // Enable input multiplexing on pin interrupt register 0 for pin (32*bank + pin_number)
-        inputmux_reg().pintsel[interrupt_number]
-            .write(|w| unsafe { w.intpin().bits(32 * pin.pin_bank() as u8 + pin.pin_number()) });
+        INPUTMUX
+            .pintsel(interrupt_number as usize)
+            .write(|w| w.set_intpin(32 * pin.pin_bank() as u8 + pin.pin_number()));
 
         match interrupt_on {
             InterruptOn::Level(level) => {
                 // Set pin interrupt register to edge sensitive or level sensitive
                 // 0 = edge sensitive, 1 = level sensitive
-                pint_reg()
-                    .isel
-                    .modify(|r, w| unsafe { w.bits(r.bits() | (1 << interrupt_number)) });
+                PINT.isel().modify(|w| w.set_pmode(w.pmode() | (1 << interrupt_number)));
 
                 // Enable level interrupt.
                 //
@@ -144,63 +140,44 @@ impl<'d> InputFuture<'d> {
                 // is activated.
 
                 // 0 = no-op, 1 = enable
-                pint_reg()
-                    .sienr
-                    .write(|w| unsafe { w.setenrl().bits(1 << interrupt_number) });
+                PINT.sienr().write(|w| w.set_setenrl(1 << interrupt_number));
 
                 // Set active level
                 match level {
                     Level::Low => {
                         // 0 = no-op, 1 = select LOW
-                        pint_reg()
-                            .cienf
-                            .write(|w| unsafe { w.cenaf().bits(1 << interrupt_number) });
+                        PINT.cienf().write(|w| w.set_cenaf(1 << interrupt_number));
                     }
                     Level::High => {
                         // 0 = no-op, 1 = select HIGH
-                        pint_reg()
-                            .sienf
-                            .write(|w| unsafe { w.setenaf().bits(1 << interrupt_number) });
+                        PINT.sienf().write(|w| w.set_setenaf(1 << interrupt_number));
                     }
                 }
             }
             InterruptOn::Edge(edge) => {
                 // Set pin interrupt register to edge sensitive or level sensitive
                 // 0 = edge sensitive, 1 = level sensitive
-                pint_reg()
-                    .isel
-                    .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << interrupt_number)) });
+                PINT.isel()
+                    .modify(|w| w.set_pmode(w.pmode() & !(1 << interrupt_number)));
 
                 // Enable rising/falling edge detection
                 match edge {
                     Edge::Rising => {
                         // 0 = no-op, 1 = enable rising edge
-                        pint_reg()
-                            .sienr
-                            .write(|w| unsafe { w.setenrl().bits(1 << interrupt_number) });
+                        PINT.sienr().write(|w| w.set_setenrl(1 << interrupt_number));
                         // 0 = no-op, 1 = disable falling edge
-                        pint_reg()
-                            .cienf
-                            .write(|w| unsafe { w.cenaf().bits(1 << interrupt_number) });
+                        PINT.cienf().write(|w| w.set_cenaf(1 << interrupt_number));
                     }
                     Edge::Falling => {
                         // 0 = no-op, 1 = enable falling edge
-                        pint_reg()
-                            .sienf
-                            .write(|w| unsafe { w.setenaf().bits(1 << interrupt_number) });
+                        PINT.sienf().write(|w| w.set_setenaf(1 << interrupt_number));
                         // 0 = no-op, 1 = disable rising edge
-                        pint_reg()
-                            .cienr
-                            .write(|w| unsafe { w.cenrl().bits(1 << interrupt_number) });
+                        PINT.cienr().write(|w| w.set_cenrl(1 << interrupt_number));
                     }
                     Edge::Both => {
                         // 0 = no-op, 1 = enable
-                        pint_reg()
-                            .sienr
-                            .write(|w| unsafe { w.setenrl().bits(1 << interrupt_number) });
-                        pint_reg()
-                            .sienf
-                            .write(|w| unsafe { w.setenaf().bits(1 << interrupt_number) });
+                        PINT.sienr().write(|w| w.set_setenrl(1 << interrupt_number));
+                        PINT.sienf().write(|w| w.set_setenaf(1 << interrupt_number));
                     }
                 }
             }
@@ -239,12 +216,8 @@ impl<'d> Drop for InputFuture<'d> {
 
         // Disable pin interrupt
         // 0 = no-op, 1 = disable
-        pint_reg()
-            .cienr
-            .write(|w| unsafe { w.cenrl().bits(1 << interrupt_number) });
-        pint_reg()
-            .cienf
-            .write(|w| unsafe { w.cenaf().bits(1 << interrupt_number) });
+        PINT.cienr().write(|w| w.set_cenrl(1 << interrupt_number));
+        PINT.cienf().write(|w| w.set_cenaf(1 << interrupt_number));
 
         critical_section::with(|cs| {
             let mut pin_interrupts = PIN_INTERRUPTS.borrow(cs).borrow_mut();
@@ -277,12 +250,8 @@ impl<'d> Future for InputFuture<'d> {
 }
 
 fn handle_interrupt(interrupt_number: usize) {
-    pint_reg()
-        .rise
-        .write(|w| unsafe { w.rdet().bits(1 << interrupt_number) });
-    pint_reg()
-        .fall
-        .write(|w| unsafe { w.fdet().bits(1 << interrupt_number) });
+    PINT.rise().write(|w| w.set_rdet(1 << interrupt_number));
+    PINT.fall().write(|w| w.set_fdet(1 << interrupt_number));
 
     critical_section::with(|cs| {
         let mut pin_interrupts = PIN_INTERRUPTS.borrow(cs).borrow_mut();
diff --git a/embassy-nxp/src/time_driver/rtc.rs b/embassy-nxp/src/time_driver/rtc.rs
index 94272e9c2..fb6de6a5e 100644
--- a/embassy-nxp/src/time_driver/rtc.rs
+++ b/embassy-nxp/src/time_driver/rtc.rs
@@ -6,7 +6,9 @@ use embassy_hal_internal::interrupt::{InterruptExt, Priority};
 use embassy_sync::blocking_mutex::CriticalSectionMutex as Mutex;
 use embassy_time_driver::{time_driver_impl, Driver};
 use embassy_time_queue_utils::Queue;
-use lpc55_pac::{interrupt, PMC, RTC, SYSCON};
+
+use crate::pac::{interrupt, pmc, rtc, PMC, RTC, SYSCON};
+
 struct AlarmState {
     timestamp: Cell<u64>,
 }
@@ -32,33 +34,32 @@ time_driver_impl!(static DRIVER: RtcDriver = RtcDriver {
 });
 impl RtcDriver {
     fn init(&'static self) {
-        let syscon = unsafe { &*SYSCON::ptr() };
-        let pmc = unsafe { &*PMC::ptr() };
-        let rtc = unsafe { &*RTC::ptr() };
+        let syscon = SYSCON;
+        let pmc = PMC;
+        let rtc = RTC;
 
-        syscon.ahbclkctrl0.modify(|_, w| w.rtc().enable());
+        syscon.ahbclkctrl0().modify(|w| w.set_rtc(true));
 
         // By default the RTC enters software reset. If for some reason it is
         // not in reset, we enter and them promptly leave.q
-        rtc.ctrl.modify(|_, w| w.swreset().set_bit());
-        rtc.ctrl.modify(|_, w| w.swreset().clear_bit());
+        rtc.ctrl().modify(|w| w.set_swreset(true));
+        rtc.ctrl().modify(|w| w.set_swreset(false));
 
         // Select clock source - either XTAL or FRO
-        // pmc.rtcosc32k.write(|w| w.sel().xtal32k());
-        pmc.rtcosc32k.write(|w| w.sel().fro32k());
+        // pmc.rtcosc32k().write(|w| w.set_sel(pmc::vals::Sel::XTAL32K));
+        pmc.rtcosc32k().write(|w| w.set_sel(pmc::vals::Sel::FRO32K));
 
         // Start the RTC peripheral
-        rtc.ctrl.modify(|_, w| w.rtc_osc_pd().power_up());
-
-        // rtc.ctrl.modify(|_, w| w.rtc_en().clear_bit()); // EXTRA
+        rtc.ctrl().modify(|w| w.set_rtc_osc_pd(rtc::vals::RtcOscPd::POWER_UP));
 
         //reset/clear(?) counter
-        rtc.count.reset();
+        rtc.count().modify(|w| w.set_val(0));
         //en rtc main counter
-        rtc.ctrl.modify(|_, w| w.rtc_en().set_bit());
-        rtc.ctrl.modify(|_, w| w.rtc1khz_en().set_bit());
+        rtc.ctrl().modify(|w| w.set_rtc_en(true));
+        rtc.ctrl().modify(|w| w.set_rtc1khz_en(true));
         // subsec counter enable
-        rtc.ctrl.modify(|_, w| w.rtc_subsec_ena().set_bit());
+        rtc.ctrl()
+            .modify(|w| w.set_rtc_subsec_ena(rtc::vals::RtcSubsecEna::POWER_UP));
 
         // enable irq
         unsafe {
@@ -68,7 +69,7 @@ impl RtcDriver {
     }
 
     fn set_alarm(&self, cs: CriticalSection, timestamp: u64) -> bool {
-        let rtc = unsafe { &*RTC::ptr() };
+        let rtc = RTC;
         let alarm = &self.alarms.borrow(cs);
         alarm.timestamp.set(timestamp);
         let now = self.now();
@@ -83,33 +84,38 @@ impl RtcDriver {
         let sec = (diff / 32768) as u32;
         let subsec = (diff % 32768) as u32;
 
-        let current_sec = rtc.count.read().val().bits();
+        let current_sec = rtc.count().read().val();
         let target_sec = current_sec.wrapping_add(sec as u32);
 
-        rtc.match_.write(|w| unsafe { w.matval().bits(target_sec) });
-        rtc.wake.write(|w| unsafe {
+        rtc.match_().write(|w| w.set_matval(target_sec));
+        rtc.wake().write(|w| {
             let ms = (subsec * 1000) / 32768;
-            w.val().bits(ms as u16)
+            w.set_val(ms as u16)
         });
+
         if subsec > 0 {
             let ms = (subsec * 1000) / 32768;
-            rtc.wake.write(|w| unsafe { w.val().bits(ms as u16) });
+            rtc.wake().write(|w| w.set_val(ms as u16));
         }
-        rtc.ctrl.modify(|_, w| w.alarm1hz().clear_bit().wake1khz().clear_bit());
+
+        rtc.ctrl().modify(|w| {
+            w.set_alarm1hz(false);
+            w.set_wake1khz(rtc::vals::Wake1khz::RUN)
+        });
         true
     }
 
     fn on_interrupt(&self) {
         critical_section::with(|cs| {
-            let rtc = unsafe { &*RTC::ptr() };
-            let flags = rtc.ctrl.read();
-            if flags.alarm1hz().bit_is_clear() {
-                rtc.ctrl.modify(|_, w| w.alarm1hz().set_bit());
+            let rtc = RTC;
+            let flags = rtc.ctrl().read();
+            if flags.alarm1hz() == false {
+                rtc.ctrl().modify(|w| w.set_alarm1hz(true));
                 self.trigger_alarm(cs);
             }
 
-            if flags.wake1khz().bit_is_clear() {
-                rtc.ctrl.modify(|_, w| w.wake1khz().set_bit());
+            if flags.wake1khz() == rtc::vals::Wake1khz::RUN {
+                rtc.ctrl().modify(|w| w.set_wake1khz(rtc::vals::Wake1khz::TIMEOUT));
                 self.trigger_alarm(cs);
             }
         });
@@ -135,13 +141,13 @@ impl RtcDriver {
 
 impl Driver for RtcDriver {
     fn now(&self) -> u64 {
-        let rtc = unsafe { &*RTC::ptr() };
+        let rtc = RTC;
 
         loop {
-            let sec1 = rtc.count.read().val().bits() as u64;
-            let sub1 = rtc.subsec.read().subsec().bits() as u64;
-            let sec2 = rtc.count.read().val().bits() as u64;
-            let sub2 = rtc.subsec.read().subsec().bits() as u64;
+            let sec1 = rtc.count().read().val() as u64;
+            let sub1 = rtc.subsec().read().subsec() as u64;
+            let sec2 = rtc.count().read().val() as u64;
+            let sub2 = rtc.subsec().read().subsec() as u64;
 
             if sec1 == sec2 && sub1 == sub2 {
                 return sec1 * 32768 + sub1;
@@ -162,7 +168,7 @@ impl Driver for RtcDriver {
         })
     }
 }
-#[cortex_m_rt::interrupt]
+#[interrupt]
 fn RTC() {
     DRIVER.on_interrupt();
 }
diff --git a/embassy-nxp/src/usart.rs b/embassy-nxp/src/usart.rs
index 009c251e2..1d8886f24 100644
--- a/embassy-nxp/src/usart.rs
+++ b/embassy-nxp/src/usart.rs
@@ -1,6 +1,5 @@
 //! Universal Synchronous/Asynchronous Receiver/Transmitter (USART) driver.
-#![macro_use]
 
-#[cfg_attr(feature = "lpc55", path = "./usart/lpc55.rs")]
+#[cfg_attr(feature = "lpc55-core0", path = "./usart/lpc55.rs")]
 mod inner;
 pub use inner::*;
diff --git a/embassy-nxp/src/usart/lpc55.rs b/embassy-nxp/src/usart/lpc55.rs
index 3f7456a2e..428b80c4b 100644
--- a/embassy-nxp/src/usart/lpc55.rs
+++ b/embassy-nxp/src/usart/lpc55.rs
@@ -2,9 +2,12 @@ use core::marker::PhantomData;
 
 use embassy_hal_internal::{Peri, PeripheralType};
 use embedded_io::{self, ErrorKind};
-pub use sealed::SealedInstance;
 
-use crate::gpio::AnyPin;
+use crate::gpio::{match_iocon, AnyPin, Bank, SealedPin};
+use crate::pac::flexcomm::Flexcomm as FlexcommReg;
+use crate::pac::iocon::vals::PioFunc;
+use crate::pac::usart::Usart as UsartReg;
+use crate::pac::*;
 use crate::{Blocking, Mode};
 
 /// Serial error
@@ -47,16 +50,6 @@ pub enum DataBits {
     DataBits9,
 }
 
-impl DataBits {
-    fn bits(&self) -> u8 {
-        match self {
-            Self::DataBits7 => 0b00,
-            Self::DataBits8 => 0b01,
-            Self::DataBits9 => 0b10,
-        }
-    }
-}
-
 /// Parity bit.
 #[derive(Clone, Copy, PartialEq, Eq, Debug)]
 pub enum Parity {
@@ -68,16 +61,6 @@ pub enum Parity {
     ParityOdd,
 }
 
-impl Parity {
-    fn bits(&self) -> u8 {
-        match self {
-            Self::ParityNone => 0b00,
-            Self::ParityEven => 0b10,
-            Self::ParityOdd => 0b11,
-        }
-    }
-}
-
 /// Stop bits.
 #[derive(Clone, Copy, PartialEq, Eq, Debug)]
 pub enum StopBits {
@@ -87,15 +70,6 @@ pub enum StopBits {
     Stop2,
 }
 
-impl StopBits {
-    fn bits(&self) -> bool {
-        return match self {
-            Self::Stop1 => false,
-            Self::Stop2 => true,
-        };
-    }
-}
-
 /// UART config.
 #[non_exhaustive]
 #[derive(Clone, Debug)]
@@ -117,7 +91,7 @@ pub struct Config {
 impl Default for Config {
     fn default() -> Self {
         Self {
-            baudrate: 9600,
+            baudrate: 115200,
             data_bits: DataBits::DataBits8,
             stop_bits: StopBits::Stop1,
             parity: Parity::ParityNone,
@@ -131,59 +105,72 @@ impl Default for Config {
 /// 'd: the lifetime marker ensuring correct borrow checking for peripherals used at compile time
 /// T: the peripheral instance type allowing usage of peripheral specific registers
 /// M: the operating mode of USART peripheral
-pub struct Usart<'d, T: Instance, M: Mode> {
-    tx: UsartTx<'d, T, M>,
-    rx: UsartRx<'d, T, M>,
+pub struct Usart<'d, M: Mode> {
+    tx: UsartTx<'d, M>,
+    rx: UsartRx<'d, M>,
 }
 
-pub struct UsartTx<'d, T: Instance, M: Mode> {
-    phantom: PhantomData<(&'d (), T, M)>,
+pub struct UsartTx<'d, M: Mode> {
+    info: &'static Info,
+    phantom: PhantomData<(&'d (), M)>,
 }
 
-pub struct UsartRx<'d, T: Instance, M: Mode> {
-    phantom: PhantomData<(&'d (), T, M)>,
+pub struct UsartRx<'d, M: Mode> {
+    info: &'static Info,
+    phantom: PhantomData<(&'d (), M)>,
 }
 
-impl<'d, T: Instance, M: Mode> UsartTx<'d, T, M> {
-    pub fn new(_usart: Peri<'d, T>, tx: Peri<'d, impl TxPin<T>>, config: Config) -> Self {
-        Usart::<T, M>::init(Some(tx.into()), None, config);
-        Self::new_inner()
+impl<'d, M: Mode> UsartTx<'d, M> {
+    pub fn new<T: Instance>(_usart: Peri<'d, T>, tx: Peri<'d, impl TxPin<T>>, config: Config) -> Self {
+        Usart::<M>::init::<T>(Some(tx.into()), None, config);
+        Self::new_inner(T::info())
     }
 
     #[inline]
-    fn new_inner() -> Self {
-        Self { phantom: PhantomData }
+    fn new_inner(info: &'static Info) -> Self {
+        Self {
+            info,
+            phantom: PhantomData,
+        }
     }
 
     pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<(), Error> {
-        T::blocking_write(buffer)
+        for &b in buffer {
+            while !(self.info.usart_reg.fifostat().read().txnotfull()) {}
+            self.info.usart_reg.fifowr().write(|w| w.set_txdata(b as u16));
+        }
+        Ok(())
     }
 
     pub fn blocking_flush(&mut self) -> Result<(), Error> {
-        T::blocking_flush()
+        while !(self.info.usart_reg.fifostat().read().txempty()) {}
+        Ok(())
     }
 
     pub fn tx_busy(&self) -> bool {
-        T::tx_busy()
+        !(self.info.usart_reg.fifostat().read().txempty())
     }
 }
 
-impl<'d, T: Instance> UsartTx<'d, T, Blocking> {
-    pub fn new_blocking(_usart: Peri<'d, T>, tx: Peri<'d, impl TxPin<T>>, config: Config) -> Self {
-        Usart::<T, Blocking>::init(Some(tx.into()), None, config);
-        Self::new_inner()
+impl<'d> UsartTx<'d, Blocking> {
+    pub fn new_blocking<T: Instance>(_usart: Peri<'d, T>, tx: Peri<'d, impl TxPin<T>>, config: Config) -> Self {
+        Usart::<Blocking>::init::<T>(Some(tx.into()), None, config);
+        Self::new_inner(T::info())
     }
 }
 
-impl<'d, T: Instance, M: Mode> UsartRx<'d, T, M> {
-    pub fn new(_usart: Peri<'d, T>, rx: Peri<'d, impl RxPin<T>>, config: Config) -> Self {
-        Usart::<T, M>::init(None, Some(rx.into()), config);
-        Self::new_inner()
+impl<'d, M: Mode> UsartRx<'d, M> {
+    pub fn new<T: Instance>(_usart: Peri<'d, T>, rx: Peri<'d, impl RxPin<T>>, config: Config) -> Self {
+        Usart::<M>::init::<T>(None, Some(rx.into()), config);
+        Self::new_inner(T::info())
     }
 
     #[inline]
-    fn new_inner() -> Self {
-        Self { phantom: PhantomData }
+    fn new_inner(info: &'static Info) -> Self {
+        Self {
+            info,
+            phantom: PhantomData,
+        }
     }
 
     pub fn blocking_read(&mut self, mut buffer: &mut [u8]) -> Result<(), Error> {
@@ -201,19 +188,35 @@ impl<'d, T: Instance, M: Mode> UsartRx<'d, T, M> {
     /// - Ok(n) -> read n bytes
     /// - Err(n, Error) -> read n-1 bytes, but encountered an error while reading nth byte
     fn drain_fifo(&mut self, buffer: &mut [u8]) -> Result<usize, (usize, Error)> {
-        T::drain_fifo(buffer)
+        for (i, b) in buffer.iter_mut().enumerate() {
+            while !(self.info.usart_reg.fifostat().read().rxnotempty()) {}
+            if self.info.usart_reg.fifostat().read().rxerr() {
+                return Err((i, Error::Overrun));
+            } else if self.info.usart_reg.fifordnopop().read().parityerr() {
+                return Err((i, Error::Parity));
+            } else if self.info.usart_reg.fifordnopop().read().framerr() {
+                return Err((i, Error::Framing));
+            } else if self.info.usart_reg.fifordnopop().read().rxnoise() {
+                return Err((i, Error::Noise));
+            } else if self.info.usart_reg.intstat().read().deltarxbrk() {
+                return Err((i, Error::Break));
+            }
+            let dr = self.info.usart_reg.fiford().read().rxdata() as u8;
+            *b = dr;
+        }
+        Ok(buffer.len())
     }
 }
 
-impl<'d, T: Instance> UsartRx<'d, T, Blocking> {
-    pub fn new_blocking(_usart: Peri<'d, T>, rx: Peri<'d, impl RxPin<T>>, config: Config) -> Self {
-        Usart::<T, Blocking>::init(None, Some(rx.into()), config);
-        Self::new_inner()
+impl<'d> UsartRx<'d, Blocking> {
+    pub fn new_blocking<T: Instance>(_usart: Peri<'d, T>, rx: Peri<'d, impl RxPin<T>>, config: Config) -> Self {
+        Usart::<Blocking>::init::<T>(None, Some(rx.into()), config);
+        Self::new_inner(T::info())
     }
 }
 
-impl<'d, T: Instance> Usart<'d, T, Blocking> {
-    pub fn new_blocking(
+impl<'d> Usart<'d, Blocking> {
+    pub fn new_blocking<T: Instance>(
         usart: Peri<'d, T>,
         tx: Peri<'d, impl TxPin<T>>,
         rx: Peri<'d, impl RxPin<T>>,
@@ -223,29 +226,70 @@ impl<'d, T: Instance> Usart<'d, T, Blocking> {
     }
 }
 
-impl<'d, T: Instance, M: Mode> Usart<'d, T, M> {
-    fn new_inner(_usart: Peri<'d, T>, mut tx: Peri<'d, AnyPin>, mut rx: Peri<'d, AnyPin>, config: Config) -> Self {
-        Self::init(Some(tx.reborrow()), Some(rx.reborrow()), config);
+impl<'d, M: Mode> Usart<'d, M> {
+    fn new_inner<T: Instance>(
+        _usart: Peri<'d, T>,
+        mut tx: Peri<'d, AnyPin>,
+        mut rx: Peri<'d, AnyPin>,
+        config: Config,
+    ) -> Self {
+        Self::init::<T>(Some(tx.reborrow()), Some(rx.reborrow()), config);
         Self {
-            tx: UsartTx::new_inner(),
-            rx: UsartRx::new_inner(),
+            tx: UsartTx::new_inner(T::info()),
+            rx: UsartRx::new_inner(T::info()),
         }
     }
 
-    fn init(_tx: Option<Peri<'_, AnyPin>>, _rx: Option<Peri<'_, AnyPin>>, config: Config) {
-        T::enable_clock();
-        T::reset_flexcomm();
-        let source_clock: u32 = T::select_clock(config.baudrate);
-        T::configure_flexcomm();
-        T::tx_pin_config();
-        T::rx_pin_config();
-        Self::set_baudrate(source_clock, config.baudrate);
-        T::configure_usart(config);
-        T::disable_dma();
-        T::enable_usart();
+    fn init<T: Instance>(tx: Option<Peri<'_, AnyPin>>, rx: Option<Peri<'_, AnyPin>>, config: Config) {
+        Self::configure_flexcomm(T::info().fc_reg, T::instance_number());
+        Self::configure_clock::<T>(&config);
+        Self::pin_config::<T>(tx, rx);
+        Self::configure_usart(T::info(), &config);
     }
 
-    fn set_baudrate(source_clock: u32, baudrate: u32) {
+    fn configure_clock<T: Instance>(config: &Config) {
+        // Select source clock
+
+        // Adaptive clock choice based on baud rate
+        // To get the desired baud rate, it is essential to choose the clock bigger than baud rate so that it can be 'chiseled'
+        // There are two types of dividers: integer divider (baud rate generator register and oversample selection value)
+        // and fractional divider (fractional rate divider).
+
+        // By default, oversampling rate is 16 which is an industry standard.
+        // That means 16 clocks are used to deliver the byte to recipient.
+        // In this way the probability of getting correct bytes instead of noise directly increases as oversampling increases as well.
+
+        // Minimum and maximum values were computed taking these formulas into account:
+        // For minimum value, MULT = 0, BRGVAL = 0
+        // For maximum value, MULT = 255, BRGVAL = 255
+        // Flexcomm Interface function clock = (clock selected via FCCLKSEL) / (1 + MULT / DIV)
+        // By default, OSRVAL = 15 (see above)
+        // Baud rate = [FCLK / (OSRVAL+1)] / (BRGVAL + 1)
+        let source_clock = match config.baudrate {
+            750_001..=6_000_000 => {
+                SYSCON
+                    .fcclksel(T::instance_number())
+                    .modify(|w| w.set_sel(syscon::vals::FcclkselSel::ENUM_0X3)); // 96 MHz
+                96_000_000
+            }
+            1501..=750_000 => {
+                SYSCON
+                    .fcclksel(T::instance_number())
+                    .modify(|w| w.set_sel(syscon::vals::FcclkselSel::ENUM_0X2)); // 12 MHz
+                12_000_000
+            }
+            121..=1500 => {
+                SYSCON
+                    .fcclksel(T::instance_number())
+                    .modify(|w| w.set_sel(syscon::vals::FcclkselSel::ENUM_0X4)); // 1 MHz
+                1_000_000
+            }
+            _ => {
+                panic!("{} baudrate is not permitted in this mode", config.baudrate);
+            }
+        };
+        // Calculate MULT and BRG values based on baudrate
+
         // There are two types of dividers: integer divider (baud rate generator register and oversample selection value)
         // and fractional divider (fractional rate divider).
         // For oversampling, the default is industry standard 16x oversampling, i.e. OSRVAL = 15
@@ -274,14 +318,167 @@ impl<'d, T: Instance, M: Mode> Usart<'d, T, M> {
         // Secondly, MULT is calculated to ultimately 'chisel' the clock to get the baud rate.
         // The deduced formulas are written below.
 
-        let brg_value = (source_clock / (16 * baudrate)).min(255);
+        let brg_value = (source_clock / (16 * config.baudrate)).min(255);
         let raw_clock = source_clock / (16 * brg_value);
-        let mult_value = ((raw_clock * 256 / baudrate) - 256).min(255);
-        T::set_baudrate(mult_value as u8, brg_value as u8);
+        let mult_value = ((raw_clock * 256 / config.baudrate) - 256).min(255);
+
+        // Write values to the registers
+
+        // FCLK =  (clock selected via FCCLKSEL) / (1+ MULT / DIV)
+        // Remark: To use the fractional baud rate generator, 0xFF must be wirtten to the DIV value
+        // to yield a denominator vale of 256. All other values are not supported
+        SYSCON.flexfrgctrl(T::instance_number()).modify(|w| {
+            w.set_div(0xFF);
+            w.set_mult(mult_value as u8);
+        });
+
+        // Baud rate = [FCLK / (OSRVAL+1)] / (BRGVAL + 1)
+        // By default, oversampling is 16x, i.e. OSRVAL = 15
+
+        // Typical industry standard USARTs use a 16x oversample clock to transmit and receive
+        // asynchronous data. This is the number of BRG clocks used for one data bit. The
+        // Oversample Select Register (OSR) allows this USART to use a 16x down to a 5x
+        // oversample clock. There is no oversampling in synchronous modes.
+        T::info()
+            .usart_reg
+            .brg()
+            .modify(|w| w.set_brgval((brg_value - 1) as u16));
+    }
+
+    fn pin_config<T: Instance>(tx: Option<Peri<'_, AnyPin>>, rx: Option<Peri<'_, AnyPin>>) {
+        if let Some(tx_pin) = tx {
+            match_iocon!(register, tx_pin.pin_bank(), tx_pin.pin_number(), {
+                register.modify(|w| {
+                    w.set_func(T::tx_pin_func());
+                    w.set_mode(iocon::vals::PioMode::INACTIVE);
+                    w.set_slew(iocon::vals::PioSlew::STANDARD);
+                    w.set_invert(false);
+                    w.set_digimode(iocon::vals::PioDigimode::DIGITAL);
+                    w.set_od(iocon::vals::PioOd::NORMAL);
+                });
+            })
+        }
+
+        if let Some(rx_pin) = rx {
+            match_iocon!(register, rx_pin.pin_bank(), rx_pin.pin_number(), {
+                register.modify(|w| {
+                    w.set_func(T::rx_pin_func());
+                    w.set_mode(iocon::vals::PioMode::INACTIVE);
+                    w.set_slew(iocon::vals::PioSlew::STANDARD);
+                    w.set_invert(false);
+                    w.set_digimode(iocon::vals::PioDigimode::DIGITAL);
+                    w.set_od(iocon::vals::PioOd::NORMAL);
+                });
+            })
+        };
+    }
+
+    fn configure_flexcomm(flexcomm_register: crate::pac::flexcomm::Flexcomm, instance_number: usize) {
+        critical_section::with(|_cs| {
+            if !(SYSCON.ahbclkctrl0().read().iocon()) {
+                SYSCON.ahbclkctrl0().modify(|w| w.set_iocon(true));
+            }
+        });
+        critical_section::with(|_cs| {
+            if !(SYSCON.ahbclkctrl1().read().fc(instance_number)) {
+                SYSCON.ahbclkctrl1().modify(|w| w.set_fc(instance_number, true));
+            }
+        });
+        SYSCON
+            .presetctrl1()
+            .modify(|w| w.set_fc_rst(instance_number, syscon::vals::FcRst::ASSERTED));
+        SYSCON
+            .presetctrl1()
+            .modify(|w| w.set_fc_rst(instance_number, syscon::vals::FcRst::RELEASED));
+        flexcomm_register
+            .pselid()
+            .modify(|w| w.set_persel(flexcomm::vals::Persel::USART));
+    }
+
+    fn configure_usart(info: &'static Info, config: &Config) {
+        let registers = info.usart_reg;
+        // See section 34.6.1
+        registers.cfg().modify(|w| {
+            // LIN break mode enable
+            // Disabled. Break detect and generate is configured for normal operation.
+            w.set_linmode(false);
+            //CTS Enable. Determines whether CTS is used for flow control. CTS can be from the
+            //input pin, or from the USART’s own RTS if loopback mode is enabled.
+            // No flow control. The transmitter does not receive any automatic flow control signal.
+            w.set_ctsen(false);
+            // Selects synchronous or asynchronous operation.
+            w.set_syncen(usart::vals::Syncen::ASYNCHRONOUS_MODE);
+            // Selects the clock polarity and sampling edge of received data in synchronous mode.
+            w.set_clkpol(usart::vals::Clkpol::RISING_EDGE);
+            // Synchronous mode Master select.
+            // When synchronous mode is enabled, the USART is a master.
+            w.set_syncmst(usart::vals::Syncmst::MASTER);
+            // Selects data loopback mode
+            w.set_loop_(usart::vals::Loop::NORMAL);
+            // Output Enable Turnaround time enable for RS-485 operation.
+            // Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of
+            // the last stop bit of a transmission.
+            w.set_oeta(false);
+            // Output enable select.
+            // Standard. The RTS signal is used as the standard flow control function.
+            w.set_oesel(usart::vals::Oesel::STANDARD);
+            // Automatic address matching enable.
+            // Disabled. When addressing is enabled by ADDRDET, address matching is done by
+            // software. This provides the possibility of versatile addressing (e.g. respond to more
+            // than one address)
+            w.set_autoaddr(false);
+            // Output enable polarity.
+            // Low. If selected by OESEL, the output enable is active low.
+            w.set_oepol(usart::vals::Oepol::LOW);
+        });
+
+        // Configurations based on the config written by a user
+        registers.cfg().modify(|w| {
+            w.set_datalen(match config.data_bits {
+                DataBits::DataBits7 => usart::vals::Datalen::BIT_7,
+                DataBits::DataBits8 => usart::vals::Datalen::BIT_8,
+                DataBits::DataBits9 => usart::vals::Datalen::BIT_9,
+            });
+            w.set_paritysel(match config.parity {
+                Parity::ParityNone => usart::vals::Paritysel::NO_PARITY,
+                Parity::ParityEven => usart::vals::Paritysel::EVEN_PARITY,
+                Parity::ParityOdd => usart::vals::Paritysel::ODD_PARITY,
+            });
+            w.set_stoplen(match config.stop_bits {
+                StopBits::Stop1 => usart::vals::Stoplen::BIT_1,
+                StopBits::Stop2 => usart::vals::Stoplen::BITS_2,
+            });
+            w.set_rxpol(match config.invert_rx {
+                false => usart::vals::Rxpol::STANDARD,
+                true => usart::vals::Rxpol::INVERTED,
+            });
+            w.set_txpol(match config.invert_tx {
+                false => usart::vals::Txpol::STANDARD,
+                true => usart::vals::Txpol::INVERTED,
+            });
+        });
+
+        // DMA-related settings
+        registers.fifocfg().modify(|w| {
+            w.set_dmatx(false);
+            w.set_dmatx(false);
+        });
+
+        // Enabling USART
+        registers.fifocfg().modify(|w| {
+            w.set_enabletx(true);
+            w.set_enablerx(true);
+        });
+        registers.cfg().modify(|w| w.set_enable(true));
+
+        // Drain RX FIFO in case it still has some unrelevant data
+        while registers.fifostat().read().rxnotempty() {
+            let _ = registers.fiford().read().0;
+        }
     }
 }
 
-impl<'d, T: Instance, M: Mode> Usart<'d, T, M> {
+impl<'d, M: Mode> Usart<'d, M> {
     /// Transmit the provided buffer blocking execution until done.
     pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<(), Error> {
         self.tx.blocking_write(buffer)
@@ -304,19 +501,19 @@ impl<'d, T: Instance, M: Mode> Usart<'d, T, M> {
 
     /// Split the Usart into a transmitter and receiver, which is particularly
     /// useful when having two tasks correlating to transmitting and receiving.
-    pub fn split(self) -> (UsartTx<'d, T, M>, UsartRx<'d, T, M>) {
+    pub fn split(self) -> (UsartTx<'d, M>, UsartRx<'d, M>) {
         (self.tx, self.rx)
     }
 
     /// Split the Usart into a transmitter and receiver by mutable reference,
     /// which is particularly useful when having two tasks correlating to
     /// transmitting and receiving.
-    pub fn split_ref(&mut self) -> (&mut UsartTx<'d, T, M>, &mut UsartRx<'d, T, M>) {
+    pub fn split_ref(&mut self) -> (&mut UsartTx<'d, M>, &mut UsartRx<'d, M>) {
         (&mut self.tx, &mut self.rx)
     }
 }
 
-impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::serial::Write<u8> for UsartTx<'d, T, M> {
+impl<'d, M: Mode> embedded_hal_02::blocking::serial::Write<u8> for UsartTx<'d, M> {
     type Error = Error;
 
     fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
@@ -328,7 +525,7 @@ impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::serial::Write<u8> for
     }
 }
 
-impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::serial::Write<u8> for Usart<'d, T, M> {
+impl<'d, M: Mode> embedded_hal_02::blocking::serial::Write<u8> for Usart<'d, M> {
     type Error = Error;
 
     fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
@@ -340,11 +537,11 @@ impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::serial::Write<u8> for
     }
 }
 
-impl<'d, T: Instance> embedded_io::ErrorType for UsartTx<'d, T, Blocking> {
+impl<'d> embedded_io::ErrorType for UsartTx<'d, Blocking> {
     type Error = Error;
 }
 
-impl<'d, T: Instance> embedded_io::Write for UsartTx<'d, T, Blocking> {
+impl<'d> embedded_io::Write for UsartTx<'d, Blocking> {
     fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
         self.blocking_write(buf).map(|_| buf.len())
     }
@@ -354,21 +551,21 @@ impl<'d, T: Instance> embedded_io::Write for UsartTx<'d, T, Blocking> {
     }
 }
 
-impl<'d, T: Instance> embedded_io::ErrorType for UsartRx<'d, T, Blocking> {
+impl<'d> embedded_io::ErrorType for UsartRx<'d, Blocking> {
     type Error = Error;
 }
 
-impl<'d, T: Instance> embedded_io::Read for UsartRx<'d, T, Blocking> {
+impl<'d> embedded_io::Read for UsartRx<'d, Blocking> {
     fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
         self.blocking_read(buf).map(|_| buf.len())
     }
 }
 
-impl<'d, T: Instance> embedded_io::ErrorType for Usart<'d, T, Blocking> {
+impl<'d> embedded_io::ErrorType for Usart<'d, Blocking> {
     type Error = Error;
 }
 
-impl<'d, T: Instance> embedded_io::Write for Usart<'d, T, Blocking> {
+impl<'d> embedded_io::Write for Usart<'d, Blocking> {
     fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
         self.blocking_write(buf).map(|_| buf.len())
     }
@@ -378,468 +575,69 @@ impl<'d, T: Instance> embedded_io::Write for Usart<'d, T, Blocking> {
     }
 }
 
-impl<'d, T: Instance> embedded_io::Read for Usart<'d, T, Blocking> {
+impl<'d> embedded_io::Read for Usart<'d, Blocking> {
     fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
         self.blocking_read(buf).map(|_| buf.len())
     }
 }
 
-type UsartRegBlock = crate::pac::usart0::RegisterBlock;
-
-mod sealed {
-    use crate::usart::inner::UsartRegBlock;
-    use crate::usart::{Config, Error};
-    pub trait SealedInstance {
-        fn usart_reg() -> &'static UsartRegBlock;
-        fn enable_clock();
-        fn select_clock(baudrate: u32) -> u32;
-        fn configure_flexcomm();
-        fn set_baudrate(mult_value: u8, brg_value: u8);
-        fn reset_flexcomm();
-        fn tx_pin_config();
-        fn rx_pin_config();
-
-        fn configure_usart(config: Config) {
-            // See section 34.6.1
-            Self::usart_reg().cfg.modify(|_, w| {
-                // LIN break mode enable
-                w.linmode()
-                    // Disabled. Break detect and generate is configured for normal operation.
-                    .disabled()
-                    //CTS Enable. Determines whether CTS is used for flow control. CTS can be from the
-                    //input pin, or from the USART’s own RTS if loopback mode is enabled.
-                    .ctsen()
-                    // No flow control. The transmitter does not receive any automatic flow control signal.
-                    .disabled()
-                    // Selects synchronous or asynchronous operation.
-                    .syncen()
-                    .asynchronous_mode()
-                    // Selects the clock polarity and sampling edge of received data in synchronous mode.
-                    .clkpol()
-                    .rising_edge()
-                    // Synchronous mode Master select.
-                    .syncmst()
-                    // When synchronous mode is enabled, the USART is a master.
-                    .master()
-                    // Selects data loopback mode
-                    .loop_()
-                    // Normal operation
-                    .normal()
-                    // Output Enable Turnaround time enable for RS-485 operation.
-                    .oeta()
-                    // Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of
-                    // the last stop bit of a transmission.
-                    .disabled()
-                    // Output enable select.
-                    .oesel()
-                    // Standard. The RTS signal is used as the standard flow control function.
-                    .standard()
-                    // Automatic address matching enable.
-                    .autoaddr()
-                    // Disabled. When addressing is enabled by ADDRDET, address matching is done by
-                    // software. This provides the possibility of versatile addressing (e.g. respond to more
-                    // than one address)
-                    .disabled()
-                    // Output enable polarity.
-                    .oepol()
-                    // Low. If selected by OESEL, the output enable is active low.
-                    .low()
-            });
+struct Info {
+    usart_reg: UsartReg,
+    fc_reg: FlexcommReg,
+}
 
-            Self::usart_reg().cfg.modify(|_, w| unsafe {
-                w.datalen()
-                    .bits(config.data_bits.bits())
-                    .paritysel()
-                    .bits(config.parity.bits())
-                    .stoplen()
-                    .bit(config.stop_bits.bits())
-                    .rxpol()
-                    .bit(config.invert_rx)
-                    .txpol()
-                    .bit(config.invert_tx)
-            });
-        }
-        fn disable_dma() {
-            Self::usart_reg()
-                .fifocfg
-                .modify(|_, w| w.dmatx().disabled().dmarx().disabled());
-        }
-        fn enable_usart() {
-            Self::usart_reg()
-                .fifocfg
-                .modify(|_, w| w.enabletx().enabled().enablerx().enabled());
-            Self::usart_reg().cfg.modify(|_, w| w.enable().enabled());
-            while Self::usart_reg().fifostat.read().rxnotempty().bit_is_set() {
-                let _ = Self::usart_reg().fiford.read().bits();
-            }
-        }
-        fn blocking_write(buffer: &[u8]) -> Result<(), Error> {
-            for &b in buffer {
-                while Self::usart_reg().fifostat.read().txnotfull().bit_is_clear() {}
-                Self::usart_reg()
-                    .fifowr
-                    .modify(|_, w| unsafe { w.txdata().bits(b as u16) });
-            }
-            Ok(())
-        }
-        fn blocking_flush() -> Result<(), Error> {
-            while Self::usart_reg().fifostat.read().txempty().bit_is_clear() {}
-            Ok(())
-        }
-        fn tx_busy() -> bool {
-            Self::usart_reg().fifostat.read().txempty().bit_is_clear()
-        }
-        fn drain_fifo(buffer: &mut [u8]) -> Result<usize, (usize, Error)> {
-            for (i, b) in buffer.iter_mut().enumerate() {
-                while Self::usart_reg().fifostat.read().rxnotempty().bit_is_clear() {}
-
-                if Self::usart_reg().fifostat.read().rxerr().bit_is_set() {
-                    return Err((i, Error::Overrun));
-                } else if Self::usart_reg().fifordnopop.read().parityerr().bit_is_set() {
-                    return Err((i, Error::Parity));
-                } else if Self::usart_reg().fifordnopop.read().framerr().bit_is_set() {
-                    return Err((i, Error::Framing));
-                } else if Self::usart_reg().fifordnopop.read().rxnoise().bit_is_set() {
-                    return Err((i, Error::Noise));
-                } else if Self::usart_reg().intstat.read().deltarxbrk().bit_is_set() {
-                    return Err((i, Error::Break));
-                }
-                let dr = Self::usart_reg().fiford.read().bits() as u8;
-                *b = dr;
-            }
-            Ok(buffer.len())
-        }
-    }
+trait SealedInstance {
+    fn info() -> &'static Info;
+    fn instance_number() -> usize;
+    fn tx_pin_func() -> PioFunc;
+    fn rx_pin_func() -> PioFunc;
 }
 
 /// UART instance.
 #[allow(private_bounds)]
-pub trait Instance: sealed::SealedInstance + PeripheralType {}
+pub trait Instance: SealedInstance + PeripheralType {}
 
-#[macro_export]
 macro_rules! impl_instance {
-    (
-        $inst:ident,
-        usart_peripheral: $USARTX:ident,
-        usart_crate: $usartX:ident,
-
-        flexcomm: {
-          field: $FLEXCOMM_FIELD:ident,
-          clock_field: $FLEXCOMM_CLK_FIELD:ident
-        },
-
-        reset: {
-            bit: $RESET_BIT:ident
-        },
-
-        clock: {
-            sel_field: $CLKSEL_FIELD:ident,
-            frg_field: $FRG_FIELD:ident
-        },
-
-        pins: {
-            tx: $TX_IOCON:ident => $TX_FUNC:expr,
-            rx: $RX_IOCON:ident => $RX_FUNC:expr
-        }
-
-    ) => {
-        impl $crate::usart::SealedInstance for $crate::peripherals::$inst {
-            fn usart_reg() -> &'static UsartRegBlock {
-                unsafe { &*$crate::pac::$USARTX::ptr() }
-            }
-
-            fn enable_clock() {
-                critical_section::with(|_cs| {
-                    if syscon_reg().ahbclkctrl0.read().iocon().is_disable() {
-                        syscon_reg().ahbclkctrl0.modify(|_, w| w.iocon().enable());
-                    }
-                    if syscon_reg().ahbclkctrl1.read().$FLEXCOMM_CLK_FIELD().is_disable() {
-                        syscon_reg()
-                            .ahbclkctrl1
-                            .modify(|_, w| w.$FLEXCOMM_CLK_FIELD().enable());
-                    }
-                });
-            }
-
-            fn configure_flexcomm() {
-                let flexcomm = unsafe { &*$crate::pac::$FLEXCOMM_FIELD::ptr() };
-                flexcomm.pselid.modify(|_, w| w.persel().usart());
-            }
-
-            fn reset_flexcomm() {
-                syscon_reg().presetctrl1.modify(|_, w| w.$RESET_BIT().set_bit());
-                syscon_reg().presetctrl1.modify(|_, w| w.$RESET_BIT().clear_bit());
-            }
-
-            fn select_clock(baudrate: u32) -> u32 {
-                // Adaptive clock choice based on baud rate
-                // To get the desired baud rate, it is essential to choose the clock bigger than baud rate so that it can be 'chiseled'
-                // There are two types of dividers: integer divider (baud rate generator register and oversample selection value)
-                // and fractional divider (fractional rate divider).
-
-                // By default, oversampling rate is 16 which is an industry standard.
-                // That means 16 clocks are used to deliver the byte to recipient.
-                // In this way the probability of getting correct bytes instead of noise directly increases as oversampling increases as well.
-
-                // Minimum and maximum values were computed taking these formulas into account:
-                // For minimum value, MULT = 0, BRGVAL = 0
-                // For maximum value, MULT = 255, BRGVAL = 255
-                // Flexcomm Interface function clock = (clock selected via FCCLKSEL) / (1 + MULT / DIV)
-                // By default, OSRVAL = 15 (see above)
-                // Baud rate = [FCLK / (OSRVAL+1)] / (BRGVAL + 1)
-                return match baudrate {
-                    750_001..=6000000 => {
-                        syscon_reg().$CLKSEL_FIELD().write(|w| w.sel().enum_0x3()); // 96 MHz
-                        96_000_000
-                    }
-                    1501..=750_000 => {
-                        syscon_reg().$CLKSEL_FIELD().write(|w| w.sel().enum_0x2()); // 12 MHz
-                        12_000_000
-                    }
-                    121..=1500 => {
-                        syscon_reg().$CLKSEL_FIELD().write(|w| w.sel().enum_0x4()); // 1 MHz
-                        1_000_000
-                    }
-                    _ => {
-                        panic!("{} baudrate is not permitted in this mode", baudrate);
-                    }
+    ($inst:ident, $fc:ident, $tx_pin:ident, $rx_pin:ident, $fc_num:expr) => {
+        impl $crate::usart::inner::SealedInstance for $crate::peripherals::$inst {
+            fn info() -> &'static Info {
+                static INFO: Info = Info {
+                    usart_reg: crate::pac::$inst,
+                    fc_reg: crate::pac::$fc,
                 };
+                &INFO
             }
-
-            fn set_baudrate(mult_value: u8, brg_value: u8) {
-                // FCLK =  (clock selected via FCCLKSEL) / (1+ MULT / DIV)
-                // Remark: To use the fractional baud rate generator, 0xFF must be wirtten to the DIV value
-                // to yield a denominator vale of 256. All other values are not supported
-                syscon_reg()
-                    .$FRG_FIELD()
-                    .modify(|_, w| unsafe { w.div().bits(0xFF).mult().bits(mult_value as u8) });
-
-                // Baud rate = [FCLK / (OSRVAL+1)] / (BRGVAL + 1)
-                // By default, oversampling is 16x, i.e. OSRVAL = 15
-
-                // Typical industry standard USARTs use a 16x oversample clock to transmit and receive
-                // asynchronous data. This is the number of BRG clocks used for one data bit. The
-                // Oversample Select Register (OSR) allows this USART to use a 16x down to a 5x
-                // oversample clock. There is no oversampling in synchronous modes.
-                Self::usart_reg()
-                    .brg
-                    .modify(|_, w| unsafe { w.brgval().bits((brg_value - 1) as u16) });
+            #[inline]
+            fn instance_number() -> usize {
+                $fc_num
             }
-
-            fn tx_pin_config() {
-                iocon_reg().$TX_IOCON.modify(|_, w| unsafe {
-                    w.func()
-                        .bits($TX_FUNC)
-                        .digimode()
-                        .digital()
-                        .slew()
-                        .standard()
-                        .mode()
-                        .inactive()
-                        .invert()
-                        .disabled()
-                        .od()
-                        .normal()
-                });
+            #[inline]
+            fn tx_pin_func() -> PioFunc {
+                PioFunc::$tx_pin
             }
-
-            fn rx_pin_config() {
-                iocon_reg().$RX_IOCON.modify(|_, w| unsafe {
-                    w.func()
-                        .bits($RX_FUNC)
-                        .digimode()
-                        .digital()
-                        .slew()
-                        .standard()
-                        .mode()
-                        .inactive()
-                        .invert()
-                        .disabled()
-                        .od()
-                        .normal()
-                });
+            #[inline]
+            fn rx_pin_func() -> PioFunc {
+                PioFunc::$rx_pin
             }
         }
-
         impl $crate::usart::Instance for $crate::peripherals::$inst {}
     };
 }
 
-impl_instance!(USART0, usart_peripheral: USART0, usart_crate: usart0,
-    flexcomm: {
-        field: FLEXCOMM0,
-        clock_field: fc0
-    },
-
-    reset: {
-        bit: fc0_rst
-    },
-
-    clock: {
-        sel_field: fcclksel0,
-        frg_field: flexfrg0ctrl
-    },
-
-    pins: {
-        tx: pio1_6 => 1,
-        rx: pio1_5 => 1
-    }
-);
-
-impl_instance!(USART1, usart_peripheral: USART1, usart_crate: usart1,
-    flexcomm: {
-        field: FLEXCOMM1,
-        clock_field: fc1
-    },
-
-    reset: {
-        bit: fc1_rst
-    },
-
-    clock: {
-        sel_field: fcclksel1,
-        frg_field: flexfrg1ctrl
-    },
-
-    pins: {
-        tx: pio1_11 => 2,
-        rx: pio1_10 => 2
-    }
-);
-
-impl_instance!(USART2, usart_peripheral: USART2, usart_crate: usart2,
-    flexcomm: {
-        field: FLEXCOMM2,
-        clock_field: fc2
-    },
-
-    reset: {
-        bit: fc2_rst
-    },
-
-    clock: {
-        sel_field: fcclksel2,
-        frg_field: flexfrg2ctrl
-    },
-
-    pins: {
-        tx: pio0_27 => 1,
-        rx: pio1_24 => 1
-    }
-);
-
-impl_instance!(USART3, usart_peripheral: USART3, usart_crate: usart3,
-    flexcomm: {
-        field: FLEXCOMM3,
-        clock_field: fc3
-    },
-
-    reset: {
-        bit: fc3_rst
-    },
-
-    clock: {
-        sel_field: fcclksel3,
-        frg_field: flexfrg3ctrl
-    },
-
-    pins: {
-        tx: pio0_2 => 1,
-        rx: pio0_3 => 1
-    }
-);
-
-impl_instance!(USART4, usart_peripheral: USART4, usart_crate: usart4,
-    flexcomm: {
-        field: FLEXCOMM4,
-        clock_field: fc4
-    },
-
-    reset: {
-        bit: fc4_rst
-    },
-
-    clock: {
-        sel_field: fcclksel4,
-        frg_field: flexfrg4ctrl
-    },
-
-    pins: {
-        tx: pio0_16 => 1,
-        rx: pio0_5 => 2
-    }
-);
-
-impl_instance!(USART5, usart_peripheral: USART5, usart_crate: usart5,
-    flexcomm: {
-        field: FLEXCOMM5,
-        clock_field: fc5
-    },
-
-    reset: {
-        bit: fc5_rst
-    },
-
-    clock: {
-        sel_field: fcclksel5,
-        frg_field: flexfrg5ctrl
-    },
-
-    pins: {
-        tx: pio0_9 => 3,
-        rx: pio0_8 => 3
-    }
-);
-
-impl_instance!(USART6, usart_peripheral: USART6, usart_crate: usart6,
-    flexcomm: {
-        field: FLEXCOMM6,
-        clock_field: fc6
-    },
-
-    reset: {
-        bit: fc6_rst
-    },
-
-    clock: {
-        sel_field: fcclksel6,
-        frg_field: flexfrg6ctrl
-    },
-
-    pins: {
-        tx: pio1_16 => 2,
-        rx: pio1_13 => 2
-    }
-);
-
-impl_instance!(USART7, usart_peripheral: USART7, usart_crate: usart7,
-    flexcomm: {
-        field: FLEXCOMM7,
-        clock_field: fc7
-    },
-
-    reset: {
-        bit: fc7_rst
-    },
-
-    clock: {
-        sel_field: fcclksel7,
-        frg_field: flexfrg7ctrl
-    },
-
-    pins: {
-        tx: pio0_19 => 7,
-        rx: pio0_20 => 7
-    }
-);
+impl_instance!(USART0, FLEXCOMM0, ALT1, ALT1, 0);
+impl_instance!(USART1, FLEXCOMM1, ALT2, ALT2, 1);
+impl_instance!(USART2, FLEXCOMM2, ALT1, ALT1, 2);
+impl_instance!(USART3, FLEXCOMM3, ALT1, ALT1, 3);
+impl_instance!(USART4, FLEXCOMM4, ALT1, ALT2, 4);
+impl_instance!(USART5, FLEXCOMM5, ALT3, ALT3, 5);
+impl_instance!(USART6, FLEXCOMM6, ALT2, ALT2, 6);
+impl_instance!(USART7, FLEXCOMM7, ALT7, ALT7, 7);
 
 /// Trait for TX pins.
 pub trait TxPin<T: Instance>: crate::gpio::Pin {}
 /// Trait for RX pins.
 pub trait RxPin<T: Instance>: crate::gpio::Pin {}
 
-// TODO: Add RTS, CTS and CLK pin traits
-
 macro_rules! impl_pin {
     ($pin:ident, $instance:ident, Tx) => {
         impl TxPin<crate::peripherals::$instance> for crate::peripherals::$pin {}
@@ -849,37 +647,19 @@ macro_rules! impl_pin {
     };
 }
 
-impl_pin!(PIO1_5, USART0, Rx);
 impl_pin!(PIO1_6, USART0, Tx);
-impl_pin!(PIO1_10, USART1, Rx);
+impl_pin!(PIO1_5, USART0, Rx);
 impl_pin!(PIO1_11, USART1, Tx);
+impl_pin!(PIO1_10, USART1, Rx);
 impl_pin!(PIO0_27, USART2, Tx);
 impl_pin!(PIO1_24, USART2, Rx);
 impl_pin!(PIO0_2, USART3, Tx);
 impl_pin!(PIO0_3, USART3, Rx);
 impl_pin!(PIO0_16, USART4, Tx);
 impl_pin!(PIO0_5, USART4, Rx);
-impl_pin!(PIO0_8, USART5, Rx);
 impl_pin!(PIO0_9, USART5, Tx);
+impl_pin!(PIO0_8, USART5, Rx);
 impl_pin!(PIO1_16, USART6, Tx);
 impl_pin!(PIO1_13, USART6, Rx);
-impl_pin!(PIO0_20, USART7, Rx);
 impl_pin!(PIO0_19, USART7, Tx);
-
-/// Get the SYSCON register block.
-///
-/// # Safety
-/// Read/Write operations on a single registers are NOT atomic. You must ensure that the GPIO
-/// registers are not accessed concurrently by multiple threads.
-pub(crate) fn syscon_reg() -> &'static crate::pac::syscon::RegisterBlock {
-    unsafe { &*crate::pac::SYSCON::ptr() }
-}
-
-/// Get the IOCON register block.
-///
-/// # Safety
-/// Read/Write operations on a single registers are NOT atomic. You must ensure that the GPIO
-/// registers are not accessed concurrently by multiple threads.
-pub(crate) fn iocon_reg() -> &'static crate::pac::iocon::RegisterBlock {
-    unsafe { &*crate::pac::IOCON::ptr() }
-}
+impl_pin!(PIO0_20, USART7, Rx);
diff --git a/embassy-rp/CHANGELOG.md b/embassy-rp/CHANGELOG.md
index ebdc3e1c8..d1265ffc4 100644
--- a/embassy-rp/CHANGELOG.md
+++ b/embassy-rp/CHANGELOG.md
@@ -8,6 +8,11 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 <!-- next-header -->
 ## Unreleased - ReleaseDate
 
+- Add PIO SPI
+- Add PIO I2S input
+- Add PIO onewire parasite power strong pullup
+- add `wait_for_alarm` and `alarm_scheduled` methods to rtc module ([#4216](https://github.com/embassy-rs/embassy/pull/4216))
+
 ## 0.8.0 - 2025-08-26
 
 ## 0.7.1 - 2025-08-26
@@ -51,7 +56,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ## 0.4.0 - 2025-03-09
 
-- Add PIO functions. ([#3857](https://github.com/embassy-rs/embassy/pull/3857))  
+- Add PIO functions. ([#3857](https://github.com/embassy-rs/embassy/pull/3857))
   The functions added in this change are `get_addr` `get_tx_threshold`, `set_tx_threshold`, `get_rx_threshold`, `set_rx_threshold`, `set_thresholds`.
 - Expose the watchdog reset reason. ([#3877](https://github.com/embassy-rs/embassy/pull/3877))
 - Update pio-rs, reexport, move instr methods to SM. ([#3865](https://github.com/embassy-rs/embassy/pull/3865))
@@ -92,7 +97,7 @@ Small release fixing a few gnarly bugs, upgrading is strongly recommended.
 - Add Clone and Copy to Error types
 - fix spinlocks staying locked after reset.
 - wait until read matches for PSM accesses.
-- Remove generics 
+- Remove generics
 - fix drop implementation of BufferedUartRx and BufferedUartTx
 - implement `embedded_storage_async::nor_flash::MultiwriteNorFlash`
 - rp usb: wake ep-wakers after stalling
diff --git a/embassy-rp/src/lib.rs b/embassy-rp/src/lib.rs
index eb497de1a..6fb680b34 100644
--- a/embassy-rp/src/lib.rs
+++ b/embassy-rp/src/lib.rs
@@ -35,7 +35,11 @@ pub mod multicore;
 #[cfg(feature = "_rp235x")]
 pub mod otp;
 pub mod pio_programs;
+#[cfg(feature = "_rp235x")]
+pub mod psram;
 pub mod pwm;
+#[cfg(feature = "_rp235x")]
+pub mod qmi_cs1;
 mod reset;
 pub mod rom_data;
 #[cfg(feature = "rp2040")]
@@ -381,6 +385,8 @@ embassy_hal_internal::peripherals! {
     SPI0,
     SPI1,
 
+    QMI_CS1,
+
     I2C0,
     I2C1,
 
diff --git a/embassy-rp/src/pio/mod.rs b/embassy-rp/src/pio/mod.rs
index 0d8a94776..5f554dfe3 100644
--- a/embassy-rp/src/pio/mod.rs
+++ b/embassy-rp/src/pio/mod.rs
@@ -12,7 +12,7 @@ use fixed::types::extra::U8;
 use fixed::FixedU32;
 use pio::{Program, SideSet, Wrap};
 
-use crate::dma::{Channel, Transfer, Word};
+use crate::dma::{self, Channel, Transfer, Word};
 use crate::gpio::{self, AnyPin, Drive, Level, Pull, SealedPin, SlewRate};
 use crate::interrupt::typelevel::{Binding, Handler, Interrupt};
 use crate::relocate::RelocatedProgram;
@@ -281,6 +281,18 @@ impl<'l, PIO: Instance> Pin<'l, PIO> {
         });
     }
 
+    /// Configure the output logic inversion of this pin.
+    #[inline]
+    pub fn set_output_inversion(&mut self, invert: bool) {
+        self.pin.gpio().ctrl().modify(|w| {
+            w.set_outover(if invert {
+                pac::io::vals::Outover::INVERT
+            } else {
+                pac::io::vals::Outover::NORMAL
+            })
+        });
+    }
+
     /// Set the pin's input sync bypass.
     pub fn set_input_sync_bypass(&mut self, bypass: bool) {
         let mask = 1 << self.pin();
@@ -360,6 +372,10 @@ impl<'d, PIO: Instance, const SM: usize> StateMachineRx<'d, PIO, SM> {
         FifoInFuture::new(self)
     }
 
+    fn dreq() -> crate::pac::dma::vals::TreqSel {
+        crate::pac::dma::vals::TreqSel::from(PIO::PIO_NO * 8 + SM as u8 + 4)
+    }
+
     /// Prepare DMA transfer from RX FIFO.
     pub fn dma_pull<'a, C: Channel, W: Word>(
         &'a mut self,
@@ -367,7 +383,6 @@ impl<'d, PIO: Instance, const SM: usize> StateMachineRx<'d, PIO, SM> {
         data: &'a mut [W],
         bswap: bool,
     ) -> Transfer<'a, C> {
-        let pio_no = PIO::PIO_NO;
         let p = ch.regs();
         p.write_addr().write_value(data.as_ptr() as u32);
         p.read_addr().write_value(PIO::PIO.rxf(SM).as_ptr() as u32);
@@ -377,8 +392,7 @@ impl<'d, PIO: Instance, const SM: usize> StateMachineRx<'d, PIO, SM> {
         p.trans_count().write(|w| w.set_count(data.len() as u32));
         compiler_fence(Ordering::SeqCst);
         p.ctrl_trig().write(|w| {
-            // Set RX DREQ for this statemachine
-            w.set_treq_sel(crate::pac::dma::vals::TreqSel::from(pio_no * 8 + SM as u8 + 4));
+            w.set_treq_sel(Self::dreq());
             w.set_data_size(W::size());
             w.set_chain_to(ch.number());
             w.set_incr_read(false);
@@ -389,6 +403,36 @@ impl<'d, PIO: Instance, const SM: usize> StateMachineRx<'d, PIO, SM> {
         compiler_fence(Ordering::SeqCst);
         Transfer::new(ch)
     }
+
+    /// Prepare a repeated DMA transfer from RX FIFO.
+    pub fn dma_pull_repeated<'a, C: Channel, W: Word>(&'a mut self, ch: Peri<'a, C>, len: usize) -> Transfer<'a, C> {
+        // This is the read version of dma::write_repeated. This allows us to
+        // discard reads from the RX FIFO through DMA.
+
+        // static mut so it gets allocated in RAM
+        static mut DUMMY: u32 = 0;
+
+        let p = ch.regs();
+        p.write_addr().write_value(core::ptr::addr_of_mut!(DUMMY) as u32);
+        p.read_addr().write_value(PIO::PIO.rxf(SM).as_ptr() as u32);
+
+        #[cfg(feature = "rp2040")]
+        p.trans_count().write(|w| *w = len as u32);
+        #[cfg(feature = "_rp235x")]
+        p.trans_count().write(|w| w.set_count(len as u32));
+
+        compiler_fence(Ordering::SeqCst);
+        p.ctrl_trig().write(|w| {
+            w.set_treq_sel(Self::dreq());
+            w.set_data_size(W::size());
+            w.set_chain_to(ch.number());
+            w.set_incr_read(false);
+            w.set_incr_write(false);
+            w.set_en(true);
+        });
+        compiler_fence(Ordering::SeqCst);
+        Transfer::new(ch)
+    }
 }
 
 /// Type representing a state machine TX FIFO.
@@ -412,7 +456,7 @@ impl<'d, PIO: Instance, const SM: usize> StateMachineTx<'d, PIO, SM> {
         (PIO::PIO.flevel().read().0 >> (SM * 8)) as u8 & 0x0f
     }
 
-    /// Check state machine has stalled on empty TX FIFO.
+    /// Check if state machine has stalled on empty TX FIFO.
     pub fn stalled(&self) -> bool {
         let fdebug = PIO::PIO.fdebug();
         let ret = fdebug.read().txstall() & (1 << SM) != 0;
@@ -451,6 +495,10 @@ impl<'d, PIO: Instance, const SM: usize> StateMachineTx<'d, PIO, SM> {
         FifoOutFuture::new(self, value)
     }
 
+    fn dreq() -> crate::pac::dma::vals::TreqSel {
+        crate::pac::dma::vals::TreqSel::from(PIO::PIO_NO * 8 + SM as u8)
+    }
+
     /// Prepare a DMA transfer to TX FIFO.
     pub fn dma_push<'a, C: Channel, W: Word>(
         &'a mut self,
@@ -458,7 +506,6 @@ impl<'d, PIO: Instance, const SM: usize> StateMachineTx<'d, PIO, SM> {
         data: &'a [W],
         bswap: bool,
     ) -> Transfer<'a, C> {
-        let pio_no = PIO::PIO_NO;
         let p = ch.regs();
         p.read_addr().write_value(data.as_ptr() as u32);
         p.write_addr().write_value(PIO::PIO.txf(SM).as_ptr() as u32);
@@ -468,8 +515,7 @@ impl<'d, PIO: Instance, const SM: usize> StateMachineTx<'d, PIO, SM> {
         p.trans_count().write(|w| w.set_count(data.len() as u32));
         compiler_fence(Ordering::SeqCst);
         p.ctrl_trig().write(|w| {
-            // Set TX DREQ for this statemachine
-            w.set_treq_sel(crate::pac::dma::vals::TreqSel::from(pio_no * 8 + SM as u8));
+            w.set_treq_sel(Self::dreq());
             w.set_data_size(W::size());
             w.set_chain_to(ch.number());
             w.set_incr_read(true);
@@ -480,6 +526,11 @@ impl<'d, PIO: Instance, const SM: usize> StateMachineTx<'d, PIO, SM> {
         compiler_fence(Ordering::SeqCst);
         Transfer::new(ch)
     }
+
+    /// Prepare a repeated DMA transfer to TX FIFO.
+    pub fn dma_push_repeated<'a, C: Channel, W: Word>(&'a mut self, ch: Peri<'a, C>, len: usize) -> Transfer<'a, C> {
+        unsafe { dma::write_repeated(ch, PIO::PIO.txf(SM).as_ptr(), len, Self::dreq()) }
+    }
 }
 
 /// A type representing a single PIO state machine.
@@ -926,13 +977,27 @@ impl<'d, PIO: Instance + 'd, const SM: usize> StateMachine<'d, PIO, SM> {
         self.set_enable(enabled);
     }
 
+    #[cfg(feature = "rp2040")]
+    fn pin_base() -> u8 {
+        0
+    }
+
+    #[cfg(feature = "_rp235x")]
+    fn pin_base() -> u8 {
+        if PIO::PIO.gpiobase().read().gpiobase() {
+            16
+        } else {
+            0
+        }
+    }
+
     /// Sets pin directions. This pauses the current state machine to run `SET` commands
     /// and temporarily unsets the `OUT_STICKY` bit.
     pub fn set_pin_dirs(&mut self, dir: Direction, pins: &[&Pin<'d, PIO>]) {
         self.with_paused(|sm| {
             for pin in pins {
                 Self::this_sm().pinctrl().write(|w| {
-                    w.set_set_base(pin.pin());
+                    w.set_set_base(pin.pin() - Self::pin_base());
                     w.set_set_count(1);
                 });
                 // SET PINDIRS, (dir)
@@ -947,7 +1012,7 @@ impl<'d, PIO: Instance + 'd, const SM: usize> StateMachine<'d, PIO, SM> {
         self.with_paused(|sm| {
             for pin in pins {
                 Self::this_sm().pinctrl().write(|w| {
-                    w.set_set_base(pin.pin());
+                    w.set_set_base(pin.pin() - Self::pin_base());
                     w.set_set_count(1);
                 });
                 // SET PINS, (dir)
@@ -1310,6 +1375,7 @@ impl<'d, PIO: Instance> Pio<'d, PIO> {
         PIO::state().users.store(5, Ordering::Release);
         PIO::state().used_pins.store(0, Ordering::Release);
         PIO::Interrupt::unpend();
+
         unsafe { PIO::Interrupt::enable() };
         Self {
             common: Common {
diff --git a/embassy-rp/src/pio_programs/i2s.rs b/embassy-rp/src/pio_programs/i2s.rs
index 7ceed3fa6..2382a3f9f 100644
--- a/embassy-rp/src/pio_programs/i2s.rs
+++ b/embassy-rp/src/pio_programs/i2s.rs
@@ -1,13 +1,101 @@
-//! Pio backed I2s output
+//! Pio backed I2s output and output drivers
 
 use fixed::traits::ToFixed;
 
 use crate::dma::{AnyChannel, Channel, Transfer};
+use crate::gpio::Pull;
 use crate::pio::{
     Common, Config, Direction, FifoJoin, Instance, LoadedProgram, PioPin, ShiftConfig, ShiftDirection, StateMachine,
 };
 use crate::Peri;
 
+/// This struct represents an i2s receiver & controller driver program
+pub struct PioI2sInProgram<'d, PIO: Instance> {
+    prg: LoadedProgram<'d, PIO>,
+}
+
+impl<'d, PIO: Instance> PioI2sInProgram<'d, PIO> {
+    /// Load the input program into the given pio
+    pub fn new(common: &mut Common<'d, PIO>) -> Self {
+        let prg = pio::pio_asm! {
+            ".side_set 2",
+            "   set x, 14               side 0b01",
+            "left_data:",
+            "   in pins, 1              side 0b00", // read one left-channel bit from SD
+            "   jmp x-- left_data       side 0b01",
+            "   in pins, 1              side 0b10", // ws changes 1 clock before MSB
+            "   set x, 14               side 0b11",
+            "right_data:",
+            "   in pins, 1             side 0b10",
+            "   jmp x-- right_data     side 0b11",
+            "   in pins, 1             side 0b00" // ws changes 1 clock before ms
+        };
+        let prg = common.load_program(&prg.program);
+        Self { prg }
+    }
+}
+
+/// Pio backed I2s input driver
+pub struct PioI2sIn<'d, P: Instance, const S: usize> {
+    dma: Peri<'d, AnyChannel>,
+    sm: StateMachine<'d, P, S>,
+}
+
+impl<'d, P: Instance, const S: usize> PioI2sIn<'d, P, S> {
+    /// Configure a state machine to act as both the controller (provider of SCK and WS) and receiver (of SD) for an I2S signal
+    pub fn new(
+        common: &mut Common<'d, P>,
+        mut sm: StateMachine<'d, P, S>,
+        dma: Peri<'d, impl Channel>,
+        // Whether or not to use the MCU's internal pull-down resistor, as the
+        // Pico 2 is known to have problems with the inbuilt pulldowns, many
+        // opt to just use an external pull down resistor to meet requirements of common
+        // i2s microphones such as the INMP441
+        data_pulldown: bool,
+        data_pin: Peri<'d, impl PioPin>,
+        bit_clock_pin: Peri<'d, impl PioPin>,
+        lr_clock_pin: Peri<'d, impl PioPin>,
+        sample_rate: u32,
+        bit_depth: u32,
+        channels: u32,
+        program: &PioI2sInProgram<'d, P>,
+    ) -> Self {
+        let mut data_pin = common.make_pio_pin(data_pin);
+        if data_pulldown {
+            data_pin.set_pull(Pull::Down);
+        }
+        let bit_clock_pin = common.make_pio_pin(bit_clock_pin);
+        let left_right_clock_pin = common.make_pio_pin(lr_clock_pin);
+
+        let cfg = {
+            let mut cfg = Config::default();
+            cfg.use_program(&program.prg, &[&bit_clock_pin, &left_right_clock_pin]);
+            cfg.set_in_pins(&[&data_pin]);
+            let clock_frequency = sample_rate * bit_depth * channels;
+            cfg.clock_divider = (crate::clocks::clk_sys_freq() as f64 / clock_frequency as f64 / 2.).to_fixed();
+            cfg.shift_in = ShiftConfig {
+                threshold: 32,
+                direction: ShiftDirection::Left,
+                auto_fill: true,
+            };
+            // join fifos to have twice the time to start the next dma transfer
+            cfg.fifo_join = FifoJoin::RxOnly; // both control signals are sent via side-setting
+            cfg
+        };
+        sm.set_config(&cfg);
+        sm.set_pin_dirs(Direction::In, &[&data_pin]);
+        sm.set_pin_dirs(Direction::Out, &[&left_right_clock_pin, &bit_clock_pin]);
+        sm.set_enable(true);
+
+        Self { dma: dma.into(), sm }
+    }
+
+    /// Return an in-prograss dma transfer future. Awaiting it will guarentee a complete transfer.
+    pub fn read<'b>(&'b mut self, buff: &'b mut [u32]) -> Transfer<'b, AnyChannel> {
+        self.sm.rx().dma_pull(self.dma.reborrow(), buff, false)
+    }
+}
+
 /// This struct represents an i2s output driver program
 ///
 /// The sample bit-depth is set through scratch register `Y`.
@@ -26,12 +114,12 @@ impl<'d, PIO: Instance> PioI2sOutProgram<'d, PIO> {
             "left_data:",
             "    out pins, 1        side 0b00",
             "    jmp x-- left_data  side 0b01",
-            "    out pins 1         side 0b10",
+            "    out pins, 1        side 0b10",
             "    mov x, y           side 0b11",
             "right_data:",
-            "    out pins 1         side 0b10",
+            "    out pins, 1         side 0b10",
             "    jmp x-- right_data side 0b11",
-            "    out pins 1         side 0b00",
+            "    out pins, 1         side 0b00",
         );
 
         let prg = common.load_program(&prg.program);
diff --git a/embassy-rp/src/pio_programs/mod.rs b/embassy-rp/src/pio_programs/mod.rs
index 8eac328b3..d05ba3884 100644
--- a/embassy-rp/src/pio_programs/mod.rs
+++ b/embassy-rp/src/pio_programs/mod.rs
@@ -6,6 +6,7 @@ pub mod i2s;
 pub mod onewire;
 pub mod pwm;
 pub mod rotary_encoder;
+pub mod spi;
 pub mod stepper;
 pub mod uart;
 pub mod ws2812;
diff --git a/embassy-rp/src/pio_programs/onewire.rs b/embassy-rp/src/pio_programs/onewire.rs
index 287ddab41..980d0fe5f 100644
--- a/embassy-rp/src/pio_programs/onewire.rs
+++ b/embassy-rp/src/pio_programs/onewire.rs
@@ -52,7 +52,8 @@ impl<'a, PIO: Instance> PioOneWireProgram<'a, PIO> {
 
                     ; The low pulse was already done, we only need to delay and poll the bit in case we are reading
                     write_1:
-                        nop                     side 0 [( 6 / CLK) - 1]     ; Delay before sampling the input pin
+                        jmp y--, continue_1     side 0 [( 6 / CLK) - 1]     ; Delay before sampling input. Always decrement y
+                    continue_1:
                         in pins, 1              side 0 [(48 / CLK) - 1]     ; This writes the state of the pin into the ISR
                         ; Fallthrough
 
@@ -61,9 +62,24 @@ impl<'a, PIO: Instance> PioOneWireProgram<'a, PIO> {
                     .wrap_target
                         out x, 1                side 0 [(12 / CLK) - 1]     ; Stalls if no data available in TX FIFO and OSR
                         jmp x--, write_1        side 1 [( 6 / CLK) - 1]     ; Do the always low part of a bit, jump to write_1 if we want to write a 1 bit
-                        in null, 1              side 1 [(54 / CLK) - 1]     ; Do the remainder of the low part of a 0 bit
-                                                                            ; This writes 0 into the ISR so that the shift count stays in sync
+                        jmp y--, continue_0     side 1 [(48 / CLK) - 1]     ; Do the remainder of the low part of a 0 bit
+                        jmp pullup              side 1 [( 6 / CLK) - 1]     ; Remain low while jumping
+                    continue_0:
+                        in null, 1              side 1 [( 6 / CLK) - 1]     ; This writes 0 into the ISR so that the shift count stays in sync
                     .wrap
+
+                    ; Assume that strong pullup commands always have MSB (the last bit) = 0,
+                    ; since the rising edge can be used to start the operation.
+                    ; That's the case for DS18B20 (44h and 48h).
+                    pullup:
+                        set pins, 1             side 1[( 6 / CLK) - 1]      ; Drive pin high output immediately.
+                                                                            ; Strong pullup must be within 10us of rise.
+                        in null, 1              side 1[( 6 / CLK) - 1]      ; Keep ISR in sync. Must occur after the y--.
+                        out null, 8             side 1[( 6 / CLK) - 1]      ; Wait for write_bytes_pullup() delay to complete.
+                                                                            ; The delay is hundreds of ms, so done externally.
+                        set pins, 0             side 0[( 6 / CLK) - 1]      ; Back to open drain, pin low when driven
+                        in null, 8              side 1[( 6 / CLK) - 1]      ; Inform write_bytes_pullup() it's ready
+                        jmp next_bit            side 0[( 6 / CLK) - 1]      ; Continue
             "#
         );
 
@@ -98,6 +114,7 @@ impl<'d, PIO: Instance, const SM: usize> PioOneWire<'d, PIO, SM> {
         let mut cfg = Config::default();
         cfg.use_program(&program.prg, &[&pin]);
         cfg.set_in_pins(&[&pin]);
+        cfg.set_set_pins(&[&pin]);
 
         let shift_cfg = ShiftConfig {
             auto_fill: true,
@@ -146,6 +163,19 @@ impl<'d, PIO: Instance, const SM: usize> PioOneWire<'d, PIO, SM> {
 
     /// Write bytes to the onewire bus
     pub async fn write_bytes(&mut self, data: &[u8]) {
+        unsafe { self.sm.set_y(u32::MAX as u32) };
+        let (rx, tx) = self.sm.rx_tx();
+        for b in data {
+            tx.wait_push(*b as u32).await;
+
+            // Empty the buffer that is being filled with every write
+            let _ = rx.wait_pull().await;
+        }
+    }
+
+    /// Write bytes to the onewire bus, then apply a strong pullup
+    pub async fn write_bytes_pullup(&mut self, data: &[u8], pullup_time: embassy_time::Duration) {
+        unsafe { self.sm.set_y(data.len() as u32 * 8 - 1) };
         let (rx, tx) = self.sm.rx_tx();
         for b in data {
             tx.wait_push(*b as u32).await;
@@ -153,10 +183,19 @@ impl<'d, PIO: Instance, const SM: usize> PioOneWire<'d, PIO, SM> {
             // Empty the buffer that is being filled with every write
             let _ = rx.wait_pull().await;
         }
+
+        // Perform the delay, usually hundreds of ms.
+        embassy_time::Timer::after(pullup_time).await;
+
+        // Signal that delay has completed
+        tx.wait_push(0 as u32).await;
+        // Wait until it's back at 0 low, open drain
+        let _ = rx.wait_pull().await;
     }
 
     /// Read bytes from the onewire bus
     pub async fn read_bytes(&mut self, data: &mut [u8]) {
+        unsafe { self.sm.set_y(u32::MAX as u32) };
         let (rx, tx) = self.sm.rx_tx();
         for b in data {
             // Write all 1's so that we can read what the device responds
diff --git a/embassy-rp/src/pio_programs/spi.rs b/embassy-rp/src/pio_programs/spi.rs
new file mode 100644
index 000000000..b10fc6628
--- /dev/null
+++ b/embassy-rp/src/pio_programs/spi.rs
@@ -0,0 +1,474 @@
+//! PIO backed SPi drivers
+
+use core::marker::PhantomData;
+
+use embassy_futures::join::join;
+use embassy_hal_internal::Peri;
+use embedded_hal_02::spi::{Phase, Polarity};
+use fixed::traits::ToFixed;
+use fixed::types::extra::U8;
+
+use crate::clocks::clk_sys_freq;
+use crate::dma::{AnyChannel, Channel};
+use crate::gpio::Level;
+use crate::pio::{Common, Direction, Instance, LoadedProgram, Pin, PioPin, ShiftDirection, StateMachine};
+use crate::spi::{Async, Blocking, Config, Mode};
+
+/// This struct represents an SPI program loaded into pio instruction memory.
+struct PioSpiProgram<'d, PIO: Instance> {
+    prg: LoadedProgram<'d, PIO>,
+    phase: Phase,
+}
+
+impl<'d, PIO: Instance> PioSpiProgram<'d, PIO> {
+    /// Load the spi program into the given pio
+    pub fn new(common: &mut Common<'d, PIO>, phase: Phase) -> Self {
+        // These PIO programs are taken straight from the datasheet (3.6.1 in
+        // RP2040 datasheet, 11.6.1 in RP2350 datasheet)
+
+        // Pin assignments:
+        // - SCK is side-set pin 0
+        // - MOSI is OUT pin 0
+        // - MISO is IN pin 0
+        //
+        // Auto-push and auto-pull must be enabled, and the serial frame size is set by
+        // configuring the push/pull threshold. Shift left/right is fine, but you must
+        // justify the data yourself. This is done most conveniently for frame sizes of
+        // 8 or 16 bits by using the narrow store replication and narrow load byte
+        // picking behavior of RP2040's IO fabric.
+
+        let prg = match phase {
+            Phase::CaptureOnFirstTransition => {
+                let prg = pio::pio_asm!(
+                    r#"
+                        .side_set 1
+
+                        ; Clock phase = 0: data is captured on the leading edge of each SCK pulse, and
+                        ; transitions on the trailing edge, or some time before the first leading edge.
+
+                        out pins, 1 side 0 [1] ; Stall here on empty (sideset proceeds even if
+                        in pins, 1  side 1 [1] ; instruction stalls, so we stall with SCK low)
+                    "#
+                );
+
+                common.load_program(&prg.program)
+            }
+            Phase::CaptureOnSecondTransition => {
+                let prg = pio::pio_asm!(
+                    r#"
+                        .side_set 1
+
+                        ; Clock phase = 1: data transitions on the leading edge of each SCK pulse, and
+                        ; is captured on the trailing edge.
+
+                        out x, 1    side 0     ; Stall here on empty (keep SCK de-asserted)
+                        mov pins, x side 1 [1] ; Output data, assert SCK (mov pins uses OUT mapping)
+                        in pins, 1  side 0     ; Input data, de-assert SCK
+                    "#
+                );
+
+                common.load_program(&prg.program)
+            }
+        };
+
+        Self { prg, phase }
+    }
+}
+
+/// PIO SPI errors.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[non_exhaustive]
+pub enum Error {
+    // No errors for now
+}
+
+/// PIO based Spi driver.
+/// Unlike other PIO programs, the PIO SPI driver owns and holds a reference to
+/// the PIO memory it uses. This is so that it can be reconfigured at runtime if
+/// desired.
+pub struct Spi<'d, PIO: Instance, const SM: usize, M: Mode> {
+    sm: StateMachine<'d, PIO, SM>,
+    cfg: crate::pio::Config<'d, PIO>,
+    program: Option<PioSpiProgram<'d, PIO>>,
+    clk_pin: Pin<'d, PIO>,
+    tx_dma: Option<Peri<'d, AnyChannel>>,
+    rx_dma: Option<Peri<'d, AnyChannel>>,
+    phantom: PhantomData<M>,
+}
+
+impl<'d, PIO: Instance, const SM: usize, M: Mode> Spi<'d, PIO, SM, M> {
+    #[allow(clippy::too_many_arguments)]
+    fn new_inner(
+        pio: &mut Common<'d, PIO>,
+        mut sm: StateMachine<'d, PIO, SM>,
+        clk_pin: Peri<'d, impl PioPin>,
+        mosi_pin: Peri<'d, impl PioPin>,
+        miso_pin: Peri<'d, impl PioPin>,
+        tx_dma: Option<Peri<'d, AnyChannel>>,
+        rx_dma: Option<Peri<'d, AnyChannel>>,
+        config: Config,
+    ) -> Self {
+        let program = PioSpiProgram::new(pio, config.phase);
+
+        let mut clk_pin = pio.make_pio_pin(clk_pin);
+        let mosi_pin = pio.make_pio_pin(mosi_pin);
+        let miso_pin = pio.make_pio_pin(miso_pin);
+
+        if let Polarity::IdleHigh = config.polarity {
+            clk_pin.set_output_inversion(true);
+        } else {
+            clk_pin.set_output_inversion(false);
+        }
+
+        let mut cfg = crate::pio::Config::default();
+
+        cfg.use_program(&program.prg, &[&clk_pin]);
+        cfg.set_out_pins(&[&mosi_pin]);
+        cfg.set_in_pins(&[&miso_pin]);
+
+        cfg.shift_in.auto_fill = true;
+        cfg.shift_in.direction = ShiftDirection::Left;
+        cfg.shift_in.threshold = 8;
+
+        cfg.shift_out.auto_fill = true;
+        cfg.shift_out.direction = ShiftDirection::Left;
+        cfg.shift_out.threshold = 8;
+
+        cfg.clock_divider = calculate_clock_divider(config.frequency);
+
+        sm.set_config(&cfg);
+
+        sm.set_pins(Level::Low, &[&clk_pin, &mosi_pin]);
+        sm.set_pin_dirs(Direction::Out, &[&clk_pin, &mosi_pin]);
+        sm.set_pin_dirs(Direction::In, &[&miso_pin]);
+
+        sm.set_enable(true);
+
+        Self {
+            sm,
+            program: Some(program),
+            cfg,
+            clk_pin,
+            tx_dma,
+            rx_dma,
+            phantom: PhantomData,
+        }
+    }
+
+    fn blocking_read_u8(&mut self) -> Result<u8, Error> {
+        while self.sm.rx().empty() {}
+        let value = self.sm.rx().pull() as u8;
+
+        Ok(value)
+    }
+
+    fn blocking_write_u8(&mut self, v: u8) -> Result<(), Error> {
+        let value = u32::from_be_bytes([v, 0, 0, 0]);
+
+        while !self.sm.tx().try_push(value) {}
+
+        // need to clear here for flush to work correctly
+        self.sm.tx().stalled();
+
+        Ok(())
+    }
+
+    /// Read data from SPI blocking execution until done.
+    pub fn blocking_read(&mut self, data: &mut [u8]) -> Result<(), Error> {
+        for v in data {
+            self.blocking_write_u8(0)?;
+            *v = self.blocking_read_u8()?;
+        }
+        self.flush()?;
+        Ok(())
+    }
+
+    /// Write data to SPI blocking execution until done.
+    pub fn blocking_write(&mut self, data: &[u8]) -> Result<(), Error> {
+        for v in data {
+            self.blocking_write_u8(*v)?;
+            let _ = self.blocking_read_u8()?;
+        }
+        self.flush()?;
+        Ok(())
+    }
+
+    /// Transfer data to SPI blocking execution until done.
+    pub fn blocking_transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Error> {
+        let len = read.len().max(write.len());
+        for i in 0..len {
+            let wb = write.get(i).copied().unwrap_or(0);
+            self.blocking_write_u8(wb)?;
+
+            let rb = self.blocking_read_u8()?;
+            if let Some(r) = read.get_mut(i) {
+                *r = rb;
+            }
+        }
+        self.flush()?;
+        Ok(())
+    }
+
+    /// Transfer data in place to SPI blocking execution until done.
+    pub fn blocking_transfer_in_place(&mut self, data: &mut [u8]) -> Result<(), Error> {
+        for v in data {
+            self.blocking_write_u8(*v)?;
+            *v = self.blocking_read_u8()?;
+        }
+        self.flush()?;
+        Ok(())
+    }
+
+    /// Block execution until SPI is done.
+    pub fn flush(&mut self) -> Result<(), Error> {
+        // Wait for all words in the FIFO to have been pulled by the SM
+        while !self.sm.tx().empty() {}
+
+        // Wait for last value to be written out to the wire
+        while !self.sm.tx().stalled() {}
+
+        Ok(())
+    }
+
+    /// Set SPI frequency.
+    pub fn set_frequency(&mut self, freq: u32) {
+        self.sm.set_enable(false);
+
+        let divider = calculate_clock_divider(freq);
+
+        // save into the config for later but dont use sm.set_config() since
+        // that operation is relatively more expensive than just setting the
+        // clock divider
+        self.cfg.clock_divider = divider;
+        self.sm.set_clock_divider(divider);
+
+        self.sm.set_enable(true);
+    }
+
+    /// Set SPI config.
+    ///
+    /// This operation will panic if the PIO program needs to be reloaded and
+    /// there is insufficient room. This is unlikely since the programs for each
+    /// phase only differ in size by a single instruction.
+    pub fn set_config(&mut self, pio: &mut Common<'d, PIO>, config: &Config) {
+        self.sm.set_enable(false);
+
+        self.cfg.clock_divider = calculate_clock_divider(config.frequency);
+
+        if let Polarity::IdleHigh = config.polarity {
+            self.clk_pin.set_output_inversion(true);
+        } else {
+            self.clk_pin.set_output_inversion(false);
+        }
+
+        if self.program.as_ref().unwrap().phase != config.phase {
+            let old_program = self.program.take().unwrap();
+
+            // SAFETY: the state machine is disabled while this happens
+            unsafe { pio.free_instr(old_program.prg.used_memory) };
+
+            let new_program = PioSpiProgram::new(pio, config.phase);
+
+            self.cfg.use_program(&new_program.prg, &[&self.clk_pin]);
+            self.program = Some(new_program);
+        }
+
+        self.sm.set_config(&self.cfg);
+        self.sm.restart();
+
+        self.sm.set_enable(true);
+    }
+}
+
+fn calculate_clock_divider(frequency_hz: u32) -> fixed::FixedU32<U8> {
+    // we multiply by 4 since each clock period is equal to 4 instructions
+
+    let sys_freq = clk_sys_freq().to_fixed::<fixed::FixedU64<U8>>();
+    let target_freq = (frequency_hz * 4).to_fixed::<fixed::FixedU64<U8>>();
+    (sys_freq / target_freq).to_fixed()
+}
+
+impl<'d, PIO: Instance, const SM: usize> Spi<'d, PIO, SM, Blocking> {
+    /// Create an SPI driver in blocking mode.
+    pub fn new_blocking(
+        pio: &mut Common<'d, PIO>,
+        sm: StateMachine<'d, PIO, SM>,
+        clk: Peri<'d, impl PioPin>,
+        mosi: Peri<'d, impl PioPin>,
+        miso: Peri<'d, impl PioPin>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(pio, sm, clk, mosi, miso, None, None, config)
+    }
+}
+
+impl<'d, PIO: Instance, const SM: usize> Spi<'d, PIO, SM, Async> {
+    /// Create an SPI driver in async mode supporting DMA operations.
+    #[allow(clippy::too_many_arguments)]
+    pub fn new(
+        pio: &mut Common<'d, PIO>,
+        sm: StateMachine<'d, PIO, SM>,
+        clk: Peri<'d, impl PioPin>,
+        mosi: Peri<'d, impl PioPin>,
+        miso: Peri<'d, impl PioPin>,
+        tx_dma: Peri<'d, impl Channel>,
+        rx_dma: Peri<'d, impl Channel>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(
+            pio,
+            sm,
+            clk,
+            mosi,
+            miso,
+            Some(tx_dma.into()),
+            Some(rx_dma.into()),
+            config,
+        )
+    }
+
+    /// Read data from SPI using DMA.
+    pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
+        let (rx, tx) = self.sm.rx_tx();
+
+        let len = buffer.len();
+
+        let rx_ch = self.rx_dma.as_mut().unwrap().reborrow();
+        let rx_transfer = rx.dma_pull(rx_ch, buffer, false);
+
+        let tx_ch = self.tx_dma.as_mut().unwrap().reborrow();
+        let tx_transfer = tx.dma_push_repeated::<_, u8>(tx_ch, len);
+
+        join(tx_transfer, rx_transfer).await;
+
+        Ok(())
+    }
+
+    /// Write data to SPI using DMA.
+    pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
+        let (rx, tx) = self.sm.rx_tx();
+
+        let rx_ch = self.rx_dma.as_mut().unwrap().reborrow();
+        let rx_transfer = rx.dma_pull_repeated::<_, u8>(rx_ch, buffer.len());
+
+        let tx_ch = self.tx_dma.as_mut().unwrap().reborrow();
+        let tx_transfer = tx.dma_push(tx_ch, buffer, false);
+
+        join(tx_transfer, rx_transfer).await;
+
+        Ok(())
+    }
+
+    /// Transfer data to SPI using DMA.
+    pub async fn transfer(&mut self, rx_buffer: &mut [u8], tx_buffer: &[u8]) -> Result<(), Error> {
+        self.transfer_inner(rx_buffer, tx_buffer).await
+    }
+
+    /// Transfer data in place to SPI using DMA.
+    pub async fn transfer_in_place(&mut self, words: &mut [u8]) -> Result<(), Error> {
+        self.transfer_inner(words, words).await
+    }
+
+    async fn transfer_inner(&mut self, rx_buffer: *mut [u8], tx_buffer: *const [u8]) -> Result<(), Error> {
+        let (rx, tx) = self.sm.rx_tx();
+
+        let mut rx_ch = self.rx_dma.as_mut().unwrap().reborrow();
+        let rx_transfer = async {
+            rx.dma_pull(rx_ch.reborrow(), unsafe { &mut *rx_buffer }, false).await;
+
+            if tx_buffer.len() > rx_buffer.len() {
+                let read_bytes_len = tx_buffer.len() - rx_buffer.len();
+
+                rx.dma_pull_repeated::<_, u8>(rx_ch, read_bytes_len).await;
+            }
+        };
+
+        let mut tx_ch = self.tx_dma.as_mut().unwrap().reborrow();
+        let tx_transfer = async {
+            tx.dma_push(tx_ch.reborrow(), unsafe { &*tx_buffer }, false).await;
+
+            if rx_buffer.len() > tx_buffer.len() {
+                let write_bytes_len = rx_buffer.len() - tx_buffer.len();
+
+                tx.dma_push_repeated::<_, u8>(tx_ch, write_bytes_len).await;
+            }
+        };
+
+        join(tx_transfer, rx_transfer).await;
+
+        Ok(())
+    }
+}
+
+// ====================
+
+impl<'d, PIO: Instance, const SM: usize, M: Mode> embedded_hal_02::blocking::spi::Transfer<u8> for Spi<'d, PIO, SM, M> {
+    type Error = Error;
+    fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
+        self.blocking_transfer_in_place(words)?;
+        Ok(words)
+    }
+}
+
+impl<'d, PIO: Instance, const SM: usize, M: Mode> embedded_hal_02::blocking::spi::Write<u8> for Spi<'d, PIO, SM, M> {
+    type Error = Error;
+
+    fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
+        self.blocking_write(words)
+    }
+}
+
+impl embedded_hal_1::spi::Error for Error {
+    fn kind(&self) -> embedded_hal_1::spi::ErrorKind {
+        match *self {}
+    }
+}
+
+impl<'d, PIO: Instance, const SM: usize, M: Mode> embedded_hal_1::spi::ErrorType for Spi<'d, PIO, SM, M> {
+    type Error = Error;
+}
+
+impl<'d, PIO: Instance, const SM: usize, M: Mode> embedded_hal_1::spi::SpiBus<u8> for Spi<'d, PIO, SM, M> {
+    fn flush(&mut self) -> Result<(), Self::Error> {
+        Ok(())
+    }
+
+    fn read(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
+        self.blocking_transfer(words, &[])
+    }
+
+    fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
+        self.blocking_write(words)
+    }
+
+    fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Self::Error> {
+        self.blocking_transfer(read, write)
+    }
+
+    fn transfer_in_place(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
+        self.blocking_transfer_in_place(words)
+    }
+}
+
+impl<'d, PIO: Instance, const SM: usize> embedded_hal_async::spi::SpiBus<u8> for Spi<'d, PIO, SM, Async> {
+    async fn flush(&mut self) -> Result<(), Self::Error> {
+        Ok(())
+    }
+
+    async fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
+        self.write(words).await
+    }
+
+    async fn read(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
+        self.read(words).await
+    }
+
+    async fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Self::Error> {
+        self.transfer(read, write).await
+    }
+
+    async fn transfer_in_place(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
+        self.transfer_in_place(words).await
+    }
+}
diff --git a/embassy-rp/src/psram.rs b/embassy-rp/src/psram.rs
new file mode 100644
index 000000000..ae43dd5aa
--- /dev/null
+++ b/embassy-rp/src/psram.rs
@@ -0,0 +1,682 @@
+//! PSRAM driver for APS6404L and compatible devices
+//!
+//! This driver provides support for PSRAM (Pseudo-Static RAM) devices connected via QMI CS1.
+//! It handles device verification, initialization, and memory-mapped access configuration.
+//!
+//! This driver is only available on RP235x chips as it requires the QMI CS1 peripheral.
+
+// Credit: Initially based on https://github.com/Altaflux/gb-rp2350 (also licensed Apache 2.0 + MIT).
+// Copyright (c) Altaflux
+
+#![cfg(feature = "_rp235x")]
+
+use critical_section::{acquire, release, CriticalSection, RestoreState};
+
+use crate::pac;
+use crate::qmi_cs1::QmiCs1;
+
+/// PSRAM errors.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[non_exhaustive]
+pub enum Error {
+    /// PSRAM device is not detected or not supported
+    DeviceNotFound,
+    /// Invalid configuration
+    InvalidConfig,
+    /// Detected PSRAM size does not match the expected size
+    SizeMismatch,
+}
+
+/// PSRAM device verification type.
+#[derive(Clone, Copy)]
+pub enum VerificationType {
+    /// Skip device verification
+    None,
+    /// Verify as APS6404L device
+    Aps6404l,
+}
+
+/// Memory configuration.
+#[derive(Clone)]
+pub struct Config {
+    /// System clock frequency in Hz
+    pub clock_hz: u32,
+    /// Maximum memory operating frequency in Hz
+    pub max_mem_freq: u32,
+    /// Maximum CS assert time in microseconds (must be <= 8 us)
+    pub max_select_us: u32,
+    /// Minimum CS deassert time in nanoseconds (must be >= 18 ns)
+    pub min_deselect_ns: u32,
+    /// Cooldown period between operations (in SCLK cycles)
+    pub cooldown: u8,
+    /// Page break size for memory operations
+    pub page_break: PageBreak,
+    /// Clock divisor for direct mode operations during initialization
+    pub init_clkdiv: u8,
+    /// Enter Quad Mode command
+    pub enter_quad_cmd: Option<u8>,
+    /// Quad Read command (fast read with 4-bit data)
+    pub quad_read_cmd: u8,
+    /// Quad Write command (page program with 4-bit data)
+    pub quad_write_cmd: Option<u8>,
+    /// Number of dummy cycles for quad read operations
+    pub dummy_cycles: u8,
+    /// Read format configuration
+    pub read_format: FormatConfig,
+    /// Write format configuration
+    pub write_format: Option<FormatConfig>,
+    /// Expected memory size in bytes
+    pub mem_size: usize,
+    /// Device verification type
+    pub verification_type: VerificationType,
+    /// Whether the memory is writable via XIP (e.g., PSRAM vs. read-only flash)
+    pub xip_writable: bool,
+}
+
+/// Page break configuration for memory window operations.
+#[derive(Clone, Copy)]
+pub enum PageBreak {
+    /// No page breaks
+    None,
+    /// Break at 256-byte boundaries
+    _256,
+    /// Break at 1024-byte boundaries
+    _1024,
+    /// Break at 4096-byte boundaries
+    _4096,
+}
+
+/// Format configuration for read/write operations.
+#[derive(Clone)]
+pub struct FormatConfig {
+    /// Width of command prefix phase
+    pub prefix_width: Width,
+    /// Width of address phase
+    pub addr_width: Width,
+    /// Width of command suffix phase
+    pub suffix_width: Width,
+    /// Width of dummy/turnaround phase
+    pub dummy_width: Width,
+    /// Width of data phase
+    pub data_width: Width,
+    /// Length of prefix (None or 8 bits)
+    pub prefix_len: bool,
+    /// Length of suffix (None or 8 bits)
+    pub suffix_len: bool,
+}
+
+/// Interface width for different phases of SPI transfer.
+#[derive(Clone, Copy)]
+pub enum Width {
+    /// Single-bit (standard SPI)
+    Single,
+    /// Dual-bit (2 data lines)
+    Dual,
+    /// Quad-bit (4 data lines)
+    Quad,
+}
+
+impl Default for Config {
+    fn default() -> Self {
+        Self::aps6404l()
+    }
+}
+
+impl Config {
+    /// Create configuration for APS6404L PSRAM.
+    pub fn aps6404l() -> Self {
+        Self {
+            clock_hz: 125_000_000,        // Default to 125MHz
+            max_mem_freq: 133_000_000,    // APS6404L max frequency
+            max_select_us: 8,             // 8 microseconds max CS assert
+            min_deselect_ns: 18,          // 18 nanoseconds min CS deassert
+            cooldown: 1,                  // 1 SCLK cycle cooldown
+            page_break: PageBreak::_1024, // 1024-byte page boundaries
+            init_clkdiv: 10,              // Medium clock for initialization
+            enter_quad_cmd: Some(0x35),   // Enter Quad Mode
+            quad_read_cmd: 0xEB,          // Fast Quad Read
+            quad_write_cmd: Some(0x38),   // Quad Page Program
+            dummy_cycles: 24,             // 24 dummy cycles for quad read
+            read_format: FormatConfig {
+                prefix_width: Width::Quad,
+                addr_width: Width::Quad,
+                suffix_width: Width::Quad,
+                dummy_width: Width::Quad,
+                data_width: Width::Quad,
+                prefix_len: true,  // 8-bit prefix
+                suffix_len: false, // No suffix
+            },
+            write_format: Some(FormatConfig {
+                prefix_width: Width::Quad,
+                addr_width: Width::Quad,
+                suffix_width: Width::Quad,
+                dummy_width: Width::Quad,
+                data_width: Width::Quad,
+                prefix_len: true,  // 8-bit prefix
+                suffix_len: false, // No suffix
+            }),
+            mem_size: 8 * 1024 * 1024, // 8MB for APS6404L
+            verification_type: VerificationType::Aps6404l,
+            xip_writable: true, // PSRAM is writable
+        }
+    }
+
+    /// Create a custom memory configuration.
+    pub fn custom(
+        clock_hz: u32,
+        max_mem_freq: u32,
+        max_select_us: u32,
+        min_deselect_ns: u32,
+        cooldown: u8,
+        page_break: PageBreak,
+        init_clkdiv: u8,
+        enter_quad_cmd: Option<u8>,
+        quad_read_cmd: u8,
+        quad_write_cmd: Option<u8>,
+        dummy_cycles: u8,
+        read_format: FormatConfig,
+        write_format: Option<FormatConfig>,
+        mem_size: usize,
+        verification_type: VerificationType,
+        xip_writable: bool,
+    ) -> Self {
+        Self {
+            clock_hz,
+            max_mem_freq,
+            max_select_us,
+            min_deselect_ns,
+            cooldown,
+            page_break,
+            init_clkdiv,
+            enter_quad_cmd,
+            quad_read_cmd,
+            quad_write_cmd,
+            dummy_cycles,
+            read_format,
+            write_format,
+            mem_size,
+            verification_type,
+            xip_writable,
+        }
+    }
+}
+
+/// PSRAM driver.
+pub struct Psram<'d> {
+    #[allow(dead_code)]
+    qmi_cs1: QmiCs1<'d>,
+    size: usize,
+}
+
+impl<'d> Psram<'d> {
+    /// Create a new PSRAM driver instance.
+    ///
+    /// This will detect the PSRAM device and configure it for memory-mapped access.
+    pub fn new(qmi_cs1: QmiCs1<'d>, config: Config) -> Result<Self, Error> {
+        let qmi = pac::QMI;
+        let xip = pac::XIP_CTRL;
+
+        // Verify PSRAM device if requested
+        match config.verification_type {
+            VerificationType::Aps6404l => {
+                Self::verify_aps6404l(&qmi, config.mem_size)?;
+                debug!("APS6404L PSRAM verified, size: {:#x}", config.mem_size);
+            }
+            VerificationType::None => {
+                debug!("Skipping PSRAM verification, assuming size: {:#x}", config.mem_size);
+            }
+        }
+
+        // Initialize PSRAM with proper timing
+        Self::init_psram(&qmi, &xip, &config)?;
+
+        Ok(Self {
+            qmi_cs1,
+            size: config.mem_size,
+        })
+    }
+
+    /// Get the detected PSRAM size in bytes.
+    pub fn size(&self) -> usize {
+        self.size
+    }
+
+    /// Get the base address for memory-mapped access.
+    ///
+    /// After initialization, PSRAM can be accessed directly through memory mapping.
+    /// The base address for CS1 is typically 0x11000000.
+    pub fn base_address(&self) -> *mut u8 {
+        0x1100_0000 as *mut u8
+    }
+
+    /// Verify APS6404L PSRAM device matches expected configuration.
+    #[link_section = ".data.ram_func"]
+    #[inline(never)]
+    fn verify_aps6404l(qmi: &pac::qmi::Qmi, expected_size: usize) -> Result<(), Error> {
+        // APS6404L-specific constants
+        const EXPECTED_KGD: u8 = 0x5D;
+        crate::multicore::pause_core1();
+        core::sync::atomic::compiler_fence(core::sync::atomic::Ordering::SeqCst);
+
+        {
+            // Helper for making sure `release` is called even if `f` panics.
+            struct Guard {
+                state: RestoreState,
+            }
+
+            impl Drop for Guard {
+                #[inline(always)]
+                fn drop(&mut self) {
+                    unsafe { release(self.state) }
+                }
+            }
+
+            let state = unsafe { acquire() };
+            let _guard = Guard { state };
+
+            let _cs = unsafe { CriticalSection::new() };
+
+            let (kgd, eid) = unsafe { Self::read_aps6404l_kgd_eid(qmi) };
+
+            let mut detected_size: u32 = 0;
+            if kgd == EXPECTED_KGD as u32 {
+                detected_size = 1024 * 1024;
+                let size_id = eid >> 5;
+                if eid == 0x26 || size_id == 2 {
+                    // APS6404L-3SQR-SN or 8MB variants
+                    detected_size *= 8;
+                } else if size_id == 0 {
+                    detected_size *= 2;
+                } else if size_id == 1 {
+                    detected_size *= 4;
+                }
+            }
+
+            // Verify the detected size matches the expected size
+            if detected_size as usize != expected_size {
+                return Err(Error::SizeMismatch);
+            }
+
+            Ok(())
+        }?;
+
+        crate::multicore::resume_core1();
+
+        Ok(())
+    }
+
+    #[link_section = ".data.ram_func"]
+    #[inline(never)]
+    unsafe fn read_aps6404l_kgd_eid(qmi: &pac::qmi::Qmi) -> (u32, u32) {
+        const RESET_ENABLE_CMD: u8 = 0xf5;
+        const READ_ID_CMD: u8 = 0x9f;
+
+        #[allow(unused_assignments)]
+        let mut kgd: u32 = 0;
+        #[allow(unused_assignments)]
+        let mut eid: u32 = 0;
+
+        let qmi_base = qmi.as_ptr() as usize;
+
+        #[cfg(target_arch = "arm")]
+        core::arch::asm!(
+        // Configure DIRECT_CSR: shift clkdiv (30) to bits 29:22 and set EN (bit 0)
+        "movs {temp}, #30",
+        "lsls {temp}, {temp}, #22",
+        "orr {temp}, {temp}, #1",        // Set EN bit
+        "str {temp}, [{qmi_base}]",
+
+        // Poll for BUSY to clear before first operation
+        "1:",
+        "ldr {temp}, [{qmi_base}]",
+        "lsls {temp}, {temp}, #30",      // Shift BUSY bit to sign position
+        "bmi 1b",                        // Branch if negative (BUSY = 1)
+
+        // Assert CS1N (bit 3)
+        "ldr {temp}, [{qmi_base}]",
+        "orr {temp}, {temp}, #8",        // Set ASSERT_CS1N bit (bit 3)
+        "str {temp}, [{qmi_base}]",
+
+        // Transmit RESET_ENABLE_CMD as quad
+        // DIRECT_TX: OE=1 (bit 19), IWIDTH=2 (bits 17:16), DATA=RESET_ENABLE_CMD
+        "movs {temp}, {reset_enable_cmd}",
+        "orr {temp}, {temp}, #0x80000",  // Set OE (bit 19)
+        "orr {temp}, {temp}, #0x20000",  // Set IWIDTH=2 (quad, bits 17:16)
+        "str {temp}, [{qmi_base}, #4]",  // Store to DIRECT_TX
+
+        // Wait for BUSY to clear
+        "2:",
+        "ldr {temp}, [{qmi_base}]",
+        "lsls {temp}, {temp}, #30",
+        "bmi 2b",
+
+        // Read and discard RX data
+        "ldr {temp}, [{qmi_base}, #8]",
+
+        // Deassert CS1N
+        "ldr {temp}, [{qmi_base}]",
+        "bic {temp}, {temp}, #8",        // Clear ASSERT_CS1N bit
+        "str {temp}, [{qmi_base}]",
+
+        // Assert CS1N again
+        "ldr {temp}, [{qmi_base}]",
+        "orr {temp}, {temp}, #8",        // Set ASSERT_CS1N bit
+        "str {temp}, [{qmi_base}]",
+
+        // Read ID loop (7 iterations)
+        "movs {counter}, #0",            // Initialize counter
+
+        "3:",                            // Loop start
+        "cmp {counter}, #0",
+        "bne 4f",                        // If not first iteration, send 0xFF
+
+        // First iteration: send READ_ID_CMD
+        "movs {temp}, {read_id_cmd}",
+        "b 5f",
+        "4:",                            // Other iterations: send 0xFF
+        "movs {temp}, #0xFF",
+        "5:",
+        "str {temp}, [{qmi_base}, #4]",  // Store to DIRECT_TX
+
+        // Wait for TXEMPTY
+        "6:",
+        "ldr {temp}, [{qmi_base}]",
+        "lsls {temp}, {temp}, #20",      // Shift TXEMPTY (bit 11) to bit 31
+        "bpl 6b",                        // Branch if positive (TXEMPTY = 0)
+
+        // Wait for BUSY to clear
+        "7:",
+        "ldr {temp}, [{qmi_base}]",
+        "lsls {temp}, {temp}, #30",      // Shift BUSY bit to sign position
+        "bmi 7b",                        // Branch if negative (BUSY = 1)
+
+        // Read RX data
+        "ldr {temp}, [{qmi_base}, #8]",
+        "uxth {temp}, {temp}",           // Extract lower 16 bits
+
+        // Store KGD or EID based on iteration
+        "cmp {counter}, #5",
+        "bne 8f",
+        "mov {kgd}, {temp}",             // Store KGD
+        "b 9f",
+        "8:",
+        "cmp {counter}, #6",
+        "bne 9f",
+        "mov {eid}, {temp}",             // Store EID
+
+        "9:",
+        "adds {counter}, #1",
+        "cmp {counter}, #7",
+        "blt 3b",                        // Continue loop if counter < 7
+
+        // Disable direct mode: clear EN and ASSERT_CS1N
+        "movs {temp}, #0",
+        "str {temp}, [{qmi_base}]",
+
+        // Memory barriers
+        "dmb",
+        "dsb",
+        "isb",
+        qmi_base = in(reg) qmi_base,
+        temp = out(reg) _,
+        counter = out(reg) _,
+        kgd = out(reg) kgd,
+        eid = out(reg) eid,
+        reset_enable_cmd = const RESET_ENABLE_CMD as u32,
+        read_id_cmd = const READ_ID_CMD as u32,
+        options(nostack),
+        );
+
+        #[cfg(target_arch = "riscv32")]
+        unimplemented!("APS6404L PSRAM verification not implemented for RISC-V");
+
+        (kgd, eid)
+    }
+
+    /// Initialize PSRAM with proper timing.
+    #[link_section = ".data.ram_func"]
+    #[inline(never)]
+    fn init_psram(qmi: &pac::qmi::Qmi, xip_ctrl: &pac::xip_ctrl::XipCtrl, config: &Config) -> Result<(), Error> {
+        // Set PSRAM timing for APS6404
+        //
+        // Using an rxdelay equal to the divisor isn't enough when running the APS6404 close to 133 MHz.
+        // So: don't allow running at divisor 1 above 100 MHz (because delay of 2 would be too late),
+        // and add an extra 1 to the rxdelay if the divided clock is > 100 MHz (i.e., sys clock > 200 MHz).
+        let clock_hz = config.clock_hz;
+        let max_psram_freq = config.max_mem_freq;
+
+        let mut divisor: u32 = (clock_hz + max_psram_freq - 1) / max_psram_freq;
+        if divisor == 1 && clock_hz > 100_000_000 {
+            divisor = 2;
+        }
+        let mut rxdelay: u32 = divisor;
+        if clock_hz / divisor > 100_000_000 {
+            rxdelay += 1;
+        }
+
+        // - Max select must be <= 8 us. The value is given in multiples of 64 system clocks.
+        // - Min deselect must be >= 18ns. The value is given in system clock cycles - ceil(divisor / 2).
+        let clock_period_fs: u64 = 1_000_000_000_000_000_u64 / u64::from(clock_hz);
+        let max_select: u8 = ((config.max_select_us as u64 * 1_000_000) / clock_period_fs) as u8;
+        let min_deselect: u32 = ((config.min_deselect_ns as u64 * 1_000_000 + (clock_period_fs - 1)) / clock_period_fs
+            - u64::from(divisor + 1) / 2) as u32;
+
+        crate::multicore::pause_core1();
+        core::sync::atomic::compiler_fence(core::sync::atomic::Ordering::SeqCst);
+
+        if let Some(enter_quad_cmd) = config.enter_quad_cmd {
+            // Helper for making sure `release` is called even if `f` panics.
+            struct Guard {
+                state: RestoreState,
+            }
+
+            impl Drop for Guard {
+                #[inline(always)]
+                fn drop(&mut self) {
+                    unsafe { release(self.state) }
+                }
+            }
+
+            let state = unsafe { acquire() };
+            let _guard = Guard { state };
+
+            let _cs = unsafe { CriticalSection::new() };
+
+            unsafe { Self::direct_csr_send_init_command(config, enter_quad_cmd) };
+
+            qmi.mem(1).timing().write(|w| {
+                w.set_cooldown(config.cooldown);
+                w.set_pagebreak(match config.page_break {
+                    PageBreak::None => pac::qmi::vals::Pagebreak::NONE,
+                    PageBreak::_256 => pac::qmi::vals::Pagebreak::_256,
+                    PageBreak::_1024 => pac::qmi::vals::Pagebreak::_1024,
+                    PageBreak::_4096 => pac::qmi::vals::Pagebreak::_4096,
+                });
+                w.set_max_select(max_select);
+                w.set_min_deselect(min_deselect as u8);
+                w.set_rxdelay(rxdelay as u8);
+                w.set_clkdiv(divisor as u8);
+            });
+
+            // Set PSRAM commands and formats
+            qmi.mem(1).rfmt().write(|w| {
+                let width_to_pac = |w: Width| match w {
+                    Width::Single => pac::qmi::vals::PrefixWidth::S,
+                    Width::Dual => pac::qmi::vals::PrefixWidth::D,
+                    Width::Quad => pac::qmi::vals::PrefixWidth::Q,
+                };
+
+                w.set_prefix_width(width_to_pac(config.read_format.prefix_width));
+                w.set_addr_width(match config.read_format.addr_width {
+                    Width::Single => pac::qmi::vals::AddrWidth::S,
+                    Width::Dual => pac::qmi::vals::AddrWidth::D,
+                    Width::Quad => pac::qmi::vals::AddrWidth::Q,
+                });
+                w.set_suffix_width(match config.read_format.suffix_width {
+                    Width::Single => pac::qmi::vals::SuffixWidth::S,
+                    Width::Dual => pac::qmi::vals::SuffixWidth::D,
+                    Width::Quad => pac::qmi::vals::SuffixWidth::Q,
+                });
+                w.set_dummy_width(match config.read_format.dummy_width {
+                    Width::Single => pac::qmi::vals::DummyWidth::S,
+                    Width::Dual => pac::qmi::vals::DummyWidth::D,
+                    Width::Quad => pac::qmi::vals::DummyWidth::Q,
+                });
+                w.set_data_width(match config.read_format.data_width {
+                    Width::Single => pac::qmi::vals::DataWidth::S,
+                    Width::Dual => pac::qmi::vals::DataWidth::D,
+                    Width::Quad => pac::qmi::vals::DataWidth::Q,
+                });
+                w.set_prefix_len(if config.read_format.prefix_len {
+                    pac::qmi::vals::PrefixLen::_8
+                } else {
+                    pac::qmi::vals::PrefixLen::NONE
+                });
+                w.set_suffix_len(if config.read_format.suffix_len {
+                    pac::qmi::vals::SuffixLen::_8
+                } else {
+                    pac::qmi::vals::SuffixLen::NONE
+                });
+                w.set_dummy_len(match config.dummy_cycles {
+                    0 => pac::qmi::vals::DummyLen::NONE,
+                    4 => pac::qmi::vals::DummyLen::_4,
+                    8 => pac::qmi::vals::DummyLen::_8,
+                    12 => pac::qmi::vals::DummyLen::_12,
+                    16 => pac::qmi::vals::DummyLen::_16,
+                    20 => pac::qmi::vals::DummyLen::_20,
+                    24 => pac::qmi::vals::DummyLen::_24,
+                    28 => pac::qmi::vals::DummyLen::_28,
+                    _ => pac::qmi::vals::DummyLen::_24, // Default to 24
+                });
+            });
+
+            qmi.mem(1).rcmd().write(|w| w.set_prefix(config.quad_read_cmd));
+
+            if let Some(ref write_format) = config.write_format {
+                qmi.mem(1).wfmt().write(|w| {
+                    w.set_prefix_width(match write_format.prefix_width {
+                        Width::Single => pac::qmi::vals::PrefixWidth::S,
+                        Width::Dual => pac::qmi::vals::PrefixWidth::D,
+                        Width::Quad => pac::qmi::vals::PrefixWidth::Q,
+                    });
+                    w.set_addr_width(match write_format.addr_width {
+                        Width::Single => pac::qmi::vals::AddrWidth::S,
+                        Width::Dual => pac::qmi::vals::AddrWidth::D,
+                        Width::Quad => pac::qmi::vals::AddrWidth::Q,
+                    });
+                    w.set_suffix_width(match write_format.suffix_width {
+                        Width::Single => pac::qmi::vals::SuffixWidth::S,
+                        Width::Dual => pac::qmi::vals::SuffixWidth::D,
+                        Width::Quad => pac::qmi::vals::SuffixWidth::Q,
+                    });
+                    w.set_dummy_width(match write_format.dummy_width {
+                        Width::Single => pac::qmi::vals::DummyWidth::S,
+                        Width::Dual => pac::qmi::vals::DummyWidth::D,
+                        Width::Quad => pac::qmi::vals::DummyWidth::Q,
+                    });
+                    w.set_data_width(match write_format.data_width {
+                        Width::Single => pac::qmi::vals::DataWidth::S,
+                        Width::Dual => pac::qmi::vals::DataWidth::D,
+                        Width::Quad => pac::qmi::vals::DataWidth::Q,
+                    });
+                    w.set_prefix_len(if write_format.prefix_len {
+                        pac::qmi::vals::PrefixLen::_8
+                    } else {
+                        pac::qmi::vals::PrefixLen::NONE
+                    });
+                    w.set_suffix_len(if write_format.suffix_len {
+                        pac::qmi::vals::SuffixLen::_8
+                    } else {
+                        pac::qmi::vals::SuffixLen::NONE
+                    });
+                });
+            }
+
+            if let Some(quad_write_cmd) = config.quad_write_cmd {
+                qmi.mem(1).wcmd().write(|w| w.set_prefix(quad_write_cmd));
+            }
+
+            if config.xip_writable {
+                // Enable XIP writable mode for PSRAM
+                xip_ctrl.ctrl().modify(|w| w.set_writable_m1(true));
+            } else {
+                // Disable XIP writable mode
+                xip_ctrl.ctrl().modify(|w| w.set_writable_m1(false));
+            }
+        }
+        crate::multicore::resume_core1();
+
+        Ok(())
+    }
+
+    #[link_section = ".data.ram_func"]
+    #[inline(never)]
+    unsafe fn direct_csr_send_init_command(config: &Config, init_cmd: u8) {
+        #[cfg(target_arch = "arm")]
+        core::arch::asm!(
+        // Full memory barrier
+        "dmb",
+        "dsb",
+        "isb",
+
+        // Configure QMI Direct CSR register
+        // Load base address of QMI (0x400D0000)
+        "movw {base}, #0x0000",
+        "movt {base}, #0x400D",
+
+        // Load init_clkdiv and shift to bits 29:22
+        "lsl {temp}, {clkdiv}, #22",
+
+        // OR with EN (bit 0) and AUTO_CS1N (bit 7)
+        "orr {temp}, {temp}, #0x81",
+
+        // Store to DIRECT_CSR register
+        "str {temp}, [{base}, #0]",
+
+        // Memory barrier
+        "dmb",
+
+        // First busy wait loop
+        "1:",
+        "ldr {temp}, [{base}, #0]",      // Load DIRECT_CSR
+        "tst {temp}, #0x2",              // Test BUSY bit (bit 1)
+        "bne 1b",                        // Branch if busy
+
+        // Write to Direct TX register
+        "mov {temp}, {enter_quad_cmd}",
+
+        // OR with NOPUSH (bit 20)
+        "orr {temp}, {temp}, #0x100000",
+
+        // Store to DIRECT_TX register (offset 0x4)
+        "str {temp}, [{base}, #4]",
+
+        // Memory barrier
+        "dmb",
+
+        // Second busy wait loop
+        "2:",
+        "ldr {temp}, [{base}, #0]",      // Load DIRECT_CSR
+        "tst {temp}, #0x2",              // Test BUSY bit (bit 1)
+        "bne 2b",                        // Branch if busy
+
+        // Disable Direct CSR
+        "mov {temp}, #0",
+        "str {temp}, [{base}, #0]",      // Clear DIRECT_CSR register
+
+        // Full memory barrier to ensure no prefetching
+        "dmb",
+        "dsb",
+        "isb",
+        base = out(reg) _,
+        temp = out(reg) _,
+        clkdiv = in(reg) config.init_clkdiv as u32,
+        enter_quad_cmd = in(reg) u32::from(init_cmd),
+        options(nostack),
+        );
+
+        #[cfg(target_arch = "riscv32")]
+        unimplemented!("Direct CSR command sending is not implemented for RISC-V yet");
+    }
+}
diff --git a/embassy-rp/src/qmi_cs1.rs b/embassy-rp/src/qmi_cs1.rs
new file mode 100644
index 000000000..b8ae41e35
--- /dev/null
+++ b/embassy-rp/src/qmi_cs1.rs
@@ -0,0 +1,57 @@
+//! QMI CS1 peripheral for RP235x
+//!
+//! This module provides access to the QMI CS1 functionality for use with external memory devices
+//! such as PSRAM. The QMI (Quad SPI) controller supports CS1 as a second chip select signal.
+//!
+//! This peripheral is only available on RP235x chips.
+
+#![cfg(feature = "_rp235x")]
+
+use embassy_hal_internal::{Peri, PeripheralType};
+
+use crate::gpio::Pin as GpioPin;
+use crate::{pac, peripherals};
+
+/// QMI CS1 driver.
+pub struct QmiCs1<'d> {
+    _inner: Peri<'d, peripherals::QMI_CS1>,
+}
+
+impl<'d> QmiCs1<'d> {
+    /// Create a new QMI CS1 instance.
+    pub fn new(qmi_cs1: Peri<'d, peripherals::QMI_CS1>, cs1: Peri<'d, impl QmiCs1Pin>) -> Self {
+        // Configure CS1 pin for QMI function (funcsel = 9)
+        cs1.gpio().ctrl().write(|w| w.set_funcsel(9));
+
+        // Configure pad settings for high-speed operation
+        cs1.pad_ctrl().write(|w| {
+            #[cfg(feature = "_rp235x")]
+            w.set_iso(false);
+            w.set_ie(true);
+            w.set_drive(pac::pads::vals::Drive::_12M_A);
+            w.set_slewfast(true);
+        });
+
+        Self { _inner: qmi_cs1 }
+    }
+}
+
+trait SealedInstance {}
+
+/// QMI CS1 instance trait.
+#[allow(private_bounds)]
+pub trait Instance: SealedInstance + PeripheralType {}
+
+impl SealedInstance for peripherals::QMI_CS1 {}
+
+impl Instance for peripherals::QMI_CS1 {}
+
+/// CS1 pin trait for QMI.
+pub trait QmiCs1Pin: GpioPin {}
+
+// Implement pin traits for CS1-capable GPIO pins
+impl QmiCs1Pin for peripherals::PIN_0 {}
+impl QmiCs1Pin for peripherals::PIN_8 {}
+impl QmiCs1Pin for peripherals::PIN_19 {}
+#[cfg(feature = "rp235xb")]
+impl QmiCs1Pin for peripherals::PIN_47 {}
diff --git a/embassy-rp/src/rtc/datetime_no_deps.rs b/embassy-rp/src/rtc/datetime_no_deps.rs
index 5de00e6b4..77d4a3055 100644
--- a/embassy-rp/src/rtc/datetime_no_deps.rs
+++ b/embassy-rp/src/rtc/datetime_no_deps.rs
@@ -46,6 +46,7 @@ pub struct DateTime {
 /// A day of the week
 #[repr(u8)]
 #[derive(Copy, Clone, Debug, PartialEq, Eq, Ord, PartialOrd, Hash)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[allow(missing_docs)]
 pub enum DayOfWeek {
     Sunday = 0,
diff --git a/embassy-rp/src/rtc/filter.rs b/embassy-rp/src/rtc/filter.rs
index d4a3bab2f..433053613 100644
--- a/embassy-rp/src/rtc/filter.rs
+++ b/embassy-rp/src/rtc/filter.rs
@@ -4,7 +4,8 @@ use crate::pac::rtc::regs::{IrqSetup0, IrqSetup1};
 /// A filter used for [`RealTimeClock::schedule_alarm`].
 ///
 /// [`RealTimeClock::schedule_alarm`]: struct.RealTimeClock.html#method.schedule_alarm
-#[derive(Default)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Default)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct DateTimeFilter {
     /// The year that this alarm should trigger on, `None` if the RTC alarm should not trigger on a year value.
     pub year: Option<u16>,
diff --git a/embassy-rp/src/rtc/mod.rs b/embassy-rp/src/rtc/mod.rs
index 63cf91d28..8b0deed21 100644
--- a/embassy-rp/src/rtc/mod.rs
+++ b/embassy-rp/src/rtc/mod.rs
@@ -1,7 +1,12 @@
 //! RTC driver.
 mod filter;
 
+use core::future::poll_fn;
+use core::sync::atomic::{compiler_fence, AtomicBool, Ordering};
+use core::task::Poll;
+
 use embassy_hal_internal::{Peri, PeripheralType};
+use embassy_sync::waitqueue::AtomicWaker;
 
 pub use self::filter::DateTimeFilter;
 
@@ -11,6 +16,13 @@ mod datetime;
 
 pub use self::datetime::{DateTime, DayOfWeek, Error as DateTimeError};
 use crate::clocks::clk_rtc_freq;
+use crate::interrupt::typelevel::Binding;
+use crate::interrupt::{self, InterruptExt};
+
+// Static waker for the interrupt handler
+static WAKER: AtomicWaker = AtomicWaker::new();
+// Static flag to indicate if an alarm has occurred
+static ALARM_OCCURRED: AtomicBool = AtomicBool::new(false);
 
 /// A reference to the real time clock of the system
 pub struct Rtc<'d, T: Instance> {
@@ -23,10 +35,15 @@ impl<'d, T: Instance> Rtc<'d, T> {
     /// # Errors
     ///
     /// Will return `RtcError::InvalidDateTime` if the datetime is not a valid range.
-    pub fn new(inner: Peri<'d, T>) -> Self {
+    pub fn new(inner: Peri<'d, T>, _irq: impl Binding<interrupt::typelevel::RTC_IRQ, InterruptHandler>) -> Self {
         // Set the RTC divider
         inner.regs().clkdiv_m1().write(|w| w.set_clkdiv_m1(clk_rtc_freq() - 1));
 
+        // Setup the IRQ
+        // Clear any pending interrupts from the RTC_IRQ interrupt and enable it, so we do not have unexpected interrupts after initialization
+        interrupt::RTC_IRQ.unpend();
+        unsafe { interrupt::RTC_IRQ.enable() };
+
         Self { inner }
     }
 
@@ -174,6 +191,110 @@ impl<'d, T: Instance> Rtc<'d, T> {
     pub fn clear_interrupt(&mut self) {
         self.disable_alarm();
     }
+
+    /// Check if an alarm is scheduled.
+    ///
+    /// This function checks if the RTC alarm is currently active. If it is, it returns the alarm configuration
+    /// as a [`DateTimeFilter`]. Otherwise, it returns `None`.
+    pub fn alarm_scheduled(&self) -> Option<DateTimeFilter> {
+        // Check if alarm is active
+        if !self.inner.regs().irq_setup_0().read().match_active() {
+            return None;
+        }
+
+        // Get values from both alarm registers
+        let irq_0 = self.inner.regs().irq_setup_0().read();
+        let irq_1 = self.inner.regs().irq_setup_1().read();
+
+        // Create a DateTimeFilter and populate it based on which fields are enabled
+        let mut filter = DateTimeFilter::default();
+
+        if irq_0.year_ena() {
+            filter.year = Some(irq_0.year());
+        }
+
+        if irq_0.month_ena() {
+            filter.month = Some(irq_0.month());
+        }
+
+        if irq_0.day_ena() {
+            filter.day = Some(irq_0.day());
+        }
+
+        if irq_1.dotw_ena() {
+            // Convert day of week value to DayOfWeek enum
+            let day_of_week = match irq_1.dotw() {
+                0 => DayOfWeek::Sunday,
+                1 => DayOfWeek::Monday,
+                2 => DayOfWeek::Tuesday,
+                3 => DayOfWeek::Wednesday,
+                4 => DayOfWeek::Thursday,
+                5 => DayOfWeek::Friday,
+                6 => DayOfWeek::Saturday,
+                _ => return None, // Invalid day of week
+            };
+            filter.day_of_week = Some(day_of_week);
+        }
+
+        if irq_1.hour_ena() {
+            filter.hour = Some(irq_1.hour());
+        }
+
+        if irq_1.min_ena() {
+            filter.minute = Some(irq_1.min());
+        }
+
+        if irq_1.sec_ena() {
+            filter.second = Some(irq_1.sec());
+        }
+
+        Some(filter)
+    }
+
+    /// Wait for an RTC alarm to trigger.
+    ///
+    /// This function will wait until the RTC alarm is triggered. If the alarm is already triggered, it will return immediately.
+    /// If no alarm is scheduled, it will wait indefinitely until one is scheduled and triggered.
+    pub async fn wait_for_alarm(&mut self) {
+        poll_fn(|cx| {
+            WAKER.register(cx.waker());
+
+            // Atomically check and clear the alarm occurred flag to prevent race conditions
+            if critical_section::with(|_| {
+                let occurred = ALARM_OCCURRED.load(Ordering::SeqCst);
+                if occurred {
+                    ALARM_OCCURRED.store(false, Ordering::SeqCst);
+                }
+                occurred
+            }) {
+                // Clear the interrupt and disable the alarm
+                self.clear_interrupt();
+
+                compiler_fence(Ordering::SeqCst);
+                return Poll::Ready(());
+            } else {
+                return Poll::Pending;
+            }
+        })
+        .await;
+    }
+}
+
+/// Interrupt handler.
+pub struct InterruptHandler {
+    _empty: (),
+}
+
+impl crate::interrupt::typelevel::Handler<crate::interrupt::typelevel::RTC_IRQ> for InterruptHandler {
+    unsafe fn on_interrupt() {
+        // Disable the alarm first thing, to prevent unexpected re-entry
+        let rtc = crate::pac::RTC;
+        rtc.irq_setup_0().modify(|w| w.set_match_ena(false));
+
+        // Set the alarm occurred flag and wake the waker
+        ALARM_OCCURRED.store(true, Ordering::SeqCst);
+        WAKER.wake();
+    }
 }
 
 /// Errors that can occur on methods on [Rtc]
diff --git a/embassy-stm32/CHANGELOG.md b/embassy-stm32/CHANGELOG.md
index dfb8ca066..190e68d6d 100644
--- a/embassy-stm32/CHANGELOG.md
+++ b/embassy-stm32/CHANGELOG.md
@@ -9,6 +9,19 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ## Unreleased - ReleaseDate
 
 - fix: Fixed STM32H5 builds requiring time feature
+- feat: Derive Clone, Copy for QSPI Config
+- fix: stm32/i2c in master mode (blocking): subsequent transmissions failed after a NACK was received
+- feat: stm32/timer: add set_polarity functions for main and complementary outputs in complementary_pwm
+- Add I2S support for STM32F1, STM32C0, STM32F0, STM32F3, STM32F7, STM32G0, STM32WL, STM32H5, STM32H7RS
+- fix: STM32: Prevent dropped DacChannel from disabling Dac peripheral if another DacChannel is still in scope ([#4577](https://github.com/embassy-rs/embassy/pull/4577))
+- feat: Added support for more OctoSPI configurations (e.g. APS6408 RAM) ([#4581](https://github.com/embassy-rs/embassy/pull/4581))
+- fix: stm32/usart: fix bug with blocking flush in buffered uart ([#4648](https://github.com/embassy-rs/embassy/pull/4648))
+- fix: stm32/(ospi/hspi/xspi): Fix the alternate bytes register config sticking around for subsequent writes
+- feat: Configurable gpio speed for QSPI
+- feat: derive Clone, Copy and defmt::Format for all *SPI-related configs
+- fix: handle address and data-length errors in OSPI
+- feat: Allow OSPI DMA writes larger than 64kB using chunking
+- feat: More ADC enums for g0 PAC, API change for oversampling, allow separate sample times
 
 ## 0.4.0 - 2025-08-26
 
@@ -22,6 +35,9 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - feat: stm32/adc/v3: allow DMA reads to loop through enable channels
 - fix: Fix XSPI not disabling alternate bytes when they were previously enabled
 - fix: Fix stm32h7rs init when using external flash via XSPI
+- feat: Add Adc::new_with_clock() to configure analog clock
+- feat: Add GPDMA linked-list + ringbuffer support ([#3923](https://github.com/embassy-rs/embassy/pull/3923))
+- feat: Added support for STM32F1 peripheral pin remapping (AFIO) ([#4430](https://github.com/embassy-rs/embassy/pull/4430))
 
 ## 0.3.0 - 2025-08-12
 
@@ -132,7 +148,7 @@ GPIO:
 - Refactor AfType ([#3031](https://github.com/embassy-rs/embassy/pull/3031))
 - Gpiov1: Do not call set_speed for AFType::Input ([#2996](https://github.com/embassy-rs/embassy/pull/2996))
 
-UART: 
+UART:
 - Add embedded-io impls ([#2739](https://github.com/embassy-rs/embassy/pull/2739))
 - Add support for changing baud rate ([#3512](https://github.com/embassy-rs/embassy/pull/3512))
 - Add split_ref ([#3500](https://github.com/embassy-rs/embassy/pull/3500))
@@ -156,7 +172,7 @@ UART:
     - Wake receive task for each received byte ([#2722](https://github.com/embassy-rs/embassy/pull/2722))
     - Fix dma and idle line detection in ringbuffereduartrx ([#3319](https://github.com/embassy-rs/embassy/pull/3319))
 
-SPI: 
+SPI:
 - Add MISO pullup configuration option ([#2943](https://github.com/embassy-rs/embassy/pull/2943))
 - Add slew rate configuration options ([#3669](https://github.com/embassy-rs/embassy/pull/3669))
 - Fix blocking_write on nosck spi. ([#3035](https://github.com/embassy-rs/embassy/pull/3035))
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index cdb4e07d1..6cd8ed262 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -173,8 +173,8 @@ cortex-m = "0.7.6"
 futures-util = { version = "0.3.30", default-features = false }
 sdio-host = "0.9.0"
 critical-section = "1.1"
-stm32-metapac = { version = "18" }
-#stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-ecb93d42a6cbcd9e09cab74873908a2ca22327f7" }
+#stm32-metapac = { version = "18" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-3cf72eac610259fd78ef16f1c63be69a144d75f7" }
 
 vcell = "0.1.3"
 nb = "1.0.0"
@@ -192,6 +192,7 @@ bitflags = "2.4.2"
 
 block-device-driver = { version = "0.2" }
 aligned = "0.4.1"
+heapless = "0.9.1"
 
 [dev-dependencies]
 critical-section = { version = "1.1", features = ["std"] }
@@ -202,8 +203,8 @@ proptest-state-machine = "0.3.0"
 proc-macro2 = "1.0.36"
 quote = "1.0.15"
 
-stm32-metapac = { version = "18", default-features = false, features = ["metadata"]}
-#stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-ecb93d42a6cbcd9e09cab74873908a2ca22327f7", default-features = false, features = ["metadata"] }
+#stm32-metapac = { version = "18", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-3cf72eac610259fd78ef16f1c63be69a144d75f7", default-features = false, features = ["metadata"] }
 
 [features]
 default = ["rt"]
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index deefb13c1..b5f1261fe 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -16,6 +16,27 @@ use stm32_metapac::metadata::{
 #[path = "./build_common.rs"]
 mod common;
 
+/// Helper function to handle peripheral versions with underscores.
+/// For a version like "v1_foo_bar", this generates all prefix combinations:
+/// - "kind_v1"
+/// - "kind_v1_foo"
+/// - "kind_v1_foo_bar"
+fn foreach_version_cfg(
+    cfgs: &mut common::CfgSet,
+    kind: &str,
+    version: &str,
+    mut cfg_fn: impl FnMut(&mut common::CfgSet, &str),
+) {
+    let parts: Vec<&str> = version.split('_').collect();
+
+    // Generate all possible prefix combinations
+    for i in 1..=parts.len() {
+        let partial_version = parts[0..i].join("_");
+        let cfg_name = format!("{}_{}", kind, partial_version);
+        cfg_fn(cfgs, &cfg_name);
+    }
+}
+
 fn main() {
     let mut cfgs = common::CfgSet::new();
     common::set_target_cfgs(&mut cfgs);
@@ -38,14 +59,18 @@ fn main() {
     for p in METADATA.peripherals {
         if let Some(r) = &p.registers {
             cfgs.enable(r.kind);
-            cfgs.enable(format!("{}_{}", r.kind, r.version));
+            foreach_version_cfg(&mut cfgs, r.kind, r.version, |cfgs, cfg_name| {
+                cfgs.enable(cfg_name);
+            });
         }
     }
 
     for &(kind, versions) in ALL_PERIPHERAL_VERSIONS.iter() {
         cfgs.declare(kind);
         for &version in versions.iter() {
-            cfgs.declare(format!("{}_{}", kind, version));
+            foreach_version_cfg(&mut cfgs, kind, version, |cfgs, cfg_name| {
+                cfgs.declare(cfg_name);
+            });
         }
     }
 
@@ -1366,9 +1391,53 @@ fn main() {
                         })
                     }
 
-                    g.extend(quote! {
-                        pin_trait_impl!(#tr, #peri, #pin_name, #af);
-                    })
+                    let pin_trait_impl = if let Some(afio) = &p.afio {
+                        let values = afio
+                            .values
+                            .iter()
+                            .filter(|v| v.pins.contains(&pin.pin))
+                            .map(|v| v.value)
+                            .collect::<Vec<_>>();
+
+                        if values.is_empty() {
+                            None
+                        } else {
+                            let reg = format_ident!("{}", afio.register.to_lowercase());
+                            let setter = format_ident!("set_{}", afio.field.to_lowercase());
+                            let type_and_values = if is_bool_field("AFIO", afio.register, afio.field) {
+                                let values = values.iter().map(|&v| v > 0);
+                                quote!(AfioRemapBool, [#(#values),*])
+                            } else {
+                                quote!(AfioRemap, [#(#values),*])
+                            };
+
+                            Some(quote! {
+                                pin_trait_afio_impl!(#tr, #peri, #pin_name, {#reg, #setter, #type_and_values});
+                            })
+                        }
+                    } else {
+                        let peripherals_with_afio = [
+                            "CAN",
+                            "CEC",
+                            "ETH",
+                            "I2C",
+                            "SPI",
+                            "SUBGHZSPI",
+                            "USART",
+                            "UART",
+                            "LPUART",
+                            "TIM",
+                        ];
+                        let not_applicable = if peripherals_with_afio.iter().any(|&x| p.name.starts_with(x)) {
+                            quote!(, crate::gpio::AfioRemapNotApplicable)
+                        } else {
+                            quote!()
+                        };
+
+                        Some(quote!(pin_trait_impl!(#tr, #peri, #pin_name, #af #not_applicable);))
+                    };
+
+                    g.extend(pin_trait_impl);
                 }
 
                 // ADC is special
@@ -1563,17 +1632,7 @@ fn main() {
                             let register = format_ident!("{}", remap_info.register.to_lowercase());
                             let setter = format_ident!("set_{}", remap_info.field.to_lowercase());
 
-                            let field_metadata = METADATA
-                                .peripherals
-                                .iter()
-                                .filter(|p| p.name == "SYSCFG")
-                                .flat_map(|p| p.registers.as_ref().unwrap().ir.fieldsets.iter())
-                                .filter(|f| f.name.eq_ignore_ascii_case(remap_info.register))
-                                .flat_map(|f| f.fields.iter())
-                                .find(|f| f.name.eq_ignore_ascii_case(remap_info.field))
-                                .unwrap();
-
-                            let value = if field_metadata.bit_size == 1 {
+                            let value = if is_bool_field("SYSCFG", &remap_info.register, &remap_info.field) {
                                 let bool_value = format_ident!("{}", remap_info.value > 0);
                                 quote!(#bool_value)
                             } else {
@@ -2275,3 +2334,17 @@ fn gcd(a: u32, b: u32) -> u32 {
     }
     gcd(b, a % b)
 }
+
+fn is_bool_field(peripheral: &str, register: &str, field: &str) -> bool {
+    let field_metadata = METADATA
+        .peripherals
+        .iter()
+        .filter(|p| p.name == peripheral)
+        .flat_map(|p| p.registers.as_ref().unwrap().ir.fieldsets.iter())
+        .filter(|f| f.name.eq_ignore_ascii_case(register))
+        .flat_map(|f| f.fields.iter())
+        .find(|f| f.name.eq_ignore_ascii_case(field))
+        .unwrap();
+
+    field_metadata.bit_size == 1
+}
diff --git a/embassy-stm32/src/adc/adc4.rs b/embassy-stm32/src/adc/adc4.rs
index 31cbdc0d7..255dc7956 100644
--- a/embassy-stm32/src/adc/adc4.rs
+++ b/embassy-stm32/src/adc/adc4.rs
@@ -83,7 +83,8 @@ pub enum DacChannel {
 }
 
 /// Number of samples used for averaging.
-#[derive(Copy, Clone)]
+#[derive(Copy, Clone, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Averaging {
     Disabled,
     Samples2,
diff --git a/embassy-stm32/src/adc/c0.rs b/embassy-stm32/src/adc/c0.rs
index f5870801e..f2837a8f1 100644
--- a/embassy-stm32/src/adc/c0.rs
+++ b/embassy-stm32/src/adc/c0.rs
@@ -138,7 +138,8 @@ impl<'a> defmt::Format for Prescaler {
 /// Number of samples used for averaging.
 /// TODO: Implement hardware averaging setting.
 #[allow(unused)]
-#[derive(Copy, Clone)]
+#[derive(Copy, Clone, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Averaging {
     Disabled,
     Samples2,
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index 778edc6f6..ea986f4cf 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -2,12 +2,12 @@
 
 #![macro_use]
 #![allow(missing_docs)] // TODO
-#![cfg_attr(adc_f3_v2, allow(unused))]
+#![cfg_attr(adc_f3v3, allow(unused))]
 
-#[cfg(not(any(adc_f3_v2, adc_wba)))]
+#[cfg(not(any(adc_f3v3, adc_wba)))]
 #[cfg_attr(adc_f1, path = "f1.rs")]
-#[cfg_attr(adc_f3, path = "f3.rs")]
-#[cfg_attr(adc_f3_v1_1, path = "f3_v1_1.rs")]
+#[cfg_attr(adc_f3v1, path = "f3.rs")]
+#[cfg_attr(adc_f3v2, path = "f3_v1_1.rs")]
 #[cfg_attr(adc_v1, path = "v1.rs")]
 #[cfg_attr(adc_l0, path = "v1.rs")]
 #[cfg_attr(adc_v2, path = "v2.rs")]
@@ -20,10 +20,10 @@ mod _version;
 use core::marker::PhantomData;
 
 #[allow(unused)]
-#[cfg(not(any(adc_f3_v2, adc_wba)))]
+#[cfg(not(any(adc_f3v3, adc_wba)))]
 pub use _version::*;
 use embassy_hal_internal::{impl_peripheral, PeripheralType};
-#[cfg(any(adc_f1, adc_f3, adc_v1, adc_l0, adc_f3_v1_1))]
+#[cfg(any(adc_f1, adc_f3v1, adc_v1, adc_l0, adc_f3v2))]
 use embassy_sync::waitqueue::AtomicWaker;
 
 #[cfg(any(adc_u5, adc_wba))]
@@ -31,7 +31,7 @@ use embassy_sync::waitqueue::AtomicWaker;
 pub mod adc4;
 
 pub use crate::pac::adc::vals;
-#[cfg(not(any(adc_f1, adc_f3_v2)))]
+#[cfg(not(any(adc_f1, adc_f3v3)))]
 pub use crate::pac::adc::vals::Res as Resolution;
 pub use crate::pac::adc::vals::SampleTime;
 use crate::peripherals;
@@ -47,16 +47,16 @@ dma_trait!(RxDma4, adc4::Instance);
 pub struct Adc<'d, T: Instance> {
     #[allow(unused)]
     adc: crate::Peri<'d, T>,
-    #[cfg(not(any(adc_f3_v2, adc_f3_v1_1, adc_wba)))]
+    #[cfg(not(any(adc_f3v3, adc_f3v2, adc_wba)))]
     sample_time: SampleTime,
 }
 
-#[cfg(any(adc_f1, adc_f3, adc_v1, adc_l0, adc_f3_v1_1))]
+#[cfg(any(adc_f1, adc_f3v1, adc_v1, adc_l0, adc_f3v2))]
 pub struct State {
     pub waker: AtomicWaker,
 }
 
-#[cfg(any(adc_f1, adc_f3, adc_v1, adc_l0, adc_f3_v1_1))]
+#[cfg(any(adc_f1, adc_f3v1, adc_v1, adc_l0, adc_f3v2))]
 impl State {
     pub const fn new() -> Self {
         Self {
@@ -69,10 +69,10 @@ trait SealedInstance {
     #[cfg(not(adc_wba))]
     #[allow(unused)]
     fn regs() -> crate::pac::adc::Adc;
-    #[cfg(not(any(adc_f1, adc_v1, adc_l0, adc_f3_v2, adc_f3_v1_1, adc_g0)))]
+    #[cfg(not(any(adc_f1, adc_v1, adc_l0, adc_f3v3, adc_f3v2, adc_g0)))]
     #[allow(unused)]
     fn common_regs() -> crate::pac::adccommon::AdcCommon;
-    #[cfg(any(adc_f1, adc_f3, adc_v1, adc_l0, adc_f3_v1_1))]
+    #[cfg(any(adc_f1, adc_f3v1, adc_v1, adc_l0, adc_f3v2))]
     fn state() -> &'static State;
 }
 
@@ -100,22 +100,8 @@ pub(crate) fn blocking_delay_us(us: u32) {
 
 /// ADC instance.
 #[cfg(not(any(
-    adc_f1,
-    adc_v1,
-    adc_l0,
-    adc_v2,
-    adc_v3,
-    adc_v4,
-    adc_g4,
-    adc_f3,
-    adc_f3_v1_1,
-    adc_g0,
-    adc_u0,
-    adc_h5,
-    adc_h7rs,
-    adc_u5,
-    adc_c0,
-    adc_wba,
+    adc_f1, adc_v1, adc_l0, adc_v2, adc_v3, adc_v4, adc_g4, adc_f3v1, adc_f3v2, adc_g0, adc_u0, adc_h5, adc_h7rs,
+    adc_u5, adc_c0, adc_wba,
 )))]
 #[allow(private_bounds)]
 pub trait Instance: SealedInstance + crate::PeripheralType {
@@ -123,22 +109,8 @@ pub trait Instance: SealedInstance + crate::PeripheralType {
 }
 /// ADC instance.
 #[cfg(any(
-    adc_f1,
-    adc_v1,
-    adc_l0,
-    adc_v2,
-    adc_v3,
-    adc_v4,
-    adc_g4,
-    adc_f3,
-    adc_f3_v1_1,
-    adc_g0,
-    adc_u0,
-    adc_h5,
-    adc_h7rs,
-    adc_u5,
-    adc_c0,
-    adc_wba,
+    adc_f1, adc_v1, adc_l0, adc_v2, adc_v3, adc_v4, adc_g4, adc_f3v1, adc_f3v2, adc_g0, adc_u0, adc_h5, adc_h7rs,
+    adc_u5, adc_c0, adc_wba,
 ))]
 #[allow(private_bounds)]
 pub trait Instance: SealedInstance + crate::PeripheralType + crate::rcc::RccPeripheral {
@@ -258,12 +230,12 @@ foreach_adc!(
                 crate::pac::$inst
             }
 
-            #[cfg(not(any(adc_f1, adc_v1, adc_l0, adc_f3_v2, adc_f3_v1_1, adc_g0, adc_u5, adc_wba)))]
+            #[cfg(not(any(adc_f1, adc_v1, adc_l0, adc_f3v3, adc_f3v2, adc_g0, adc_u5, adc_wba)))]
             fn common_regs() -> crate::pac::adccommon::AdcCommon {
                 return crate::pac::$common_inst
             }
 
-            #[cfg(any(adc_f1, adc_f3, adc_v1, adc_l0, adc_f3_v1_1))]
+            #[cfg(any(adc_f1, adc_f3v1, adc_v1, adc_l0, adc_f3v2))]
             fn state() -> &'static State {
                 static STATE: State = State::new();
                 &STATE
@@ -295,7 +267,7 @@ macro_rules! impl_adc_pin {
 /// Get the maximum reading value for this resolution.
 ///
 /// This is `2**n - 1`.
-#[cfg(not(any(adc_f1, adc_f3_v2)))]
+#[cfg(not(any(adc_f1, adc_f3v3)))]
 pub const fn resolution_to_max_count(res: Resolution) -> u32 {
     match res {
         #[cfg(adc_v4)]
@@ -309,7 +281,7 @@ pub const fn resolution_to_max_count(res: Resolution) -> u32 {
         Resolution::BITS12 => (1 << 12) - 1,
         Resolution::BITS10 => (1 << 10) - 1,
         Resolution::BITS8 => (1 << 8) - 1,
-        #[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_c0, adc_g0, adc_f3, adc_f3_v1_1, adc_h5))]
+        #[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_c0, adc_g0, adc_f3v1, adc_f3v2, adc_h5))]
         Resolution::BITS6 => (1 << 6) - 1,
         #[allow(unreachable_patterns)]
         _ => core::unreachable!(),
diff --git a/embassy-stm32/src/adc/v1.rs b/embassy-stm32/src/adc/v1.rs
index 7fe502da0..d09374876 100644
--- a/embassy-stm32/src/adc/v1.rs
+++ b/embassy-stm32/src/adc/v1.rs
@@ -66,7 +66,11 @@ pub struct Temperature;
 impl AdcChannel<ADC1> for Temperature {}
 impl super::SealedAdcChannel<ADC1> for Temperature {
     fn channel(&self) -> u8 {
-        16
+        if cfg!(adc_l0) {
+            18
+        } else {
+            16
+        }
     }
 }
 
diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs
index dc1faa4d1..16063ce4d 100644
--- a/embassy-stm32/src/adc/v3.rs
+++ b/embassy-stm32/src/adc/v3.rs
@@ -1,7 +1,13 @@
 use cfg_if::cfg_if;
+#[cfg(adc_g0)]
+use heapless::Vec;
 use pac::adc::vals::Dmacfg;
+#[cfg(adc_g0)]
+use pac::adc::vals::{Ckmode, Smpsel};
 #[cfg(adc_v3)]
 use pac::adc::vals::{OversamplingRatio, OversamplingShift, Rovsm, Trovs};
+#[cfg(adc_g0)]
+pub use pac::adc::vals::{Ovsr, Ovss, Presc};
 
 use super::{
     blocking_delay_us, Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel,
@@ -14,6 +20,11 @@ pub const VREF_DEFAULT_MV: u32 = 3300;
 /// VREF voltage used for factory calibration of VREFINTCAL register.
 pub const VREF_CALIB_MV: u32 = 3000;
 
+#[cfg(adc_g0)]
+/// The number of variants in Smpsel
+// TODO: Use [#![feature(variant_count)]](https://github.com/rust-lang/rust/issues/73662) when stable
+const SAMPLE_TIMES_CAPACITY: usize = 2;
+
 pub struct VrefInt;
 impl<T: Instance> AdcChannel<T> for VrefInt {}
 impl<T: Instance> SealedAdcChannel<T> for VrefInt {
@@ -96,6 +107,8 @@ cfg_if! {
 }
 
 /// Number of samples used for averaging.
+#[derive(Copy, Clone, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Averaging {
     Disabled,
     Samples2,
@@ -107,8 +120,30 @@ pub enum Averaging {
     Samples128,
     Samples256,
 }
+
+cfg_if! { if #[cfg(adc_g0)] {
+
+/// Synchronous PCLK prescaler
+pub enum CkModePclk {
+    DIV1,
+    DIV2,
+    DIV4,
+}
+
+/// The analog clock is either the synchronous prescaled PCLK or
+/// the asynchronous prescaled ADCCLK configured by the RCC mux.
+/// The data sheet states the maximum analog clock frequency -
+/// for STM32WL55CC it is 36 MHz.
+pub enum Clock {
+    Sync { div: CkModePclk },
+    Async { div: Presc },
+}
+
+}}
+
 impl<'d, T: Instance> Adc<'d, T> {
-    pub fn new(adc: Peri<'d, T>) -> Self {
+    /// Enable the voltage regulator
+    fn init_regulator() {
         rcc::enable_and_reset::<T>();
         T::regs().cr().modify(|reg| {
             #[cfg(not(any(adc_g0, adc_u0)))]
@@ -117,13 +152,17 @@ impl<'d, T: Instance> Adc<'d, T> {
         });
 
         // If this is false then each ADC_CHSELR bit enables an input channel.
+        // This is the reset value, so has no effect.
         #[cfg(any(adc_g0, adc_u0))]
         T::regs().cfgr1().modify(|reg| {
             reg.set_chselrmod(false);
         });
 
         blocking_delay_us(20);
+    }
 
+    /// Calibrate to remove conversion offset
+    fn init_calibrate() {
         T::regs().cr().modify(|reg| {
             reg.set_adcal(true);
         });
@@ -133,6 +172,51 @@ impl<'d, T: Instance> Adc<'d, T> {
         }
 
         blocking_delay_us(1);
+    }
+
+    /// Initialize the ADC leaving any analog clock at reset value.
+    /// For G0 and WL, this is the async clock without prescaler.
+    pub fn new(adc: Peri<'d, T>) -> Self {
+        Self::init_regulator();
+        Self::init_calibrate();
+        Self {
+            adc,
+            sample_time: SampleTime::from_bits(0),
+        }
+    }
+
+    #[cfg(adc_g0)]
+    /// Initialize ADC with explicit clock for the analog ADC
+    pub fn new_with_clock(adc: Peri<'d, T>, clock: Clock) -> Self {
+        Self::init_regulator();
+
+        #[cfg(any(stm32wl5x))]
+        {
+            // Reset value 0 is actually _No clock selected_ in the STM32WL5x reference manual
+            let async_clock_available = pac::RCC.ccipr().read().adcsel() != pac::rcc::vals::Adcsel::_RESERVED_0;
+            match clock {
+                Clock::Async { div: _ } => {
+                    assert!(async_clock_available);
+                }
+                Clock::Sync { div: _ } => {
+                    if async_clock_available {
+                        warn!("Not using configured ADC clock");
+                    }
+                }
+            }
+        }
+        match clock {
+            Clock::Async { div } => T::regs().ccr().modify(|reg| reg.set_presc(div)),
+            Clock::Sync { div } => T::regs().cfgr2().modify(|reg| {
+                reg.set_ckmode(match div {
+                    CkModePclk::DIV1 => Ckmode::PCLK,
+                    CkModePclk::DIV2 => Ckmode::PCLK_DIV2,
+                    CkModePclk::DIV4 => Ckmode::PCLK_DIV4,
+                })
+            }),
+        }
+
+        Self::init_calibrate();
 
         Self {
             adc,
@@ -349,53 +433,78 @@ impl<'d, T: Instance> Adc<'d, T> {
             w.set_l(sequence.len() as u8 - 1);
         });
 
-        #[cfg(any(adc_g0, adc_u0))]
-        let mut channel_mask = 0;
-
-        // Configure channels and ranks
-        for (_i, (channel, sample_time)) in sequence.enumerate() {
-            Self::configure_channel(channel, sample_time);
-
-            // Each channel is sampled according to sequence
-            #[cfg(not(any(adc_g0, adc_u0)))]
-            match _i {
-                0..=3 => {
-                    T::regs().sqr1().modify(|w| {
-                        w.set_sq(_i, channel.channel());
-                    });
-                }
-                4..=8 => {
-                    T::regs().sqr2().modify(|w| {
-                        w.set_sq(_i - 4, channel.channel());
-                    });
-                }
-                9..=13 => {
-                    T::regs().sqr3().modify(|w| {
-                        w.set_sq(_i - 9, channel.channel());
-                    });
+        #[cfg(adc_g0)]
+        {
+            let mut sample_times = Vec::<SampleTime, SAMPLE_TIMES_CAPACITY>::new();
+
+            T::regs().chselr().write(|chselr| {
+                T::regs().smpr().write(|smpr| {
+                    for (channel, sample_time) in sequence {
+                        chselr.set_chsel(channel.channel.into(), true);
+                        if let Some(i) = sample_times.iter().position(|&t| t == sample_time) {
+                            smpr.set_smpsel(channel.channel.into(), (i as u8).into());
+                        } else {
+                            smpr.set_sample_time(sample_times.len(), sample_time);
+                            if let Err(_) = sample_times.push(sample_time) {
+                                panic!(
+                                    "Implementation is limited to {} unique sample times among all channels.",
+                                    SAMPLE_TIMES_CAPACITY
+                                );
+                            }
+                        }
+                    }
+                })
+            });
+        }
+        #[cfg(not(adc_g0))]
+        {
+            #[cfg(adc_u0)]
+            let mut channel_mask = 0;
+
+            // Configure channels and ranks
+            for (_i, (channel, sample_time)) in sequence.enumerate() {
+                Self::configure_channel(channel, sample_time);
+
+                // Each channel is sampled according to sequence
+                #[cfg(not(any(adc_g0, adc_u0)))]
+                match _i {
+                    0..=3 => {
+                        T::regs().sqr1().modify(|w| {
+                            w.set_sq(_i, channel.channel());
+                        });
+                    }
+                    4..=8 => {
+                        T::regs().sqr2().modify(|w| {
+                            w.set_sq(_i - 4, channel.channel());
+                        });
+                    }
+                    9..=13 => {
+                        T::regs().sqr3().modify(|w| {
+                            w.set_sq(_i - 9, channel.channel());
+                        });
+                    }
+                    14..=15 => {
+                        T::regs().sqr4().modify(|w| {
+                            w.set_sq(_i - 14, channel.channel());
+                        });
+                    }
+                    _ => unreachable!(),
                 }
-                14..=15 => {
-                    T::regs().sqr4().modify(|w| {
-                        w.set_sq(_i - 14, channel.channel());
-                    });
+
+                #[cfg(adc_u0)]
+                {
+                    channel_mask |= 1 << channel.channel();
                 }
-                _ => unreachable!(),
             }
 
-            #[cfg(any(adc_g0, adc_u0))]
-            {
-                channel_mask |= 1 << channel.channel();
-            }
+            // On G0 and U0 enabled channels are sampled from 0 to last channel.
+            // It is possible to add up to 8 sequences if CHSELRMOD = 1.
+            // However for supporting more than 8 channels alternative CHSELRMOD = 0 approach is used.
+            #[cfg(adc_u0)]
+            T::regs().chselr().modify(|reg| {
+                reg.set_chsel(channel_mask);
+            });
         }
-
-        // On G0 and U0 enabled channels are sampled from 0 to last channel.
-        // It is possible to add up to 8 sequences if CHSELRMOD = 1.
-        // However for supporting more than 8 channels alternative CHSELRMOD = 0 approach is used.
-        #[cfg(any(adc_g0, adc_u0))]
-        T::regs().chselr().modify(|reg| {
-            reg.set_chsel(channel_mask);
-        });
-
         // Set continuous mode with oneshot dma.
         // Clear overrun flag before starting transfer.
         T::regs().isr().modify(|reg| {
@@ -450,6 +559,7 @@ impl<'d, T: Instance> Adc<'d, T> {
         });
     }
 
+    #[cfg(not(adc_g0))]
     fn configure_channel(channel: &mut impl AdcChannel<T>, sample_time: SampleTime) {
         // RM0492, RM0481, etc.
         // "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
@@ -464,13 +574,23 @@ impl<'d, T: Instance> Adc<'d, T> {
 
     fn read_channel(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
         self.enable();
+        #[cfg(not(adc_g0))]
         Self::configure_channel(channel, self.sample_time);
-
+        #[cfg(adc_g0)]
+        T::regs().smpr().write(|reg| {
+            reg.set_sample_time(0, self.sample_time);
+            reg.set_smpsel(channel.channel().into(), Smpsel::SMP1);
+        });
         // Select channel
         #[cfg(not(any(adc_g0, adc_u0)))]
         T::regs().sqr1().write(|reg| reg.set_sq(0, channel.channel()));
         #[cfg(any(adc_g0, adc_u0))]
-        T::regs().chselr().write(|reg| reg.set_chsel(1 << channel.channel()));
+        T::regs().chselr().write(|reg| {
+            #[cfg(adc_g0)]
+            reg.set_chsel(channel.channel().into(), true);
+            #[cfg(adc_u0)]
+            reg.set_chsel(1 << channel.channel());
+        });
 
         // Some models are affected by an erratum:
         // If we perform conversions slower than 1 kHz, the first read ADC value can be
@@ -494,12 +614,20 @@ impl<'d, T: Instance> Adc<'d, T> {
         val
     }
 
-    #[cfg(any(adc_g0, adc_u0))]
+    #[cfg(adc_g0)]
+    pub fn set_oversampling_shift(&mut self, shift: Ovss) {
+        T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
+    }
+    #[cfg(adc_u0)]
     pub fn set_oversampling_shift(&mut self, shift: u8) {
         T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
     }
 
-    #[cfg(any(adc_g0, adc_u0))]
+    #[cfg(adc_g0)]
+    pub fn set_oversampling_ratio(&mut self, ratio: Ovsr) {
+        T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
+    }
+    #[cfg(adc_u0)]
     pub fn set_oversampling_ratio(&mut self, ratio: u8) {
         T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
     }
@@ -526,9 +654,10 @@ impl<'d, T: Instance> Adc<'d, T> {
         T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
     }
 
+    #[cfg(not(adc_g0))]
     fn set_channel_sample_time(_ch: u8, sample_time: SampleTime) {
         cfg_if! {
-            if #[cfg(any(adc_g0, adc_u0))] {
+            if #[cfg(adc_u0)] {
                 // On G0 and U6 all channels use the same sampling time.
                 T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into()));
             } else if #[cfg(any(adc_h5, adc_h7rs))] {
diff --git a/embassy-stm32/src/adc/v4.rs b/embassy-stm32/src/adc/v4.rs
index b0871019a..b66437e6e 100644
--- a/embassy-stm32/src/adc/v4.rs
+++ b/embassy-stm32/src/adc/v4.rs
@@ -142,7 +142,8 @@ impl Prescaler {
 }
 
 /// Number of samples used for averaging.
-#[derive(Copy, Clone)]
+#[derive(Copy, Clone, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Averaging {
     Disabled,
     Samples2,
diff --git a/embassy-stm32/src/can/bxcan/mod.rs b/embassy-stm32/src/can/bxcan/mod.rs
index 4c0795a2a..8eb188560 100644
--- a/embassy-stm32/src/can/bxcan/mod.rs
+++ b/embassy-stm32/src/can/bxcan/mod.rs
@@ -181,10 +181,10 @@ pub enum TryWriteError {
 impl<'d> Can<'d> {
     /// Creates a new Bxcan instance, keeping the peripheral in sleep mode.
     /// You must call [Can::enable_non_blocking] to use the peripheral.
-    pub fn new<T: Instance>(
+    pub fn new<T: Instance, #[cfg(afio)] A>(
         _peri: Peri<'d, T>,
-        rx: Peri<'d, impl RxPin<T>>,
-        tx: Peri<'d, impl TxPin<T>>,
+        rx: Peri<'d, if_afio!(impl RxPin<T, A>)>,
+        tx: Peri<'d, if_afio!(impl TxPin<T, A>)>,
         _irqs: impl interrupt::typelevel::Binding<T::TXInterrupt, TxInterruptHandler<T>>
             + interrupt::typelevel::Binding<T::RX0Interrupt, Rx0InterruptHandler<T>>
             + interrupt::typelevel::Binding<T::RX1Interrupt, Rx1InterruptHandler<T>>
@@ -194,8 +194,8 @@ impl<'d> Can<'d> {
         let info = T::info();
         let regs = &T::info().regs;
 
-        rx.set_as_af(rx.af_num(), AfType::input(Pull::None));
-        tx.set_as_af(tx.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
+        set_as_af!(rx, AfType::input(Pull::None));
+        set_as_af!(tx, AfType::output(OutputType::PushPull, Speed::VeryHigh));
 
         rcc::enable_and_reset::<T>();
 
@@ -229,8 +229,8 @@ impl<'d> Can<'d> {
             info.sce_interrupt.enable();
         }
 
-        rx.set_as_af(rx.af_num(), AfType::input(Pull::None));
-        tx.set_as_af(tx.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
+        set_as_af!(rx, AfType::input(Pull::None));
+        set_as_af!(tx, AfType::output(OutputType::PushPull, Speed::VeryHigh));
 
         Registers(T::regs()).leave_init_mode();
 
@@ -1218,8 +1218,8 @@ foreach_peripheral!(
     };
 );
 
-pin_trait!(RxPin, Instance);
-pin_trait!(TxPin, Instance);
+pin_trait!(RxPin, Instance, @A);
+pin_trait!(TxPin, Instance, @A);
 
 trait Index {
     fn index(&self) -> usize;
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index 99e40ba62..d8f71e03e 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -185,8 +185,8 @@ impl<'d> CanConfigurator<'d> {
             + interrupt::typelevel::Binding<T::IT1Interrupt, IT1InterruptHandler<T>>
             + 'd,
     ) -> CanConfigurator<'d> {
-        rx.set_as_af(rx.af_num(), AfType::input(Pull::None));
-        tx.set_as_af(tx.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
+        set_as_af!(rx, AfType::input(Pull::None));
+        set_as_af!(tx, AfType::output(OutputType::PushPull, Speed::VeryHigh));
 
         rcc::enable_and_reset::<T>();
 
diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs
index 35d9f8cce..0173b2b5d 100644
--- a/embassy-stm32/src/cryp/mod.rs
+++ b/embassy-stm32/src/cryp/mod.rs
@@ -1814,7 +1814,6 @@ impl<'d, T: Instance> Cryp<'d, T, Async> {
         // Configure DMA to transfer input to crypto core.
         let dst_ptr: *mut u32 = T::regs().din().as_ptr();
         let options = TransferOptions {
-            #[cfg(not(gpdma))]
             priority: crate::dma::Priority::High,
             ..Default::default()
         };
@@ -1834,7 +1833,6 @@ impl<'d, T: Instance> Cryp<'d, T, Async> {
         // Configure DMA to transfer input to crypto core.
         let dst_ptr: *mut u32 = T::regs().din().as_ptr();
         let options = TransferOptions {
-            #[cfg(not(gpdma))]
             priority: crate::dma::Priority::High,
             ..Default::default()
         };
@@ -1853,7 +1851,6 @@ impl<'d, T: Instance> Cryp<'d, T, Async> {
         // Configure DMA to get output from crypto core.
         let src_ptr = T::regs().dout().as_ptr();
         let options = TransferOptions {
-            #[cfg(not(gpdma))]
             priority: crate::dma::Priority::VeryHigh,
             ..Default::default()
         };
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index d8f1f96f2..08e001337 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -12,6 +12,7 @@ use crate::{peripherals, Peri};
 
 mod tsel;
 use embassy_hal_internal::PeripheralType;
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 pub use tsel::TriggerSel;
 
 /// Operating mode for DAC channel
@@ -96,6 +97,41 @@ pub enum ValueArray<'a> {
     Bit12Right(&'a [u16]),
 }
 
+#[derive(Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+enum ChannelEvent {
+    Enable,
+    Disable,
+}
+
+struct InnerState {
+    channel_count: usize,
+}
+
+type SharedState = embassy_sync::blocking_mutex::Mutex<CriticalSectionRawMutex, core::cell::RefCell<InnerState>>;
+struct State {
+    state: SharedState,
+}
+
+impl State {
+    /// Adjusts the channel count in response to a `ChannelEvent`, returning the updated value.
+    pub fn adjust_channel_count(&self, event: ChannelEvent) -> usize {
+        self.state.lock(|state| {
+            {
+                let mut mut_state = state.borrow_mut();
+                match event {
+                    ChannelEvent::Enable => {
+                        mut_state.channel_count += 1;
+                    }
+                    ChannelEvent::Disable => {
+                        mut_state.channel_count -= 1;
+                    }
+                };
+            }
+            state.borrow().channel_count
+        })
+    }
+}
 /// Driver for a single DAC channel.
 ///
 /// If you want to use both channels, either together or independently,
@@ -249,6 +285,16 @@ impl<'d, T: Instance, C: Channel, M: PeriMode> DacChannel<'d, T, C, M> {
                 reg.set_en(C::IDX, on);
             });
         });
+        let event = if on {
+            ChannelEvent::Enable
+        } else {
+            ChannelEvent::Disable
+        };
+        let channel_count = T::state().adjust_channel_count(event);
+        // Disable the DAC only if no more channels are using it.
+        if channel_count == 0 {
+            rcc::disable::<T>();
+        }
     }
 
     /// Enable this channel.
@@ -354,7 +400,7 @@ impl<'d, T: Instance, C: Channel, M: PeriMode> DacChannel<'d, T, C, M> {
 
 impl<'d, T: Instance, C: Channel, M: PeriMode> Drop for DacChannel<'d, T, C, M> {
     fn drop(&mut self) {
-        rcc::disable::<T>();
+        self.disable();
     }
 }
 
@@ -529,8 +575,6 @@ impl<'d, T: Instance, M: PeriMode> Dac<'d, T, M> {
         dma_ch2: Option<ChannelAndRequest<'d>>,
         #[cfg(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7))] mode: Mode,
     ) -> Self {
-        // Enable twice to increment the DAC refcount for each channel.
-        rcc::enable_and_reset::<T>();
         rcc::enable_and_reset::<T>();
 
         let mut ch1 = DacCh1 {
@@ -597,6 +641,13 @@ impl<'d, T: Instance, M: PeriMode> Dac<'d, T, M> {
 
 trait SealedInstance {
     fn regs() -> crate::pac::dac::Dac;
+
+    fn state() -> &'static State {
+        static STATE: State = State {
+            state: embassy_sync::blocking_mutex::Mutex::new(core::cell::RefCell::new(InnerState { channel_count: 0 })),
+        };
+        &STATE
+    }
 }
 
 /// DAC instance.
diff --git a/embassy-stm32/src/dcmi.rs b/embassy-stm32/src/dcmi.rs
index d05faee21..bd03f1e00 100644
--- a/embassy-stm32/src/dcmi.rs
+++ b/embassy-stm32/src/dcmi.rs
@@ -108,7 +108,7 @@ macro_rules! config_pins {
     ($($pin:ident),*) => {
                 critical_section::with(|_| {
             $(
-                $pin.set_as_af($pin.af_num(), AfType::input(Pull::None));
+                set_as_af!($pin, AfType::input(Pull::None));
             )*
         })
     };
diff --git a/embassy-stm32/src/dma/dma_bdma.rs b/embassy-stm32/src/dma/dma_bdma.rs
index 464823bfc..73ecab070 100644
--- a/embassy-stm32/src/dma/dma_bdma.rs
+++ b/embassy-stm32/src/dma/dma_bdma.rs
@@ -498,46 +498,52 @@ impl AnyChannel {
         }
     }
 
-    fn request_stop(&self) {
+    fn request_pause(&self) {
         let info = self.info();
         match self.info().dma {
             #[cfg(dma)]
             DmaInfo::Dma(r) => {
-                // Disable the channel. Keep the IEs enabled so the irqs still fire.
-                r.st(info.num).cr().write(|w| {
-                    w.set_teie(true);
-                    w.set_tcie(true);
+                // Disable the channel without overwriting the existing configuration
+                r.st(info.num).cr().modify(|w| {
+                    w.set_en(false);
                 });
             }
             #[cfg(bdma)]
             DmaInfo::Bdma(r) => {
-                // Disable the channel. Keep the IEs enabled so the irqs still fire.
-                r.ch(info.num).cr().write(|w| {
-                    w.set_teie(true);
-                    w.set_tcie(true);
+                // Disable the channel without overwriting the existing configuration
+                r.ch(info.num).cr().modify(|w| {
+                    w.set_en(false);
                 });
             }
         }
     }
 
-    fn request_pause(&self) {
+    fn request_resume(&self) {
+        self.start()
+    }
+
+    fn request_reset(&self) {
         let info = self.info();
         match self.info().dma {
             #[cfg(dma)]
             DmaInfo::Dma(r) => {
-                // Disable the channel without overwriting the existing configuration
-                r.st(info.num).cr().modify(|w| {
-                    w.set_en(false);
+                // Disable the channel. Keep the IEs enabled so the irqs still fire.
+                r.st(info.num).cr().write(|w| {
+                    w.set_teie(true);
+                    w.set_tcie(true);
                 });
             }
             #[cfg(bdma)]
             DmaInfo::Bdma(r) => {
-                // Disable the channel without overwriting the existing configuration
-                r.ch(info.num).cr().modify(|w| {
-                    w.set_en(false);
+                // Disable the channel. Keep the IEs enabled so the irqs still fire.
+                r.ch(info.num).cr().write(|w| {
+                    w.set_teie(true);
+                    w.set_tcie(true);
                 });
             }
         }
+
+        while self.is_running() {}
     }
 
     fn is_running(&self) -> bool {
@@ -710,27 +716,31 @@ impl<'a> Transfer<'a> {
         Self { channel }
     }
 
-    /// Request the transfer to stop.
-    /// The configuration for this channel will **not be preserved**. If you need to restart the transfer
-    /// at a later point with the same configuration, see [`request_pause`](Self::request_pause) instead.
-    ///
-    /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
-    pub fn request_stop(&mut self) {
-        self.channel.request_stop()
-    }
-
     /// Request the transfer to pause, keeping the existing configuration for this channel.
-    /// To restart the transfer, call [`start`](Self::start) again.
     ///
+    /// To resume the transfer, call [`request_resume`](Self::request_resume) again.
     /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
     pub fn request_pause(&mut self) {
         self.channel.request_pause()
     }
 
+    /// Request the transfer to resume after having been paused.
+    pub fn request_resume(&mut self) {
+        self.channel.request_resume()
+    }
+
+    /// Request the DMA to reset.
+    ///
+    /// The configuration for this channel will **not be preserved**. If you need to restart the transfer
+    /// at a later point with the same configuration, see [`request_pause`](Self::request_pause) instead.
+    pub fn request_reset(&mut self) {
+        self.channel.request_reset()
+    }
+
     /// Return whether this transfer is still running.
     ///
     /// If this returns `false`, it can be because either the transfer finished, or
-    /// it was requested to stop early with [`request_stop`](Self::request_stop).
+    /// it was requested to stop early with [`request_pause`](Self::request_pause).
     pub fn is_running(&mut self) -> bool {
         self.channel.is_running()
     }
@@ -754,7 +764,7 @@ impl<'a> Transfer<'a> {
 
 impl<'a> Drop for Transfer<'a> {
     fn drop(&mut self) {
-        self.request_stop();
+        self.request_reset();
         while self.is_running() {}
 
         // "Subsequent reads and writes cannot be moved ahead of preceding reads."
@@ -901,15 +911,6 @@ impl<'a, W: Word> ReadableRingBuffer<'a, W> {
         DmaCtrlImpl(self.channel.reborrow()).set_waker(waker);
     }
 
-    /// Request the DMA to stop.
-    /// The configuration for this channel will **not be preserved**. If you need to restart the transfer
-    /// at a later point with the same configuration, see [`request_pause`](Self::request_pause) instead.
-    ///
-    /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
-    pub fn request_stop(&mut self) {
-        self.channel.request_stop()
-    }
-
     /// Request the transfer to pause, keeping the existing configuration for this channel.
     /// To restart the transfer, call [`start`](Self::start) again.
     ///
@@ -918,10 +919,23 @@ impl<'a, W: Word> ReadableRingBuffer<'a, W> {
         self.channel.request_pause()
     }
 
+    /// Request the transfer to resume after having been paused.
+    pub fn request_resume(&mut self) {
+        self.channel.request_resume()
+    }
+
+    /// Request the DMA to reset.
+    ///
+    /// The configuration for this channel will **not be preserved**. If you need to restart the transfer
+    /// at a later point with the same configuration, see [`request_pause`](Self::request_pause) instead.
+    pub fn request_reset(&mut self) {
+        self.channel.request_reset()
+    }
+
     /// Return whether DMA is still running.
     ///
     /// If this returns `false`, it can be because either the transfer finished, or
-    /// it was requested to stop early with [`request_stop`](Self::request_stop).
+    /// it was requested to stop early with [`request_reset`](Self::request_reset).
     pub fn is_running(&mut self) -> bool {
         self.channel.is_running()
     }
@@ -934,7 +948,7 @@ impl<'a, W: Word> ReadableRingBuffer<'a, W> {
     /// This is designed to be used with streaming input data such as the
     /// I2S/SAI or ADC.
     ///
-    /// When using the UART, you probably want `request_stop()`.
+    /// When using the UART, you probably want `request_reset()`.
     pub async fn stop(&mut self) {
         self.channel.disable_circular_mode();
         //wait until cr.susp reads as true
@@ -948,7 +962,7 @@ impl<'a, W: Word> ReadableRingBuffer<'a, W> {
 
 impl<'a, W: Word> Drop for ReadableRingBuffer<'a, W> {
     fn drop(&mut self) {
-        self.request_stop();
+        self.request_reset();
         while self.is_running() {}
 
         // "Subsequent reads and writes cannot be moved ahead of preceding reads."
@@ -1058,8 +1072,8 @@ impl<'a, W: Word> WritableRingBuffer<'a, W> {
     /// at a later point with the same configuration, see [`request_pause`](Self::request_pause) instead.
     ///
     /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
-    pub fn request_stop(&mut self) {
-        self.channel.request_stop()
+    pub fn request_reset(&mut self) {
+        self.channel.request_reset()
     }
 
     /// Request the transfer to pause, keeping the existing configuration for this channel.
@@ -1073,7 +1087,7 @@ impl<'a, W: Word> WritableRingBuffer<'a, W> {
     /// Return whether DMA is still running.
     ///
     /// If this returns `false`, it can be because either the transfer finished, or
-    /// it was requested to stop early with [`request_stop`](Self::request_stop).
+    /// it was requested to stop early with [`request_reset`](Self::request_reset).
     pub fn is_running(&mut self) -> bool {
         self.channel.is_running()
     }
@@ -1098,7 +1112,7 @@ impl<'a, W: Word> WritableRingBuffer<'a, W> {
 
 impl<'a, W: Word> Drop for WritableRingBuffer<'a, W> {
     fn drop(&mut self) {
-        self.request_stop();
+        self.request_reset();
         while self.is_running() {}
 
         // "Subsequent reads and writes cannot be moved ahead of preceding reads."
diff --git a/embassy-stm32/src/dma/gpdma.rs b/embassy-stm32/src/dma/gpdma.rs
deleted file mode 100644
index 151e4ab9f..000000000
--- a/embassy-stm32/src/dma/gpdma.rs
+++ /dev/null
@@ -1,339 +0,0 @@
-#![macro_use]
-
-use core::future::Future;
-use core::pin::Pin;
-use core::sync::atomic::{fence, Ordering};
-use core::task::{Context, Poll};
-
-use embassy_hal_internal::Peri;
-use embassy_sync::waitqueue::AtomicWaker;
-
-use super::word::{Word, WordSize};
-use super::{AnyChannel, Channel, Dir, Request, STATE};
-use crate::interrupt::typelevel::Interrupt;
-use crate::interrupt::Priority;
-use crate::pac;
-use crate::pac::gpdma::vals;
-
-pub(crate) struct ChannelInfo {
-    pub(crate) dma: pac::gpdma::Gpdma,
-    pub(crate) num: usize,
-    #[cfg(feature = "_dual-core")]
-    pub(crate) irq: pac::Interrupt,
-}
-
-/// GPDMA transfer options.
-#[derive(Debug, Copy, Clone, PartialEq, Eq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-#[non_exhaustive]
-pub struct TransferOptions {}
-
-impl Default for TransferOptions {
-    fn default() -> Self {
-        Self {}
-    }
-}
-
-impl From<WordSize> for vals::Dw {
-    fn from(raw: WordSize) -> Self {
-        match raw {
-            WordSize::OneByte => Self::BYTE,
-            WordSize::TwoBytes => Self::HALF_WORD,
-            WordSize::FourBytes => Self::WORD,
-        }
-    }
-}
-
-pub(crate) struct ChannelState {
-    waker: AtomicWaker,
-}
-
-impl ChannelState {
-    pub(crate) const NEW: Self = Self {
-        waker: AtomicWaker::new(),
-    };
-}
-
-/// safety: must be called only once
-pub(crate) unsafe fn init(cs: critical_section::CriticalSection, irq_priority: Priority) {
-    foreach_interrupt! {
-        ($peri:ident, gpdma, $block:ident, $signal_name:ident, $irq:ident) => {
-            crate::interrupt::typelevel::$irq::set_priority_with_cs(cs, irq_priority);
-            #[cfg(not(feature = "_dual-core"))]
-            crate::interrupt::typelevel::$irq::enable();
-        };
-    }
-    crate::_generated::init_gpdma();
-}
-
-impl AnyChannel {
-    /// Safety: Must be called with a matching set of parameters for a valid dma channel
-    pub(crate) unsafe fn on_irq(&self) {
-        let info = self.info();
-        #[cfg(feature = "_dual-core")]
-        {
-            use embassy_hal_internal::interrupt::InterruptExt as _;
-            info.irq.enable();
-        }
-
-        let state = &STATE[self.id as usize];
-
-        let ch = info.dma.ch(info.num);
-        let sr = ch.sr().read();
-
-        if sr.dtef() {
-            panic!(
-                "DMA: data transfer error on DMA@{:08x} channel {}",
-                info.dma.as_ptr() as u32,
-                info.num
-            );
-        }
-        if sr.usef() {
-            panic!(
-                "DMA: user settings error on DMA@{:08x} channel {}",
-                info.dma.as_ptr() as u32,
-                info.num
-            );
-        }
-
-        if sr.suspf() || sr.tcf() {
-            // disable all xxIEs to prevent the irq from firing again.
-            ch.cr().write(|_| {});
-
-            // Wake the future. It'll look at tcf and see it's set.
-            state.waker.wake();
-        }
-    }
-}
-
-/// DMA transfer.
-#[must_use = "futures do nothing unless you `.await` or poll them"]
-pub struct Transfer<'a> {
-    channel: Peri<'a, AnyChannel>,
-}
-
-impl<'a> Transfer<'a> {
-    /// Create a new read DMA transfer (peripheral to memory).
-    pub unsafe fn new_read<W: Word>(
-        channel: Peri<'a, impl Channel>,
-        request: Request,
-        peri_addr: *mut W,
-        buf: &'a mut [W],
-        options: TransferOptions,
-    ) -> Self {
-        Self::new_read_raw(channel, request, peri_addr, buf, options)
-    }
-
-    /// Create a new read DMA transfer (peripheral to memory), using raw pointers.
-    pub unsafe fn new_read_raw<MW: Word, PW: Word>(
-        channel: Peri<'a, impl Channel>,
-        request: Request,
-        peri_addr: *mut PW,
-        buf: *mut [MW],
-        options: TransferOptions,
-    ) -> Self {
-        Self::new_inner(
-            channel.into(),
-            request,
-            Dir::PeripheralToMemory,
-            peri_addr as *const u32,
-            buf as *mut MW as *mut u32,
-            buf.len(),
-            true,
-            PW::size(),
-            MW::size(),
-            options,
-        )
-    }
-
-    /// Create a new write DMA transfer (memory to peripheral).
-    pub unsafe fn new_write<MW: Word, PW: Word>(
-        channel: Peri<'a, impl Channel>,
-        request: Request,
-        buf: &'a [MW],
-        peri_addr: *mut PW,
-        options: TransferOptions,
-    ) -> Self {
-        Self::new_write_raw(channel, request, buf, peri_addr, options)
-    }
-
-    /// Create a new write DMA transfer (memory to peripheral), using raw pointers.
-    pub unsafe fn new_write_raw<MW: Word, PW: Word>(
-        channel: Peri<'a, impl Channel>,
-        request: Request,
-        buf: *const [MW],
-        peri_addr: *mut PW,
-        options: TransferOptions,
-    ) -> Self {
-        Self::new_inner(
-            channel.into(),
-            request,
-            Dir::MemoryToPeripheral,
-            peri_addr as *const u32,
-            buf as *const MW as *mut u32,
-            buf.len(),
-            true,
-            MW::size(),
-            PW::size(),
-            options,
-        )
-    }
-
-    /// Create a new write DMA transfer (memory to peripheral), writing the same value repeatedly.
-    pub unsafe fn new_write_repeated<MW: Word, PW: Word>(
-        channel: Peri<'a, impl Channel>,
-        request: Request,
-        repeated: &'a MW,
-        count: usize,
-        peri_addr: *mut PW,
-        options: TransferOptions,
-    ) -> Self {
-        Self::new_inner(
-            channel.into(),
-            request,
-            Dir::MemoryToPeripheral,
-            peri_addr as *const u32,
-            repeated as *const MW as *mut u32,
-            count,
-            false,
-            MW::size(),
-            PW::size(),
-            options,
-        )
-    }
-
-    unsafe fn new_inner(
-        channel: Peri<'a, AnyChannel>,
-        request: Request,
-        dir: Dir,
-        peri_addr: *const u32,
-        mem_addr: *mut u32,
-        mem_len: usize,
-        incr_mem: bool,
-        data_size: WordSize,
-        dst_size: WordSize,
-        _options: TransferOptions,
-    ) -> Self {
-        // BNDT is specified as bytes, not as number of transfers.
-        let Ok(bndt) = (mem_len * data_size.bytes()).try_into() else {
-            panic!("DMA transfers may not be larger than 65535 bytes.");
-        };
-
-        let info = channel.info();
-        let ch = info.dma.ch(info.num);
-
-        // "Preceding reads and writes cannot be moved past subsequent writes."
-        fence(Ordering::SeqCst);
-
-        let this = Self { channel };
-
-        ch.cr().write(|w| w.set_reset(true));
-        ch.fcr().write(|w| w.0 = 0xFFFF_FFFF); // clear all irqs
-        ch.llr().write(|_| {}); // no linked list
-        ch.tr1().write(|w| {
-            w.set_sdw(data_size.into());
-            w.set_ddw(dst_size.into());
-            w.set_sinc(dir == Dir::MemoryToPeripheral && incr_mem);
-            w.set_dinc(dir == Dir::PeripheralToMemory && incr_mem);
-        });
-        ch.tr2().write(|w| {
-            w.set_dreq(match dir {
-                Dir::MemoryToPeripheral => vals::Dreq::DESTINATION_PERIPHERAL,
-                Dir::PeripheralToMemory => vals::Dreq::SOURCE_PERIPHERAL,
-            });
-            w.set_reqsel(request);
-        });
-        ch.tr3().write(|_| {}); // no address offsets.
-        ch.br1().write(|w| w.set_bndt(bndt));
-
-        match dir {
-            Dir::MemoryToPeripheral => {
-                ch.sar().write_value(mem_addr as _);
-                ch.dar().write_value(peri_addr as _);
-            }
-            Dir::PeripheralToMemory => {
-                ch.sar().write_value(peri_addr as _);
-                ch.dar().write_value(mem_addr as _);
-            }
-        }
-
-        ch.cr().write(|w| {
-            // Enable interrupts
-            w.set_tcie(true);
-            w.set_useie(true);
-            w.set_dteie(true);
-            w.set_suspie(true);
-
-            // Start it
-            w.set_en(true);
-        });
-
-        this
-    }
-
-    /// Request the transfer to stop.
-    ///
-    /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
-    pub fn request_stop(&mut self) {
-        let info = self.channel.info();
-        let ch = info.dma.ch(info.num);
-
-        ch.cr().modify(|w| w.set_susp(true))
-    }
-
-    /// Return whether this transfer is still running.
-    ///
-    /// If this returns `false`, it can be because either the transfer finished, or
-    /// it was requested to stop early with [`request_stop`](Self::request_stop).
-    pub fn is_running(&mut self) -> bool {
-        let info = self.channel.info();
-        let ch = info.dma.ch(info.num);
-
-        let sr = ch.sr().read();
-        !sr.tcf() && !sr.suspf()
-    }
-
-    /// Gets the total remaining transfers for the channel
-    /// Note: this will be zero for transfers that completed without cancellation.
-    pub fn get_remaining_transfers(&self) -> u16 {
-        let info = self.channel.info();
-        let ch = info.dma.ch(info.num);
-
-        ch.br1().read().bndt()
-    }
-
-    /// Blocking wait until the transfer finishes.
-    pub fn blocking_wait(mut self) {
-        while self.is_running() {}
-
-        // "Subsequent reads and writes cannot be moved ahead of preceding reads."
-        fence(Ordering::SeqCst);
-
-        core::mem::forget(self);
-    }
-}
-
-impl<'a> Drop for Transfer<'a> {
-    fn drop(&mut self) {
-        self.request_stop();
-        while self.is_running() {}
-
-        // "Subsequent reads and writes cannot be moved ahead of preceding reads."
-        fence(Ordering::SeqCst);
-    }
-}
-
-impl<'a> Unpin for Transfer<'a> {}
-impl<'a> Future for Transfer<'a> {
-    type Output = ();
-    fn poll(mut self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
-        let state = &STATE[self.channel.id as usize];
-        state.waker.register(cx.waker());
-
-        if self.is_running() {
-            Poll::Pending
-        } else {
-            Poll::Ready(())
-        }
-    }
-}
diff --git a/embassy-stm32/src/dma/gpdma/linked_list.rs b/embassy-stm32/src/dma/gpdma/linked_list.rs
new file mode 100644
index 000000000..f7c1fbbed
--- /dev/null
+++ b/embassy-stm32/src/dma/gpdma/linked_list.rs
@@ -0,0 +1,267 @@
+//! Implementation of the GPDMA linked list and linked list items.
+#![macro_use]
+
+use stm32_metapac::gpdma::regs;
+use stm32_metapac::gpdma::vals::Dreq;
+
+use crate::dma::word::{Word, WordSize};
+use crate::dma::{Dir, Request};
+
+/// The mode in which to run the linked list.
+#[derive(Debug)]
+pub enum RunMode {
+    /// List items are not linked together.
+    Unlinked,
+    /// The list is linked sequentially and only run once.
+    Once,
+    /// The list is linked sequentially, and the end of the list is linked to the beginning.
+    Circular,
+}
+
+/// A linked-list item for linear GPDMA transfers.
+///
+/// Also works for 2D-capable GPDMA channels, but does not use 2D capabilities.
+#[derive(Debug, Copy, Clone, Default)]
+#[repr(C)]
+pub struct LinearItem {
+    /// Transfer register 1.
+    pub tr1: regs::ChTr1,
+    /// Transfer register 2.
+    pub tr2: regs::ChTr2,
+    /// Block register 2.
+    pub br1: regs::ChBr1,
+    /// Source address register.
+    pub sar: u32,
+    /// Destination address register.
+    pub dar: u32,
+    /// Linked-list address register.
+    pub llr: regs::ChLlr,
+}
+
+impl LinearItem {
+    /// Create a new read DMA transfer (peripheral to memory).
+    pub unsafe fn new_read<'d, W: Word>(request: Request, peri_addr: *mut W, buf: &'d mut [W]) -> Self {
+        Self::new_inner(
+            request,
+            Dir::PeripheralToMemory,
+            peri_addr as *const u32,
+            buf as *mut [W] as *mut W as *mut u32,
+            buf.len(),
+            true,
+            W::size(),
+            W::size(),
+        )
+    }
+
+    /// Create a new write DMA transfer (memory to peripheral).
+    pub unsafe fn new_write<'d, MW: Word, PW: Word>(request: Request, buf: &'d [MW], peri_addr: *mut PW) -> Self {
+        Self::new_inner(
+            request,
+            Dir::MemoryToPeripheral,
+            peri_addr as *const u32,
+            buf as *const [MW] as *const MW as *mut u32,
+            buf.len(),
+            true,
+            MW::size(),
+            PW::size(),
+        )
+    }
+
+    unsafe fn new_inner(
+        request: Request,
+        dir: Dir,
+        peri_addr: *const u32,
+        mem_addr: *mut u32,
+        mem_len: usize,
+        incr_mem: bool,
+        data_size: WordSize,
+        dst_size: WordSize,
+    ) -> Self {
+        // BNDT is specified as bytes, not as number of transfers.
+        let Ok(bndt) = (mem_len * data_size.bytes()).try_into() else {
+            panic!("DMA transfers may not be larger than 65535 bytes.");
+        };
+
+        let mut br1 = regs::ChBr1(0);
+        br1.set_bndt(bndt);
+
+        let mut tr1 = regs::ChTr1(0);
+        tr1.set_sdw(data_size.into());
+        tr1.set_ddw(dst_size.into());
+        tr1.set_sinc(dir == Dir::MemoryToPeripheral && incr_mem);
+        tr1.set_dinc(dir == Dir::PeripheralToMemory && incr_mem);
+
+        let mut tr2 = regs::ChTr2(0);
+        tr2.set_dreq(match dir {
+            Dir::MemoryToPeripheral => Dreq::DESTINATION_PERIPHERAL,
+            Dir::PeripheralToMemory => Dreq::SOURCE_PERIPHERAL,
+        });
+        tr2.set_reqsel(request);
+
+        let (sar, dar) = match dir {
+            Dir::MemoryToPeripheral => (mem_addr as _, peri_addr as _),
+            Dir::PeripheralToMemory => (peri_addr as _, mem_addr as _),
+        };
+
+        let llr = regs::ChLlr(0);
+
+        Self {
+            tr1,
+            tr2,
+            br1,
+            sar,
+            dar,
+            llr,
+        }
+    }
+
+    /// Link to the next linear item at the given address.
+    ///
+    /// Enables channel update bits.
+    fn link_to(&mut self, next: u16) {
+        let mut llr = regs::ChLlr(0);
+
+        llr.set_ut1(true);
+        llr.set_ut2(true);
+        llr.set_ub1(true);
+        llr.set_usa(true);
+        llr.set_uda(true);
+        llr.set_ull(true);
+
+        // Lower two bits are ignored: 32 bit aligned.
+        llr.set_la(next >> 2);
+
+        self.llr = llr;
+    }
+
+    /// Unlink the next linear item.
+    ///
+    /// Disables channel update bits.
+    fn unlink(&mut self) {
+        self.llr = regs::ChLlr(0);
+    }
+
+    /// The item's transfer count in number of words.
+    fn transfer_count(&self) -> usize {
+        let word_size: WordSize = self.tr1.ddw().into();
+        self.br1.bndt() as usize / word_size.bytes()
+    }
+}
+
+/// A table of linked list items.
+#[repr(C)]
+pub struct Table<const ITEM_COUNT: usize> {
+    /// The items.
+    pub items: [LinearItem; ITEM_COUNT],
+}
+
+impl<const ITEM_COUNT: usize> Table<ITEM_COUNT> {
+    /// Create a new table.
+    pub fn new(items: [LinearItem; ITEM_COUNT]) -> Self {
+        assert!(!items.is_empty());
+
+        Self { items }
+    }
+
+    /// Create a ping-pong linked-list table.
+    ///
+    /// This uses two linked-list items, one for each half of the buffer.
+    pub unsafe fn new_ping_pong<W: Word>(
+        request: Request,
+        peri_addr: *mut W,
+        buffer: &mut [W],
+        direction: Dir,
+    ) -> Table<2> {
+        // Buffer halves should be the same length.
+        let half_len = buffer.len() / 2;
+        assert_eq!(half_len * 2, buffer.len());
+
+        let items = match direction {
+            Dir::MemoryToPeripheral => [
+                LinearItem::new_write(request, &mut buffer[..half_len], peri_addr),
+                LinearItem::new_write(request, &mut buffer[half_len..], peri_addr),
+            ],
+            Dir::PeripheralToMemory => [
+                LinearItem::new_read(request, peri_addr, &mut buffer[..half_len]),
+                LinearItem::new_read(request, peri_addr, &mut buffer[half_len..]),
+            ],
+        };
+
+        Table::new(items)
+    }
+
+    /// Link the table as given by the run mode.
+    pub fn link(&mut self, run_mode: RunMode) {
+        if matches!(run_mode, RunMode::Once | RunMode::Circular) {
+            self.link_sequential();
+        }
+
+        if matches!(run_mode, RunMode::Circular) {
+            self.link_repeat();
+        }
+    }
+
+    /// The number of linked list items.
+    pub fn len(&self) -> usize {
+        self.items.len()
+    }
+
+    /// The total transfer count of the table in number of words.
+    pub fn transfer_count(&self) -> usize {
+        let mut count = 0;
+        for item in self.items {
+            count += item.transfer_count() as usize
+        }
+
+        count
+    }
+
+    /// Link items of given indices together: first -> second.
+    pub fn link_indices(&mut self, first: usize, second: usize) {
+        assert!(first < self.len());
+        assert!(second < self.len());
+
+        let second_item = self.offset_address(second);
+        self.items[first].link_to(second_item);
+    }
+
+    /// Link items sequentially.
+    pub fn link_sequential(&mut self) {
+        if self.len() > 1 {
+            for index in 0..(self.items.len() - 1) {
+                let next = self.offset_address(index + 1);
+                self.items[index].link_to(next);
+            }
+        }
+    }
+
+    /// Link last to first item.
+    pub fn link_repeat(&mut self) {
+        let first_address = self.offset_address(0);
+        self.items.last_mut().unwrap().link_to(first_address);
+    }
+
+    /// Unlink all items.
+    pub fn unlink(&mut self) {
+        for item in self.items.iter_mut() {
+            item.unlink();
+        }
+    }
+
+    /// Linked list base address (upper 16 address bits).
+    pub fn base_address(&self) -> u16 {
+        ((&raw const self.items as u32) >> 16) as _
+    }
+
+    /// Linked list offset address (lower 16 address bits) at the selected index.
+    pub fn offset_address(&self, index: usize) -> u16 {
+        assert!(self.items.len() > index);
+
+        let address = &raw const self.items[index] as _;
+
+        // Ensure 32 bit address alignment.
+        assert_eq!(address & 0b11, 0);
+
+        address
+    }
+}
diff --git a/embassy-stm32/src/dma/gpdma/mod.rs b/embassy-stm32/src/dma/gpdma/mod.rs
new file mode 100644
index 000000000..4a14c2a8e
--- /dev/null
+++ b/embassy-stm32/src/dma/gpdma/mod.rs
@@ -0,0 +1,699 @@
+#![macro_use]
+
+use core::future::Future;
+use core::pin::Pin;
+use core::sync::atomic::{fence, AtomicUsize, Ordering};
+use core::task::{Context, Poll};
+
+use embassy_hal_internal::Peri;
+use embassy_sync::waitqueue::AtomicWaker;
+use linked_list::Table;
+
+use super::word::{Word, WordSize};
+use super::{AnyChannel, Channel, Dir, Request, STATE};
+use crate::interrupt::typelevel::Interrupt;
+use crate::pac;
+use crate::pac::gpdma::vals;
+
+pub mod linked_list;
+pub mod ringbuffered;
+
+pub(crate) struct ChannelInfo {
+    pub(crate) dma: pac::gpdma::Gpdma,
+    pub(crate) num: usize,
+    #[cfg(feature = "_dual-core")]
+    pub(crate) irq: pac::Interrupt,
+}
+
+/// DMA request priority
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Priority {
+    /// Low Priority
+    Low,
+    /// Medium Priority
+    Medium,
+    /// High Priority
+    High,
+    /// Very High Priority
+    VeryHigh,
+}
+
+impl From<Priority> for pac::gpdma::vals::Prio {
+    fn from(value: Priority) -> Self {
+        match value {
+            Priority::Low => pac::gpdma::vals::Prio::LOW_WITH_LOWH_WEIGHT,
+            Priority::Medium => pac::gpdma::vals::Prio::LOW_WITH_MID_WEIGHT,
+            Priority::High => pac::gpdma::vals::Prio::LOW_WITH_HIGH_WEIGHT,
+            Priority::VeryHigh => pac::gpdma::vals::Prio::HIGH,
+        }
+    }
+}
+
+/// GPDMA transfer options.
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[non_exhaustive]
+pub struct TransferOptions {
+    /// Request priority level.
+    pub priority: Priority,
+    /// Enable half transfer interrupt.
+    pub half_transfer_ir: bool,
+    /// Enable transfer complete interrupt.
+    pub complete_transfer_ir: bool,
+}
+
+impl Default for TransferOptions {
+    fn default() -> Self {
+        Self {
+            priority: Priority::VeryHigh,
+            half_transfer_ir: false,
+            complete_transfer_ir: true,
+        }
+    }
+}
+
+impl From<WordSize> for vals::Dw {
+    fn from(raw: WordSize) -> Self {
+        match raw {
+            WordSize::OneByte => Self::BYTE,
+            WordSize::TwoBytes => Self::HALF_WORD,
+            WordSize::FourBytes => Self::WORD,
+        }
+    }
+}
+
+impl From<vals::Dw> for WordSize {
+    fn from(raw: vals::Dw) -> Self {
+        match raw {
+            vals::Dw::BYTE => Self::OneByte,
+            vals::Dw::HALF_WORD => Self::TwoBytes,
+            vals::Dw::WORD => Self::FourBytes,
+            _ => panic!("Invalid word size"),
+        }
+    }
+}
+
+pub(crate) struct LLiState {
+    /// The number of linked-list items.
+    count: AtomicUsize,
+    /// The index of the current linked-list item.
+    index: AtomicUsize,
+    /// The total transfer count of all linked-list items in number of words.
+    transfer_count: AtomicUsize,
+}
+
+pub(crate) struct ChannelState {
+    waker: AtomicWaker,
+    complete_count: AtomicUsize,
+    lli_state: LLiState,
+}
+
+impl ChannelState {
+    pub(crate) const NEW: Self = Self {
+        waker: AtomicWaker::new(),
+        complete_count: AtomicUsize::new(0),
+
+        lli_state: LLiState {
+            count: AtomicUsize::new(0),
+            index: AtomicUsize::new(0),
+            transfer_count: AtomicUsize::new(0),
+        },
+    };
+}
+
+/// safety: must be called only once
+pub(crate) unsafe fn init(cs: critical_section::CriticalSection, irq_priority: crate::interrupt::Priority) {
+    foreach_interrupt! {
+        ($peri:ident, gpdma, $block:ident, $signal_name:ident, $irq:ident) => {
+            crate::interrupt::typelevel::$irq::set_priority_with_cs(cs, irq_priority);
+            #[cfg(not(feature = "_dual-core"))]
+            crate::interrupt::typelevel::$irq::enable();
+        };
+    }
+    crate::_generated::init_gpdma();
+}
+
+impl AnyChannel {
+    /// Safety: Must be called with a matching set of parameters for a valid dma channel
+    pub(crate) unsafe fn on_irq(&self) {
+        let info = self.info();
+        #[cfg(feature = "_dual-core")]
+        {
+            use embassy_hal_internal::interrupt::InterruptExt as _;
+            info.irq.enable();
+        }
+
+        let state = &STATE[self.id as usize];
+
+        let ch = info.dma.ch(info.num);
+        let sr = ch.sr().read();
+
+        if sr.dtef() {
+            panic!(
+                "DMA: data transfer error on DMA@{:08x} channel {}",
+                info.dma.as_ptr() as u32,
+                info.num
+            );
+        }
+        if sr.usef() {
+            panic!(
+                "DMA: user settings error on DMA@{:08x} channel {}",
+                info.dma.as_ptr() as u32,
+                info.num
+            );
+        }
+        if sr.ulef() {
+            panic!(
+                "DMA: link transfer error on DMA@{:08x} channel {}",
+                info.dma.as_ptr() as u32,
+                info.num
+            );
+        }
+
+        if sr.htf() {
+            ch.fcr().write(|w| w.set_htf(true));
+        }
+
+        if sr.tcf() {
+            ch.fcr().write(|w| w.set_tcf(true));
+
+            let lli_count = state.lli_state.count.load(Ordering::Acquire);
+            let complete = if lli_count > 0 {
+                let next_lli_index = state.lli_state.index.load(Ordering::Acquire) + 1;
+                let complete = next_lli_index >= lli_count;
+
+                state
+                    .lli_state
+                    .index
+                    .store(if complete { 0 } else { next_lli_index }, Ordering::Release);
+
+                complete
+            } else {
+                true
+            };
+
+            if complete {
+                state.complete_count.fetch_add(1, Ordering::Release);
+            }
+        }
+
+        if sr.suspf() {
+            // Disable all xxIEs to prevent the irq from firing again.
+            ch.cr().write(|_| {});
+        }
+        state.waker.wake();
+    }
+
+    fn get_remaining_transfers(&self) -> u16 {
+        let info = self.info();
+        let ch = info.dma.ch(info.num);
+        let word_size: WordSize = ch.tr1().read().ddw().into();
+
+        ch.br1().read().bndt() / word_size.bytes() as u16
+    }
+
+    unsafe fn configure(
+        &self,
+        request: Request,
+        dir: Dir,
+        peri_addr: *const u32,
+        mem_addr: *mut u32,
+        mem_len: usize,
+        incr_mem: bool,
+        data_size: WordSize,
+        dst_size: WordSize,
+        options: TransferOptions,
+    ) {
+        // BNDT is specified as bytes, not as number of transfers.
+        let Ok(bndt) = (mem_len * data_size.bytes()).try_into() else {
+            panic!("DMA transfers may not be larger than 65535 bytes.");
+        };
+
+        let info = self.info();
+        let ch = info.dma.ch(info.num);
+
+        // "Preceding reads and writes cannot be moved past subsequent writes."
+        fence(Ordering::SeqCst);
+
+        ch.cr().write(|w| w.set_reset(true));
+        ch.fcr().write(|w| {
+            // Clear all irqs
+            w.set_dtef(true);
+            w.set_htf(true);
+            w.set_suspf(true);
+            w.set_tcf(true);
+            w.set_tof(true);
+            w.set_ulef(true);
+            w.set_usef(true);
+        });
+        ch.llr().write(|_| {}); // no linked list
+        ch.tr1().write(|w| {
+            w.set_sdw(data_size.into());
+            w.set_ddw(dst_size.into());
+            w.set_sinc(dir == Dir::MemoryToPeripheral && incr_mem);
+            w.set_dinc(dir == Dir::PeripheralToMemory && incr_mem);
+        });
+        ch.tr2().write(|w| {
+            w.set_dreq(match dir {
+                Dir::MemoryToPeripheral => vals::Dreq::DESTINATION_PERIPHERAL,
+                Dir::PeripheralToMemory => vals::Dreq::SOURCE_PERIPHERAL,
+            });
+            w.set_reqsel(request);
+        });
+        ch.tr3().write(|_| {}); // no address offsets.
+        ch.br1().write(|w| w.set_bndt(bndt));
+
+        match dir {
+            Dir::MemoryToPeripheral => {
+                ch.sar().write_value(mem_addr as _);
+                ch.dar().write_value(peri_addr as _);
+            }
+            Dir::PeripheralToMemory => {
+                ch.sar().write_value(peri_addr as _);
+                ch.dar().write_value(mem_addr as _);
+            }
+        }
+
+        ch.cr().write(|w| {
+            w.set_prio(options.priority.into());
+            w.set_htie(options.half_transfer_ir);
+            w.set_tcie(options.complete_transfer_ir);
+            w.set_useie(true);
+            w.set_dteie(true);
+            w.set_suspie(true);
+        });
+
+        let state = &STATE[self.id as usize];
+        state.lli_state.count.store(0, Ordering::Relaxed);
+        state.lli_state.index.store(0, Ordering::Relaxed);
+        state.lli_state.transfer_count.store(0, Ordering::Relaxed)
+    }
+
+    /// Configure a linked-list transfer.
+    unsafe fn configure_linked_list<const ITEM_COUNT: usize>(
+        &self,
+        table: &Table<ITEM_COUNT>,
+        options: TransferOptions,
+    ) {
+        let info = self.info();
+        let ch = info.dma.ch(info.num);
+
+        // "Preceding reads and writes cannot be moved past subsequent writes."
+        fence(Ordering::SeqCst);
+
+        ch.cr().write(|w| w.set_reset(true));
+        ch.fcr().write(|w| {
+            // Clear all irqs
+            w.set_dtef(true);
+            w.set_htf(true);
+            w.set_suspf(true);
+            w.set_tcf(true);
+            w.set_tof(true);
+            w.set_ulef(true);
+            w.set_usef(true);
+        });
+        ch.lbar().write(|reg| reg.set_lba(table.base_address()));
+
+        // Empty LLI0.
+        ch.br1().write(|w| w.set_bndt(0));
+
+        // Enable all linked-list field updates.
+        ch.llr().write(|w| {
+            w.set_ut1(true);
+            w.set_ut2(true);
+            w.set_ub1(true);
+            w.set_usa(true);
+            w.set_uda(true);
+            w.set_ull(true);
+
+            // Lower two bits are ignored: 32 bit aligned.
+            w.set_la(table.offset_address(0) >> 2);
+        });
+
+        ch.tr3().write(|_| {}); // no address offsets.
+
+        ch.cr().write(|w| {
+            w.set_prio(options.priority.into());
+            w.set_htie(options.half_transfer_ir);
+            w.set_tcie(options.complete_transfer_ir);
+            w.set_useie(true);
+            w.set_uleie(true);
+            w.set_dteie(true);
+            w.set_suspie(true);
+        });
+
+        let state = &STATE[self.id as usize];
+        state.lli_state.count.store(ITEM_COUNT, Ordering::Relaxed);
+        state.lli_state.index.store(0, Ordering::Relaxed);
+        state
+            .lli_state
+            .transfer_count
+            .store(table.transfer_count(), Ordering::Relaxed)
+    }
+
+    fn start(&self) {
+        let info = self.info();
+        let ch = info.dma.ch(info.num);
+
+        ch.cr().modify(|w| w.set_en(true));
+    }
+
+    fn request_pause(&self) {
+        let info = self.info();
+        let ch = info.dma.ch(info.num);
+
+        ch.cr().modify(|w| w.set_susp(true))
+    }
+
+    fn request_resume(&self) {
+        let info = self.info();
+        let ch = info.dma.ch(info.num);
+
+        ch.cr().modify(|w| w.set_susp(false));
+    }
+
+    fn request_reset(&self) {
+        let info = self.info();
+        let ch = info.dma.ch(info.num);
+
+        self.request_pause();
+        while self.is_running() {}
+
+        ch.cr().modify(|w| w.set_reset(true));
+    }
+
+    fn is_running(&self) -> bool {
+        let info = self.info();
+        let ch = info.dma.ch(info.num);
+
+        let sr = ch.sr().read();
+
+        !sr.suspf() && !sr.idlef()
+    }
+
+    fn poll_stop(&self) -> Poll<()> {
+        use core::sync::atomic::compiler_fence;
+        compiler_fence(Ordering::SeqCst);
+
+        if !self.is_running() {
+            Poll::Ready(())
+        } else {
+            Poll::Pending
+        }
+    }
+}
+
+/// Linked-list DMA transfer.
+#[must_use = "futures do nothing unless you `.await` or poll them"]
+pub struct LinkedListTransfer<'a, const ITEM_COUNT: usize> {
+    channel: Peri<'a, AnyChannel>,
+}
+
+impl<'a, const ITEM_COUNT: usize> LinkedListTransfer<'a, ITEM_COUNT> {
+    /// Create a new linked-list transfer.
+    pub unsafe fn new_linked_list<const N: usize>(
+        channel: Peri<'a, impl Channel>,
+        table: Table<ITEM_COUNT>,
+        options: TransferOptions,
+    ) -> Self {
+        Self::new_inner_linked_list(channel.into(), table, options)
+    }
+
+    unsafe fn new_inner_linked_list(
+        channel: Peri<'a, AnyChannel>,
+        table: Table<ITEM_COUNT>,
+        options: TransferOptions,
+    ) -> Self {
+        channel.configure_linked_list(&table, options);
+        channel.start();
+
+        Self { channel }
+    }
+
+    /// Request the transfer to pause, keeping the existing configuration for this channel.
+    ///
+    /// To resume the transfer, call [`request_resume`](Self::request_resume) again.
+    /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
+    pub fn request_pause(&mut self) {
+        self.channel.request_pause()
+    }
+
+    /// Request the transfer to resume after having been paused.
+    pub fn request_resume(&mut self) {
+        self.channel.request_resume()
+    }
+
+    /// Request the DMA to reset.
+    ///
+    /// The configuration for this channel will **not be preserved**. If you need to restart the transfer
+    /// at a later point with the same configuration, see [`request_pause`](Self::request_pause) instead.
+    pub fn request_reset(&mut self) {
+        self.channel.request_reset()
+    }
+
+    /// Return whether this transfer is still running.
+    ///
+    /// If this returns `false`, it can be because either the transfer finished, or
+    /// it was requested to stop early with [`request_pause`](Self::request_pause).
+    pub fn is_running(&mut self) -> bool {
+        self.channel.is_running()
+    }
+
+    /// Gets the total remaining transfers for the channel
+    /// Note: this will be zero for transfers that completed without cancellation.
+    pub fn get_remaining_transfers(&self) -> u16 {
+        self.channel.get_remaining_transfers()
+    }
+
+    /// Blocking wait until the transfer finishes.
+    pub fn blocking_wait(mut self) {
+        while self.is_running() {}
+
+        // "Subsequent reads and writes cannot be moved ahead of preceding reads."
+        fence(Ordering::SeqCst);
+
+        core::mem::forget(self);
+    }
+}
+
+impl<'a, const ITEM_COUNT: usize> Drop for LinkedListTransfer<'a, ITEM_COUNT> {
+    fn drop(&mut self) {
+        self.request_reset();
+
+        // "Subsequent reads and writes cannot be moved ahead of preceding reads."
+        fence(Ordering::SeqCst);
+    }
+}
+
+impl<'a, const ITEM_COUNT: usize> Unpin for LinkedListTransfer<'a, ITEM_COUNT> {}
+impl<'a, const ITEM_COUNT: usize> Future for LinkedListTransfer<'a, ITEM_COUNT> {
+    type Output = ();
+    fn poll(mut self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
+        let state = &STATE[self.channel.id as usize];
+        state.waker.register(cx.waker());
+
+        if self.is_running() {
+            Poll::Pending
+        } else {
+            Poll::Ready(())
+        }
+    }
+}
+
+/// DMA transfer.
+#[must_use = "futures do nothing unless you `.await` or poll them"]
+pub struct Transfer<'a> {
+    channel: Peri<'a, AnyChannel>,
+}
+
+impl<'a> Transfer<'a> {
+    /// Create a new read DMA transfer (peripheral to memory).
+    pub unsafe fn new_read<W: Word>(
+        channel: Peri<'a, impl Channel>,
+        request: Request,
+        peri_addr: *mut W,
+        buf: &'a mut [W],
+        options: TransferOptions,
+    ) -> Self {
+        Self::new_read_raw(channel, request, peri_addr, buf, options)
+    }
+
+    /// Create a new read DMA transfer (peripheral to memory), using raw pointers.
+    pub unsafe fn new_read_raw<MW: Word, PW: Word>(
+        channel: Peri<'a, impl Channel>,
+        request: Request,
+        peri_addr: *mut PW,
+        buf: *mut [MW],
+        options: TransferOptions,
+    ) -> Self {
+        Self::new_inner(
+            channel.into(),
+            request,
+            Dir::PeripheralToMemory,
+            peri_addr as *const u32,
+            buf as *mut MW as *mut u32,
+            buf.len(),
+            true,
+            PW::size(),
+            MW::size(),
+            options,
+        )
+    }
+
+    /// Create a new write DMA transfer (memory to peripheral).
+    pub unsafe fn new_write<MW: Word, PW: Word>(
+        channel: Peri<'a, impl Channel>,
+        request: Request,
+        buf: &'a [MW],
+        peri_addr: *mut PW,
+        options: TransferOptions,
+    ) -> Self {
+        Self::new_write_raw(channel, request, buf, peri_addr, options)
+    }
+
+    /// Create a new write DMA transfer (memory to peripheral), using raw pointers.
+    pub unsafe fn new_write_raw<MW: Word, PW: Word>(
+        channel: Peri<'a, impl Channel>,
+        request: Request,
+        buf: *const [MW],
+        peri_addr: *mut PW,
+        options: TransferOptions,
+    ) -> Self {
+        Self::new_inner(
+            channel.into(),
+            request,
+            Dir::MemoryToPeripheral,
+            peri_addr as *const u32,
+            buf as *const MW as *mut u32,
+            buf.len(),
+            true,
+            MW::size(),
+            PW::size(),
+            options,
+        )
+    }
+
+    /// Create a new write DMA transfer (memory to peripheral), writing the same value repeatedly.
+    pub unsafe fn new_write_repeated<MW: Word, PW: Word>(
+        channel: Peri<'a, impl Channel>,
+        request: Request,
+        repeated: &'a MW,
+        count: usize,
+        peri_addr: *mut PW,
+        options: TransferOptions,
+    ) -> Self {
+        Self::new_inner(
+            channel.into(),
+            request,
+            Dir::MemoryToPeripheral,
+            peri_addr as *const u32,
+            repeated as *const MW as *mut u32,
+            count,
+            false,
+            MW::size(),
+            PW::size(),
+            options,
+        )
+    }
+
+    unsafe fn new_inner(
+        channel: Peri<'a, AnyChannel>,
+        request: Request,
+        dir: Dir,
+        peri_addr: *const u32,
+        mem_addr: *mut u32,
+        mem_len: usize,
+        incr_mem: bool,
+        data_size: WordSize,
+        peripheral_size: WordSize,
+        options: TransferOptions,
+    ) -> Self {
+        assert!(mem_len > 0 && mem_len <= 0xFFFF);
+
+        channel.configure(
+            request,
+            dir,
+            peri_addr,
+            mem_addr,
+            mem_len,
+            incr_mem,
+            data_size,
+            peripheral_size,
+            options,
+        );
+        channel.start();
+
+        Self { channel }
+    }
+
+    /// Request the transfer to pause, keeping the existing configuration for this channel.
+    /// To restart the transfer, call [`start`](Self::start) again.
+    ///
+    /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
+    pub fn request_pause(&mut self) {
+        self.channel.request_pause()
+    }
+
+    /// Request the transfer to resume after being suspended.
+    pub fn request_resume(&mut self) {
+        self.channel.request_resume()
+    }
+
+    /// Request the DMA to reset.
+    ///
+    /// The configuration for this channel will **not be preserved**. If you need to restart the transfer
+    /// at a later point with the same configuration, see [`request_pause`](Self::request_pause) instead.
+    pub fn request_reset(&mut self) {
+        self.channel.request_reset()
+    }
+
+    /// Return whether this transfer is still running.
+    ///
+    /// If this returns `false`, it can be because either the transfer finished, or
+    /// it was requested to stop early with [`request_pause`](Self::request_pause).
+    pub fn is_running(&mut self) -> bool {
+        self.channel.is_running()
+    }
+
+    /// Gets the total remaining transfers for the channel
+    /// Note: this will be zero for transfers that completed without cancellation.
+    pub fn get_remaining_transfers(&self) -> u16 {
+        self.channel.get_remaining_transfers()
+    }
+
+    /// Blocking wait until the transfer finishes.
+    pub fn blocking_wait(mut self) {
+        while self.is_running() {}
+
+        // "Subsequent reads and writes cannot be moved ahead of preceding reads."
+        fence(Ordering::SeqCst);
+
+        core::mem::forget(self);
+    }
+}
+
+impl<'a> Drop for Transfer<'a> {
+    fn drop(&mut self) {
+        self.request_pause();
+        while self.is_running() {}
+
+        // "Subsequent reads and writes cannot be moved ahead of preceding reads."
+        fence(Ordering::SeqCst);
+    }
+}
+
+impl<'a> Unpin for Transfer<'a> {}
+impl<'a> Future for Transfer<'a> {
+    type Output = ();
+    fn poll(mut self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
+        let state = &STATE[self.channel.id as usize];
+        state.waker.register(cx.waker());
+
+        if self.is_running() {
+            Poll::Pending
+        } else {
+            Poll::Ready(())
+        }
+    }
+}
diff --git a/embassy-stm32/src/dma/gpdma/ringbuffered.rs b/embassy-stm32/src/dma/gpdma/ringbuffered.rs
new file mode 100644
index 000000000..9ee52193b
--- /dev/null
+++ b/embassy-stm32/src/dma/gpdma/ringbuffered.rs
@@ -0,0 +1,332 @@
+//! GPDMA ring buffer implementation.
+//!
+//! FIXME: Add request_pause functionality?
+//! FIXME: Stop the DMA, if a user does not queue new transfers (chain of linked-list items ends automatically).
+use core::future::poll_fn;
+use core::sync::atomic::{fence, Ordering};
+use core::task::Waker;
+
+use embassy_hal_internal::Peri;
+
+use super::{AnyChannel, TransferOptions, STATE};
+use crate::dma::gpdma::linked_list::{RunMode, Table};
+use crate::dma::ringbuffer::{DmaCtrl, Error, ReadableDmaRingBuffer, WritableDmaRingBuffer};
+use crate::dma::word::Word;
+use crate::dma::{Channel, Dir, Request};
+
+struct DmaCtrlImpl<'a>(Peri<'a, AnyChannel>);
+
+impl<'a> DmaCtrl for DmaCtrlImpl<'a> {
+    fn get_remaining_transfers(&self) -> usize {
+        let state = &STATE[self.0.id as usize];
+        let current_remaining = self.0.get_remaining_transfers() as usize;
+
+        let lli_count = state.lli_state.count.load(Ordering::Acquire);
+
+        if lli_count > 0 {
+            // In linked-list mode, the remaining transfers are the sum of the full lengths of LLIs that follow,
+            // and the remaining transfers for the current LLI.
+            let lli_index = state.lli_state.index.load(Ordering::Acquire);
+            let single_transfer_count = state.lli_state.transfer_count.load(Ordering::Acquire) / lli_count;
+
+            (lli_count - lli_index - 1) * single_transfer_count + current_remaining
+        } else {
+            // No linked-list mode.
+            current_remaining
+        }
+    }
+
+    fn reset_complete_count(&mut self) -> usize {
+        let state = &STATE[self.0.id as usize];
+
+        state.complete_count.swap(0, Ordering::AcqRel)
+    }
+
+    fn set_waker(&mut self, waker: &Waker) {
+        STATE[self.0.id as usize].waker.register(waker);
+    }
+}
+
+/// Ringbuffer for receiving data using GPDMA linked-list mode.
+pub struct ReadableRingBuffer<'a, W: Word> {
+    channel: Peri<'a, AnyChannel>,
+    ringbuf: ReadableDmaRingBuffer<'a, W>,
+    table: Table<2>,
+    options: TransferOptions,
+}
+
+impl<'a, W: Word> ReadableRingBuffer<'a, W> {
+    /// Create a new ring buffer.
+    ///
+    /// Transfer options are applied to the individual linked list items.
+    pub unsafe fn new(
+        channel: Peri<'a, impl Channel>,
+        request: Request,
+        peri_addr: *mut W,
+        buffer: &'a mut [W],
+        options: TransferOptions,
+    ) -> Self {
+        let channel: Peri<'a, AnyChannel> = channel.into();
+        let table = Table::<2>::new_ping_pong::<W>(request, peri_addr, buffer, Dir::PeripheralToMemory);
+
+        Self {
+            channel,
+            ringbuf: ReadableDmaRingBuffer::new(buffer),
+            table,
+            options,
+        }
+    }
+
+    /// Start the ring buffer operation.
+    pub fn start(&mut self) {
+        // Apply the default configuration to the channel.
+        unsafe { self.channel.configure_linked_list(&self.table, self.options) };
+        self.table.link(RunMode::Circular);
+        self.channel.start();
+    }
+
+    /// Clear all data in the ring buffer.
+    pub fn clear(&mut self) {
+        self.ringbuf.reset(&mut DmaCtrlImpl(self.channel.reborrow()));
+    }
+
+    /// Read elements from the ring buffer
+    /// Return a tuple of the length read and the length remaining in the buffer
+    /// If not all of the elements were read, then there will be some elements in the buffer remaining
+    /// The length remaining is the capacity, ring_buf.len(), less the elements remaining after the read
+    /// Error is returned if the portion to be read was overwritten by the DMA controller.
+    pub fn read(&mut self, buf: &mut [W]) -> Result<(usize, usize), Error> {
+        self.ringbuf.read(&mut DmaCtrlImpl(self.channel.reborrow()), buf)
+    }
+
+    /// Read an exact number of elements from the ringbuffer.
+    ///
+    /// Returns the remaining number of elements available for immediate reading.
+    /// Error is returned if the portion to be read was overwritten by the DMA controller.
+    ///
+    /// Async/Wake Behavior:
+    /// The underlying DMA peripheral only can wake us when its buffer pointer has reached the halfway point,
+    /// and when it wraps around. This means that when called with a buffer of length 'M', when this
+    /// ring buffer was created with a buffer of size 'N':
+    /// - If M equals N/2 or N/2 divides evenly into M, this function will return every N/2 elements read on the DMA source.
+    /// - Otherwise, this function may need up to N/2 extra elements to arrive before returning.
+    pub async fn read_exact(&mut self, buffer: &mut [W]) -> Result<usize, Error> {
+        self.ringbuf
+            .read_exact(&mut DmaCtrlImpl(self.channel.reborrow()), buffer)
+            .await
+    }
+
+    /// The current length of the ringbuffer
+    pub fn len(&mut self) -> Result<usize, Error> {
+        Ok(self.ringbuf.len(&mut DmaCtrlImpl(self.channel.reborrow()))?)
+    }
+
+    /// The capacity of the ringbuffer
+    pub const fn capacity(&self) -> usize {
+        self.ringbuf.cap()
+    }
+
+    /// Set a waker to be woken when at least one byte is received.
+    pub fn set_waker(&mut self, waker: &Waker) {
+        DmaCtrlImpl(self.channel.reborrow()).set_waker(waker);
+    }
+
+    /// Request the transfer to pause, keeping the existing configuration for this channel.
+    ///
+    /// To resume the transfer, call [`request_resume`](Self::request_resume) again.
+    /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
+    pub fn request_pause(&mut self) {
+        self.channel.request_pause()
+    }
+
+    /// Request the transfer to resume after having been paused.
+    pub fn request_resume(&mut self) {
+        self.channel.request_resume()
+    }
+
+    /// Request the DMA to reset.
+    ///
+    /// The configuration for this channel will **not be preserved**. If you need to restart the transfer
+    /// at a later point with the same configuration, see [`request_pause`](Self::request_pause) instead.
+    pub fn request_reset(&mut self) {
+        self.channel.request_reset()
+    }
+
+    /// Return whether this transfer is still running.
+    ///
+    /// If this returns `false`, it can be because either the transfer finished, or
+    /// it was requested to stop early with [`request_pause`](Self::request_pause).
+    pub fn is_running(&mut self) -> bool {
+        self.channel.is_running()
+    }
+
+    /// Stop the DMA transfer and await until the buffer is full.
+    ///
+    /// This disables the DMA transfer's circular mode so that the transfer
+    /// stops when the buffer is full.
+    ///
+    /// This is designed to be used with streaming input data such as the
+    /// I2S/SAI or ADC.
+    pub async fn stop(&mut self) {
+        // wait until cr.susp reads as true
+        poll_fn(|cx| {
+            self.set_waker(cx.waker());
+            self.channel.poll_stop()
+        })
+        .await
+    }
+}
+
+impl<'a, W: Word> Drop for ReadableRingBuffer<'a, W> {
+    fn drop(&mut self) {
+        self.request_pause();
+        while self.is_running() {}
+
+        // "Subsequent reads and writes cannot be moved ahead of preceding reads."
+        fence(Ordering::SeqCst);
+    }
+}
+
+/// Ringbuffer for writing data using GPDMA linked-list mode.
+pub struct WritableRingBuffer<'a, W: Word> {
+    channel: Peri<'a, AnyChannel>,
+    ringbuf: WritableDmaRingBuffer<'a, W>,
+    table: Table<2>,
+    options: TransferOptions,
+}
+
+impl<'a, W: Word> WritableRingBuffer<'a, W> {
+    /// Create a new ring buffer.
+    ///
+    /// Transfer options are applied to the individual linked list items.
+    pub unsafe fn new(
+        channel: Peri<'a, impl Channel>,
+        request: Request,
+        peri_addr: *mut W,
+        buffer: &'a mut [W],
+        options: TransferOptions,
+    ) -> Self {
+        let channel: Peri<'a, AnyChannel> = channel.into();
+        let table = Table::<2>::new_ping_pong::<W>(request, peri_addr, buffer, Dir::MemoryToPeripheral);
+
+        Self {
+            channel,
+            ringbuf: WritableDmaRingBuffer::new(buffer),
+            table,
+            options,
+        }
+    }
+
+    /// Start the ring buffer operation.
+    pub fn start(&mut self) {
+        // Apply the default configuration to the channel.
+        unsafe { self.channel.configure_linked_list(&self.table, self.options) };
+        self.table.link(RunMode::Circular);
+
+        self.channel.start();
+    }
+
+    /// Clear all data in the ring buffer.
+    pub fn clear(&mut self) {
+        self.ringbuf.reset(&mut DmaCtrlImpl(self.channel.reborrow()));
+    }
+
+    /// Write elements directly to the raw buffer.
+    /// This can be used to fill the buffer before starting the DMA transfer.
+    pub fn write_immediate(&mut self, buf: &[W]) -> Result<(usize, usize), Error> {
+        self.ringbuf.write_immediate(buf)
+    }
+
+    /// Write elements from the ring buffer
+    /// Return a tuple of the length written and the length remaining in the buffer
+    pub fn write(&mut self, buf: &[W]) -> Result<(usize, usize), Error> {
+        self.ringbuf.write(&mut DmaCtrlImpl(self.channel.reborrow()), buf)
+    }
+
+    /// Write an exact number of elements to the ringbuffer.
+    pub async fn write_exact(&mut self, buffer: &[W]) -> Result<usize, Error> {
+        self.ringbuf
+            .write_exact(&mut DmaCtrlImpl(self.channel.reborrow()), buffer)
+            .await
+    }
+
+    /// Wait for any ring buffer write error.
+    pub async fn wait_write_error(&mut self) -> Result<usize, Error> {
+        self.ringbuf
+            .wait_write_error(&mut DmaCtrlImpl(self.channel.reborrow()))
+            .await
+    }
+
+    /// The current length of the ringbuffer
+    pub fn len(&mut self) -> Result<usize, Error> {
+        Ok(self.ringbuf.len(&mut DmaCtrlImpl(self.channel.reborrow()))?)
+    }
+
+    /// The capacity of the ringbuffer
+    pub const fn capacity(&self) -> usize {
+        self.ringbuf.cap()
+    }
+
+    /// Set a waker to be woken when at least one byte is received.
+    pub fn set_waker(&mut self, waker: &Waker) {
+        DmaCtrlImpl(self.channel.reborrow()).set_waker(waker);
+    }
+
+    /// Request the DMA to suspend.
+    ///
+    /// To resume the transfer, call [`request_resume`](Self::request_resume) again.
+    ///
+    /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
+    pub fn request_pause(&mut self) {
+        self.channel.request_pause()
+    }
+
+    /// Request the DMA to resume transfers after being suspended.
+    pub fn request_resume(&mut self) {
+        self.channel.request_resume()
+    }
+
+    /// Request the DMA to reset.
+    ///
+    /// The configuration for this channel will **not be preserved**. If you need to restart the transfer
+    /// at a later point with the same configuration, see [`request_pause`](Self::request_pause) instead.
+    pub fn request_reset(&mut self) {
+        self.channel.request_reset()
+    }
+
+    /// Return whether DMA is still running.
+    ///
+    /// If this returns `false`, it can be because either the transfer finished, or
+    /// it was requested to stop early with [`request_stop`](Self::request_stop).
+    pub fn is_running(&mut self) -> bool {
+        self.channel.is_running()
+    }
+
+    /// Stop the DMA transfer and await until the buffer is full.
+    ///
+    /// This disables the DMA transfer's circular mode so that the transfer
+    /// stops when the buffer is full.
+    ///
+    /// This is designed to be used with streaming input data such as the
+    /// I2S/SAI or ADC.
+    ///
+    /// When using the UART, you probably want `request_stop()`.
+    pub async fn stop(&mut self) {
+        // wait until cr.susp reads as true
+        poll_fn(|cx| {
+            self.set_waker(cx.waker());
+            self.channel.poll_stop()
+        })
+        .await
+    }
+}
+
+impl<'a, W: Word> Drop for WritableRingBuffer<'a, W> {
+    fn drop(&mut self) {
+        self.request_pause();
+        while self.is_running() {}
+
+        // "Subsequent reads and writes cannot be moved ahead of preceding reads."
+        fence(Ordering::SeqCst);
+    }
+}
diff --git a/embassy-stm32/src/dma/mod.rs b/embassy-stm32/src/dma/mod.rs
index d3b070a6d..5989bfd7c 100644
--- a/embassy-stm32/src/dma/mod.rs
+++ b/embassy-stm32/src/dma/mod.rs
@@ -9,6 +9,8 @@ pub use dma_bdma::*;
 #[cfg(gpdma)]
 pub(crate) mod gpdma;
 #[cfg(gpdma)]
+pub use gpdma::ringbuffered::*;
+#[cfg(gpdma)]
 pub use gpdma::*;
 
 #[cfg(dmamux)]
@@ -26,10 +28,13 @@ use embassy_hal_internal::{impl_peripheral, PeripheralType};
 
 use crate::interrupt;
 
+/// The direction of a DMA transfer.
 #[derive(Debug, Copy, Clone, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
-enum Dir {
+pub enum Dir {
+    /// Transfer from memory to a peripheral.
     MemoryToPeripheral,
+    /// Transfer from a peripheral to memory.
     PeripheralToMemory,
 }
 
diff --git a/embassy-stm32/src/dma/ringbuffer/mod.rs b/embassy-stm32/src/dma/ringbuffer/mod.rs
index 44ea497fe..659ffa9e5 100644
--- a/embassy-stm32/src/dma/ringbuffer/mod.rs
+++ b/embassy-stm32/src/dma/ringbuffer/mod.rs
@@ -1,5 +1,3 @@
-#![cfg_attr(gpdma, allow(unused))]
-
 use core::future::poll_fn;
 use core::task::{Poll, Waker};
 
@@ -285,17 +283,20 @@ impl<'a, W: Word> WritableDmaRingBuffer<'a, W> {
     }
 
     /// Write an exact number of elements to the ringbuffer.
+    ///
+    /// Returns the remaining write capacity in the buffer.
+    #[allow(dead_code)]
     pub async fn write_exact(&mut self, dma: &mut impl DmaCtrl, buffer: &[W]) -> Result<usize, Error> {
-        let mut written_data = 0;
+        let mut written_len = 0;
         let buffer_len = buffer.len();
 
         poll_fn(|cx| {
             dma.set_waker(cx.waker());
 
-            match self.write(dma, &buffer[written_data..buffer_len]) {
+            match self.write(dma, &buffer[written_len..buffer_len]) {
                 Ok((len, remaining)) => {
-                    written_data += len;
-                    if written_data == buffer_len {
+                    written_len += len;
+                    if written_len == buffer_len {
                         Poll::Ready(Ok(remaining))
                     } else {
                         Poll::Pending
diff --git a/embassy-stm32/src/dsihost.rs b/embassy-stm32/src/dsihost.rs
index e97ccd9d0..deda956af 100644
--- a/embassy-stm32/src/dsihost.rs
+++ b/embassy-stm32/src/dsihost.rs
@@ -78,7 +78,7 @@ impl<'d, T: Instance> DsiHost<'d, T> {
         rcc::enable_and_reset::<T>();
 
         // Set Tearing Enable pin according to CubeMx example
-        te.set_as_af(te.af_num(), AfType::output(OutputType::PushPull, Speed::Low));
+        set_as_af!(te, AfType::output(OutputType::PushPull, Speed::Low));
         /*
                 T::regs().wcr().modify(|w| {
                     w.set_dsien(true);
diff --git a/embassy-stm32/src/eth/mod.rs b/embassy-stm32/src/eth/mod.rs
index 97d7b4347..10b3a0517 100644
--- a/embassy-stm32/src/eth/mod.rs
+++ b/embassy-stm32/src/eth/mod.rs
@@ -209,19 +209,19 @@ impl SealedInstance for crate::peripherals::ETH {
 }
 impl Instance for crate::peripherals::ETH {}
 
-pin_trait!(RXClkPin, Instance);
-pin_trait!(TXClkPin, Instance);
-pin_trait!(RefClkPin, Instance);
-pin_trait!(MDIOPin, Instance);
-pin_trait!(MDCPin, Instance);
-pin_trait!(RXDVPin, Instance);
-pin_trait!(CRSPin, Instance);
-pin_trait!(RXD0Pin, Instance);
-pin_trait!(RXD1Pin, Instance);
-pin_trait!(RXD2Pin, Instance);
-pin_trait!(RXD3Pin, Instance);
-pin_trait!(TXD0Pin, Instance);
-pin_trait!(TXD1Pin, Instance);
-pin_trait!(TXD2Pin, Instance);
-pin_trait!(TXD3Pin, Instance);
-pin_trait!(TXEnPin, Instance);
+pin_trait!(RXClkPin, Instance, @A);
+pin_trait!(TXClkPin, Instance, @A);
+pin_trait!(RefClkPin, Instance, @A);
+pin_trait!(MDIOPin, Instance, @A);
+pin_trait!(MDCPin, Instance, @A);
+pin_trait!(RXDVPin, Instance, @A);
+pin_trait!(CRSPin, Instance, @A);
+pin_trait!(RXD0Pin, Instance, @A);
+pin_trait!(RXD1Pin, Instance, @A);
+pin_trait!(RXD2Pin, Instance, @A);
+pin_trait!(RXD3Pin, Instance, @A);
+pin_trait!(TXD0Pin, Instance, @A);
+pin_trait!(TXD1Pin, Instance, @A);
+pin_trait!(TXD2Pin, Instance, @A);
+pin_trait!(TXD3Pin, Instance, @A);
+pin_trait!(TXEnPin, Instance, @A);
diff --git a/embassy-stm32/src/eth/v1/mod.rs b/embassy-stm32/src/eth/v1/mod.rs
index b9746231f..5be1c9739 100644
--- a/embassy-stm32/src/eth/v1/mod.rs
+++ b/embassy-stm32/src/eth/v1/mod.rs
@@ -69,7 +69,7 @@ macro_rules! config_in_pins {
         critical_section::with(|_| {
             $(
                 // TODO properly create a set_as_input function
-                $pin.set_as_af($pin.af_num(), AfType::input(Pull::None));
+                set_as_af!($pin, AfType::input(Pull::None));
             )*
         })
     }
@@ -80,7 +80,7 @@ macro_rules! config_af_pins {
     ($($pin:ident),*) => {
         critical_section::with(|_| {
             $(
-                $pin.set_as_af($pin.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
+                set_as_af!($pin, AfType::output(OutputType::PushPull, Speed::VeryHigh));
             )*
         })
     };
@@ -91,7 +91,7 @@ macro_rules! config_pins {
     ($($pin:ident),*) => {
         critical_section::with(|_| {
             $(
-                $pin.set_as_af($pin.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
+                set_as_af!($pin, AfType::output(OutputType::PushPull, Speed::VeryHigh));
             )*
         })
     };
@@ -99,19 +99,19 @@ macro_rules! config_pins {
 
 impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
     /// safety: the returned instance is not leak-safe
-    pub fn new<const TX: usize, const RX: usize>(
+    pub fn new<const TX: usize, const RX: usize, #[cfg(afio)] A>(
         queue: &'d mut PacketQueue<TX, RX>,
         peri: Peri<'d, T>,
         irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
-        ref_clk: Peri<'d, impl RefClkPin<T>>,
-        mdio: Peri<'d, impl MDIOPin<T>>,
-        mdc: Peri<'d, impl MDCPin<T>>,
-        crs: Peri<'d, impl CRSPin<T>>,
-        rx_d0: Peri<'d, impl RXD0Pin<T>>,
-        rx_d1: Peri<'d, impl RXD1Pin<T>>,
-        tx_d0: Peri<'d, impl TXD0Pin<T>>,
-        tx_d1: Peri<'d, impl TXD1Pin<T>>,
-        tx_en: Peri<'d, impl TXEnPin<T>>,
+        ref_clk: Peri<'d, if_afio!(impl RefClkPin<T, A>)>,
+        mdio: Peri<'d, if_afio!(impl MDIOPin<T, A>)>,
+        mdc: Peri<'d, if_afio!(impl MDCPin<T, A>)>,
+        crs: Peri<'d, if_afio!(impl CRSPin<T, A>)>,
+        rx_d0: Peri<'d, if_afio!(impl RXD0Pin<T, A>)>,
+        rx_d1: Peri<'d, if_afio!(impl RXD1Pin<T, A>)>,
+        tx_d0: Peri<'d, if_afio!(impl TXD0Pin<T, A>)>,
+        tx_d1: Peri<'d, if_afio!(impl TXD1Pin<T, A>)>,
+        tx_en: Peri<'d, if_afio!(impl TXEnPin<T, A>)>,
         phy: P,
         mac_addr: [u8; 6],
     ) -> Self {
@@ -289,24 +289,24 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
     }
 
     /// Create a new MII ethernet driver using 14 pins.
-    pub fn new_mii<const TX: usize, const RX: usize>(
+    pub fn new_mii<const TX: usize, const RX: usize, #[cfg(afio)] A>(
         queue: &'d mut PacketQueue<TX, RX>,
         peri: Peri<'d, T>,
         irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
-        rx_clk: Peri<'d, impl RXClkPin<T>>,
-        tx_clk: Peri<'d, impl TXClkPin<T>>,
-        mdio: Peri<'d, impl MDIOPin<T>>,
-        mdc: Peri<'d, impl MDCPin<T>>,
-        rxdv: Peri<'d, impl RXDVPin<T>>,
-        rx_d0: Peri<'d, impl RXD0Pin<T>>,
-        rx_d1: Peri<'d, impl RXD1Pin<T>>,
-        rx_d2: Peri<'d, impl RXD2Pin<T>>,
-        rx_d3: Peri<'d, impl RXD3Pin<T>>,
-        tx_d0: Peri<'d, impl TXD0Pin<T>>,
-        tx_d1: Peri<'d, impl TXD1Pin<T>>,
-        tx_d2: Peri<'d, impl TXD2Pin<T>>,
-        tx_d3: Peri<'d, impl TXD3Pin<T>>,
-        tx_en: Peri<'d, impl TXEnPin<T>>,
+        rx_clk: Peri<'d, if_afio!(impl RXClkPin<T, A>)>,
+        tx_clk: Peri<'d, if_afio!(impl TXClkPin<T, A>)>,
+        mdio: Peri<'d, if_afio!(impl MDIOPin<T, A>)>,
+        mdc: Peri<'d, if_afio!(impl MDCPin<T, A>)>,
+        rxdv: Peri<'d, if_afio!(impl RXDVPin<T, A>)>,
+        rx_d0: Peri<'d, if_afio!(impl RXD0Pin<T, A>)>,
+        rx_d1: Peri<'d, if_afio!(impl RXD1Pin<T, A>)>,
+        rx_d2: Peri<'d, if_afio!(impl RXD2Pin<T, A>)>,
+        rx_d3: Peri<'d, if_afio!(impl RXD3Pin<T, A>)>,
+        tx_d0: Peri<'d, if_afio!(impl TXD0Pin<T, A>)>,
+        tx_d1: Peri<'d, if_afio!(impl TXD1Pin<T, A>)>,
+        tx_d2: Peri<'d, if_afio!(impl TXD2Pin<T, A>)>,
+        tx_d3: Peri<'d, if_afio!(impl TXD3Pin<T, A>)>,
+        tx_en: Peri<'d, if_afio!(impl TXEnPin<T, A>)>,
         phy: P,
         mac_addr: [u8; 6],
     ) -> Self {
diff --git a/embassy-stm32/src/eth/v2/mod.rs b/embassy-stm32/src/eth/v2/mod.rs
index 034c5dd88..cf7a9901b 100644
--- a/embassy-stm32/src/eth/v2/mod.rs
+++ b/embassy-stm32/src/eth/v2/mod.rs
@@ -57,7 +57,7 @@ macro_rules! config_pins {
         critical_section::with(|_| {
             $(
                 // TODO: shouldn't some pins be configured as inputs?
-                $pin.set_as_af($pin.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
+                set_as_af!($pin, AfType::output(OutputType::PushPull, Speed::VeryHigh));
             )*
         })
     };
diff --git a/embassy-stm32/src/fmc.rs b/embassy-stm32/src/fmc.rs
index 71ca775cb..ff18a8bee 100644
--- a/embassy-stm32/src/fmc.rs
+++ b/embassy-stm32/src/fmc.rs
@@ -75,7 +75,7 @@ where
 macro_rules! config_pins {
     ($($pin:ident),*) => {
                 $(
-            $pin.set_as_af($pin.af_num(), AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up));
+            set_as_af!($pin, AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up));
         )*
     };
 }
diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs
index bb37c4194..5a8d23183 100644
--- a/embassy-stm32/src/gpio.rs
+++ b/embassy-stm32/src/gpio.rs
@@ -150,9 +150,13 @@ impl<'d> Flex<'d> {
     /// This puts the pin into the AF mode, with the requested number and AF type. This is
     /// completely unchecked, it can attach the pin to literally any peripheral, so use with care.
     #[inline]
-    pub fn set_as_af_unchecked(&mut self, af_num: u8, af_type: AfType) {
+    pub fn set_as_af_unchecked(&mut self, #[cfg(not(afio))] af_num: u8, af_type: AfType) {
         critical_section::with(|_| {
-            self.pin.set_as_af(af_num, af_type);
+            self.pin.set_as_af(
+                #[cfg(not(afio))]
+                af_num,
+                af_type,
+            );
         });
     }
 
@@ -588,7 +592,7 @@ impl AfType {
 
 #[inline(never)]
 #[cfg(gpio_v1)]
-fn set_as_af(pin_port: u8, _af_num: u8, af_type: AfType) {
+fn set_as_af(pin_port: u8, af_type: AfType) {
     let pin = unsafe { AnyPin::steal(pin_port) };
     let r = pin.block();
     let n = pin._pin() as usize;
@@ -710,6 +714,18 @@ fn get_pull(pin_port: u8) -> Pull {
     };
 }
 
+#[cfg(afio)]
+/// Holds the AFIO remap value for a peripheral's pin
+pub struct AfioRemap<const V: u8>;
+
+#[cfg(afio)]
+/// Holds the AFIO remap value for a peripheral's pin
+pub struct AfioRemapBool<const V: bool>;
+
+#[cfg(afio)]
+/// Placeholder for a peripheral's pin which cannot be remapped via AFIO.
+pub struct AfioRemapNotApplicable;
+
 pub(crate) trait SealedPin {
     fn pin_port(&self) -> u8;
 
@@ -743,8 +759,13 @@ pub(crate) trait SealedPin {
     }
 
     #[inline]
-    fn set_as_af(&self, af_num: u8, af_type: AfType) {
-        set_as_af(self.pin_port(), af_num, af_type)
+    fn set_as_af(&self, #[cfg(not(afio))] af_num: u8, af_type: AfType) {
+        set_as_af(
+            self.pin_port(),
+            #[cfg(not(afio))]
+            af_num,
+            af_type,
+        )
     }
 
     #[inline]
diff --git a/embassy-stm32/src/hrtim/mod.rs b/embassy-stm32/src/hrtim/mod.rs
index 1d0594125..6fece5eb2 100644
--- a/embassy-stm32/src/hrtim/mod.rs
+++ b/embassy-stm32/src/hrtim/mod.rs
@@ -79,10 +79,7 @@ macro_rules! advanced_channel_impl {
             pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>) -> Self {
                 critical_section::with(|_| {
                     pin.set_low();
-                    pin.set_as_af(
-                        pin.af_num(),
-                        AfType::output(OutputType::PushPull, Speed::VeryHigh),
-                    );
+                    set_as_af!(pin, AfType::output(OutputType::PushPull, Speed::VeryHigh));
                 });
                 PwmPin {
                     _pin: pin.into(),
@@ -96,10 +93,7 @@ macro_rules! advanced_channel_impl {
             pub fn $new_chx(pin: Peri<'d, impl $complementary_pin_trait<T>>) -> Self {
                 critical_section::with(|_| {
                     pin.set_low();
-                    pin.set_as_af(
-                        pin.af_num(),
-                        AfType::output(OutputType::PushPull, Speed::VeryHigh),
-                    );
+                    set_as_af!(pin, AfType::output(OutputType::PushPull, Speed::VeryHigh));
                 });
                 ComplementaryPwmPin {
                     _pin: pin.into(),
diff --git a/embassy-stm32/src/hspi/mod.rs b/embassy-stm32/src/hspi/mod.rs
index 62bc0e979..95d9e5099 100644
--- a/embassy-stm32/src/hspi/mod.rs
+++ b/embassy-stm32/src/hspi/mod.rs
@@ -86,6 +86,8 @@ impl Default for Config {
 }
 
 /// HSPI transfer configuration.
+#[derive(Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct TransferConfig {
     /// Instruction width (IMODE)
     pub iwidth: HspiWidth,
@@ -116,7 +118,7 @@ pub struct TransferConfig {
 
     /// Data width (DMODE)
     pub dwidth: HspiWidth,
-    /// Data buffer
+    /// Data Double Transfer rate enable
     pub ddtr: bool,
 
     /// Number of dummy cycles (DCYC)
@@ -395,11 +397,6 @@ impl<'d, T: Instance, M: PeriMode> Hspi<'d, T, M> {
         // Configure alternate bytes
         if let Some(ab) = command.alternate_bytes {
             T::REGS.abr().write(|v| v.set_alternate(ab));
-            T::REGS.ccr().modify(|w| {
-                w.set_abmode(command.abwidth.into());
-                w.set_abdtr(command.abdtr);
-                w.set_absize(command.absize.into());
-            })
         }
 
         // Configure dummy cycles
@@ -411,14 +408,14 @@ impl<'d, T: Instance, M: PeriMode> Hspi<'d, T, M> {
         if let Some(data_length) = data_len {
             T::REGS.dlr().write(|v| {
                 v.set_dl((data_length - 1) as u32);
-            })
+            });
         } else {
             T::REGS.dlr().write(|v| {
                 v.set_dl((0) as u32);
-            })
+            });
         }
 
-        // Configure instruction/address/data modes
+        // Configure instruction/address/alternate bytes/data modes
         T::REGS.ccr().modify(|w| {
             w.set_imode(command.iwidth.into());
             w.set_idtr(command.idtr);
@@ -428,6 +425,10 @@ impl<'d, T: Instance, M: PeriMode> Hspi<'d, T, M> {
             w.set_addtr(command.addtr);
             w.set_adsize(command.adsize.into());
 
+            w.set_abmode(command.abwidth.into());
+            w.set_abdtr(command.abdtr);
+            w.set_absize(command.absize.into());
+
             w.set_dmode(command.dwidth.into());
             w.set_ddtr(command.ddtr);
         });
diff --git a/embassy-stm32/src/i2c/mod.rs b/embassy-stm32/src/i2c/mod.rs
index 5fb49f943..249bac41c 100644
--- a/embassy-stm32/src/i2c/mod.rs
+++ b/embassy-stm32/src/i2c/mod.rs
@@ -149,10 +149,10 @@ pub struct I2c<'d, M: Mode, IM: MasterMode> {
 
 impl<'d> I2c<'d, Async, Master> {
     /// Create a new I2C driver.
-    pub fn new<T: Instance>(
+    pub fn new<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        scl: Peri<'d, impl SclPin<T>>,
-        sda: Peri<'d, impl SdaPin<T>>,
+        scl: Peri<'d, if_afio!(impl SclPin<T, A>)>,
+        sda: Peri<'d, if_afio!(impl SdaPin<T, A>)>,
         _irq: impl interrupt::typelevel::Binding<T::EventInterrupt, EventInterruptHandler<T>>
             + interrupt::typelevel::Binding<T::ErrorInterrupt, ErrorInterruptHandler<T>>
             + 'd,
@@ -173,10 +173,10 @@ impl<'d> I2c<'d, Async, Master> {
 
 impl<'d> I2c<'d, Blocking, Master> {
     /// Create a new blocking I2C driver.
-    pub fn new_blocking<T: Instance>(
+    pub fn new_blocking<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        scl: Peri<'d, impl SclPin<T>>,
-        sda: Peri<'d, impl SdaPin<T>>,
+        scl: Peri<'d, if_afio!(impl SclPin<T, A>)>,
+        sda: Peri<'d, if_afio!(impl SdaPin<T, A>)>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -296,8 +296,8 @@ peri_trait!(
     irqs: [EventInterrupt, ErrorInterrupt],
 );
 
-pin_trait!(SclPin, Instance);
-pin_trait!(SdaPin, Instance);
+pin_trait!(SclPin, Instance, @A);
+pin_trait!(SdaPin, Instance, @A);
 dma_trait!(RxDma, Instance);
 dma_trait!(TxDma, Instance);
 
diff --git a/embassy-stm32/src/i2c/v2.rs b/embassy-stm32/src/i2c/v2.rs
index 3b09f1b34..0bfc795ac 100644
--- a/embassy-stm32/src/i2c/v2.rs
+++ b/embassy-stm32/src/i2c/v2.rs
@@ -454,7 +454,8 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
                 // (START has been ACKed or last byte when
                 // through)
                 if let Err(err) = self.wait_txis(timeout) {
-                    if send_stop {
+                    if send_stop && err != Error::Nack {
+                        // STOP is sent automatically if a NACK was received
                         self.master_stop();
                     }
                     return Err(err);
@@ -548,7 +549,9 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
                     (idx != last_slice_index) || (slice_len > 255),
                     timeout,
                 ) {
-                    self.master_stop();
+                    if err != Error::Nack {
+                        self.master_stop();
+                    }
                     return Err(err);
                 }
             }
@@ -561,7 +564,9 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
                         (number != last_chunk_idx) || (idx != last_slice_index),
                         timeout,
                     ) {
-                        self.master_stop();
+                        if err != Error::Nack {
+                            self.master_stop();
+                        }
                         return Err(err);
                     }
                 }
@@ -571,7 +576,9 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
                     // (START has been ACKed or last byte when
                     // through)
                     if let Err(err) = self.wait_txis(timeout) {
-                        self.master_stop();
+                        if err != Error::Nack {
+                            self.master_stop();
+                        }
                         return Err(err);
                     }
 
@@ -1276,7 +1283,7 @@ impl<'d> I2c<'d, Async, MultiMaster> {
             } else if isr.stopf() {
                 self.info.regs.icr().write(|reg| reg.set_stopcf(true));
                 if remaining_len > 0 {
-                    dma_transfer.request_stop();
+                    dma_transfer.request_pause();
                     Poll::Ready(Ok(SendStatus::LeftoverBytes(remaining_len as usize)))
                 } else {
                     Poll::Ready(Ok(SendStatus::Done))
diff --git a/embassy-stm32/src/i2s.rs b/embassy-stm32/src/i2s.rs
index a51d21bb0..b6d3daf54 100644
--- a/embassy-stm32/src/i2s.rs
+++ b/embassy-stm32/src/i2s.rs
@@ -27,7 +27,8 @@ enum Function {
     Transmit,
     /// Receive audio data
     Receive,
-    #[cfg(spi_v3)]
+    #[cfg(any(spi_v4, spi_v5))]
+
     /// Transmit and Receive audio data
     FullDuplex,
 }
@@ -72,7 +73,6 @@ impl From<ringbuffer::Error> for Error {
 }
 
 impl Standard {
-    #[cfg(any(spi_v1, spi_v3, spi_f1))]
     const fn i2sstd(&self) -> vals::I2sstd {
         match self {
             Standard::Philips => vals::I2sstd::PHILIPS,
@@ -83,7 +83,6 @@ impl Standard {
         }
     }
 
-    #[cfg(any(spi_v1, spi_v3, spi_f1))]
     const fn pcmsync(&self) -> vals::Pcmsync {
         match self {
             Standard::PcmLongSync => vals::Pcmsync::LONG,
@@ -106,7 +105,6 @@ pub enum Format {
 }
 
 impl Format {
-    #[cfg(any(spi_v1, spi_v3, spi_f1))]
     const fn datlen(&self) -> vals::Datlen {
         match self {
             Format::Data16Channel16 => vals::Datlen::BITS16,
@@ -116,7 +114,6 @@ impl Format {
         }
     }
 
-    #[cfg(any(spi_v1, spi_v3, spi_f1))]
     const fn chlen(&self) -> vals::Chlen {
         match self {
             Format::Data16Channel16 => vals::Chlen::BITS16,
@@ -137,7 +134,6 @@ pub enum ClockPolarity {
 }
 
 impl ClockPolarity {
-    #[cfg(any(spi_v1, spi_v3, spi_f1))]
     const fn ckpol(&self) -> vals::Ckpol {
         match self {
             ClockPolarity::IdleHigh => vals::Ckpol::IDLE_HIGH,
@@ -241,12 +237,12 @@ pub struct I2S<'d, W: Word> {
 
 impl<'d, W: Word> I2S<'d, W> {
     /// Create a transmitter driver.
-    pub fn new_txonly<T: Instance>(
+    pub fn new_txonly<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        sd: Peri<'d, impl MosiPin<T>>,
-        ws: Peri<'d, impl WsPin<T>>,
-        ck: Peri<'d, impl CkPin<T>>,
-        mck: Peri<'d, impl MckPin<T>>,
+        sd: Peri<'d, if_afio!(impl MosiPin<T, A>)>,
+        ws: Peri<'d, if_afio!(impl WsPin<T, A>)>,
+        ck: Peri<'d, if_afio!(impl CkPin<T, A>)>,
+        mck: Peri<'d, if_afio!(impl MckPin<T, A>)>,
         txdma: Peri<'d, impl TxDma<T>>,
         txdma_buf: &'d mut [W],
         config: Config,
@@ -266,11 +262,11 @@ impl<'d, W: Word> I2S<'d, W> {
     }
 
     /// Create a transmitter driver without a master clock pin.
-    pub fn new_txonly_nomck<T: Instance>(
+    pub fn new_txonly_nomck<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        sd: Peri<'d, impl MosiPin<T>>,
-        ws: Peri<'d, impl WsPin<T>>,
-        ck: Peri<'d, impl CkPin<T>>,
+        sd: Peri<'d, if_afio!(impl MosiPin<T, A>)>,
+        ws: Peri<'d, if_afio!(impl WsPin<T, A>)>,
+        ck: Peri<'d, if_afio!(impl CkPin<T, A>)>,
         txdma: Peri<'d, impl TxDma<T>>,
         txdma_buf: &'d mut [W],
         config: Config,
@@ -290,12 +286,12 @@ impl<'d, W: Word> I2S<'d, W> {
     }
 
     /// Create a receiver driver.
-    pub fn new_rxonly<T: Instance>(
+    pub fn new_rxonly<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        sd: Peri<'d, impl MisoPin<T>>,
-        ws: Peri<'d, impl WsPin<T>>,
-        ck: Peri<'d, impl CkPin<T>>,
-        mck: Peri<'d, impl MckPin<T>>,
+        sd: Peri<'d, if_afio!(impl MisoPin<T, A>)>,
+        ws: Peri<'d, if_afio!(impl WsPin<T, A>)>,
+        ck: Peri<'d, if_afio!(impl CkPin<T, A>)>,
+        mck: Peri<'d, if_afio!(impl MckPin<T, A>)>,
         rxdma: Peri<'d, impl RxDma<T>>,
         rxdma_buf: &'d mut [W],
         config: Config,
@@ -314,15 +310,16 @@ impl<'d, W: Word> I2S<'d, W> {
         )
     }
 
-    #[cfg(spi_v3)]
+    #[cfg(any(spi_v4, spi_v5))]
+
     /// Create a full duplex driver.
-    pub fn new_full_duplex<T: Instance>(
+    pub fn new_full_duplex<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        txsd: Peri<'d, impl MosiPin<T>>,
-        rxsd: Peri<'d, impl MisoPin<T>>,
-        ws: Peri<'d, impl WsPin<T>>,
-        ck: Peri<'d, impl CkPin<T>>,
-        mck: Peri<'d, impl MckPin<T>>,
+        txsd: Peri<'d, if_afio!(impl MosiPin<T, A>)>,
+        rxsd: Peri<'d, if_afio!(impl MisoPin<T, A>)>,
+        ws: Peri<'d, if_afio!(impl WsPin<T, A>)>,
+        ck: Peri<'d, if_afio!(impl CkPin<T, A>)>,
+        mck: Peri<'d, if_afio!(impl MckPin<T, A>)>,
         txdma: Peri<'d, impl TxDma<T>>,
         txdma_buf: &'d mut [W],
         rxdma: Peri<'d, impl RxDma<T>>,
@@ -357,7 +354,7 @@ impl<'d, W: Word> I2S<'d, W> {
         if let Some(rx_ring_buffer) = &mut self.rx_ring_buffer {
             rx_ring_buffer.start();
             // SPIv3 clears rxfifo on SPE=0
-            #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
+            #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
             flush_rx_fifo(self.spi.info.regs);
 
             set_rxdmaen(self.spi.info.regs, true);
@@ -365,7 +362,7 @@ impl<'d, W: Word> I2S<'d, W> {
         self.spi.info.regs.cr1().modify(|w| {
             w.set_spe(true);
         });
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         self.spi.info.regs.cr1().modify(|w| {
             w.set_cstart(true);
         });
@@ -404,7 +401,7 @@ impl<'d, W: Word> I2S<'d, W> {
 
         join(rx_f, tx_f).await;
 
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         {
             if let Mode::Master = self.mode {
                 regs.cr1().modify(|w| {
@@ -462,20 +459,20 @@ impl<'d, W: Word> I2S<'d, W> {
         }
     }
 
-    fn new_inner<T: Instance>(
+    fn new_inner<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
         txsd: Option<Peri<'d, AnyPin>>,
         rxsd: Option<Peri<'d, AnyPin>>,
-        ws: Peri<'d, impl WsPin<T>>,
-        ck: Peri<'d, impl CkPin<T>>,
+        ws: Peri<'d, if_afio!(impl WsPin<T, A>)>,
+        ck: Peri<'d, if_afio!(impl CkPin<T, A>)>,
         mck: Option<Peri<'d, AnyPin>>,
         txdma: Option<(ChannelAndRequest<'d>, &'d mut [W])>,
         rxdma: Option<(ChannelAndRequest<'d>, &'d mut [W])>,
         config: Config,
         function: Function,
     ) -> Self {
-        ws.set_as_af(ws.af_num(), AfType::output(OutputType::PushPull, config.gpio_speed));
-        ck.set_as_af(ck.af_num(), AfType::output(OutputType::PushPull, config.gpio_speed));
+        set_as_af!(ws, AfType::output(OutputType::PushPull, config.gpio_speed));
+        set_as_af!(ck, AfType::output(OutputType::PushPull, config.gpio_speed));
 
         let spi = Spi::new_internal(peri, None, None, {
             let mut spi_config = SpiConfig::default();
@@ -492,103 +489,98 @@ impl<'d, W: Word> I2S<'d, W> {
 
         let (odd, div) = compute_baud_rate(pclk, config.frequency, config.master_clock, config.format);
 
-        #[cfg(any(spi_v1, spi_v3, spi_f1))]
+        #[cfg(any(spi_v4, spi_v5))]
         {
-            #[cfg(spi_v3)]
-            {
-                regs.cr1().modify(|w| w.set_spe(false));
+            regs.cr1().modify(|w| w.set_spe(false));
 
-                reset_incompatible_bitfields::<T>();
-            }
+            reset_incompatible_bitfields::<T>();
+        }
 
-            use stm32_metapac::spi::vals::{I2scfg, Odd};
-
-            // 1. Select the I2SDIV[7:0] bits in the SPI_I2SPR/SPI_I2SCFGR register to define the serial clock baud
-            // rate to reach the proper audio sample frequency. The ODD bit in the
-            // SPI_I2SPR/SPI_I2SCFGR register also has to be defined.
-
-            // 2. Select the CKPOL bit to define the steady level for the communication clock. Set the
-            // MCKOE bit in the SPI_I2SPR/SPI_I2SCFGR register if the master clock MCK needs to be provided to
-            // the external DAC/ADC audio component (the I2SDIV and ODD values should be
-            // computed depending on the state of the MCK output, for more details refer to
-            // Section 28.4.4: Clock generator).
-
-            // 3. Set the I2SMOD bit in SPI_I2SCFGR to activate the I2S functionalities and choose the
-            // I2S standard through the I2SSTD[1:0] and PCMSYNC bits, the data length through the
-            // DATLEN[1:0] bits and the number of bits per channel by configuring the CHLEN bit.
-            // Select also the I2S master mode and direction (Transmitter or Receiver) through the
-            // I2SCFG[1:0] bits in the SPI_I2SCFGR register.
-
-            // 4. If needed, select all the potential interruption sources and the DMA capabilities by
-            // writing the SPI_CR2 register.
-
-            // 5. The I2SE bit in SPI_I2SCFGR register must be set.
-
-            let clk_reg = {
-                #[cfg(any(spi_v1, spi_f1))]
-                {
-                    regs.i2spr()
-                }
-                #[cfg(spi_v3)]
-                {
-                    regs.i2scfgr()
-                }
-            };
-
-            clk_reg.modify(|w| {
-                w.set_i2sdiv(div);
-                w.set_odd(match odd {
-                    true => Odd::ODD,
-                    false => Odd::EVEN,
-                });
+        use stm32_metapac::spi::vals::{I2scfg, Odd};
+
+        // 1. Select the I2SDIV[7:0] bits in the SPI_I2SPR/SPI_I2SCFGR register to define the serial clock baud
+        // rate to reach the proper audio sample frequency. The ODD bit in the
+        // SPI_I2SPR/SPI_I2SCFGR register also has to be defined.
 
-                w.set_mckoe(config.master_clock);
+        // 2. Select the CKPOL bit to define the steady level for the communication clock. Set the
+        // MCKOE bit in the SPI_I2SPR/SPI_I2SCFGR register if the master clock MCK needs to be provided to
+        // the external DAC/ADC audio component (the I2SDIV and ODD values should be
+        // computed depending on the state of the MCK output, for more details refer to
+        // Section 28.4.4: Clock generator).
+
+        // 3. Set the I2SMOD bit in SPI_I2SCFGR to activate the I2S functionalities and choose the
+        // I2S standard through the I2SSTD[1:0] and PCMSYNC bits, the data length through the
+        // DATLEN[1:0] bits and the number of bits per channel by configuring the CHLEN bit.
+        // Select also the I2S master mode and direction (Transmitter or Receiver) through the
+        // I2SCFG[1:0] bits in the SPI_I2SCFGR register.
+
+        // 4. If needed, select all the potential interruption sources and the DMA capabilities by
+        // writing the SPI_CR2 register.
+
+        // 5. The I2SE bit in SPI_I2SCFGR register must be set.
+
+        let clk_reg = {
+            #[cfg(any(spi_v1, spi_v2, spi_v3))]
+            {
+                regs.i2spr()
+            }
+            #[cfg(any(spi_v4, spi_v5))]
+            {
+                regs.i2scfgr()
+            }
+        };
+
+        clk_reg.modify(|w| {
+            w.set_i2sdiv(div);
+            w.set_odd(match odd {
+                true => Odd::ODD,
+                false => Odd::EVEN,
             });
 
-            regs.i2scfgr().modify(|w| {
-                w.set_ckpol(config.clock_polarity.ckpol());
+            w.set_mckoe(config.master_clock);
+        });
 
-                w.set_i2smod(true);
+        regs.i2scfgr().modify(|w| {
+            w.set_ckpol(config.clock_polarity.ckpol());
 
-                w.set_i2sstd(config.standard.i2sstd());
-                w.set_pcmsync(config.standard.pcmsync());
+            w.set_i2smod(true);
 
-                w.set_datlen(config.format.datlen());
-                w.set_chlen(config.format.chlen());
+            w.set_i2sstd(config.standard.i2sstd());
+            w.set_pcmsync(config.standard.pcmsync());
 
-                w.set_i2scfg(match (config.mode, function) {
-                    (Mode::Master, Function::Transmit) => I2scfg::MASTER_TX,
-                    (Mode::Master, Function::Receive) => I2scfg::MASTER_RX,
-                    #[cfg(spi_v3)]
-                    (Mode::Master, Function::FullDuplex) => I2scfg::MASTER_FULL_DUPLEX,
-                    (Mode::Slave, Function::Transmit) => I2scfg::SLAVE_TX,
-                    (Mode::Slave, Function::Receive) => I2scfg::SLAVE_RX,
-                    #[cfg(spi_v3)]
-                    (Mode::Slave, Function::FullDuplex) => I2scfg::SLAVE_FULL_DUPLEX,
-                });
+            w.set_datlen(config.format.datlen());
+            w.set_chlen(config.format.chlen());
 
-                #[cfg(any(spi_v1, spi_f1))]
-                w.set_i2se(true);
+            w.set_i2scfg(match (config.mode, function) {
+                (Mode::Master, Function::Transmit) => I2scfg::MASTER_TX,
+                (Mode::Master, Function::Receive) => I2scfg::MASTER_RX,
+                #[cfg(any(spi_v4, spi_v5))]
+                (Mode::Master, Function::FullDuplex) => I2scfg::MASTER_FULL_DUPLEX,
+                (Mode::Slave, Function::Transmit) => I2scfg::SLAVE_TX,
+                (Mode::Slave, Function::Receive) => I2scfg::SLAVE_RX,
+                #[cfg(any(spi_v4, spi_v5))]
+                (Mode::Slave, Function::FullDuplex) => I2scfg::SLAVE_FULL_DUPLEX,
             });
 
-            let mut opts = TransferOptions::default();
-            opts.half_transfer_ir = true;
-
-            Self {
-                mode: config.mode,
-                spi,
-                txsd: txsd.map(|w| w.into()),
-                rxsd: rxsd.map(|w| w.into()),
-                ws: Some(ws.into()),
-                ck: Some(ck.into()),
-                mck: mck.map(|w| w.into()),
-                tx_ring_buffer: txdma.map(|(ch, buf)| unsafe {
-                    WritableRingBuffer::new(ch.channel, ch.request, regs.tx_ptr(), buf, opts)
-                }),
-                rx_ring_buffer: rxdma.map(|(ch, buf)| unsafe {
-                    ReadableRingBuffer::new(ch.channel, ch.request, regs.rx_ptr(), buf, opts)
-                }),
-            }
+            #[cfg(any(spi_v1, spi_v2, spi_v3))]
+            w.set_i2se(true);
+        });
+
+        let mut opts = TransferOptions::default();
+        opts.half_transfer_ir = true;
+
+        Self {
+            mode: config.mode,
+            spi,
+            txsd: txsd.map(|w| w.into()),
+            rxsd: rxsd.map(|w| w.into()),
+            ws: Some(ws.into()),
+            ck: Some(ck.into()),
+            mck: mck.map(|w| w.into()),
+            tx_ring_buffer: txdma
+                .map(|(ch, buf)| unsafe { WritableRingBuffer::new(ch.channel, ch.request, regs.tx_ptr(), buf, opts) }),
+            rx_ring_buffer: rxdma
+                .map(|(ch, buf)| unsafe { ReadableRingBuffer::new(ch.channel, ch.request, regs.rx_ptr(), buf, opts) }),
         }
     }
 }
@@ -639,7 +631,8 @@ fn compute_baud_rate(i2s_clock: Hertz, request_freq: Hertz, mclk: bool, data_for
     }
 }
 
-#[cfg(spi_v3)]
+#[cfg(any(spi_v4, spi_v5))]
+
 // The STM32H7 reference manual specifies that any incompatible bitfields should be reset
 // to their reset values while operating in I2S mode.
 fn reset_incompatible_bitfields<T: Instance>() {
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs
index 3be98c462..7e0f7884e 100644
--- a/embassy-stm32/src/lib.rs
+++ b/embassy-stm32/src/lib.rs
@@ -87,7 +87,7 @@ pub mod hsem;
 pub mod hspi;
 #[cfg(i2c)]
 pub mod i2c;
-#[cfg(any(all(spi_v1, rcc_f4), spi_v3))]
+#[cfg(any(spi_v1_i2s, spi_v2_i2s, spi_v3_i2s, spi_v4_i2s, spi_v5_i2s))]
 pub mod i2s;
 #[cfg(stm32wb)]
 pub mod ipcc;
diff --git a/embassy-stm32/src/lptim/pwm.rs b/embassy-stm32/src/lptim/pwm.rs
index 2f2d7ba01..96af9f4d9 100644
--- a/embassy-stm32/src/lptim/pwm.rs
+++ b/embassy-stm32/src/lptim/pwm.rs
@@ -50,10 +50,7 @@ macro_rules! channel_impl {
             pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>) -> Self {
                 critical_section::with(|_| {
                     pin.set_low();
-                    pin.set_as_af(
-                        pin.af_num(),
-                        AfType::output(OutputType::PushPull, Speed::VeryHigh),
-                    );
+                    set_as_af!(pin, AfType::output(OutputType::PushPull, Speed::VeryHigh));
                 });
                 PwmPin {
                     _pin: pin.into(),
@@ -64,12 +61,12 @@ macro_rules! channel_impl {
             pub fn $new_chx_with_config(pin: Peri<'d, impl $pin_trait<T>>, pin_config: PwmPinConfig) -> Self {
                 critical_section::with(|_| {
                     pin.set_low();
-                    pin.set_as_af(
-                        pin.af_num(),
-                        #[cfg(gpio_v1)]
-                        AfType::output(pin_config.output_type, pin_config.speed),
-                        #[cfg(gpio_v2)]
-                        AfType::output_pull(pin_config.output_type, pin_config.speed, pin_config.pull),
+                    #[cfg(gpio_v1)]
+                    set_as_af!(pin, AfType::output(pin_config.output_type, pin_config.speed));
+                    #[cfg(gpio_v2)]
+                    set_as_af!(
+                        pin,
+                        AfType::output_pull(pin_config.output_type, pin_config.speed, pin_config.pull)
                     );
                 });
                 PwmPin {
diff --git a/embassy-stm32/src/macros.rs b/embassy-stm32/src/macros.rs
index 3a0b490ba..22cc2e049 100644
--- a/embassy-stm32/src/macros.rs
+++ b/embassy-stm32/src/macros.rs
@@ -41,17 +41,30 @@ macro_rules! peri_trait_impl {
 }
 
 macro_rules! pin_trait {
-    ($signal:ident, $instance:path $(, $mode:path)?) => {
+    ($signal:ident, $instance:path $(, $mode:path)? $(, @$afio:ident)?) => {
         #[doc = concat!(stringify!($signal), " pin trait")]
-        pub trait $signal<T: $instance $(, M: $mode)?>: crate::gpio::Pin {
+        pub trait $signal<T: $instance $(, M: $mode)? $(, #[cfg(afio)] $afio)?>: crate::gpio::Pin {
+            #[cfg(not(afio))]
             #[doc = concat!("Get the AF number needed to use this pin as ", stringify!($signal))]
             fn af_num(&self) -> u8;
+
+            #[cfg(afio)]
+            #[doc = concat!("Configures AFIO_MAPR to use this pin as ", stringify!($signal))]
+            fn afio_remap(&self);
         }
     };
 }
 
 macro_rules! pin_trait_impl {
-    (crate::$mod:ident::$trait:ident$(<$mode:ident>)?, $instance:ident, $pin:ident, $af:expr) => {
+    (crate::$mod:ident::$trait:ident$(<$mode:ident>)?, $instance:ident, $pin:ident, $af:expr $(, $afio:path)?) => {
+        #[cfg(afio)]
+        impl crate::$mod::$trait<crate::peripherals::$instance $(, crate::$mod::$mode)? $(, $afio)?> for crate::peripherals::$pin {
+            fn afio_remap(&self) {
+                // nothing
+            }
+        }
+
+        #[cfg(not(afio))]
         impl crate::$mod::$trait<crate::peripherals::$instance $(, crate::$mod::$mode)?> for crate::peripherals::$pin {
             fn af_num(&self) -> u8 {
                 $af
@@ -60,6 +73,39 @@ macro_rules! pin_trait_impl {
     };
 }
 
+#[cfg(afio)]
+macro_rules! pin_trait_afio_impl {
+    (@set mapr, $setter:ident, $val:expr) => {
+        crate::pac::AFIO.mapr().modify(|w| {
+            w.set_swj_cfg(crate::pac::afio::vals::SwjCfg::NO_OP);
+            w.$setter($val);
+        });
+    };
+    (@set mapr2, $setter:ident, $val:expr) => {
+        crate::pac::AFIO.mapr2().modify(|w| {
+            w.$setter($val);
+        });
+    };
+    (crate::$mod:ident::$trait:ident<$mode:ident>, $instance:ident, $pin:ident, {$reg:ident, $setter:ident, $type:ident, [$($val:expr),+]}) => {
+        $(
+            impl crate::$mod::$trait<crate::peripherals::$instance, crate::$mod::$mode, crate::gpio::$type<$val>> for crate::peripherals::$pin {
+                fn afio_remap(&self) {
+                    pin_trait_afio_impl!(@set $reg, $setter, $val);
+                }
+            }
+        )+
+    };
+    (crate::$mod:ident::$trait:ident, $instance:ident, $pin:ident, {$reg:ident, $setter:ident, $type:ident, [$($val:expr),+]}) => {
+        $(
+            impl crate::$mod::$trait<crate::peripherals::$instance, crate::gpio::$type<$val>> for crate::peripherals::$pin {
+                fn afio_remap(&self) {
+                    pin_trait_afio_impl!(@set $reg, $setter, $val);
+                }
+            }
+        )+
+    };
+}
+
 #[allow(unused_macros)]
 macro_rules! sel_trait_impl {
     (crate::$mod:ident::$trait:ident$(<$mode:ident>)?, $instance:ident, $pin:ident, $sel:expr) => {
@@ -134,7 +180,73 @@ macro_rules! new_dma {
 macro_rules! new_pin {
     ($name:ident, $af_type:expr) => {{
         let pin = $name;
-        pin.set_as_af(pin.af_num(), $af_type);
+        #[cfg(afio)]
+        pin.afio_remap();
+        pin.set_as_af(
+            #[cfg(not(afio))]
+            pin.af_num(),
+            $af_type,
+        );
         Some(pin.into())
     }};
 }
+
+/// Macro to configure a pin for alternate function use.
+/// For AFIO chips (STM32F1), it calls afio_remap().
+/// For non-AFIO chips, it calls set_as_af() with the pin's af_num().
+macro_rules! set_as_af {
+    ($pin:expr, $af_type:expr) => {
+        #[cfg(afio)]
+        {
+            $pin.set_as_af($af_type);
+            $pin.afio_remap();
+        }
+        #[cfg(not(afio))]
+        {
+            $pin.set_as_af($pin.af_num(), $af_type);
+        }
+    };
+}
+
+#[cfg(afio)]
+macro_rules! if_afio {
+    ($($t:tt)*) => {
+        $($t)*
+    }
+}
+#[cfg(not(afio))]
+macro_rules! if_afio {
+    (($a:ty, A)) => {
+        ($a,)
+    };
+    (($a:ty, $b:ty, A)) => {
+        ($a,$b)
+    };
+    (($a:ty, $b:ty, $c:ty, A)) => {
+        ($a,$b, $c)
+    };
+    ($type:ident<$lt:lifetime, $a:ty, $b:ty, A>) => {
+        $type<$lt, $a, $b>
+    };
+    ($type:ident<$lt:lifetime, $a:ty, $b:ty, $c:ty, A>) => {
+        $type<$lt, $a, $b, $c>
+    };
+    ($type:ident<$a:ty, A>) => {
+        $type<$a>
+    };
+    ($type:ident<$a:ty, $b:ty, A>) => {
+        $type<$a, $b>
+    };
+    ($type:ident<$a:ty, $b:ty, $c:ty, A>) => {
+        $type<$a, $b, $c>
+    };
+    (impl $trait:ident<$a:ty, A>) => {
+        impl $trait<$a>
+    };
+    (impl $trait:ident<$a:ty, $b:ty, A>) => {
+        impl $trait<$a, $b>
+    };
+    (impl $trait:ident<$a:ty, $b:ty, $c:ty, A>) => {
+        impl $trait<$a, $b, $c>
+    };
+}
diff --git a/embassy-stm32/src/ospi/enums.rs b/embassy-stm32/src/ospi/enums.rs
index 4021f7ce3..4db801752 100644
--- a/embassy-stm32/src/ospi/enums.rs
+++ b/embassy-stm32/src/ospi/enums.rs
@@ -23,6 +23,7 @@ impl Into<u8> for OspiMode {
 /// Ospi lane width
 #[allow(dead_code)]
 #[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum OspiWidth {
     /// None
     NONE,
@@ -71,6 +72,7 @@ impl Into<bool> for FlashSelection {
 #[allow(dead_code)]
 #[allow(missing_docs)]
 #[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum WrapSize {
     None,
     _16Bytes,
@@ -95,6 +97,7 @@ impl Into<u8> for WrapSize {
 #[allow(missing_docs)]
 #[allow(dead_code)]
 #[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum MemoryType {
     Micron,
     Macronix,
@@ -120,6 +123,7 @@ impl Into<u8> for MemoryType {
 /// Ospi memory size.
 #[allow(missing_docs)]
 #[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum MemorySize {
     _1KiB,
     _2KiB,
@@ -180,6 +184,7 @@ impl Into<u8> for MemorySize {
 
 /// Ospi Address size
 #[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum AddressSize {
     /// 8-bit address
     _8Bit,
@@ -205,6 +210,7 @@ impl Into<u8> for AddressSize {
 /// Time the Chip Select line stays high.
 #[allow(missing_docs)]
 #[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum ChipSelectHighTime {
     _1Cycle,
     _2Cycle,
@@ -234,6 +240,7 @@ impl Into<u8> for ChipSelectHighTime {
 /// FIFO threshold.
 #[allow(missing_docs)]
 #[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum FIFOThresholdLevel {
     _1Bytes,
     _2Bytes,
@@ -311,6 +318,7 @@ impl Into<u8> for FIFOThresholdLevel {
 /// Dummy cycle count
 #[allow(missing_docs)]
 #[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum DummyCycles {
     _0,
     _1,
diff --git a/embassy-stm32/src/ospi/mod.rs b/embassy-stm32/src/ospi/mod.rs
index 74edfd5e4..d93cecb69 100644
--- a/embassy-stm32/src/ospi/mod.rs
+++ b/embassy-stm32/src/ospi/mod.rs
@@ -23,6 +23,7 @@ use crate::{peripherals, Peri};
 
 /// OPSI driver config.
 #[derive(Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct Config {
     /// Fifo threshold used by the peripheral to generate the interrupt indicating data
     /// or space is available in the FIFO
@@ -30,7 +31,9 @@ pub struct Config {
     /// Indicates the type of external device connected
     pub memory_type: MemoryType, // Need to add an additional enum to provide this public interface
     /// Defines the size of the external device connected to the OSPI corresponding
-    /// to the number of address bits required to access the device
+    /// to the number of address bits required to access the device.
+    /// When using indirect mode, [`TransferConfig::address`] + the length of the data being read
+    /// or written must fit within the configured `device_size`, otherwise an error is returned.
     pub device_size: MemorySize,
     /// Sets the minimum number of clock cycles that the chip select signal must be held high
     /// between commands
@@ -83,6 +86,8 @@ impl Default for Config {
 }
 
 /// OSPI transfer configuration.
+#[derive(Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct TransferConfig {
     /// Instruction width (IMODE)
     pub iwidth: OspiWidth,
@@ -92,10 +97,11 @@ pub struct TransferConfig {
     pub isize: AddressSize,
     /// Instruction Double Transfer rate enable
     pub idtr: bool,
-
     /// Address width (ADMODE)
     pub adwidth: OspiWidth,
-    /// Device memory address
+    /// Device memory address.
+    /// In indirect mode, this value + the length of the data being read or written must be within
+    /// configured [`Config::device_size`], otherwise the transfer returns an error.
     pub address: Option<u32>,
     /// Number of Address Bytes
     pub adsize: AddressSize,
@@ -113,11 +119,16 @@ pub struct TransferConfig {
 
     /// Data width (DMODE)
     pub dwidth: OspiWidth,
-    /// Data buffer
+    /// Data Double Transfer rate enable
     pub ddtr: bool,
 
     /// Number of dummy cycles (DCYC)
     pub dummy: DummyCycles,
+
+    /// Data strobe (DQS) management enable
+    pub dqse: bool,
+    /// Send instruction only once (SIOO) mode enable
+    pub sioo: bool,
 }
 
 impl Default for TransferConfig {
@@ -142,6 +153,9 @@ impl Default for TransferConfig {
             ddtr: false,
 
             dummy: DummyCycles::_0,
+
+            dqse: false,
+            sioo: true,
         }
     }
 }
@@ -192,26 +206,27 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
         let reg = T::REGS;
         while reg.sr().read().busy() {}
 
-        reg.ccr().modify(|r| {
-            r.set_dqse(false);
-            r.set_sioo(true);
-        });
+        if let Some(instruction) = write_config.instruction {
+            reg.wir().write(|r| {
+                r.set_instruction(instruction);
+            });
+        }
 
-        // Set wrting configurations, there are separate registers for write configurations in memory mapped mode
+        // Set writing configurations, there are separate registers for write configurations in memory mapped mode
         reg.wccr().modify(|w| {
             w.set_imode(PhaseMode::from_bits(write_config.iwidth.into()));
             w.set_idtr(write_config.idtr);
             w.set_isize(SizeInBits::from_bits(write_config.isize.into()));
 
             w.set_admode(PhaseMode::from_bits(write_config.adwidth.into()));
-            w.set_addtr(write_config.idtr);
+            w.set_addtr(write_config.addtr);
             w.set_adsize(SizeInBits::from_bits(write_config.adsize.into()));
 
             w.set_dmode(PhaseMode::from_bits(write_config.dwidth.into()));
             w.set_ddtr(write_config.ddtr);
 
             w.set_abmode(PhaseMode::from_bits(write_config.abwidth.into()));
-            w.set_dqse(true);
+            w.set_dqse(write_config.dqse);
         });
 
         reg.wtcr().modify(|w| w.set_dcyc(write_config.dummy.into()));
@@ -442,11 +457,6 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
         // Configure alternate bytes
         if let Some(ab) = command.alternate_bytes {
             T::REGS.abr().write(|v| v.set_alternate(ab));
-            T::REGS.ccr().modify(|w| {
-                w.set_abmode(PhaseMode::from_bits(command.abwidth.into()));
-                w.set_abdtr(command.abdtr);
-                w.set_absize(SizeInBits::from_bits(command.absize.into()));
-            })
         }
 
         // Configure dummy cycles
@@ -458,28 +468,35 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
         if let Some(data_length) = data_len {
             T::REGS.dlr().write(|v| {
                 v.set_dl((data_length - 1) as u32);
-            })
+            });
         } else {
             T::REGS.dlr().write(|v| {
                 v.set_dl((0) as u32);
-            })
+            });
         }
 
-        // Configure instruction/address/data modes
+        // Configure instruction/address/alternate bytes/data/communication modes
         T::REGS.ccr().modify(|w| {
             w.set_imode(PhaseMode::from_bits(command.iwidth.into()));
             w.set_idtr(command.idtr);
             w.set_isize(SizeInBits::from_bits(command.isize.into()));
 
             w.set_admode(PhaseMode::from_bits(command.adwidth.into()));
-            w.set_addtr(command.idtr);
+            w.set_addtr(command.addtr);
             w.set_adsize(SizeInBits::from_bits(command.adsize.into()));
 
+            w.set_abmode(PhaseMode::from_bits(command.abwidth.into()));
+            w.set_abdtr(command.abdtr);
+            w.set_absize(SizeInBits::from_bits(command.absize.into()));
+
             w.set_dmode(PhaseMode::from_bits(command.dwidth.into()));
             w.set_ddtr(command.ddtr);
+
+            w.set_dqse(command.dqse);
+            w.set_sioo(command.sioo);
         });
 
-        // Set informationrequired to initiate transaction
+        // Set information required to initiate transaction
         if let Some(instruction) = command.instruction {
             if let Some(address) = command.address {
                 T::REGS.ir().write(|v| {
@@ -514,6 +531,18 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
             }
         }
 
+        // The following errors set the TEF flag in OCTOSPI_SR register:
+        // - in indirect or automatic status-polling mode, when a wrong address has been programmed
+        //   in OCTOSPI_AR (according to the device size defined by DEVSIZE[4:0])
+        // - in indirect mode, if the address plus the data length exceed the device size: TEF is
+        // set as soon as the access is triggered.
+        if T::REGS.sr().read().tef() {
+            // Clear the TEF register to make it ready for the next transfer.
+            T::REGS.fcr().write(|w| w.set_ctef(true));
+
+            return Err(OspiError::InvalidCommand);
+        }
+
         Ok(())
     }
 
@@ -854,6 +883,45 @@ impl<'d, T: Instance> Ospi<'d, T, Blocking> {
             false,
         )
     }
+
+    /// Create new blocking OSPI driver for octospi external chips with DQS support
+    pub fn new_blocking_octospi_with_dqs(
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        d4: Peri<'d, impl D4Pin<T>>,
+        d5: Peri<'d, impl D5Pin<T>>,
+        d6: Peri<'d, impl D6Pin<T>>,
+        d7: Peri<'d, impl D7Pin<T>>,
+        nss: Peri<'d, impl NSSPin<T>>,
+        dqs: Peri<'d, impl DQSPin<T>>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(
+            peri,
+            new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d2, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d3, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d4, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d5, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d6, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d7, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(sck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(
+                nss,
+                AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
+            ),
+            new_pin!(dqs, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            None,
+            config,
+            OspiWidth::OCTO,
+            false,
+        )
+    }
 }
 
 impl<'d, T: Instance> Ospi<'d, T, Async> {
@@ -1036,6 +1104,46 @@ impl<'d, T: Instance> Ospi<'d, T, Async> {
         )
     }
 
+    /// Create new blocking OSPI driver for octospi external chips with DQS support
+    pub fn new_octospi_with_dqs(
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        d4: Peri<'d, impl D4Pin<T>>,
+        d5: Peri<'d, impl D5Pin<T>>,
+        d6: Peri<'d, impl D6Pin<T>>,
+        d7: Peri<'d, impl D7Pin<T>>,
+        nss: Peri<'d, impl NSSPin<T>>,
+        dqs: Peri<'d, impl DQSPin<T>>,
+        dma: Peri<'d, impl OctoDma<T>>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(
+            peri,
+            new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d2, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d3, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d4, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d5, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d6, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d7, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(sck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(
+                nss,
+                AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
+            ),
+            new_pin!(dqs, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_dma!(dma),
+            config,
+            OspiWidth::OCTO,
+            false,
+        )
+    }
+
     /// Blocking read with DMA transfer
     pub fn blocking_read_dma<W: Word>(&mut self, buf: &mut [W], transaction: TransferConfig) -> Result<(), OspiError> {
         if buf.is_empty() {
@@ -1090,16 +1198,19 @@ impl<'d, T: Instance> Ospi<'d, T, Async> {
             .cr()
             .modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECT_WRITE));
 
-        let transfer = unsafe {
-            self.dma
-                .as_mut()
-                .unwrap()
-                .write(buf, T::REGS.dr().as_ptr() as *mut W, Default::default())
-        };
+        // TODO: implement this using a LinkedList DMA to offload the whole transfer off the CPU.
+        for chunk in buf.chunks(0xFFFF) {
+            let transfer = unsafe {
+                self.dma
+                    .as_mut()
+                    .unwrap()
+                    .write(chunk, T::REGS.dr().as_ptr() as *mut W, Default::default())
+            };
 
-        T::REGS.cr().modify(|w| w.set_dmaen(true));
+            T::REGS.cr().modify(|w| w.set_dmaen(true));
 
-        transfer.blocking_wait();
+            transfer.blocking_wait();
+        }
 
         finish_dma(T::REGS);
 
@@ -1160,16 +1271,19 @@ impl<'d, T: Instance> Ospi<'d, T, Async> {
             .cr()
             .modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECT_WRITE));
 
-        let transfer = unsafe {
-            self.dma
-                .as_mut()
-                .unwrap()
-                .write(buf, T::REGS.dr().as_ptr() as *mut W, Default::default())
-        };
+        // TODO: implement this using a LinkedList DMA to offload the whole transfer off the CPU.
+        for chunk in buf.chunks(0xFFFF) {
+            let transfer = unsafe {
+                self.dma
+                    .as_mut()
+                    .unwrap()
+                    .write(chunk, T::REGS.dr().as_ptr() as *mut W, Default::default())
+            };
 
-        T::REGS.cr().modify(|w| w.set_dmaen(true));
+            T::REGS.cr().modify(|w| w.set_dmaen(true));
 
-        transfer.await;
+            transfer.await;
+        }
 
         finish_dma(T::REGS);
 
diff --git a/embassy-stm32/src/qspi/enums.rs b/embassy-stm32/src/qspi/enums.rs
index fa5e36d06..8a8420127 100644
--- a/embassy-stm32/src/qspi/enums.rs
+++ b/embassy-stm32/src/qspi/enums.rs
@@ -23,6 +23,7 @@ impl From<QspiMode> for u8 {
 /// QSPI lane width
 #[allow(dead_code)]
 #[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum QspiWidth {
     /// None
     NONE,
@@ -67,6 +68,7 @@ impl From<FlashSelection> for bool {
 /// QSPI memory size.
 #[allow(missing_docs)]
 #[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum MemorySize {
     _1KiB,
     _2KiB,
@@ -127,6 +129,7 @@ impl From<MemorySize> for u8 {
 
 /// QSPI Address size
 #[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum AddressSize {
     /// 8-bit address
     _8Bit,
@@ -152,6 +155,7 @@ impl From<AddressSize> for u8 {
 /// Time the Chip Select line stays high.
 #[allow(missing_docs)]
 #[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum ChipSelectHighTime {
     _1Cycle,
     _2Cycle,
@@ -181,6 +185,7 @@ impl From<ChipSelectHighTime> for u8 {
 /// FIFO threshold.
 #[allow(missing_docs)]
 #[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum FIFOThresholdLevel {
     _1Bytes,
     _2Bytes,
@@ -258,6 +263,7 @@ impl From<FIFOThresholdLevel> for u8 {
 /// Dummy cycle count
 #[allow(missing_docs)]
 #[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum DummyCycles {
     _0,
     _1,
@@ -334,6 +340,7 @@ impl From<DummyCycles> for u8 {
 
 #[allow(missing_docs)]
 #[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum SampleShifting {
     None,
     HalfCycle,
diff --git a/embassy-stm32/src/qspi/mod.rs b/embassy-stm32/src/qspi/mod.rs
index 1e20d7cd3..b03cd9009 100644
--- a/embassy-stm32/src/qspi/mod.rs
+++ b/embassy-stm32/src/qspi/mod.rs
@@ -17,6 +17,8 @@ use crate::rcc::{self, RccPeripheral};
 use crate::{peripherals, Peri};
 
 /// QSPI transfer configuration.
+#[derive(Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct TransferConfig {
     /// Instruction width (IMODE)
     pub iwidth: QspiWidth,
@@ -46,6 +48,9 @@ impl Default for TransferConfig {
 }
 
 /// QSPI driver configuration.
+#[derive(Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[non_exhaustive]
 pub struct Config {
     /// Flash memory size representend as 2^[0-32], as reasonable minimum 1KiB(9) was chosen.
     /// If you need other value the whose predefined use `Other` variant.
@@ -60,6 +65,8 @@ pub struct Config {
     pub cs_high_time: ChipSelectHighTime,
     /// Shift sampling point of input data (none, or half-cycle)
     pub sample_shifting: SampleShifting,
+    /// GPIO Speed
+    pub gpio_speed: Speed,
 }
 
 impl Default for Config {
@@ -71,6 +78,7 @@ impl Default for Config {
             fifo_threshold: FIFOThresholdLevel::_17Bytes,
             cs_high_time: ChipSelectHighTime::_5Cycle,
             sample_shifting: SampleShifting::None,
+            gpio_speed: Speed::VeryHigh,
         }
     }
 }
@@ -284,14 +292,14 @@ impl<'d, T: Instance> Qspi<'d, T, Blocking> {
     ) -> Self {
         Self::new_inner(
             peri,
-            new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(d2, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(d3, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(sck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d0, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(d1, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(d2, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(d3, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(sck, AfType::output(OutputType::PushPull, config.gpio_speed)),
             new_pin!(
                 nss,
-                AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
+                AfType::output_pull(OutputType::PushPull, config.gpio_speed, Pull::Up)
             ),
             None,
             config,
@@ -312,14 +320,14 @@ impl<'d, T: Instance> Qspi<'d, T, Blocking> {
     ) -> Self {
         Self::new_inner(
             peri,
-            new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(d2, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(d3, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(sck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d0, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(d1, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(d2, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(d3, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(sck, AfType::output(OutputType::PushPull, config.gpio_speed)),
             new_pin!(
                 nss,
-                AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
+                AfType::output_pull(OutputType::PushPull, config.gpio_speed, Pull::Up)
             ),
             None,
             config,
@@ -343,14 +351,14 @@ impl<'d, T: Instance> Qspi<'d, T, Async> {
     ) -> Self {
         Self::new_inner(
             peri,
-            new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(d2, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(d3, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(sck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d0, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(d1, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(d2, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(d3, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(sck, AfType::output(OutputType::PushPull, config.gpio_speed)),
             new_pin!(
                 nss,
-                AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
+                AfType::output_pull(OutputType::PushPull, config.gpio_speed, Pull::Up)
             ),
             new_dma!(dma),
             config,
@@ -372,14 +380,14 @@ impl<'d, T: Instance> Qspi<'d, T, Async> {
     ) -> Self {
         Self::new_inner(
             peri,
-            new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(d2, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(d3, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_pin!(sck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d0, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(d1, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(d2, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(d3, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(sck, AfType::output(OutputType::PushPull, config.gpio_speed)),
             new_pin!(
                 nss,
-                AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
+                AfType::output_pull(OutputType::PushPull, config.gpio_speed, Pull::Up)
             ),
             new_dma!(dma),
             config,
diff --git a/embassy-stm32/src/rcc/mco.rs b/embassy-stm32/src/rcc/mco.rs
index 96e628b1a..59ccc8cb5 100644
--- a/embassy-stm32/src/rcc/mco.rs
+++ b/embassy-stm32/src/rcc/mco.rs
@@ -94,7 +94,7 @@ impl<'d, T: McoInstance> Mco<'d, T> {
     pub fn new(_peri: Peri<'d, T>, pin: Peri<'d, impl McoPin<T>>, source: T::Source, prescaler: McoPrescaler) -> Self {
         critical_section::with(|_| unsafe {
             T::_apply_clock_settings(source, prescaler);
-            pin.set_as_af(pin.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
+            set_as_af!(pin, AfType::output(OutputType::PushPull, Speed::VeryHigh));
         });
 
         Self { phantom: PhantomData }
diff --git a/embassy-stm32/src/sai/mod.rs b/embassy-stm32/src/sai/mod.rs
index 4965f8b04..fb8b23b79 100644
--- a/embassy-stm32/src/sai/mod.rs
+++ b/embassy-stm32/src/sai/mod.rs
@@ -1,15 +1,14 @@
 //! Serial Audio Interface (SAI)
 #![macro_use]
-#![cfg_attr(gpdma, allow(unused))]
 
 use core::marker::PhantomData;
 
 use embassy_hal_internal::PeripheralType;
 
 pub use crate::dma::word;
-#[cfg(not(gpdma))]
 use crate::dma::{ringbuffer, Channel, ReadableRingBuffer, Request, TransferOptions, WritableRingBuffer};
 use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed};
+pub use crate::pac::sai::vals::Mckdiv as MasterClockDivider;
 use crate::pac::sai::{vals, Sai as Regs};
 use crate::rcc::{self, RccPeripheral};
 use crate::{peripherals, Peri};
@@ -26,7 +25,6 @@ pub enum Error {
     Overrun,
 }
 
-#[cfg(not(gpdma))]
 impl From<ringbuffer::Error> for Error {
     fn from(#[allow(unused)] err: ringbuffer::Error) -> Self {
         #[cfg(feature = "defmt")]
@@ -48,7 +46,6 @@ pub enum Mode {
 }
 
 impl Mode {
-    #[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
     const fn mode(&self, tx_rx: TxRx) -> vals::Mode {
         match tx_rx {
             TxRx::Transmitter => match self {
@@ -83,7 +80,6 @@ pub enum SlotSize {
 }
 
 impl SlotSize {
-    #[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
     const fn slotsz(&self) -> vals::Slotsz {
         match self {
             SlotSize::DataSize => vals::Slotsz::DATA_SIZE,
@@ -106,7 +102,6 @@ pub enum DataSize {
 }
 
 impl DataSize {
-    #[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
     const fn ds(&self) -> vals::Ds {
         match self {
             DataSize::Data8 => vals::Ds::BIT8,
@@ -131,7 +126,6 @@ pub enum FifoThreshold {
 }
 
 impl FifoThreshold {
-    #[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
     const fn fth(&self) -> vals::Fth {
         match self {
             FifoThreshold::Empty => vals::Fth::EMPTY,
@@ -152,7 +146,6 @@ pub enum MuteValue {
 }
 
 impl MuteValue {
-    #[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
     const fn muteval(&self) -> vals::Muteval {
         match self {
             MuteValue::Zero => vals::Muteval::SEND_ZERO,
@@ -171,7 +164,6 @@ pub enum Protocol {
 }
 
 impl Protocol {
-    #[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
     const fn prtcfg(&self) -> vals::Prtcfg {
         match self {
             Protocol::Free => vals::Prtcfg::FREE,
@@ -190,7 +182,7 @@ pub enum SyncInput {
     /// Syncs with the other A/B sub-block within the SAI unit
     Internal,
     /// Syncs with a sub-block in the other SAI unit
-    #[cfg(any(sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
+    #[cfg(any(sai_v3, sai_v4))]
     External(SyncInputInstance),
 }
 
@@ -199,14 +191,14 @@ impl SyncInput {
         match self {
             SyncInput::None => vals::Syncen::ASYNCHRONOUS,
             SyncInput::Internal => vals::Syncen::INTERNAL,
-            #[cfg(any(sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
+            #[cfg(any(sai_v3, sai_v4))]
             SyncInput::External(_) => vals::Syncen::EXTERNAL,
         }
     }
 }
 
 /// SAI instance to sync from.
-#[cfg(any(sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
+#[cfg(any(sai_v3, sai_v4))]
 #[derive(Copy, Clone, PartialEq)]
 #[allow(missing_docs)]
 pub enum SyncInputInstance {
@@ -229,7 +221,6 @@ pub enum StereoMono {
 }
 
 impl StereoMono {
-    #[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
     const fn mono(&self) -> vals::Mono {
         match self {
             StereoMono::Stereo => vals::Mono::STEREO,
@@ -248,7 +239,6 @@ pub enum BitOrder {
 }
 
 impl BitOrder {
-    #[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
     const fn lsbfirst(&self) -> vals::Lsbfirst {
         match self {
             BitOrder::LsbFirst => vals::Lsbfirst::LSB_FIRST,
@@ -267,7 +257,6 @@ pub enum FrameSyncOffset {
 }
 
 impl FrameSyncOffset {
-    #[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
     const fn fsoff(&self) -> vals::Fsoff {
         match self {
             FrameSyncOffset::OnFirstBit => vals::Fsoff::ON_FIRST,
@@ -286,7 +275,6 @@ pub enum FrameSyncPolarity {
 }
 
 impl FrameSyncPolarity {
-    #[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
     const fn fspol(&self) -> vals::Fspol {
         match self {
             FrameSyncPolarity::ActiveLow => vals::Fspol::FALLING_EDGE,
@@ -304,7 +292,6 @@ pub enum FrameSyncDefinition {
 }
 
 impl FrameSyncDefinition {
-    #[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
     const fn fsdef(&self) -> bool {
         match self {
             FrameSyncDefinition::StartOfFrame => false,
@@ -322,7 +309,6 @@ pub enum ClockStrobe {
 }
 
 impl ClockStrobe {
-    #[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
     const fn ckstr(&self) -> vals::Ckstr {
         match self {
             ClockStrobe::Falling => vals::Ckstr::FALLING_EDGE,
@@ -340,7 +326,6 @@ pub enum ComplementFormat {
 }
 
 impl ComplementFormat {
-    #[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
     const fn cpl(&self) -> vals::Cpl {
         match self {
             ComplementFormat::OnesComplement => vals::Cpl::ONES_COMPLEMENT,
@@ -359,7 +344,6 @@ pub enum Companding {
 }
 
 impl Companding {
-    #[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
     const fn comp(&self) -> vals::Comp {
         match self {
             Companding::None => vals::Comp::NO_COMPANDING,
@@ -378,7 +362,6 @@ pub enum OutputDrive {
 }
 
 impl OutputDrive {
-    #[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
     const fn outdriv(&self) -> vals::Outdriv {
         match self {
             OutputDrive::OnStart => vals::Outdriv::ON_START,
@@ -387,196 +370,6 @@ impl OutputDrive {
     }
 }
 
-/// Master clock divider.
-#[derive(Copy, Clone, PartialEq)]
-#[allow(missing_docs)]
-#[cfg(any(sai_v1, sai_v2))]
-pub enum MasterClockDivider {
-    MasterClockDisabled,
-    Div1,
-    Div2,
-    Div4,
-    Div6,
-    Div8,
-    Div10,
-    Div12,
-    Div14,
-    Div16,
-    Div18,
-    Div20,
-    Div22,
-    Div24,
-    Div26,
-    Div28,
-    Div30,
-}
-
-/// Master clock divider.
-#[derive(Copy, Clone, PartialEq)]
-#[allow(missing_docs)]
-#[cfg(any(sai_v1_4pdm, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
-pub enum MasterClockDivider {
-    MasterClockDisabled,
-    Div1,
-    Div2,
-    Div3,
-    Div4,
-    Div5,
-    Div6,
-    Div7,
-    Div8,
-    Div9,
-    Div10,
-    Div11,
-    Div12,
-    Div13,
-    Div14,
-    Div15,
-    Div16,
-    Div17,
-    Div18,
-    Div19,
-    Div20,
-    Div21,
-    Div22,
-    Div23,
-    Div24,
-    Div25,
-    Div26,
-    Div27,
-    Div28,
-    Div29,
-    Div30,
-    Div31,
-    Div32,
-    Div33,
-    Div34,
-    Div35,
-    Div36,
-    Div37,
-    Div38,
-    Div39,
-    Div40,
-    Div41,
-    Div42,
-    Div43,
-    Div44,
-    Div45,
-    Div46,
-    Div47,
-    Div48,
-    Div49,
-    Div50,
-    Div51,
-    Div52,
-    Div53,
-    Div54,
-    Div55,
-    Div56,
-    Div57,
-    Div58,
-    Div59,
-    Div60,
-    Div61,
-    Div62,
-    Div63,
-}
-
-impl MasterClockDivider {
-    #[cfg(any(sai_v1, sai_v2))]
-    const fn mckdiv(&self) -> u8 {
-        match self {
-            MasterClockDivider::MasterClockDisabled => 0,
-            MasterClockDivider::Div1 => 0,
-            MasterClockDivider::Div2 => 1,
-            MasterClockDivider::Div4 => 2,
-            MasterClockDivider::Div6 => 3,
-            MasterClockDivider::Div8 => 4,
-            MasterClockDivider::Div10 => 5,
-            MasterClockDivider::Div12 => 6,
-            MasterClockDivider::Div14 => 7,
-            MasterClockDivider::Div16 => 8,
-            MasterClockDivider::Div18 => 9,
-            MasterClockDivider::Div20 => 10,
-            MasterClockDivider::Div22 => 11,
-            MasterClockDivider::Div24 => 12,
-            MasterClockDivider::Div26 => 13,
-            MasterClockDivider::Div28 => 14,
-            MasterClockDivider::Div30 => 15,
-        }
-    }
-
-    #[cfg(any(sai_v1_4pdm, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
-    const fn mckdiv(&self) -> u8 {
-        match self {
-            MasterClockDivider::MasterClockDisabled => 0,
-            MasterClockDivider::Div1 => 1,
-            MasterClockDivider::Div2 => 2,
-            MasterClockDivider::Div3 => 3,
-            MasterClockDivider::Div4 => 4,
-            MasterClockDivider::Div5 => 5,
-            MasterClockDivider::Div6 => 6,
-            MasterClockDivider::Div7 => 7,
-            MasterClockDivider::Div8 => 8,
-            MasterClockDivider::Div9 => 9,
-            MasterClockDivider::Div10 => 10,
-            MasterClockDivider::Div11 => 11,
-            MasterClockDivider::Div12 => 12,
-            MasterClockDivider::Div13 => 13,
-            MasterClockDivider::Div14 => 14,
-            MasterClockDivider::Div15 => 15,
-            MasterClockDivider::Div16 => 16,
-            MasterClockDivider::Div17 => 17,
-            MasterClockDivider::Div18 => 18,
-            MasterClockDivider::Div19 => 19,
-            MasterClockDivider::Div20 => 20,
-            MasterClockDivider::Div21 => 21,
-            MasterClockDivider::Div22 => 22,
-            MasterClockDivider::Div23 => 23,
-            MasterClockDivider::Div24 => 24,
-            MasterClockDivider::Div25 => 25,
-            MasterClockDivider::Div26 => 26,
-            MasterClockDivider::Div27 => 27,
-            MasterClockDivider::Div28 => 28,
-            MasterClockDivider::Div29 => 29,
-            MasterClockDivider::Div30 => 30,
-            MasterClockDivider::Div31 => 31,
-            MasterClockDivider::Div32 => 32,
-            MasterClockDivider::Div33 => 33,
-            MasterClockDivider::Div34 => 34,
-            MasterClockDivider::Div35 => 35,
-            MasterClockDivider::Div36 => 36,
-            MasterClockDivider::Div37 => 37,
-            MasterClockDivider::Div38 => 38,
-            MasterClockDivider::Div39 => 39,
-            MasterClockDivider::Div40 => 40,
-            MasterClockDivider::Div41 => 41,
-            MasterClockDivider::Div42 => 42,
-            MasterClockDivider::Div43 => 43,
-            MasterClockDivider::Div44 => 44,
-            MasterClockDivider::Div45 => 45,
-            MasterClockDivider::Div46 => 46,
-            MasterClockDivider::Div47 => 47,
-            MasterClockDivider::Div48 => 48,
-            MasterClockDivider::Div49 => 49,
-            MasterClockDivider::Div50 => 50,
-            MasterClockDivider::Div51 => 51,
-            MasterClockDivider::Div52 => 52,
-            MasterClockDivider::Div53 => 53,
-            MasterClockDivider::Div54 => 54,
-            MasterClockDivider::Div55 => 55,
-            MasterClockDivider::Div56 => 56,
-            MasterClockDivider::Div57 => 57,
-            MasterClockDivider::Div58 => 58,
-            MasterClockDivider::Div59 => 59,
-            MasterClockDivider::Div60 => 60,
-            MasterClockDivider::Div61 => 61,
-            MasterClockDivider::Div62 => 62,
-            MasterClockDivider::Div63 => 63,
-        }
-    }
-}
-
 /// [`SAI`] configuration.
 #[allow(missing_docs)]
 #[non_exhaustive]
@@ -601,8 +394,7 @@ pub struct Config {
     pub frame_length: u8,
     pub clock_strobe: ClockStrobe,
     pub output_drive: OutputDrive,
-    pub master_clock_divider: MasterClockDivider,
-    pub nodiv: bool,
+    pub master_clock_divider: Option<MasterClockDivider>,
     pub is_high_impedance_on_inactive_slot: bool,
     pub fifo_threshold: FifoThreshold,
     pub companding: Companding,
@@ -631,8 +423,7 @@ impl Default for Config {
             frame_sync_active_level_length: word::U7(16),
             frame_sync_definition: FrameSyncDefinition::ChannelIdentification,
             frame_length: 32,
-            master_clock_divider: MasterClockDivider::MasterClockDisabled,
-            nodiv: false,
+            master_clock_divider: None,
             clock_strobe: ClockStrobe::Rising,
             output_drive: OutputDrive::Immediately,
             is_high_impedance_on_inactive_slot: false,
@@ -652,7 +443,6 @@ impl Config {
     }
 }
 
-#[cfg(not(gpdma))]
 enum RingBuffer<'d, W: word::Word> {
     Writable(WritableRingBuffer<'d, W>),
     Readable(ReadableRingBuffer<'d, W>),
@@ -679,7 +469,6 @@ fn get_af_types(mode: Mode, tx_rx: TxRx) -> (AfType, AfType) {
     )
 }
 
-#[cfg(not(gpdma))]
 fn get_ring_buffer<'d, T: Instance, W: word::Word>(
     dma: Peri<'d, impl Channel>,
     dma_buf: &'d mut [W],
@@ -711,7 +500,7 @@ fn update_synchronous_config(config: &mut Config) {
         config.sync_input = SyncInput::Internal;
     }
 
-    #[cfg(any(sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
+    #[cfg(any(sai_v3, sai_v4))]
     {
         //this must either be Internal or External
         //The asynchronous sub-block on the same SAI needs to enable sync_output
@@ -750,14 +539,10 @@ pub struct Sai<'d, T: Instance, W: word::Word> {
     fs: Option<Peri<'d, AnyPin>>,
     sck: Option<Peri<'d, AnyPin>>,
     mclk: Option<Peri<'d, AnyPin>>,
-    #[cfg(gpdma)]
-    ring_buffer: PhantomData<W>,
-    #[cfg(not(gpdma))]
     ring_buffer: RingBuffer<'d, W>,
     sub_block: WhichSubBlock,
 }
 
-#[cfg(not(gpdma))]
 impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
     /// Create a new SAI driver in asynchronous mode with MCLK.
     ///
@@ -770,14 +555,10 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
         mclk: Peri<'d, impl MclkPin<T, S>>,
         dma: Peri<'d, impl Channel + Dma<T, S>>,
         dma_buf: &'d mut [W],
-        mut config: Config,
+        config: Config,
     ) -> Self {
         let (_sd_af_type, ck_af_type) = get_af_types(config.mode, config.tx_rx);
-        mclk.set_as_af(mclk.af_num(), ck_af_type);
-
-        if config.master_clock_divider == MasterClockDivider::MasterClockDisabled {
-            config.master_clock_divider = MasterClockDivider::Div1;
-        }
+        set_as_af!(mclk, ck_af_type);
 
         Self::new_asynchronous(peri, sck, sd, fs, dma, dma_buf, config)
     }
@@ -797,9 +578,9 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
         let peri = peri.peri;
 
         let (sd_af_type, ck_af_type) = get_af_types(config.mode, config.tx_rx);
-        sd.set_as_af(sd.af_num(), sd_af_type);
-        sck.set_as_af(sck.af_num(), ck_af_type);
-        fs.set_as_af(fs.af_num(), ck_af_type);
+        set_as_af!(sd, sd_af_type);
+        set_as_af!(sck, ck_af_type);
+        set_as_af!(fs, ck_af_type);
 
         let sub_block = S::WHICH;
         let request = dma.request();
@@ -831,7 +612,7 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
         let peri = peri.peri;
 
         let (sd_af_type, _ck_af_type) = get_af_types(config.mode, config.tx_rx);
-        sd.set_as_af(sd.af_num(), sd_af_type);
+        set_as_af!(sd, sd_af_type);
 
         let sub_block = S::WHICH;
         let request = dma.request();
@@ -860,14 +641,11 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
     ) -> Self {
         let ch = T::REGS.ch(sub_block as usize);
 
-        #[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
-        {
-            ch.cr1().modify(|w| w.set_saien(false));
-        }
+        ch.cr1().modify(|w| w.set_saien(false));
 
         ch.cr2().modify(|w| w.set_fflush(true));
 
-        #[cfg(any(sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
+        #[cfg(any(sai_v3, sai_v4))]
         {
             if let SyncInput::External(i) = config.sync_input {
                 T::REGS.gcr().modify(|w| {
@@ -886,55 +664,52 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
             }
         }
 
-        #[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
-        {
-            ch.cr1().modify(|w| {
-                w.set_mode(config.mode.mode(if Self::is_transmitter(&ring_buffer) {
-                    TxRx::Transmitter
-                } else {
-                    TxRx::Receiver
-                }));
-                w.set_prtcfg(config.protocol.prtcfg());
-                w.set_ds(config.data_size.ds());
-                w.set_lsbfirst(config.bit_order.lsbfirst());
-                w.set_ckstr(config.clock_strobe.ckstr());
-                w.set_syncen(config.sync_input.syncen());
-                w.set_mono(config.stereo_mono.mono());
-                w.set_outdriv(config.output_drive.outdriv());
-                w.set_mckdiv(config.master_clock_divider.mckdiv().into());
-                w.set_nodiv(config.nodiv);
-                w.set_dmaen(true);
-            });
-
-            ch.cr2().modify(|w| {
-                w.set_fth(config.fifo_threshold.fth());
-                w.set_comp(config.companding.comp());
-                w.set_cpl(config.complement_format.cpl());
-                w.set_muteval(config.mute_value.muteval());
-                w.set_mutecnt(config.mute_detection_counter.0 as u8);
-                w.set_tris(config.is_high_impedance_on_inactive_slot);
-            });
-
-            ch.frcr().modify(|w| {
-                w.set_fsoff(config.frame_sync_offset.fsoff());
-                w.set_fspol(config.frame_sync_polarity.fspol());
-                w.set_fsdef(config.frame_sync_definition.fsdef());
-                w.set_fsall(config.frame_sync_active_level_length.0 as u8 - 1);
-                w.set_frl(config.frame_length - 1);
-            });
-
-            ch.slotr().modify(|w| {
-                w.set_nbslot(config.slot_count.0 as u8 - 1);
-                w.set_slotsz(config.slot_size.slotsz());
-                w.set_fboff(config.first_bit_offset.0 as u8);
-                w.set_sloten(vals::Sloten::from_bits(config.slot_enable as u16));
-            });
-
-            ch.cr1().modify(|w| w.set_saien(true));
-
-            if ch.cr1().read().saien() == false {
-                panic!("SAI failed to enable. Check that config is valid (frame length, slot count, etc)");
-            }
+        ch.cr1().modify(|w| {
+            w.set_mode(config.mode.mode(if Self::is_transmitter(&ring_buffer) {
+                TxRx::Transmitter
+            } else {
+                TxRx::Receiver
+            }));
+            w.set_prtcfg(config.protocol.prtcfg());
+            w.set_ds(config.data_size.ds());
+            w.set_lsbfirst(config.bit_order.lsbfirst());
+            w.set_ckstr(config.clock_strobe.ckstr());
+            w.set_syncen(config.sync_input.syncen());
+            w.set_mono(config.stereo_mono.mono());
+            w.set_outdriv(config.output_drive.outdriv());
+            w.set_mckdiv(config.master_clock_divider.unwrap_or(MasterClockDivider::DIV1));
+            w.set_nodiv(config.master_clock_divider.is_none());
+            w.set_dmaen(true);
+        });
+
+        ch.cr2().modify(|w| {
+            w.set_fth(config.fifo_threshold.fth());
+            w.set_comp(config.companding.comp());
+            w.set_cpl(config.complement_format.cpl());
+            w.set_muteval(config.mute_value.muteval());
+            w.set_mutecnt(config.mute_detection_counter.0 as u8);
+            w.set_tris(config.is_high_impedance_on_inactive_slot);
+        });
+
+        ch.frcr().modify(|w| {
+            w.set_fsoff(config.frame_sync_offset.fsoff());
+            w.set_fspol(config.frame_sync_polarity.fspol());
+            w.set_fsdef(config.frame_sync_definition.fsdef());
+            w.set_fsall(config.frame_sync_active_level_length.0 as u8 - 1);
+            w.set_frl(config.frame_length - 1);
+        });
+
+        ch.slotr().modify(|w| {
+            w.set_nbslot(config.slot_count.0 as u8 - 1);
+            w.set_slotsz(config.slot_size.slotsz());
+            w.set_fboff(config.first_bit_offset.0 as u8);
+            w.set_sloten(vals::Sloten::from_bits(config.slot_enable as u16));
+        });
+
+        ch.cr1().modify(|w| w.set_saien(true));
+
+        if ch.cr1().read().saien() == false {
+            panic!("SAI failed to enable. Check that config is valid (frame length, slot count, etc)");
         }
 
         Self {
diff --git a/embassy-stm32/src/sdmmc/mod.rs b/embassy-stm32/src/sdmmc/mod.rs
index 6e5d735d7..ccbd16cbf 100644
--- a/embassy-stm32/src/sdmmc/mod.rs
+++ b/embassy-stm32/src/sdmmc/mod.rs
@@ -428,9 +428,9 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
         config: Config,
     ) -> Self {
         critical_section::with(|_| {
-            clk.set_as_af(clk.af_num(), CLK_AF);
-            cmd.set_as_af(cmd.af_num(), CMD_AF);
-            d0.set_as_af(d0.af_num(), DATA_AF);
+            set_as_af!(clk, CLK_AF);
+            set_as_af!(cmd, CMD_AF);
+            set_as_af!(d0, DATA_AF);
         });
 
         Self::new_inner(
@@ -464,12 +464,12 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
         config: Config,
     ) -> Self {
         critical_section::with(|_| {
-            clk.set_as_af(clk.af_num(), CLK_AF);
-            cmd.set_as_af(cmd.af_num(), CMD_AF);
-            d0.set_as_af(d0.af_num(), DATA_AF);
-            d1.set_as_af(d1.af_num(), DATA_AF);
-            d2.set_as_af(d2.af_num(), DATA_AF);
-            d3.set_as_af(d3.af_num(), DATA_AF);
+            set_as_af!(clk, CLK_AF);
+            set_as_af!(cmd, CMD_AF);
+            set_as_af!(d0, DATA_AF);
+            set_as_af!(d1, DATA_AF);
+            set_as_af!(d2, DATA_AF);
+            set_as_af!(d3, DATA_AF);
         });
 
         Self::new_inner(
@@ -510,16 +510,16 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
         config: Config,
     ) -> Self {
         critical_section::with(|_| {
-            clk.set_as_af(clk.af_num(), CLK_AF);
-            cmd.set_as_af(cmd.af_num(), CMD_AF);
-            d0.set_as_af(d0.af_num(), DATA_AF);
-            d1.set_as_af(d1.af_num(), DATA_AF);
-            d2.set_as_af(d2.af_num(), DATA_AF);
-            d3.set_as_af(d3.af_num(), DATA_AF);
-            d4.set_as_af(d4.af_num(), DATA_AF);
-            d5.set_as_af(d5.af_num(), DATA_AF);
-            d6.set_as_af(d6.af_num(), DATA_AF);
-            d7.set_as_af(d7.af_num(), DATA_AF);
+            set_as_af!(clk, CLK_AF);
+            set_as_af!(cmd, CMD_AF);
+            set_as_af!(d0, DATA_AF);
+            set_as_af!(d1, DATA_AF);
+            set_as_af!(d2, DATA_AF);
+            set_as_af!(d3, DATA_AF);
+            set_as_af!(d4, DATA_AF);
+            set_as_af!(d5, DATA_AF);
+            set_as_af!(d6, DATA_AF);
+            set_as_af!(d7, DATA_AF);
         });
 
         Self::new_inner(
@@ -552,9 +552,9 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
         config: Config,
     ) -> Self {
         critical_section::with(|_| {
-            clk.set_as_af(clk.af_num(), CLK_AF);
-            cmd.set_as_af(cmd.af_num(), CMD_AF);
-            d0.set_as_af(d0.af_num(), DATA_AF);
+            set_as_af!(clk, CLK_AF);
+            set_as_af!(cmd, CMD_AF);
+            set_as_af!(d0, DATA_AF);
         });
 
         Self::new_inner(
@@ -586,12 +586,12 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
         config: Config,
     ) -> Self {
         critical_section::with(|_| {
-            clk.set_as_af(clk.af_num(), CLK_AF);
-            cmd.set_as_af(cmd.af_num(), CMD_AF);
-            d0.set_as_af(d0.af_num(), DATA_AF);
-            d1.set_as_af(d1.af_num(), DATA_AF);
-            d2.set_as_af(d2.af_num(), DATA_AF);
-            d3.set_as_af(d3.af_num(), DATA_AF);
+            set_as_af!(clk, CLK_AF);
+            set_as_af!(cmd, CMD_AF);
+            set_as_af!(d0, DATA_AF);
+            set_as_af!(d1, DATA_AF);
+            set_as_af!(d2, DATA_AF);
+            set_as_af!(d3, DATA_AF);
         });
 
         Self::new_inner(
@@ -630,16 +630,16 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
         config: Config,
     ) -> Self {
         critical_section::with(|_| {
-            clk.set_as_af(clk.af_num(), CLK_AF);
-            cmd.set_as_af(cmd.af_num(), CMD_AF);
-            d0.set_as_af(d0.af_num(), DATA_AF);
-            d1.set_as_af(d1.af_num(), DATA_AF);
-            d2.set_as_af(d2.af_num(), DATA_AF);
-            d3.set_as_af(d3.af_num(), DATA_AF);
-            d4.set_as_af(d4.af_num(), DATA_AF);
-            d5.set_as_af(d5.af_num(), DATA_AF);
-            d6.set_as_af(d6.af_num(), DATA_AF);
-            d7.set_as_af(d7.af_num(), DATA_AF);
+            set_as_af!(clk, CLK_AF);
+            set_as_af!(cmd, CMD_AF);
+            set_as_af!(d0, DATA_AF);
+            set_as_af!(d1, DATA_AF);
+            set_as_af!(d2, DATA_AF);
+            set_as_af!(d3, DATA_AF);
+            set_as_af!(d4, DATA_AF);
+            set_as_af!(d5, DATA_AF);
+            set_as_af!(d6, DATA_AF);
+            set_as_af!(d7, DATA_AF);
         });
 
         Self::new_inner(
diff --git a/embassy-stm32/src/spdifrx/mod.rs b/embassy-stm32/src/spdifrx/mod.rs
index 9c42217f0..b0a32d5d1 100644
--- a/embassy-stm32/src/spdifrx/mod.rs
+++ b/embassy-stm32/src/spdifrx/mod.rs
@@ -8,9 +8,7 @@ use embassy_sync::waitqueue::AtomicWaker;
 
 use crate::dma::ringbuffer::Error as RingbufferError;
 pub use crate::dma::word;
-#[cfg(not(gpdma))]
-use crate::dma::ReadableRingBuffer;
-use crate::dma::{Channel, TransferOptions};
+use crate::dma::{Channel, ReadableRingBuffer, TransferOptions};
 use crate::gpio::{AfType, AnyPin, Pull, SealedPin as _};
 use crate::interrupt::typelevel::Interrupt;
 use crate::pac::spdifrx::Spdifrx as Regs;
@@ -37,7 +35,7 @@ macro_rules! new_spdifrx_pin {
     ($name:ident, $af_type:expr) => {{
         let pin = $name;
         let input_sel = pin.input_sel();
-        pin.set_as_af(pin.af_num(), $af_type);
+        set_as_af!(pin, $af_type);
         (Some(pin.into()), input_sel)
     }};
 }
@@ -58,7 +56,6 @@ macro_rules! impl_spdifrx_pin {
 /// Ring-buffered SPDIFRX driver.
 ///
 /// Data is read by DMAs and stored in a ring buffer.
-#[cfg(not(gpdma))]
 pub struct Spdifrx<'d, T: Instance> {
     _peri: Peri<'d, T>,
     spdifrx_in: Option<Peri<'d, AnyPin>>,
@@ -118,7 +115,6 @@ impl Default for Config {
     }
 }
 
-#[cfg(not(gpdma))]
 impl<'d, T: Instance> Spdifrx<'d, T> {
     fn dma_opts() -> TransferOptions {
         TransferOptions {
@@ -236,7 +232,6 @@ impl<'d, T: Instance> Spdifrx<'d, T> {
     }
 }
 
-#[cfg(not(gpdma))]
 impl<'d, T: Instance> Drop for Spdifrx<'d, T> {
     fn drop(&mut self) {
         T::info().regs.cr().modify(|cr| cr.set_spdifen(0x00));
diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs
index 4c5308eba..c5373a54d 100644
--- a/embassy-stm32/src/spi/mod.rs
+++ b/embassy-stm32/src/spi/mod.rs
@@ -174,7 +174,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
         self.info.rcc.enable_and_reset();
 
         let regs = self.info.regs;
-        #[cfg(any(spi_v1, spi_f1))]
+        #[cfg(any(spi_v1, spi_v2))]
         {
             regs.cr2().modify(|w| {
                 w.set_ssoe(false);
@@ -198,7 +198,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
                 w.set_dff(<u8 as SealedWord>::CONFIG)
             });
         }
-        #[cfg(spi_v2)]
+        #[cfg(spi_v3)]
         {
             regs.cr2().modify(|w| {
                 let (ds, frxth) = <u8 as SealedWord>::CONFIG;
@@ -220,7 +220,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
                 w.set_spe(true);
             });
         }
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         {
             regs.ifcr().write(|w| w.0 = 0xffff_ffff);
             regs.cfg2().modify(|w| {
@@ -274,7 +274,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
             }
         }
 
-        #[cfg(any(spi_v1, spi_f1, spi_v2))]
+        #[cfg(any(spi_v1, spi_v2, spi_v3))]
         self.info.regs.cr1().modify(|w| {
             w.set_cpha(cpha);
             w.set_cpol(cpol);
@@ -282,7 +282,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
             w.set_lsbfirst(lsbfirst);
         });
 
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         {
             self.info.regs.cr1().modify(|w| {
                 w.set_spe(false);
@@ -306,11 +306,11 @@ impl<'d, M: PeriMode> Spi<'d, M> {
 
     /// Get current SPI configuration.
     pub fn get_current_config(&self) -> Config {
-        #[cfg(any(spi_v1, spi_f1, spi_v2))]
+        #[cfg(any(spi_v1, spi_v2, spi_v3))]
         let cfg = self.info.regs.cr1().read();
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         let cfg = self.info.regs.cfg2().read();
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         let cfg1 = self.info.regs.cfg1().read();
 
         let polarity = if cfg.cpol() == vals::Cpol::IDLE_LOW {
@@ -335,9 +335,9 @@ impl<'d, M: PeriMode> Spi<'d, M> {
             Some(pin) => pin.pull(),
         };
 
-        #[cfg(any(spi_v1, spi_f1, spi_v2))]
+        #[cfg(any(spi_v1, spi_v2, spi_v3))]
         let br = cfg.br();
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         let br = cfg1.mbr();
 
         let frequency = compute_frequency(self.kernel_clock, br);
@@ -360,16 +360,16 @@ impl<'d, M: PeriMode> Spi<'d, M> {
             w.set_spe(false);
         });
 
-        #[cfg(any(spi_v1, spi_f1))]
+        #[cfg(any(spi_v1, spi_v2))]
         self.info.regs.cr1().modify(|reg| {
             reg.set_dff(word_size);
         });
-        #[cfg(spi_v2)]
+        #[cfg(spi_v3)]
         self.info.regs.cr2().modify(|w| {
             w.set_frxth(word_size.1);
             w.set_ds(word_size.0);
         });
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         self.info.regs.cfg1().modify(|w| {
             w.set_dsize(word_size);
         });
@@ -380,7 +380,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
     /// Blocking write.
     pub fn blocking_write<W: Word>(&mut self, words: &[W]) -> Result<(), Error> {
         // needed in v3+ to avoid overrun causing the SPI RX state machine to get stuck...?
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         self.info.regs.cr1().modify(|w| w.set_spe(false));
         self.set_word_size(W::CONFIG);
         self.info.regs.cr1().modify(|w| w.set_spe(true));
@@ -391,7 +391,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
             // This is the case when the SPI has been created with `new_(blocking_?)txonly_nosck`.
             // See https://github.com/embassy-rs/embassy/issues/2902
             // This is not documented as an errata by ST, and I've been unable to find anything online...
-            #[cfg(not(any(spi_v1, spi_f1)))]
+            #[cfg(not(any(spi_v1, spi_v2)))]
             write_word(self.info.regs, *word)?;
 
             // if we're doing tx only, after writing the last byte to FIFO we have to wait
@@ -401,14 +401,14 @@ impl<'d, M: PeriMode> Spi<'d, M> {
             // Luckily this doesn't affect SPIv2+.
             // See http://efton.sk/STM32/gotcha/g68.html
             // ST doesn't seem to document this in errata sheets (?)
-            #[cfg(any(spi_v1, spi_f1))]
+            #[cfg(any(spi_v1, spi_v2))]
             transfer_word(self.info.regs, *word)?;
         }
 
         // wait until last word is transmitted. (except on v1, see above)
-        #[cfg(not(any(spi_v1, spi_f1, spi_v2)))]
+        #[cfg(not(any(spi_v1, spi_v2, spi_v3)))]
         while !self.info.regs.sr().read().txc() {}
-        #[cfg(spi_v2)]
+        #[cfg(spi_v3)]
         while self.info.regs.sr().read().bsy() {}
 
         Ok(())
@@ -417,7 +417,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
     /// Blocking read.
     pub fn blocking_read<W: Word>(&mut self, words: &mut [W]) -> Result<(), Error> {
         // needed in v3+ to avoid overrun causing the SPI RX state machine to get stuck...?
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         self.info.regs.cr1().modify(|w| w.set_spe(false));
         self.set_word_size(W::CONFIG);
         self.info.regs.cr1().modify(|w| w.set_spe(true));
@@ -433,7 +433,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
     /// This writes the contents of `data` on MOSI, and puts the received data on MISO in `data`, at the same time.
     pub fn blocking_transfer_in_place<W: Word>(&mut self, words: &mut [W]) -> Result<(), Error> {
         // needed in v3+ to avoid overrun causing the SPI RX state machine to get stuck...?
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         self.info.regs.cr1().modify(|w| w.set_spe(false));
         self.set_word_size(W::CONFIG);
         self.info.regs.cr1().modify(|w| w.set_spe(true));
@@ -452,7 +452,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
     /// If `write` is shorter it is padded with zero bytes.
     pub fn blocking_transfer<W: Word>(&mut self, read: &mut [W], write: &[W]) -> Result<(), Error> {
         // needed in v3+ to avoid overrun causing the SPI RX state machine to get stuck...?
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         self.info.regs.cr1().modify(|w| w.set_spe(false));
         self.set_word_size(W::CONFIG);
         self.info.regs.cr1().modify(|w| w.set_spe(true));
@@ -471,11 +471,11 @@ impl<'d, M: PeriMode> Spi<'d, M> {
 
 impl<'d> Spi<'d, Blocking> {
     /// Create a new blocking SPI driver.
-    pub fn new_blocking<T: Instance>(
+    pub fn new_blocking<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        sck: Peri<'d, impl SckPin<T>>,
-        mosi: Peri<'d, impl MosiPin<T>>,
-        miso: Peri<'d, impl MisoPin<T>>,
+        sck: Peri<'d, if_afio!(impl SckPin<T, A>)>,
+        mosi: Peri<'d, if_afio!(impl MosiPin<T, A>)>,
+        miso: Peri<'d, if_afio!(impl MisoPin<T, A>)>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -490,10 +490,10 @@ impl<'d> Spi<'d, Blocking> {
     }
 
     /// Create a new blocking SPI driver, in RX-only mode (only MISO pin, no MOSI).
-    pub fn new_blocking_rxonly<T: Instance>(
+    pub fn new_blocking_rxonly<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        sck: Peri<'d, impl SckPin<T>>,
-        miso: Peri<'d, impl MisoPin<T>>,
+        sck: Peri<'d, if_afio!(impl SckPin<T, A>)>,
+        miso: Peri<'d, if_afio!(impl MisoPin<T, A>)>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -508,10 +508,10 @@ impl<'d> Spi<'d, Blocking> {
     }
 
     /// Create a new blocking SPI driver, in TX-only mode (only MOSI pin, no MISO).
-    pub fn new_blocking_txonly<T: Instance>(
+    pub fn new_blocking_txonly<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        sck: Peri<'d, impl SckPin<T>>,
-        mosi: Peri<'d, impl MosiPin<T>>,
+        sck: Peri<'d, if_afio!(impl SckPin<T, A>)>,
+        mosi: Peri<'d, if_afio!(impl MosiPin<T, A>)>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -528,9 +528,9 @@ impl<'d> Spi<'d, Blocking> {
     /// Create a new SPI driver, in TX-only mode, without SCK pin.
     ///
     /// This can be useful for bit-banging non-SPI protocols.
-    pub fn new_blocking_txonly_nosck<T: Instance>(
+    pub fn new_blocking_txonly_nosck<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        mosi: Peri<'d, impl MosiPin<T>>,
+        mosi: Peri<'d, if_afio!(impl MosiPin<T, A>)>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -547,11 +547,11 @@ impl<'d> Spi<'d, Blocking> {
 
 impl<'d> Spi<'d, Async> {
     /// Create a new SPI driver.
-    pub fn new<T: Instance>(
+    pub fn new<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        sck: Peri<'d, impl SckPin<T>>,
-        mosi: Peri<'d, impl MosiPin<T>>,
-        miso: Peri<'d, impl MisoPin<T>>,
+        sck: Peri<'d, if_afio!(impl SckPin<T, A>)>,
+        mosi: Peri<'d, if_afio!(impl MosiPin<T, A>)>,
+        miso: Peri<'d, if_afio!(impl MisoPin<T, A>)>,
         tx_dma: Peri<'d, impl TxDma<T>>,
         rx_dma: Peri<'d, impl RxDma<T>>,
         config: Config,
@@ -568,11 +568,11 @@ impl<'d> Spi<'d, Async> {
     }
 
     /// Create a new SPI driver, in RX-only mode (only MISO pin, no MOSI).
-    pub fn new_rxonly<T: Instance>(
+    pub fn new_rxonly<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        sck: Peri<'d, impl SckPin<T>>,
-        miso: Peri<'d, impl MisoPin<T>>,
-        #[cfg(any(spi_v1, spi_f1, spi_v2))] tx_dma: Peri<'d, impl TxDma<T>>,
+        sck: Peri<'d, if_afio!(impl SckPin<T, A>)>,
+        miso: Peri<'d, if_afio!(impl MisoPin<T, A>)>,
+        #[cfg(any(spi_v1, spi_v2, spi_v3))] tx_dma: Peri<'d, impl TxDma<T>>,
         rx_dma: Peri<'d, impl RxDma<T>>,
         config: Config,
     ) -> Self {
@@ -581,9 +581,9 @@ impl<'d> Spi<'d, Async> {
             new_pin!(sck, config.sck_af()),
             None,
             new_pin!(miso, AfType::input(config.miso_pull)),
-            #[cfg(any(spi_v1, spi_f1, spi_v2))]
+            #[cfg(any(spi_v1, spi_v2, spi_v3))]
             new_dma!(tx_dma),
-            #[cfg(any(spi_v3, spi_v4, spi_v5))]
+            #[cfg(any(spi_v4, spi_v5, spi_v6))]
             None,
             new_dma!(rx_dma),
             config,
@@ -591,10 +591,10 @@ impl<'d> Spi<'d, Async> {
     }
 
     /// Create a new SPI driver, in TX-only mode (only MOSI pin, no MISO).
-    pub fn new_txonly<T: Instance>(
+    pub fn new_txonly<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        sck: Peri<'d, impl SckPin<T>>,
-        mosi: Peri<'d, impl MosiPin<T>>,
+        sck: Peri<'d, if_afio!(impl SckPin<T, A>)>,
+        mosi: Peri<'d, if_afio!(impl MosiPin<T, A>)>,
         tx_dma: Peri<'d, impl TxDma<T>>,
         config: Config,
     ) -> Self {
@@ -612,9 +612,9 @@ impl<'d> Spi<'d, Async> {
     /// Create a new SPI driver, in TX-only mode, without SCK pin.
     ///
     /// This can be useful for bit-banging non-SPI protocols.
-    pub fn new_txonly_nosck<T: Instance>(
+    pub fn new_txonly_nosck<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        mosi: Peri<'d, impl MosiPin<T>>,
+        mosi: Peri<'d, if_afio!(impl MosiPin<T, A>)>,
         tx_dma: Peri<'d, impl TxDma<T>>,
         config: Config,
     ) -> Self {
@@ -677,7 +677,7 @@ impl<'d> Spi<'d, Async> {
         self.info.regs.cr1().modify(|w| {
             w.set_spe(true);
         });
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         self.info.regs.cr1().modify(|w| {
             w.set_cstart(true);
         });
@@ -690,7 +690,7 @@ impl<'d> Spi<'d, Async> {
     }
 
     /// SPI read, using DMA.
-    #[cfg(any(spi_v3, spi_v4, spi_v5))]
+    #[cfg(any(spi_v4, spi_v5, spi_v6))]
     pub async fn read<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error> {
         if data.is_empty() {
             return Ok(());
@@ -710,7 +710,7 @@ impl<'d> Spi<'d, Async> {
             prev
         });
 
-        #[cfg(spi_v3)]
+        #[cfg(spi_v4)]
         let i2scfg = regs.i2scfgr().modify(|w| {
             w.i2smod().then(|| {
                 let prev = w.i2scfg();
@@ -766,7 +766,7 @@ impl<'d> Spi<'d, Async> {
             w.set_tsize(0);
         });
 
-        #[cfg(spi_v3)]
+        #[cfg(spi_v4)]
         if let Some(i2scfg) = i2scfg {
             regs.i2scfgr().modify(|w| {
                 w.set_i2scfg(i2scfg);
@@ -777,7 +777,7 @@ impl<'d> Spi<'d, Async> {
     }
 
     /// SPI read, using DMA.
-    #[cfg(any(spi_v1, spi_f1, spi_v2))]
+    #[cfg(any(spi_v1, spi_v2, spi_v3))]
     pub async fn read<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error> {
         if data.is_empty() {
             return Ok(());
@@ -790,7 +790,7 @@ impl<'d> Spi<'d, Async> {
         self.set_word_size(W::CONFIG);
 
         // SPIv3 clears rxfifo on SPE=0
-        #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
+        #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
         flush_rx_fifo(self.info.regs);
 
         set_rxdmaen(self.info.regs, true);
@@ -813,7 +813,7 @@ impl<'d> Spi<'d, Async> {
         self.info.regs.cr1().modify(|w| {
             w.set_spe(true);
         });
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         self.info.regs.cr1().modify(|w| {
             w.set_cstart(true);
         });
@@ -838,7 +838,7 @@ impl<'d> Spi<'d, Async> {
         self.set_word_size(W::CONFIG);
 
         // SPIv3 clears rxfifo on SPE=0
-        #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
+        #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
         flush_rx_fifo(self.info.regs);
 
         set_rxdmaen(self.info.regs, true);
@@ -858,7 +858,7 @@ impl<'d> Spi<'d, Async> {
         self.info.regs.cr1().modify(|w| {
             w.set_spe(true);
         });
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         self.info.regs.cr1().modify(|w| {
             w.set_cstart(true);
         });
@@ -898,9 +898,9 @@ impl<'d, M: PeriMode> Drop for Spi<'d, M> {
     }
 }
 
-#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
+#[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
 use vals::Br;
-#[cfg(any(spi_v3, spi_v4, spi_v5))]
+#[cfg(any(spi_v4, spi_v5, spi_v6))]
 use vals::Mbr as Br;
 
 fn compute_baud_rate(kernel_clock: Hertz, freq: Hertz) -> Br {
@@ -941,21 +941,21 @@ pub(crate) trait RegsExt {
 
 impl RegsExt for Regs {
     fn tx_ptr<W>(&self) -> *mut W {
-        #[cfg(any(spi_v1, spi_f1))]
+        #[cfg(any(spi_v1, spi_v2))]
         let dr = self.dr();
-        #[cfg(spi_v2)]
+        #[cfg(spi_v3)]
         let dr = self.dr16();
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         let dr = self.txdr32();
         dr.as_ptr() as *mut W
     }
 
     fn rx_ptr<W>(&self) -> *mut W {
-        #[cfg(any(spi_v1, spi_f1))]
+        #[cfg(any(spi_v1, spi_v2))]
         let dr = self.dr();
-        #[cfg(spi_v2)]
+        #[cfg(spi_v3)]
         let dr = self.dr16();
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         let dr = self.rxdr32();
         dr.as_ptr() as *mut W
     }
@@ -965,22 +965,22 @@ fn check_error_flags(sr: regs::Sr, ovr: bool) -> Result<(), Error> {
     if sr.ovr() && ovr {
         return Err(Error::Overrun);
     }
-    #[cfg(not(any(spi_f1, spi_v3, spi_v4, spi_v5)))]
+    #[cfg(not(any(spi_v1, spi_v4, spi_v5, spi_v6)))]
     if sr.fre() {
         return Err(Error::Framing);
     }
-    #[cfg(any(spi_v3, spi_v4, spi_v5))]
+    #[cfg(any(spi_v4, spi_v5, spi_v6))]
     if sr.tifre() {
         return Err(Error::Framing);
     }
     if sr.modf() {
         return Err(Error::ModeFault);
     }
-    #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
+    #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
     if sr.crcerr() {
         return Err(Error::Crc);
     }
-    #[cfg(any(spi_v3, spi_v4, spi_v5))]
+    #[cfg(any(spi_v4, spi_v5, spi_v6))]
     if sr.crce() {
         return Err(Error::Crc);
     }
@@ -994,11 +994,11 @@ fn spin_until_tx_ready(regs: Regs, ovr: bool) -> Result<(), Error> {
 
         check_error_flags(sr, ovr)?;
 
-        #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
+        #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
         if sr.txe() {
             return Ok(());
         }
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         if sr.txp() {
             return Ok(());
         }
@@ -1011,11 +1011,11 @@ fn spin_until_rx_ready(regs: Regs) -> Result<(), Error> {
 
         check_error_flags(sr, true)?;
 
-        #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
+        #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
         if sr.rxne() {
             return Ok(());
         }
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         if sr.rxp() {
             return Ok(());
         }
@@ -1023,46 +1023,46 @@ fn spin_until_rx_ready(regs: Regs) -> Result<(), Error> {
 }
 
 pub(crate) fn flush_rx_fifo(regs: Regs) {
-    #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
+    #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
     while regs.sr().read().rxne() {
-        #[cfg(not(spi_v2))]
+        #[cfg(not(spi_v3))]
         let _ = regs.dr().read();
-        #[cfg(spi_v2)]
+        #[cfg(spi_v3)]
         let _ = regs.dr16().read();
     }
-    #[cfg(any(spi_v3, spi_v4, spi_v5))]
+    #[cfg(any(spi_v4, spi_v5, spi_v6))]
     while regs.sr().read().rxp() {
         let _ = regs.rxdr32().read();
     }
 }
 
 pub(crate) fn set_txdmaen(regs: Regs, val: bool) {
-    #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
+    #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
     regs.cr2().modify(|reg| {
         reg.set_txdmaen(val);
     });
-    #[cfg(any(spi_v3, spi_v4, spi_v5))]
+    #[cfg(any(spi_v4, spi_v5, spi_v6))]
     regs.cfg1().modify(|reg| {
         reg.set_txdmaen(val);
     });
 }
 
 pub(crate) fn set_rxdmaen(regs: Regs, val: bool) {
-    #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
+    #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
     regs.cr2().modify(|reg| {
         reg.set_rxdmaen(val);
     });
-    #[cfg(any(spi_v3, spi_v4, spi_v5))]
+    #[cfg(any(spi_v4, spi_v5, spi_v6))]
     regs.cfg1().modify(|reg| {
         reg.set_rxdmaen(val);
     });
 }
 
 fn finish_dma(regs: Regs) {
-    #[cfg(spi_v2)]
+    #[cfg(spi_v3)]
     while regs.sr().read().ftlvl().to_bits() > 0 {}
 
-    #[cfg(any(spi_v3, spi_v4, spi_v5))]
+    #[cfg(any(spi_v4, spi_v5, spi_v6))]
     {
         if regs.cr2().read().tsize() == 0 {
             while !regs.sr().read().txc() {}
@@ -1070,7 +1070,7 @@ fn finish_dma(regs: Regs) {
             while !regs.sr().read().eot() {}
         }
     }
-    #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
+    #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
     while regs.sr().read().bsy() {}
 
     // Disable the spi peripheral
@@ -1080,12 +1080,12 @@ fn finish_dma(regs: Regs) {
 
     // The peripheral automatically disables the DMA stream on completion without error,
     // but it does not clear the RXDMAEN/TXDMAEN flag in CR2.
-    #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
+    #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
     regs.cr2().modify(|reg| {
         reg.set_txdmaen(false);
         reg.set_rxdmaen(false);
     });
-    #[cfg(any(spi_v3, spi_v4, spi_v5))]
+    #[cfg(any(spi_v4, spi_v5, spi_v6))]
     regs.cfg1().modify(|reg| {
         reg.set_txdmaen(false);
         reg.set_rxdmaen(false);
@@ -1098,7 +1098,7 @@ fn transfer_word<W: Word>(regs: Regs, tx_word: W) -> Result<W, Error> {
     unsafe {
         ptr::write_volatile(regs.tx_ptr(), tx_word);
 
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         regs.cr1().modify(|reg| reg.set_cstart(true));
     }
 
@@ -1117,7 +1117,7 @@ fn write_word<W: Word>(regs: Regs, tx_word: W) -> Result<(), Error> {
     unsafe {
         ptr::write_volatile(regs.tx_ptr(), tx_word);
 
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         regs.cr1().modify(|reg| reg.set_cstart(true));
     }
     Ok(())
@@ -1225,7 +1225,7 @@ macro_rules! impl_word {
     };
 }
 
-#[cfg(any(spi_v1, spi_f1))]
+#[cfg(any(spi_v1, spi_v2))]
 mod word_impl {
     use super::*;
 
@@ -1235,7 +1235,7 @@ mod word_impl {
     impl_word!(u16, vals::Dff::BITS16);
 }
 
-#[cfg(spi_v2)]
+#[cfg(spi_v3)]
 mod word_impl {
     use super::*;
 
@@ -1256,7 +1256,7 @@ mod word_impl {
     impl_word!(u16, (vals::Ds::BITS16, vals::Frxth::HALF));
 }
 
-#[cfg(any(spi_v3, spi_v4, spi_v5))]
+#[cfg(any(spi_v4, spi_v5, spi_v6))]
 mod word_impl {
     use super::*;
 
@@ -1309,13 +1309,13 @@ impl State {
 
 peri_trait!();
 
-pin_trait!(SckPin, Instance);
-pin_trait!(MosiPin, Instance);
-pin_trait!(MisoPin, Instance);
-pin_trait!(CsPin, Instance);
-pin_trait!(MckPin, Instance);
-pin_trait!(CkPin, Instance);
-pin_trait!(WsPin, Instance);
+pin_trait!(SckPin, Instance, @A);
+pin_trait!(MosiPin, Instance, @A);
+pin_trait!(MisoPin, Instance, @A);
+pin_trait!(CsPin, Instance, @A);
+pin_trait!(MckPin, Instance, @A);
+pin_trait!(CkPin, Instance, @A);
+pin_trait!(WsPin, Instance, @A);
 dma_trait!(RxDma, Instance);
 dma_trait!(TxDma, Instance);
 
diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs
index b291fc155..484aae1d0 100644
--- a/embassy-stm32/src/timer/complementary_pwm.rs
+++ b/embassy-stm32/src/timer/complementary_pwm.rs
@@ -16,23 +16,24 @@ use crate::Peri;
 /// Complementary PWM pin wrapper.
 ///
 /// This wraps a pin to make it usable with PWM.
-pub struct ComplementaryPwmPin<'d, T, C> {
-    _pin: Peri<'d, AnyPin>,
-    phantom: PhantomData<(T, C)>,
+pub struct ComplementaryPwmPin<'d, T, C, #[cfg(afio)] A> {
+    #[allow(unused)]
+    pin: Peri<'d, AnyPin>,
+    phantom: PhantomData<if_afio!((T, C, A))>,
 }
 
-impl<'d, T: AdvancedInstance4Channel, C: TimerChannel> ComplementaryPwmPin<'d, T, C> {
+impl<'d, T: AdvancedInstance4Channel, C: TimerChannel, #[cfg(afio)] A> if_afio!(ComplementaryPwmPin<'d, T, C, A>) {
     /// Create a new  complementary PWM pin instance.
-    pub fn new(pin: Peri<'d, impl TimerComplementaryPin<T, C>>, output_type: OutputType) -> Self {
+    pub fn new(pin: Peri<'d, if_afio!(impl TimerComplementaryPin<T, C, A>)>, output_type: OutputType) -> Self {
         critical_section::with(|_| {
             pin.set_low();
-            pin.set_as_af(
-                pin.af_num(),
-                crate::gpio::AfType::output(output_type, crate::gpio::Speed::VeryHigh),
+            set_as_af!(
+                pin,
+                crate::gpio::AfType::output(output_type, crate::gpio::Speed::VeryHigh)
             );
         });
         ComplementaryPwmPin {
-            _pin: pin.into(),
+            pin: pin.into(),
             phantom: PhantomData,
         }
     }
@@ -54,17 +55,17 @@ pub enum IdlePolarity {
 
 impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
     /// Create a new complementary PWM driver.
-    #[allow(clippy::too_many_arguments)]
-    pub fn new(
+    #[allow(clippy::too_many_arguments, unused)]
+    pub fn new<#[cfg(afio)] A>(
         tim: Peri<'d, T>,
-        _ch1: Option<PwmPin<'d, T, Ch1>>,
-        _ch1n: Option<ComplementaryPwmPin<'d, T, Ch1>>,
-        _ch2: Option<PwmPin<'d, T, Ch2>>,
-        _ch2n: Option<ComplementaryPwmPin<'d, T, Ch2>>,
-        _ch3: Option<PwmPin<'d, T, Ch3>>,
-        _ch3n: Option<ComplementaryPwmPin<'d, T, Ch3>>,
-        _ch4: Option<PwmPin<'d, T, Ch4>>,
-        _ch4n: Option<ComplementaryPwmPin<'d, T, Ch4>>,
+        ch1: Option<if_afio!(PwmPin<'d, T, Ch1, A>)>,
+        ch1n: Option<if_afio!(ComplementaryPwmPin<'d, T, Ch1, A>)>,
+        ch2: Option<if_afio!(PwmPin<'d, T, Ch2, A>)>,
+        ch2n: Option<if_afio!(ComplementaryPwmPin<'d, T, Ch2, A>)>,
+        ch3: Option<if_afio!(PwmPin<'d, T, Ch3, A>)>,
+        ch3n: Option<if_afio!(ComplementaryPwmPin<'d, T, Ch3, A>)>,
+        ch4: Option<if_afio!(PwmPin<'d, T, Ch4, A>)>,
+        ch4n: Option<if_afio!(ComplementaryPwmPin<'d, T, Ch4, A>)>,
         freq: Hertz,
         counting_mode: CountingMode,
     ) -> Self {
@@ -185,6 +186,16 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
         self.inner.set_complementary_output_polarity(channel, polarity);
     }
 
+    /// Set the main output polarity for a given channel.
+    pub fn set_main_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
+        self.inner.set_output_polarity(channel, polarity);
+    }
+
+    /// Set the complementary output polarity for a given channel.
+    pub fn set_complementary_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
+        self.inner.set_complementary_output_polarity(channel, polarity);
+    }
+
     /// Set the dead time as a proportion of max_duty
     pub fn set_dead_time(&mut self, value: u16) {
         let (ckd, value) = compute_dead_time_value(value);
@@ -192,6 +203,66 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
         self.inner.set_dead_time_clock_division(ckd);
         self.inner.set_dead_time_value(value);
     }
+
+    /// Generate a sequence of PWM waveform
+    ///
+    /// Note:
+    /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
+    pub async fn waveform_up(&mut self, dma: Peri<'_, impl super::UpDma<T>>, channel: Channel, duty: &[u16]) {
+        #[allow(clippy::let_unit_value)] // eg. stm32f334
+        let req = dma.request();
+
+        let original_duty_state = self.inner.get_compare_value(channel);
+        let original_enable_state = self.inner.get_channel_enable_state(channel);
+        let original_update_dma_state = self.inner.get_update_dma_state();
+
+        if !original_update_dma_state {
+            self.inner.enable_update_dma(true);
+        }
+
+        if !original_enable_state {
+            self.inner.enable_channel(channel, true);
+        }
+
+        unsafe {
+            #[cfg(not(any(bdma, gpdma)))]
+            use crate::dma::{Burst, FifoThreshold};
+            use crate::dma::{Transfer, TransferOptions};
+
+            let dma_transfer_option = TransferOptions {
+                #[cfg(not(any(bdma, gpdma)))]
+                fifo_threshold: Some(FifoThreshold::Full),
+                #[cfg(not(any(bdma, gpdma)))]
+                mburst: Burst::Incr8,
+                ..Default::default()
+            };
+
+            Transfer::new_write(
+                dma,
+                req,
+                duty,
+                self.inner.regs_gp16().ccr(channel.index()).as_ptr() as *mut u16,
+                dma_transfer_option,
+            )
+            .await
+        };
+
+        // restore output compare state
+        if !original_enable_state {
+            self.inner.enable_channel(channel, false);
+        }
+
+        self.inner.set_compare_value(channel, original_duty_state);
+
+        // Since DMA is closed before timer update event trigger DMA is turn off,
+        // this can almost always trigger a DMA FIFO error.
+        //
+        // optional TODO:
+        // clean FEIF after disable UDE
+        if !original_update_dma_state {
+            self.inner.enable_update_dma(false);
+        }
+    }
 }
 
 impl<'d, T: AdvancedInstance4Channel> embedded_hal_02::Pwm for ComplementaryPwm<'d, T> {
diff --git a/embassy-stm32/src/timer/input_capture.rs b/embassy-stm32/src/timer/input_capture.rs
index dda33e7f1..7a25e6c21 100644
--- a/embassy-stm32/src/timer/input_capture.rs
+++ b/embassy-stm32/src/timer/input_capture.rs
@@ -17,16 +17,17 @@ use crate::Peri;
 /// Capture pin wrapper.
 ///
 /// This wraps a pin to make it usable with capture.
-pub struct CapturePin<'d, T, C> {
-    _pin: Peri<'d, AnyPin>,
-    phantom: PhantomData<(T, C)>,
+pub struct CapturePin<'d, T, C, #[cfg(afio)] A> {
+    #[allow(unused)]
+    pin: Peri<'d, AnyPin>,
+    phantom: PhantomData<if_afio!((T, C, A))>,
 }
-impl<'d, T: GeneralInstance4Channel, C: TimerChannel> CapturePin<'d, T, C> {
+impl<'d, T: GeneralInstance4Channel, C: TimerChannel, #[cfg(afio)] A> if_afio!(CapturePin<'d, T, C, A>) {
     /// Create a new capture pin instance.
-    pub fn new(pin: Peri<'d, impl TimerPin<T, C>>, pull: Pull) -> Self {
-        pin.set_as_af(pin.af_num(), AfType::input(pull));
+    pub fn new(pin: Peri<'d, if_afio!(impl TimerPin<T, C, A>)>, pull: Pull) -> Self {
+        set_as_af!(pin, AfType::input(pull));
         CapturePin {
-            _pin: pin.into(),
+            pin: pin.into(),
             phantom: PhantomData,
         }
     }
@@ -39,12 +40,13 @@ pub struct InputCapture<'d, T: GeneralInstance4Channel> {
 
 impl<'d, T: GeneralInstance4Channel> InputCapture<'d, T> {
     /// Create a new input capture driver.
-    pub fn new(
+    #[allow(unused)]
+    pub fn new<#[cfg(afio)] A>(
         tim: Peri<'d, T>,
-        _ch1: Option<CapturePin<'d, T, Ch1>>,
-        _ch2: Option<CapturePin<'d, T, Ch2>>,
-        _ch3: Option<CapturePin<'d, T, Ch3>>,
-        _ch4: Option<CapturePin<'d, T, Ch4>>,
+        ch1: Option<if_afio!(CapturePin<'d, T, Ch1, A>)>,
+        ch2: Option<if_afio!(CapturePin<'d, T, Ch2, A>)>,
+        ch3: Option<if_afio!(CapturePin<'d, T, Ch3, A>)>,
+        ch4: Option<if_afio!(CapturePin<'d, T, Ch4, A>)>,
         _irq: impl Binding<T::CaptureCompareInterrupt, CaptureCompareInterruptHandler<T>> + 'd,
         freq: Hertz,
         counting_mode: CountingMode,
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index 7062f5f4c..b09bc7166 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -223,15 +223,15 @@ pub trait AdvancedInstance2Channel: BasicInstance + GeneralInstance2Channel + Ad
 /// Advanced 16-bit timer with 4 channels instance.
 pub trait AdvancedInstance4Channel: AdvancedInstance2Channel + GeneralInstance4Channel {}
 
-pin_trait!(TimerPin, GeneralInstance4Channel, TimerChannel);
-pin_trait!(ExternalTriggerPin, GeneralInstance4Channel);
+pin_trait!(TimerPin, GeneralInstance4Channel, TimerChannel, @A);
+pin_trait!(ExternalTriggerPin, GeneralInstance4Channel, @A);
 
-pin_trait!(TimerComplementaryPin, AdvancedInstance4Channel, TimerChannel);
+pin_trait!(TimerComplementaryPin, AdvancedInstance4Channel, TimerChannel, @A);
 
-pin_trait!(BreakInputPin, AdvancedInstance4Channel, BreakInput);
+pin_trait!(BreakInputPin, AdvancedInstance4Channel, BreakInput, @A);
 
-pin_trait!(BreakInputComparator1Pin, AdvancedInstance4Channel, BreakInput);
-pin_trait!(BreakInputComparator2Pin, AdvancedInstance4Channel, BreakInput);
+pin_trait!(BreakInputComparator1Pin, AdvancedInstance4Channel, BreakInput, @A);
+pin_trait!(BreakInputComparator2Pin, AdvancedInstance4Channel, BreakInput, @A);
 
 // Update Event trigger DMA for every timer
 dma_trait!(UpDma, BasicInstance);
diff --git a/embassy-stm32/src/timer/one_pulse.rs b/embassy-stm32/src/timer/one_pulse.rs
index 498d9c082..a75b41bd7 100644
--- a/embassy-stm32/src/timer/one_pulse.rs
+++ b/embassy-stm32/src/timer/one_pulse.rs
@@ -15,6 +15,7 @@ use crate::gpio::{AfType, AnyPin, Pull};
 use crate::interrupt::typelevel::{Binding, Interrupt};
 use crate::pac::timer::vals::Etp;
 use crate::time::Hertz;
+use crate::timer::TimerChannel;
 use crate::Peri;
 
 /// External input marker type.
@@ -42,7 +43,8 @@ impl From<ExternalTriggerPolarity> for Etp {
 ///
 /// This wraps a pin to make it usable as a timer trigger.
 pub struct TriggerPin<'d, T, C> {
-    _pin: Peri<'d, AnyPin>,
+    #[allow(unused)]
+    pin: Peri<'d, AnyPin>,
     phantom: PhantomData<(T, C)>,
 }
 
@@ -60,60 +62,23 @@ impl SealedTriggerSource for Ch1 {}
 impl SealedTriggerSource for Ch2 {}
 impl SealedTriggerSource for Ext {}
 
-trait SealedTimerTriggerPin<T, S>: crate::gpio::Pin {}
-
-/// Marker trait for a trigger pin.
-#[expect(private_bounds)]
-// TODO: find better naming scheme than prefixing all pin traits with "Timer".
-// The trait name cannot conflict with the corresponding type's name.
-// Applies to other timer submodules as well.
-pub trait TimerTriggerPin<T, S>: SealedTimerTriggerPin<T, S> {
-    /// Get the AF number needed to use this pin as a trigger source.
-    fn af_num(&self) -> u8;
-}
-
-impl<T, P, C> TimerTriggerPin<T, C> for P
-where
-    T: GeneralInstance4Channel,
-    P: TimerPin<T, C>,
-    C: super::TimerChannel + TriggerSource,
-{
-    fn af_num(&self) -> u8 {
-        TimerPin::af_num(self)
-    }
-}
-
-impl<T, P> TimerTriggerPin<T, Ext> for P
-where
-    T: GeneralInstance4Channel,
-    P: ExternalTriggerPin<T>,
-{
-    fn af_num(&self) -> u8 {
-        ExternalTriggerPin::af_num(self)
+impl<'d, T: GeneralInstance4Channel, C: TriggerSource + TimerChannel> TriggerPin<'d, T, C> {
+    /// Create a new Channel trigger pin instance.
+    pub fn new<#[cfg(afio)] A>(pin: Peri<'d, if_afio!(impl TimerPin<T, C, A>)>, pull: Pull) -> Self {
+        set_as_af!(pin, AfType::input(pull));
+        TriggerPin {
+            pin: pin.into(),
+            phantom: PhantomData,
+        }
     }
 }
 
-impl<T, P, C> SealedTimerTriggerPin<T, C> for P
-where
-    T: GeneralInstance4Channel,
-    P: TimerPin<T, C>,
-    C: super::TimerChannel + TriggerSource,
-{
-}
-
-impl<T, P> SealedTimerTriggerPin<T, Ext> for P
-where
-    T: GeneralInstance4Channel,
-    P: ExternalTriggerPin<T>,
-{
-}
-
-impl<'d, T: GeneralInstance4Channel, C: TriggerSource> TriggerPin<'d, T, C> {
-    /// "Create a new Ch1 trigger pin instance.
-    pub fn new(pin: Peri<'d, impl TimerTriggerPin<T, C>>, pull: Pull) -> Self {
-        pin.set_as_af(pin.af_num(), AfType::input(pull));
+impl<'d, T: GeneralInstance4Channel> TriggerPin<'d, T, Ext> {
+    /// Create a new external trigger pin instance.
+    pub fn new_external<#[cfg(afio)] A>(pin: Peri<'d, if_afio!(impl ExternalTriggerPin<T, A>)>, pull: Pull) -> Self {
+        set_as_af!(pin, AfType::input(pull));
         TriggerPin {
-            _pin: pin.into(),
+            pin: pin.into(),
             phantom: PhantomData,
         }
     }
@@ -131,9 +96,10 @@ impl<'d, T: GeneralInstance4Channel> OnePulse<'d, T> {
     ///
     /// The pulse is triggered by a channel 1 input pin on both rising and
     /// falling edges. Channel 1 will unusable as an output.
+    #[allow(unused)]
     pub fn new_ch1_edge_detect(
         tim: Peri<'d, T>,
-        _pin: TriggerPin<'d, T, Ch1>,
+        pin: TriggerPin<'d, T, Ch1>,
         _irq: impl Binding<T::CaptureCompareInterrupt, CaptureCompareInterruptHandler<T>> + 'd,
         freq: Hertz,
         pulse_end: u32,
diff --git a/embassy-stm32/src/timer/pwm_input.rs b/embassy-stm32/src/timer/pwm_input.rs
index 1e55f2919..159b5a177 100644
--- a/embassy-stm32/src/timer/pwm_input.rs
+++ b/embassy-stm32/src/timer/pwm_input.rs
@@ -18,15 +18,25 @@ pub struct PwmInput<'d, T: GeneralInstance4Channel> {
 
 impl<'d, T: GeneralInstance4Channel> PwmInput<'d, T> {
     /// Create a new PWM input driver.
-    pub fn new_ch1(tim: Peri<'d, T>, pin: Peri<'d, impl TimerPin<T, Ch1>>, pull: Pull, freq: Hertz) -> Self {
-        pin.set_as_af(pin.af_num(), AfType::input(pull));
+    pub fn new_ch1<#[cfg(afio)] A>(
+        tim: Peri<'d, T>,
+        pin: Peri<'d, if_afio!(impl TimerPin<T, Ch1, A>)>,
+        pull: Pull,
+        freq: Hertz,
+    ) -> Self {
+        set_as_af!(pin, AfType::input(pull));
 
         Self::new_inner(tim, freq, Channel::Ch1, Channel::Ch2)
     }
 
     /// Create a new PWM input driver.
-    pub fn new_ch2(tim: Peri<'d, T>, pin: Peri<'d, impl TimerPin<T, Ch2>>, pull: Pull, freq: Hertz) -> Self {
-        pin.set_as_af(pin.af_num(), AfType::input(pull));
+    pub fn new_ch2<#[cfg(afio)] A>(
+        tim: Peri<'d, T>,
+        pin: Peri<'d, if_afio!(impl TimerPin<T, Ch2, A>)>,
+        pull: Pull,
+        freq: Hertz,
+    ) -> Self {
+        set_as_af!(pin, AfType::input(pull));
 
         Self::new_inner(tim, freq, Channel::Ch2, Channel::Ch1)
     }
diff --git a/embassy-stm32/src/timer/qei.rs b/embassy-stm32/src/timer/qei.rs
index eabe1b22a..82b5968b0 100644
--- a/embassy-stm32/src/timer/qei.rs
+++ b/embassy-stm32/src/timer/qei.rs
@@ -20,20 +20,21 @@ pub enum Direction {
 }
 
 /// Wrapper for using a pin with QEI.
-pub struct QeiPin<'d, T, Channel> {
-    _pin: Peri<'d, AnyPin>,
-    phantom: PhantomData<(T, Channel)>,
+pub struct QeiPin<'d, T, Channel, #[cfg(afio)] A> {
+    #[allow(unused)]
+    pin: Peri<'d, AnyPin>,
+    phantom: PhantomData<if_afio!((T, Channel, A))>,
 }
 
-impl<'d, T: GeneralInstance4Channel, C: QeiChannel> QeiPin<'d, T, C> {
-    /// Create a new  QEI pin instance.
-    pub fn new(pin: Peri<'d, impl TimerPin<T, C>>) -> Self {
+impl<'d, T: GeneralInstance4Channel, C: QeiChannel, #[cfg(afio)] A> if_afio!(QeiPin<'d, T, C, A>) {
+    /// Create a new QEI pin instance.
+    pub fn new(pin: Peri<'d, if_afio!(impl TimerPin<T, C, A>)>) -> Self {
         critical_section::with(|_| {
             pin.set_low();
-            pin.set_as_af(pin.af_num(), AfType::input(Pull::None));
+            set_as_af!(pin, AfType::input(Pull::None));
         });
         QeiPin {
-            _pin: pin.into(),
+            pin: pin.into(),
             phantom: PhantomData,
         }
     }
@@ -58,7 +59,12 @@ pub struct Qei<'d, T: GeneralInstance4Channel> {
 
 impl<'d, T: GeneralInstance4Channel> Qei<'d, T> {
     /// Create a new quadrature decoder driver.
-    pub fn new(tim: Peri<'d, T>, _ch1: QeiPin<'d, T, Ch1>, _ch2: QeiPin<'d, T, Ch2>) -> Self {
+    #[allow(unused)]
+    pub fn new<#[cfg(afio)] A>(
+        tim: Peri<'d, T>,
+        ch1: if_afio!(QeiPin<'d, T, Ch1, A>),
+        ch2: if_afio!(QeiPin<'d, T, Ch2, A>),
+    ) -> Self {
         Self::new_inner(tim)
     }
 
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index c04b1ab97..e6165e42b 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -14,9 +14,10 @@ use crate::Peri;
 /// PWM pin wrapper.
 ///
 /// This wraps a pin to make it usable with PWM.
-pub struct PwmPin<'d, T, C> {
-    _pin: Peri<'d, AnyPin>,
-    phantom: PhantomData<(T, C)>,
+pub struct PwmPin<'d, T, C, #[cfg(afio)] A> {
+    #[allow(unused)]
+    pub(crate) pin: Peri<'d, AnyPin>,
+    phantom: PhantomData<if_afio!((T, C, A))>,
 }
 
 /// PWM pin config
@@ -34,33 +35,33 @@ pub struct PwmPinConfig {
     pub pull: Pull,
 }
 
-impl<'d, T: GeneralInstance4Channel, C: TimerChannel> PwmPin<'d, T, C> {
+impl<'d, T: GeneralInstance4Channel, C: TimerChannel, #[cfg(afio)] A> if_afio!(PwmPin<'d, T, C, A>) {
     /// Create a new PWM pin instance.
-    pub fn new(pin: Peri<'d, impl TimerPin<T, C>>, output_type: OutputType) -> Self {
+    pub fn new(pin: Peri<'d, if_afio!(impl TimerPin<T, C, A>)>, output_type: OutputType) -> Self {
         critical_section::with(|_| {
             pin.set_low();
-            pin.set_as_af(pin.af_num(), AfType::output(output_type, Speed::VeryHigh));
+            set_as_af!(pin, AfType::output(output_type, Speed::VeryHigh));
         });
         PwmPin {
-            _pin: pin.into(),
+            pin: pin.into(),
             phantom: PhantomData,
         }
     }
 
-    /// Create a new PWM pin instance with config.
-    pub fn new_with_config(pin: Peri<'d, impl TimerPin<T, C>>, pin_config: PwmPinConfig) -> Self {
+    /// Create a new PWM pin instance with a specific configuration.
+    pub fn new_with_config(pin: Peri<'d, if_afio!(impl TimerPin<T, C, A>)>, pin_config: PwmPinConfig) -> Self {
         critical_section::with(|_| {
             pin.set_low();
-            pin.set_as_af(
-                pin.af_num(),
-                #[cfg(gpio_v1)]
-                AfType::output(pin_config.output_type, pin_config.speed),
-                #[cfg(gpio_v2)]
-                AfType::output_pull(pin_config.output_type, pin_config.speed, pin_config.pull),
+            #[cfg(gpio_v1)]
+            set_as_af!(pin, AfType::output(pin_config.output_type, pin_config.speed));
+            #[cfg(gpio_v2)]
+            set_as_af!(
+                pin,
+                AfType::output_pull(pin_config.output_type, pin_config.speed, pin_config.pull)
             );
         });
         PwmPin {
-            _pin: pin.into(),
+            pin: pin.into(),
             phantom: PhantomData,
         }
     }
@@ -178,12 +179,13 @@ pub struct SimplePwm<'d, T: GeneralInstance4Channel> {
 
 impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
     /// Create a new simple PWM driver.
-    pub fn new(
+    #[allow(unused)]
+    pub fn new<#[cfg(afio)] A>(
         tim: Peri<'d, T>,
-        _ch1: Option<PwmPin<'d, T, Ch1>>,
-        _ch2: Option<PwmPin<'d, T, Ch2>>,
-        _ch3: Option<PwmPin<'d, T, Ch3>>,
-        _ch4: Option<PwmPin<'d, T, Ch4>>,
+        ch1: Option<if_afio!(PwmPin<'d, T, Ch1, A>)>,
+        ch2: Option<if_afio!(PwmPin<'d, T, Ch2, A>)>,
+        ch3: Option<if_afio!(PwmPin<'d, T, Ch3, A>)>,
+        ch4: Option<if_afio!(PwmPin<'d, T, Ch4, A>)>,
         freq: Hertz,
         counting_mode: CountingMode,
     ) -> Self {
diff --git a/embassy-stm32/src/tsc/pin_groups.rs b/embassy-stm32/src/tsc/pin_groups.rs
index 6f914a94e..84421f7ff 100644
--- a/embassy-stm32/src/tsc/pin_groups.rs
+++ b/embassy-stm32/src/tsc/pin_groups.rs
@@ -427,7 +427,7 @@ macro_rules! impl_set_io {
         pub fn $method<Role: pin_roles::Role>(&mut self, pin: Peri<'d, impl $trait<T>>) -> IOPinWithRole<$group, Role> {
             critical_section::with(|_| {
                 pin.set_low();
-                pin.set_as_af(pin.af_num(), AfType::output(Role::output_type(), Speed::VeryHigh));
+                set_as_af!(pin, AfType::output(Role::output_type(), Speed::VeryHigh));
                 let tsc_io_pin = trait_to_io_pin!($trait);
                 let new_pin = Pin {
                     _pin: pin.into(),
diff --git a/embassy-stm32/src/ucpd.rs b/embassy-stm32/src/ucpd.rs
index 0a80adb8f..18aff4fbd 100644
--- a/embassy-stm32/src/ucpd.rs
+++ b/embassy-stm32/src/ucpd.rs
@@ -490,14 +490,14 @@ impl<'d, T: Instance> PdPhy<'d, T> {
             let sr = r.sr().read();
 
             if sr.rxhrstdet() {
-                dma.request_stop();
+                dma.request_pause();
 
                 // Clean and re-enable hard reset receive interrupt.
                 r.icr().write(|w| w.set_rxhrstdetcf(true));
                 r.imr().modify(|w| w.set_rxhrstdetie(true));
                 Poll::Ready(Err(RxError::HardReset))
             } else if sr.rxmsgend() {
-                dma.request_stop();
+                dma.request_pause();
                 // Should be read immediately on interrupt.
                 rxpaysz = r.rx_payszr().read().rxpaysz().into();
 
diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs
index 729440c46..c734eed49 100644
--- a/embassy-stm32/src/usart/buffered.rs
+++ b/embassy-stm32/src/usart/buffered.rs
@@ -208,10 +208,10 @@ impl<'d> SetConfig for BufferedUartTx<'d> {
 
 impl<'d> BufferedUart<'d> {
     /// Create a new bidirectional buffered UART driver
-    pub fn new<T: Instance>(
+    pub fn new<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        rx: Peri<'d, impl RxPin<T>>,
-        tx: Peri<'d, impl TxPin<T>>,
+        rx: Peri<'d, if_afio!(impl RxPin<T, A>)>,
+        tx: Peri<'d, if_afio!(impl TxPin<T, A>)>,
         tx_buffer: &'d mut [u8],
         rx_buffer: &'d mut [u8],
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
@@ -231,12 +231,12 @@ impl<'d> BufferedUart<'d> {
     }
 
     /// Create a new bidirectional buffered UART driver with request-to-send and clear-to-send pins
-    pub fn new_with_rtscts<T: Instance>(
+    pub fn new_with_rtscts<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        rx: Peri<'d, impl RxPin<T>>,
-        tx: Peri<'d, impl TxPin<T>>,
-        rts: Peri<'d, impl RtsPin<T>>,
-        cts: Peri<'d, impl CtsPin<T>>,
+        rx: Peri<'d, if_afio!(impl RxPin<T, A>)>,
+        tx: Peri<'d, if_afio!(impl TxPin<T, A>)>,
+        rts: Peri<'d, if_afio!(impl RtsPin<T, A>)>,
+        cts: Peri<'d, if_afio!(impl CtsPin<T, A>)>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         tx_buffer: &'d mut [u8],
         rx_buffer: &'d mut [u8],
@@ -256,11 +256,11 @@ impl<'d> BufferedUart<'d> {
     }
 
     /// Create a new bidirectional buffered UART driver with only the RTS pin as the DE pin
-    pub fn new_with_rts_as_de<T: Instance>(
+    pub fn new_with_rts_as_de<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        rx: Peri<'d, impl RxPin<T>>,
-        tx: Peri<'d, impl TxPin<T>>,
-        rts: Peri<'d, impl RtsPin<T>>,
+        rx: Peri<'d, if_afio!(impl RxPin<T, A>)>,
+        tx: Peri<'d, if_afio!(impl TxPin<T, A>)>,
+        rts: Peri<'d, if_afio!(impl RtsPin<T, A>)>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         tx_buffer: &'d mut [u8],
         rx_buffer: &'d mut [u8],
@@ -280,11 +280,11 @@ impl<'d> BufferedUart<'d> {
     }
 
     /// Create a new bidirectional buffered UART driver with only the request-to-send pin
-    pub fn new_with_rts<T: Instance>(
+    pub fn new_with_rts<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        rx: Peri<'d, impl RxPin<T>>,
-        tx: Peri<'d, impl TxPin<T>>,
-        rts: Peri<'d, impl RtsPin<T>>,
+        rx: Peri<'d, if_afio!(impl RxPin<T, A>)>,
+        tx: Peri<'d, if_afio!(impl TxPin<T, A>)>,
+        rts: Peri<'d, if_afio!(impl RtsPin<T, A>)>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         tx_buffer: &'d mut [u8],
         rx_buffer: &'d mut [u8],
@@ -305,11 +305,11 @@ impl<'d> BufferedUart<'d> {
 
     /// Create a new bidirectional buffered UART driver with a driver-enable pin
     #[cfg(not(any(usart_v1, usart_v2)))]
-    pub fn new_with_de<T: Instance>(
+    pub fn new_with_de<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        rx: Peri<'d, impl RxPin<T>>,
-        tx: Peri<'d, impl TxPin<T>>,
-        de: Peri<'d, impl DePin<T>>,
+        rx: Peri<'d, if_afio!(impl RxPin<T, A>)>,
+        tx: Peri<'d, if_afio!(impl TxPin<T, A>)>,
+        de: Peri<'d, if_afio!(impl DePin<T, A>)>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         tx_buffer: &'d mut [u8],
         rx_buffer: &'d mut [u8],
@@ -340,9 +340,9 @@ impl<'d> BufferedUart<'d> {
     /// Apart from this, the communication protocol is similar to normal USART mode. Any conflict
     /// on the line must be managed by software (for instance by using a centralized arbiter).
     #[doc(alias("HDSEL"))]
-    pub fn new_half_duplex<T: Instance>(
+    pub fn new_half_duplex<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        tx: Peri<'d, impl TxPin<T>>,
+        tx: Peri<'d, if_afio!(impl TxPin<T, A>)>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         tx_buffer: &'d mut [u8],
         rx_buffer: &'d mut [u8],
@@ -379,9 +379,9 @@ impl<'d> BufferedUart<'d> {
     /// on the line must be managed by software (for instance by using a centralized arbiter).
     #[cfg(not(any(usart_v1, usart_v2)))]
     #[doc(alias("HDSEL"))]
-    pub fn new_half_duplex_on_rx<T: Instance>(
+    pub fn new_half_duplex_on_rx<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        rx: Peri<'d, impl RxPin<T>>,
+        rx: Peri<'d, if_afio!(impl RxPin<T, A>)>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         tx_buffer: &'d mut [u8],
         rx_buffer: &'d mut [u8],
@@ -692,6 +692,8 @@ impl<'d> BufferedUartTx<'d> {
     fn blocking_write(&self, buf: &[u8]) -> Result<usize, Error> {
         loop {
             let state = self.state;
+            state.tx_done.store(false, Ordering::Release);
+
             let empty = state.tx_buf.is_empty();
 
             let mut tx_writer = unsafe { state.tx_buf.writer() };
@@ -713,7 +715,7 @@ impl<'d> BufferedUartTx<'d> {
     fn blocking_flush(&self) -> Result<(), Error> {
         loop {
             let state = self.state;
-            if state.tx_buf.is_empty() {
+            if state.tx_done.load(Ordering::Acquire) {
                 return Ok(());
             }
         }
diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs
index 5bece6d66..ff211e0c9 100644
--- a/embassy-stm32/src/usart/mod.rs
+++ b/embassy-stm32/src/usart/mod.rs
@@ -429,9 +429,9 @@ impl<'d, M: Mode> SetConfig for UartRx<'d, M> {
 
 impl<'d> UartTx<'d, Async> {
     /// Useful if you only want Uart Tx. It saves 1 pin and consumes a little less power.
-    pub fn new<T: Instance>(
+    pub fn new<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        tx: Peri<'d, impl TxPin<T>>,
+        tx: Peri<'d, if_afio!(impl TxPin<T, A>)>,
         tx_dma: Peri<'d, impl TxDma<T>>,
         config: Config,
     ) -> Result<Self, ConfigError> {
@@ -439,10 +439,10 @@ impl<'d> UartTx<'d, Async> {
     }
 
     /// Create a new tx-only UART with a clear-to-send pin
-    pub fn new_with_cts<T: Instance>(
+    pub fn new_with_cts<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        tx: Peri<'d, impl TxPin<T>>,
-        cts: Peri<'d, impl CtsPin<T>>,
+        tx: Peri<'d, if_afio!(impl TxPin<T, A>)>,
+        cts: Peri<'d, if_afio!(impl CtsPin<T, A>)>,
         tx_dma: Peri<'d, impl TxDma<T>>,
         config: Config,
     ) -> Result<Self, ConfigError> {
@@ -482,19 +482,19 @@ impl<'d> UartTx<'d, Blocking> {
     /// Create a new blocking tx-only UART with no hardware flow control.
     ///
     /// Useful if you only want Uart Tx. It saves 1 pin and consumes a little less power.
-    pub fn new_blocking<T: Instance>(
+    pub fn new_blocking<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        tx: Peri<'d, impl TxPin<T>>,
+        tx: Peri<'d, if_afio!(impl TxPin<T, A>)>,
         config: Config,
     ) -> Result<Self, ConfigError> {
         Self::new_inner(peri, new_pin!(tx, config.tx_af()), None, None, config)
     }
 
     /// Create a new blocking tx-only UART with a clear-to-send pin
-    pub fn new_blocking_with_cts<T: Instance>(
+    pub fn new_blocking_with_cts<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        tx: Peri<'d, impl TxPin<T>>,
-        cts: Peri<'d, impl CtsPin<T>>,
+        tx: Peri<'d, if_afio!(impl TxPin<T, A>)>,
+        cts: Peri<'d, if_afio!(impl CtsPin<T, A>)>,
         config: Config,
     ) -> Result<Self, ConfigError> {
         Self::new_inner(
@@ -662,10 +662,10 @@ impl<'d> UartRx<'d, Async> {
     /// Create a new rx-only UART with no hardware flow control.
     ///
     /// Useful if you only want Uart Rx. It saves 1 pin and consumes a little less power.
-    pub fn new<T: Instance>(
+    pub fn new<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        rx: Peri<'d, impl RxPin<T>>,
+        rx: Peri<'d, if_afio!(impl RxPin<T, A>)>,
         rx_dma: Peri<'d, impl RxDma<T>>,
         config: Config,
     ) -> Result<Self, ConfigError> {
@@ -673,11 +673,11 @@ impl<'d> UartRx<'d, Async> {
     }
 
     /// Create a new rx-only UART with a request-to-send pin
-    pub fn new_with_rts<T: Instance>(
+    pub fn new_with_rts<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        rx: Peri<'d, impl RxPin<T>>,
-        rts: Peri<'d, impl RtsPin<T>>,
+        rx: Peri<'d, if_afio!(impl RxPin<T, A>)>,
+        rts: Peri<'d, if_afio!(impl RtsPin<T, A>)>,
         rx_dma: Peri<'d, impl RxDma<T>>,
         config: Config,
     ) -> Result<Self, ConfigError> {
@@ -913,19 +913,19 @@ impl<'d> UartRx<'d, Blocking> {
     /// Create a new rx-only UART with no hardware flow control.
     ///
     /// Useful if you only want Uart Rx. It saves 1 pin and consumes a little less power.
-    pub fn new_blocking<T: Instance>(
+    pub fn new_blocking<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        rx: Peri<'d, impl RxPin<T>>,
+        rx: Peri<'d, if_afio!(impl RxPin<T, A>)>,
         config: Config,
     ) -> Result<Self, ConfigError> {
         Self::new_inner(peri, new_pin!(rx, config.rx_af()), None, None, config)
     }
 
     /// Create a new rx-only UART with a request-to-send pin
-    pub fn new_blocking_with_rts<T: Instance>(
+    pub fn new_blocking_with_rts<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        rx: Peri<'d, impl RxPin<T>>,
-        rts: Peri<'d, impl RtsPin<T>>,
+        rx: Peri<'d, if_afio!(impl RxPin<T, A>)>,
+        rts: Peri<'d, if_afio!(impl RtsPin<T, A>)>,
         config: Config,
     ) -> Result<Self, ConfigError> {
         Self::new_inner(
@@ -1109,10 +1109,10 @@ fn drop_tx_rx(info: &Info, state: &State) {
 
 impl<'d> Uart<'d, Async> {
     /// Create a new bidirectional UART
-    pub fn new<T: Instance>(
+    pub fn new<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        rx: Peri<'d, impl RxPin<T>>,
-        tx: Peri<'d, impl TxPin<T>>,
+        rx: Peri<'d, if_afio!(impl RxPin<T, A>)>,
+        tx: Peri<'d, if_afio!(impl TxPin<T, A>)>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         tx_dma: Peri<'d, impl TxDma<T>>,
         rx_dma: Peri<'d, impl RxDma<T>>,
@@ -1132,13 +1132,13 @@ impl<'d> Uart<'d, Async> {
     }
 
     /// Create a new bidirectional UART with request-to-send and clear-to-send pins
-    pub fn new_with_rtscts<T: Instance>(
+    pub fn new_with_rtscts<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        rx: Peri<'d, impl RxPin<T>>,
-        tx: Peri<'d, impl TxPin<T>>,
+        rx: Peri<'d, if_afio!(impl RxPin<T, A>)>,
+        tx: Peri<'d, if_afio!(impl TxPin<T, A>)>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        rts: Peri<'d, impl RtsPin<T>>,
-        cts: Peri<'d, impl CtsPin<T>>,
+        rts: Peri<'d, if_afio!(impl RtsPin<T, A>)>,
+        cts: Peri<'d, if_afio!(impl CtsPin<T, A>)>,
         tx_dma: Peri<'d, impl TxDma<T>>,
         rx_dma: Peri<'d, impl RxDma<T>>,
         config: Config,
@@ -1158,12 +1158,12 @@ impl<'d> Uart<'d, Async> {
 
     #[cfg(not(any(usart_v1, usart_v2)))]
     /// Create a new bidirectional UART with a driver-enable pin
-    pub fn new_with_de<T: Instance>(
+    pub fn new_with_de<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        rx: Peri<'d, impl RxPin<T>>,
-        tx: Peri<'d, impl TxPin<T>>,
+        rx: Peri<'d, if_afio!(impl RxPin<T, A>)>,
+        tx: Peri<'d, if_afio!(impl TxPin<T, A>)>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        de: Peri<'d, impl DePin<T>>,
+        de: Peri<'d, if_afio!(impl DePin<T, A>)>,
         tx_dma: Peri<'d, impl TxDma<T>>,
         rx_dma: Peri<'d, impl RxDma<T>>,
         config: Config,
@@ -1193,9 +1193,9 @@ impl<'d> Uart<'d, Async> {
     /// Apart from this, the communication protocol is similar to normal USART mode. Any conflict
     /// on the line must be managed by software (for instance by using a centralized arbiter).
     #[doc(alias("HDSEL"))]
-    pub fn new_half_duplex<T: Instance>(
+    pub fn new_half_duplex<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        tx: Peri<'d, impl TxPin<T>>,
+        tx: Peri<'d, if_afio!(impl TxPin<T, A>)>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         tx_dma: Peri<'d, impl TxDma<T>>,
         rx_dma: Peri<'d, impl RxDma<T>>,
@@ -1232,9 +1232,9 @@ impl<'d> Uart<'d, Async> {
     /// on the line must be managed by software (for instance by using a centralized arbiter).
     #[cfg(not(any(usart_v1, usart_v2)))]
     #[doc(alias("HDSEL"))]
-    pub fn new_half_duplex_on_rx<T: Instance>(
+    pub fn new_half_duplex_on_rx<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        rx: Peri<'d, impl RxPin<T>>,
+        rx: Peri<'d, if_afio!(impl RxPin<T, A>)>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         tx_dma: Peri<'d, impl TxDma<T>>,
         rx_dma: Peri<'d, impl RxDma<T>>,
@@ -1280,10 +1280,10 @@ impl<'d> Uart<'d, Async> {
 
 impl<'d> Uart<'d, Blocking> {
     /// Create a new blocking bidirectional UART.
-    pub fn new_blocking<T: Instance>(
+    pub fn new_blocking<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        rx: Peri<'d, impl RxPin<T>>,
-        tx: Peri<'d, impl TxPin<T>>,
+        rx: Peri<'d, if_afio!(impl RxPin<T, A>)>,
+        tx: Peri<'d, if_afio!(impl TxPin<T, A>)>,
         config: Config,
     ) -> Result<Self, ConfigError> {
         Self::new_inner(
@@ -1300,12 +1300,12 @@ impl<'d> Uart<'d, Blocking> {
     }
 
     /// Create a new bidirectional UART with request-to-send and clear-to-send pins
-    pub fn new_blocking_with_rtscts<T: Instance>(
+    pub fn new_blocking_with_rtscts<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        rx: Peri<'d, impl RxPin<T>>,
-        tx: Peri<'d, impl TxPin<T>>,
-        rts: Peri<'d, impl RtsPin<T>>,
-        cts: Peri<'d, impl CtsPin<T>>,
+        rx: Peri<'d, if_afio!(impl RxPin<T, A>)>,
+        tx: Peri<'d, if_afio!(impl TxPin<T, A>)>,
+        rts: Peri<'d, if_afio!(impl RtsPin<T, A>)>,
+        cts: Peri<'d, if_afio!(impl CtsPin<T, A>)>,
         config: Config,
     ) -> Result<Self, ConfigError> {
         Self::new_inner(
@@ -1323,11 +1323,11 @@ impl<'d> Uart<'d, Blocking> {
 
     #[cfg(not(any(usart_v1, usart_v2)))]
     /// Create a new bidirectional UART with a driver-enable pin
-    pub fn new_blocking_with_de<T: Instance>(
+    pub fn new_blocking_with_de<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        rx: Peri<'d, impl RxPin<T>>,
-        tx: Peri<'d, impl TxPin<T>>,
-        de: Peri<'d, impl DePin<T>>,
+        rx: Peri<'d, if_afio!(impl RxPin<T, A>)>,
+        tx: Peri<'d, if_afio!(impl TxPin<T, A>)>,
+        de: Peri<'d, if_afio!(impl DePin<T, A>)>,
         config: Config,
     ) -> Result<Self, ConfigError> {
         Self::new_inner(
@@ -1354,9 +1354,9 @@ impl<'d> Uart<'d, Blocking> {
     /// Apart from this, the communication protocol is similar to normal USART mode. Any conflict
     /// on the line must be managed by software (for instance by using a centralized arbiter).
     #[doc(alias("HDSEL"))]
-    pub fn new_blocking_half_duplex<T: Instance>(
+    pub fn new_blocking_half_duplex<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        tx: Peri<'d, impl TxPin<T>>,
+        tx: Peri<'d, if_afio!(impl TxPin<T, A>)>,
         mut config: Config,
         readback: HalfDuplexReadback,
     ) -> Result<Self, ConfigError> {
@@ -1390,9 +1390,9 @@ impl<'d> Uart<'d, Blocking> {
     /// on the line must be managed by software (for instance by using a centralized arbiter).
     #[cfg(not(any(usart_v1, usart_v2)))]
     #[doc(alias("HDSEL"))]
-    pub fn new_blocking_half_duplex_on_rx<T: Instance>(
+    pub fn new_blocking_half_duplex_on_rx<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
-        rx: Peri<'d, impl RxPin<T>>,
+        rx: Peri<'d, if_afio!(impl RxPin<T, A>)>,
         mut config: Config,
         readback: HalfDuplexReadback,
     ) -> Result<Self, ConfigError> {
@@ -1965,9 +1965,7 @@ pub use buffered::*;
 pub use crate::usart::buffered::InterruptHandler as BufferedInterruptHandler;
 mod buffered;
 
-#[cfg(not(gpdma))]
 mod ringbuffered;
-#[cfg(not(gpdma))]
 pub use ringbuffered::RingBufferedUartRx;
 
 #[cfg(any(usart_v1, usart_v2))]
@@ -2057,12 +2055,12 @@ pub trait Instance: SealedInstance + PeripheralType + 'static + Send {
     type Interrupt: interrupt::typelevel::Interrupt;
 }
 
-pin_trait!(RxPin, Instance);
-pin_trait!(TxPin, Instance);
-pin_trait!(CtsPin, Instance);
-pin_trait!(RtsPin, Instance);
-pin_trait!(CkPin, Instance);
-pin_trait!(DePin, Instance);
+pin_trait!(RxPin, Instance, @A);
+pin_trait!(TxPin, Instance, @A);
+pin_trait!(CtsPin, Instance, @A);
+pin_trait!(RtsPin, Instance, @A);
+pin_trait!(CkPin, Instance, @A);
+pin_trait!(DePin, Instance, @A);
 
 dma_trait!(TxDma, Instance);
 dma_trait!(RxDma, Instance);
diff --git a/embassy-stm32/src/usart/ringbuffered.rs b/embassy-stm32/src/usart/ringbuffered.rs
index 1d4a44896..5f4e87834 100644
--- a/embassy-stm32/src/usart/ringbuffered.rs
+++ b/embassy-stm32/src/usart/ringbuffered.rs
@@ -381,7 +381,7 @@ impl ReadReady for RingBufferedUartRx<'_> {
             crate::dma::ringbuffer::Error::Overrun => Self::Error::Overrun,
             crate::dma::ringbuffer::Error::DmaUnsynced => {
                 error!(
-                    "Ringbuffer error: DmaUNsynced, driver implementation is 
+                    "Ringbuffer error: DmaUNsynced, driver implementation is
                     probably bugged please open an issue"
                 );
                 // we report this as overrun since its recoverable in the same way
diff --git a/embassy-stm32/src/usb/otg.rs b/embassy-stm32/src/usb/otg.rs
index 1c3b99b93..5ce81b131 100644
--- a/embassy-stm32/src/usb/otg.rs
+++ b/embassy-stm32/src/usb/otg.rs
@@ -34,7 +34,7 @@ macro_rules! config_ulpi_pins {
     ($($pin:ident),*) => {
                 critical_section::with(|_| {
             $(
-                $pin.set_as_af($pin.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
+                set_as_af!($pin, AfType::output(OutputType::PushPull, Speed::VeryHigh));
             )*
         })
     };
@@ -68,8 +68,8 @@ impl<'d, T: Instance> Driver<'d, T> {
         ep_out_buffer: &'d mut [u8],
         config: Config,
     ) -> Self {
-        dp.set_as_af(dp.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
-        dm.set_as_af(dm.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
+        set_as_af!(dp, AfType::output(OutputType::PushPull, Speed::VeryHigh));
+        set_as_af!(dm, AfType::output(OutputType::PushPull, Speed::VeryHigh));
 
         let regs = T::regs();
 
@@ -107,8 +107,8 @@ impl<'d, T: Instance> Driver<'d, T> {
         // For STM32U5 High speed pins need to be left in analog mode
         #[cfg(not(any(all(stm32u5, peri_usb_otg_hs), all(stm32wba, peri_usb_otg_hs))))]
         {
-            _dp.set_as_af(_dp.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
-            _dm.set_as_af(_dm.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
+            set_as_af!(_dp, AfType::output(OutputType::PushPull, Speed::VeryHigh));
+            set_as_af!(_dm, AfType::output(OutputType::PushPull, Speed::VeryHigh));
         }
 
         let instance = OtgInstance {
diff --git a/embassy-stm32/src/usb/usb.rs b/embassy-stm32/src/usb/usb.rs
index 54596aeae..9e08d99b3 100644
--- a/embassy-stm32/src/usb/usb.rs
+++ b/embassy-stm32/src/usb/usb.rs
@@ -298,7 +298,7 @@ impl<'d, T: Instance> Driver<'d, T> {
     ) -> Self {
         {
             use crate::gpio::{AfType, OutputType, Speed};
-            sof.set_as_af(sof.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
+            set_as_af!(sof, AfType::output(OutputType::PushPull, Speed::VeryHigh));
         }
 
         Self::new(_usb, _irq, dp, dm)
@@ -329,8 +329,8 @@ impl<'d, T: Instance> Driver<'d, T> {
         #[cfg(not(stm32l1))]
         {
             use crate::gpio::{AfType, OutputType, Speed};
-            dp.set_as_af(dp.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
-            dm.set_as_af(dm.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
+            set_as_af!(dp, AfType::output(OutputType::PushPull, Speed::VeryHigh));
+            set_as_af!(dm, AfType::output(OutputType::PushPull, Speed::VeryHigh));
         }
         #[cfg(stm32l1)]
         let _ = (dp, dm); // suppress "unused" warnings.
diff --git a/embassy-stm32/src/xspi/enums.rs b/embassy-stm32/src/xspi/enums.rs
index c96641180..2e510fada 100644
--- a/embassy-stm32/src/xspi/enums.rs
+++ b/embassy-stm32/src/xspi/enums.rs
@@ -22,6 +22,7 @@ impl Into<u8> for XspiMode {
 
 /// Xspi lane width
 #[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum XspiWidth {
     /// None
     NONE,
@@ -50,6 +51,7 @@ impl Into<u8> for XspiWidth {
 /// Wrap Size
 #[allow(missing_docs)]
 #[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum WrapSize {
     None,
     _16Bytes,
@@ -73,6 +75,7 @@ impl Into<u8> for WrapSize {
 /// Memory Type
 #[allow(missing_docs)]
 #[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum MemoryType {
     Micron,
     Macronix,
@@ -98,6 +101,7 @@ impl Into<u8> for MemoryType {
 /// Xspi memory size.
 #[allow(missing_docs)]
 #[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum MemorySize {
     _1KiB,
     _2KiB,
@@ -158,6 +162,7 @@ impl Into<u8> for MemorySize {
 
 /// Xspi Address size
 #[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum AddressSize {
     /// 8-bit address
     _8bit,
@@ -183,6 +188,7 @@ impl Into<u8> for AddressSize {
 /// Time the Chip Select line stays high.
 #[allow(missing_docs)]
 #[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum ChipSelectHighTime {
     _1Cycle,
     _2Cycle,
@@ -212,6 +218,7 @@ impl Into<u8> for ChipSelectHighTime {
 /// FIFO threshold.
 #[allow(missing_docs)]
 #[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum FIFOThresholdLevel {
     _1Bytes,
     _2Bytes,
@@ -289,6 +296,7 @@ impl Into<u8> for FIFOThresholdLevel {
 /// Dummy cycle count
 #[allow(missing_docs)]
 #[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum DummyCycles {
     _0,
     _1,
diff --git a/embassy-stm32/src/xspi/mod.rs b/embassy-stm32/src/xspi/mod.rs
index 60ccf3c97..901569f64 100644
--- a/embassy-stm32/src/xspi/mod.rs
+++ b/embassy-stm32/src/xspi/mod.rs
@@ -23,6 +23,7 @@ use crate::{peripherals, Peri};
 
 /// XPSI driver config.
 #[derive(Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct Config {
     /// Fifo threshold used by the peripheral to generate the interrupt indicating data
     /// or space is available in the FIFO
@@ -80,6 +81,8 @@ impl Default for Config {
 }
 
 /// XSPI transfer configuration.
+#[derive(Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct TransferConfig {
     /// Instruction width (IMODE)
     pub iwidth: XspiWidth,
@@ -110,7 +113,7 @@ pub struct TransferConfig {
 
     /// Data width (DMODE)
     pub dwidth: XspiWidth,
-    /// Data buffer
+    /// Data Double Transfer rate enable
     pub ddtr: bool,
 
     /// Number of dummy cycles (DCYC)
@@ -424,11 +427,6 @@ impl<'d, T: Instance, M: PeriMode> Xspi<'d, T, M> {
         // Configure alternate bytes
         if let Some(ab) = command.alternate_bytes {
             T::REGS.abr().write(|v| v.set_alternate(ab));
-            T::REGS.ccr().modify(|w| {
-                w.set_abmode(CcrAbmode::from_bits(command.abwidth.into()));
-                w.set_abdtr(command.abdtr);
-                w.set_absize(CcrAbsize::from_bits(command.absize.into()));
-            })
         } else {
             T::REGS.ccr().modify(|w| {
                 // disable alternate bytes
@@ -445,14 +443,14 @@ impl<'d, T: Instance, M: PeriMode> Xspi<'d, T, M> {
         if let Some(data_length) = data_len {
             T::REGS.dlr().write(|v| {
                 v.set_dl((data_length - 1) as u32);
-            })
+            });
         } else {
             T::REGS.dlr().write(|v| {
                 v.set_dl((0) as u32);
-            })
+            });
         }
 
-        // Configure instruction/address/data modes
+        // Configure instruction/address/alternate bytes/data modes
         T::REGS.ccr().modify(|w| {
             w.set_imode(CcrImode::from_bits(command.iwidth.into()));
             w.set_idtr(command.idtr);
@@ -462,6 +460,10 @@ impl<'d, T: Instance, M: PeriMode> Xspi<'d, T, M> {
             w.set_addtr(command.addtr);
             w.set_adsize(CcrAdsize::from_bits(command.adsize.into()));
 
+            w.set_abmode(CcrAbmode::from_bits(command.abwidth.into()));
+            w.set_abdtr(command.abdtr);
+            w.set_absize(CcrAbsize::from_bits(command.absize.into()));
+
             w.set_dmode(CcrDmode::from_bits(command.dwidth.into()));
             w.set_ddtr(command.ddtr);
         });
diff --git a/embassy-sync/CHANGELOG.md b/embassy-sync/CHANGELOG.md
index a53d5f5b1..242b8b7ab 100644
--- a/embassy-sync/CHANGELOG.md
+++ b/embassy-sync/CHANGELOG.md
@@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 <!-- next-header -->
 ## Unreleased - ReleaseDate
 - Fix wakers getting dropped by `Signal::reset`
+- Remove `Sized` trait bound from `MutexGuard::map`
 
 ## 0.7.2 - 2025-08-26
 
diff --git a/embassy-sync/Cargo.toml b/embassy-sync/Cargo.toml
index 30a27c13f..6494da727 100644
--- a/embassy-sync/Cargo.toml
+++ b/embassy-sync/Cargo.toml
@@ -17,6 +17,8 @@ categories = [
 [package.metadata.embassy]
 build = [
     {target = "thumbv6m-none-eabi", features = ["defmt"]},
+    # Xtensa builds
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32s2-none-elf", features = ["defmt"]},
 ]
 
 [package.metadata.embassy_docs]
diff --git a/embassy-sync/src/mutex.rs b/embassy-sync/src/mutex.rs
index 4ce6dd987..aea682899 100644
--- a/embassy-sync/src/mutex.rs
+++ b/embassy-sync/src/mutex.rs
@@ -187,7 +187,7 @@ where
     T: ?Sized,
 {
     /// Returns a locked view over a portion of the locked data.
-    pub fn map<U>(this: Self, fun: impl FnOnce(&mut T) -> &mut U) -> MappedMutexGuard<'a, M, U> {
+    pub fn map<U: ?Sized>(this: Self, fun: impl FnOnce(&mut T) -> &mut U) -> MappedMutexGuard<'a, M, U> {
         let mutex = this.mutex;
         let value = fun(unsafe { &mut *this.mutex.inner.get() });
         // Don't run the `drop` method for MutexGuard. The ownership of the underlying
@@ -279,7 +279,7 @@ where
     T: ?Sized,
 {
     /// Returns a locked view over a portion of the locked data.
-    pub fn map<U>(this: Self, fun: impl FnOnce(&mut T) -> &mut U) -> MappedMutexGuard<'a, M, U> {
+    pub fn map<U: ?Sized>(this: Self, fun: impl FnOnce(&mut T) -> &mut U) -> MappedMutexGuard<'a, M, U> {
         let state = this.state;
         let value = fun(unsafe { &mut *this.value });
         // Don't run the `drop` method for MutexGuard. The ownership of the underlying
diff --git a/embassy-time-queue-utils/Cargo.toml b/embassy-time-queue-utils/Cargo.toml
index e1abf1cd8..13da62874 100644
--- a/embassy-time-queue-utils/Cargo.toml
+++ b/embassy-time-queue-utils/Cargo.toml
@@ -56,6 +56,9 @@ _generic-queue = []
 build = [
     {target = "thumbv6m-none-eabi", features = []},
     {target = "thumbv6m-none-eabi", features = ["generic-queue-8"]},
+    # Xtensa builds
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32s2-none-elf", features = []},
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32s2-none-elf", features = ["generic-queue-8"]},
 ]
 
 [package.metadata.embassy_docs]
diff --git a/embassy-time/Cargo.toml b/embassy-time/Cargo.toml
index 6ebf0a468..2d7c3c1fa 100644
--- a/embassy-time/Cargo.toml
+++ b/embassy-time/Cargo.toml
@@ -17,6 +17,8 @@ categories = [
 [package.metadata.embassy]
 build = [
     {target = "thumbv6m-none-eabi", features = ["defmt", "defmt-timestamp-uptime", "mock-driver"]},
+    # Xtensa builds
+    {group = "xtensa", build-std = ["core", "alloc"],  target = "xtensa-esp32s2-none-elf", features = ["defmt", "defmt-timestamp-uptime", "mock-driver"]},
 ]
 
 [package.metadata.embassy_docs]
diff --git a/embassy-usb-dfu/CHANGELOG.md b/embassy-usb-dfu/CHANGELOG.md
index 7e5adb1f2..0088e66fe 100644
--- a/embassy-usb-dfu/CHANGELOG.md
+++ b/embassy-usb-dfu/CHANGELOG.md
@@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ## Unreleased - ReleaseDate
 
 - changed: Do not reset in the GetStatus request
+- Allow enabling the `application` and `dfu` feature at the same time
 
 ## 0.2.0 - 2025-08-27
 
diff --git a/embassy-usb-dfu/src/application.rs b/embassy-usb-dfu/src/application.rs
index 4b7b72073..78eb2c083 100644
--- a/embassy-usb-dfu/src/application.rs
+++ b/embassy-usb-dfu/src/application.rs
@@ -1,3 +1,4 @@
+//! Application part of DFU logic
 use embassy_boot::BlockingFirmwareState;
 use embassy_time::{Duration, Instant};
 use embassy_usb::control::{InResponse, OutResponse, Recipient, RequestType};
diff --git a/embassy-usb-dfu/src/dfu.rs b/embassy-usb-dfu/src/dfu.rs
index 3a390a37a..7c28d04cf 100644
--- a/embassy-usb-dfu/src/dfu.rs
+++ b/embassy-usb-dfu/src/dfu.rs
@@ -1,3 +1,4 @@
+//! DFU bootloader part of DFU logic
 use embassy_boot::{AlignedBuffer, BlockingFirmwareUpdater, FirmwareUpdaterError};
 use embassy_usb::control::{InResponse, OutResponse, Recipient, RequestType};
 use embassy_usb::driver::Driver;
diff --git a/embassy-usb-dfu/src/lib.rs b/embassy-usb-dfu/src/lib.rs
index 54ffa7276..e9f4278b6 100644
--- a/embassy-usb-dfu/src/lib.rs
+++ b/embassy-usb-dfu/src/lib.rs
@@ -6,21 +6,15 @@ mod fmt;
 pub mod consts;
 
 #[cfg(feature = "dfu")]
-mod dfu;
-#[cfg(feature = "dfu")]
+pub mod dfu;
+#[cfg(all(feature = "dfu", not(feature = "application")))]
 pub use self::dfu::*;
 
 #[cfg(feature = "application")]
-mod application;
-#[cfg(feature = "application")]
+pub mod application;
+#[cfg(all(feature = "application", not(feature = "dfu")))]
 pub use self::application::*;
 
-#[cfg(any(
-    all(feature = "dfu", feature = "application"),
-    not(any(feature = "dfu", feature = "application"))
-))]
-compile_error!("usb-dfu must be compiled with exactly one of `dfu`, or `application` features");
-
 /// Provides a platform-agnostic interface for initiating a system reset.
 ///
 /// This crate exposes `ResetImmediate` when compiled with cortex-m or esp32c3 support, which immediately issues a
diff --git a/embassy-usb-driver/CHANGELOG.md b/embassy-usb-driver/CHANGELOG.md
index 15875e087..71768d7e5 100644
--- a/embassy-usb-driver/CHANGELOG.md
+++ b/embassy-usb-driver/CHANGELOG.md
@@ -8,6 +8,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 <!-- next-header -->
 ## Unreleased - ReleaseDate
 
+- Add `EndpointOut::read_data()` and `EndpointIn::write_data()` provided methods.
+
 ## 0.2.0 - 2025-07-16
 
 - Make USB endpoint allocator methods accept an optional `EndpointAddress`.
diff --git a/embassy-usb-driver/src/lib.rs b/embassy-usb-driver/src/lib.rs
index 99616f1ec..3ad96c61d 100644
--- a/embassy-usb-driver/src/lib.rs
+++ b/embassy-usb-driver/src/lib.rs
@@ -236,6 +236,22 @@ pub trait EndpointOut: Endpoint {
     ///
     /// This should also clear any NAK flags and prepare the endpoint to receive the next packet.
     async fn read(&mut self, buf: &mut [u8]) -> Result<usize, EndpointError>;
+
+    /// Read until the buffer is full or we receive a short packet from the USB host returning the
+    /// actual length of the entire data block.
+    ///
+    /// This should also clear any NAK flags and prepare the endpoint to receive the next packet or
+    /// data block.
+    async fn read_transfer(&mut self, buf: &mut [u8]) -> Result<usize, EndpointError> {
+        let mut n = 0;
+        loop {
+            let i = self.read(&mut buf[n..]).await?;
+            n += i;
+            if i < self.info().max_packet_size as usize {
+                return Ok(n);
+            }
+        }
+    }
 }
 
 /// USB control pipe trait.
@@ -349,6 +365,20 @@ pub trait ControlPipe {
 pub trait EndpointIn: Endpoint {
     /// Write a single packet of data to the endpoint.
     async fn write(&mut self, buf: &[u8]) -> Result<(), EndpointError>;
+
+    /// Write all the data from buf to the endpoint one wMaxPacketSize chunk at a time.
+    ///
+    /// If the buffer size is evenly divisible by wMaxPacketSize, this will also ensure the
+    /// terminating zero-length-packet is transmitted.
+    async fn write_transfer(&mut self, buf: &[u8], needs_zlp: bool) -> Result<(), EndpointError> {
+        for chunk in buf.chunks(self.info().max_packet_size as usize) {
+            self.write(chunk).await?;
+        }
+        if needs_zlp && buf.len() % self.info().max_packet_size as usize == 0 {
+            self.write(&[]).await?;
+        }
+        Ok(())
+    }
 }
 
 #[derive(Copy, Clone, Eq, PartialEq, Debug)]
diff --git a/embassy-usb-synopsys-otg/CHANGELOG.md b/embassy-usb-synopsys-otg/CHANGELOG.md
index 9ca90f5e9..45353d907 100644
--- a/embassy-usb-synopsys-otg/CHANGELOG.md
+++ b/embassy-usb-synopsys-otg/CHANGELOG.md
@@ -10,6 +10,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ## 0.3.1 - 2025-08-26
 
+- Improve receive performance, more efficient copy from FIFO
+
 ## 0.3.0 - 2025-07-22
 
 - Bump `embassy-usb-driver` to v0.2.0
diff --git a/embassy-usb-synopsys-otg/src/lib.rs b/embassy-usb-synopsys-otg/src/lib.rs
index 9d74c046d..6b4a87bdf 100644
--- a/embassy-usb-synopsys-otg/src/lib.rs
+++ b/embassy-usb-synopsys-otg/src/lib.rs
@@ -76,10 +76,16 @@ pub unsafe fn on_interrupt<const MAX_EP_COUNT: usize>(r: Otg, state: &State<MAX_
                     let buf =
                         unsafe { core::slice::from_raw_parts_mut(*state.ep_states[ep_num].out_buffer.get(), len) };
 
-                    for chunk in buf.chunks_mut(4) {
+                    let mut chunks = buf.chunks_exact_mut(4);
+                    for chunk in &mut chunks {
                         // RX FIFO is shared so always read from fifo(0)
                         let data = r.fifo(0).read().0;
-                        chunk.copy_from_slice(&data.to_ne_bytes()[0..chunk.len()]);
+                        chunk.copy_from_slice(&data.to_ne_bytes());
+                    }
+                    let rem = chunks.into_remainder();
+                    if !rem.is_empty() {
+                        let data = r.fifo(0).read().0;
+                        rem.copy_from_slice(&data.to_ne_bytes()[0..rem.len()]);
                     }
 
                     state.ep_states[ep_num].out_size.store(len as u16, Ordering::Release);
@@ -1229,23 +1235,19 @@ impl<'d> embassy_usb_driver::EndpointIn for Endpoint<'d, In> {
             });
 
             // Write data to FIFO
-            let chunks = buf.chunks_exact(4);
-            // Stash the last partial chunk
-            let rem = chunks.remainder();
-            let last_chunk = (!rem.is_empty()).then(|| {
-                let mut tmp = [0u8; 4];
-                tmp[0..rem.len()].copy_from_slice(rem);
-                u32::from_ne_bytes(tmp)
-            });
-
             let fifo = self.regs.fifo(index);
-            for chunk in chunks {
+            let mut chunks = buf.chunks_exact(4);
+            for chunk in &mut chunks {
                 let val = u32::from_ne_bytes(chunk.try_into().unwrap());
                 fifo.write_value(regs::Fifo(val));
             }
             // Write any last chunk
-            if let Some(val) = last_chunk {
-                fifo.write_value(regs::Fifo(val));
+            let rem = chunks.remainder();
+            if !rem.is_empty() {
+                let mut tmp = [0u8; 4];
+                tmp[0..rem.len()].copy_from_slice(rem);
+                let tmp = u32::from_ne_bytes(tmp);
+                fifo.write_value(regs::Fifo(tmp));
             }
         });
 
diff --git a/examples/lpc55s69/Cargo.toml b/examples/lpc55s69/Cargo.toml
index 79b27f269..579748595 100644
--- a/examples/lpc55s69/Cargo.toml
+++ b/examples/lpc55s69/Cargo.toml
@@ -7,7 +7,7 @@ license = "MIT OR Apache-2.0"
 publish = false
 
 [dependencies]
-embassy-nxp = { version = "0.1.0", path = "../../embassy-nxp", features = ["lpc55", "rt", "defmt", "time-driver-rtc"] }
+embassy-nxp = { version = "0.1.0", path = "../../embassy-nxp", features = ["lpc55-core0", "rt", "defmt", "time-driver-rtc"] }
 embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt"] }
 embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt"] }
 embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "tick-hz-32_768"] }
diff --git a/examples/mspm0c1104/Cargo.toml b/examples/mspm0c1104/Cargo.toml
index 4daddbbb4..21434106a 100644
--- a/examples/mspm0c1104/Cargo.toml
+++ b/examples/mspm0c1104/Cargo.toml
@@ -33,7 +33,6 @@ lto = true
 codegen-units = 1
 
 [package.metadata.embassy]
-skip = true # TODO: remove when we find a way to decrease the defmt buffer size in ci.
 build = [
-  { target = "thumbv6m-none-eabi", artifact-dir = "out/examples/mspm0c1104" }
+  { target = "thumbv6m-none-eabi", artifact-dir = "out/examples/mspm0c1104", env = { DEFMT_RTT_BUFFER_SIZE = "72" }}
 ]
diff --git a/examples/mspm0g3507/src/bin/adc.rs b/examples/mspm0g3507/src/bin/adc.rs
new file mode 100644
index 000000000..ceccc7c02
--- /dev/null
+++ b/examples/mspm0g3507/src/bin/adc.rs
@@ -0,0 +1,39 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_mspm0::adc::{self, Adc, Vrsel};
+use embassy_mspm0::{bind_interrupts, peripherals, Config};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_halt as _};
+
+bind_interrupts!(struct Irqs {
+    ADC0 => adc::InterruptHandler<peripherals::ADC0>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) -> ! {
+    info!("Hello world!");
+    let p = embassy_mspm0::init(Config::default());
+
+    // Configure adc with sequence 0 to 1
+    let mut adc = Adc::new_async(p.ADC0, Default::default(), Irqs);
+    let sequence = [(&p.PA22.into(), Vrsel::VddaVssa), (&p.PB20.into(), Vrsel::VddaVssa)];
+    let mut readings = [0u16; 2];
+
+    loop {
+        let r = adc.read_channel(&p.PA27).await;
+        info!("Raw adc PA27: {}", r);
+        // With a voltage range of 0-3.3V and a resolution of 12 bits, the raw value can be
+        // approximated to voltage (~0.0008 per step).
+        let mut x = r as u32;
+        x = x * 8;
+        info!("Adc voltage PA27: {},{:#04}", x / 10_000, x % 10_000);
+        // Read a sequence of channels
+        adc.read_sequence(sequence.into_iter(), &mut readings).await;
+        info!("Raw adc sequence: {}", readings);
+
+        Timer::after_millis(400).await;
+    }
+}
diff --git a/examples/mspm0l1306/src/bin/adc.rs b/examples/mspm0l1306/src/bin/adc.rs
new file mode 100644
index 000000000..2806b98cc
--- /dev/null
+++ b/examples/mspm0l1306/src/bin/adc.rs
@@ -0,0 +1,39 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_mspm0::adc::{self, Adc, Vrsel};
+use embassy_mspm0::{bind_interrupts, peripherals, Config};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_halt as _};
+
+bind_interrupts!(struct Irqs {
+    ADC0 => adc::InterruptHandler<peripherals::ADC0>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) -> ! {
+    info!("Hello world!");
+    let p = embassy_mspm0::init(Config::default());
+
+    // Configure adc with sequence 0 to 1
+    let mut adc = Adc::new_async(p.ADC0, Default::default(), Irqs);
+    let sequence = [(&p.PA22.into(), Vrsel::VddaVssa), (&p.PA20.into(), Vrsel::VddaVssa)];
+    let mut readings = [0u16; 2];
+
+    loop {
+        let r = adc.read_channel(&p.PA27).await;
+        info!("Raw adc PA27: {}", r);
+        // With a voltage range of 0-3.3V and a resolution of 12 bits, the raw value can be
+        // approximated to voltage (~0.0008 per step).
+        let mut x = r as u32;
+        x = x * 8;
+        info!("Adc voltage PA27: {},{:#04}", x / 10_000, x % 10_000);
+        // Read a sequence of channels
+        adc.read_sequence(sequence.into_iter(), &mut readings).await;
+        info!("Raw adc sequence: {}", readings);
+
+        Timer::after_millis(400).await;
+    }
+}
diff --git a/examples/nrf52840-edf/.cargo/config.toml b/examples/nrf52840-edf/.cargo/config.toml
new file mode 100644
index 000000000..e0b9ce59e
--- /dev/null
+++ b/examples/nrf52840-edf/.cargo/config.toml
@@ -0,0 +1,9 @@
+[target.'cfg(all(target_arch = "arm", target_os = "none"))']
+# replace nRF82840_xxAA with your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip nRF52840_xxAA"
+
+[build]
+target = "thumbv7em-none-eabi"
+
+[env]
+DEFMT_LOG = "debug"
diff --git a/examples/nrf52840-edf/Cargo.toml b/examples/nrf52840-edf/Cargo.toml
new file mode 100644
index 000000000..1e8803233
--- /dev/null
+++ b/examples/nrf52840-edf/Cargo.toml
@@ -0,0 +1,27 @@
+[package]
+edition = "2021"
+name = "embassy-nrf52840-edf-examples"
+version = "0.1.0"
+license = "MIT OR Apache-2.0"
+publish = false
+
+[dependencies]
+# NOTE: "scheduler-deadline" and "embassy-time-driver" features are enabled
+embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "scheduler-deadline", "embassy-time-driver"] }
+embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
+embassy-nrf = { version = "0.7.0", path = "../../embassy-nrf", features = ["defmt", "nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
+
+defmt = "1.0.1"
+defmt-rtt = "1.0.0"
+
+cortex-m = { version = "0.7.6", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = "0.7.0"
+panic-probe = { version = "1.0.0", features = ["print-defmt"] }
+
+[profile.release]
+debug = 2
+
+[package.metadata.embassy]
+build = [
+  { target = "thumbv7em-none-eabi", artifact-dir = "out/examples/nrf52840-edf" }
+]
diff --git a/examples/nrf52840-edf/build.rs b/examples/nrf52840-edf/build.rs
new file mode 100644
index 000000000..30691aa97
--- /dev/null
+++ b/examples/nrf52840-edf/build.rs
@@ -0,0 +1,35 @@
+//! This build script copies the `memory.x` file from the crate root into
+//! a directory where the linker can always find it at build time.
+//! For many projects this is optional, as the linker always searches the
+//! project root directory -- wherever `Cargo.toml` is. However, if you
+//! are using a workspace or have a more complicated build setup, this
+//! build script becomes required. Additionally, by requesting that
+//! Cargo re-run the build script whenever `memory.x` is changed,
+//! updating `memory.x` ensures a rebuild of the application with the
+//! new memory settings.
+
+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+
+fn main() {
+    // Put `memory.x` in our output directory and ensure it's
+    // on the linker search path.
+    let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+    File::create(out.join("memory.x"))
+        .unwrap()
+        .write_all(include_bytes!("memory.x"))
+        .unwrap();
+    println!("cargo:rustc-link-search={}", out.display());
+
+    // By default, Cargo will re-run a build script whenever
+    // any file in the project changes. By specifying `memory.x`
+    // here, we ensure the build script is only re-run when
+    // `memory.x` is changed.
+    println!("cargo:rerun-if-changed=memory.x");
+
+    println!("cargo:rustc-link-arg-bins=--nmagic");
+    println!("cargo:rustc-link-arg-bins=-Tlink.x");
+    println!("cargo:rustc-link-arg-bins=-Tdefmt.x");
+}
diff --git a/examples/nrf52840-edf/memory.x b/examples/nrf52840-edf/memory.x
new file mode 100644
index 000000000..15b492bce
--- /dev/null
+++ b/examples/nrf52840-edf/memory.x
@@ -0,0 +1,12 @@
+MEMORY
+{
+  /* NOTE 1 K = 1 KiBi = 1024 bytes */
+  FLASH : ORIGIN = 0x00000000, LENGTH = 1024K
+  RAM : ORIGIN = 0x20000000, LENGTH = 256K
+
+  /* These values correspond to the NRF52840 with Softdevices S140 7.3.0 */
+  /*
+     FLASH : ORIGIN = 0x00027000, LENGTH = 868K
+     RAM : ORIGIN = 0x20020000, LENGTH = 128K
+  */
+}
diff --git a/examples/nrf52840-edf/src/bin/basic.rs b/examples/nrf52840-edf/src/bin/basic.rs
new file mode 100644
index 000000000..d888e17d1
--- /dev/null
+++ b/examples/nrf52840-edf/src/bin/basic.rs
@@ -0,0 +1,194 @@
+//! Basic side-by-side example of the Earliest Deadline First scheduler
+//!
+//! This test spawns a number of background "ambient system load" workers
+//! that are constantly working, and runs two sets of trials.
+//!
+//! The first trial runs with no deadline set, so our trial task is at the
+//! same prioritization level as the background worker tasks.
+//!
+//! The second trial sets a deadline, meaning that it will be given higher
+//! scheduling priority than background tasks, that have no deadline set
+
+#![no_std]
+#![no_main]
+
+use core::sync::atomic::{compiler_fence, Ordering};
+
+use defmt::unwrap;
+use embassy_executor::Spawner;
+use embassy_time::{Duration, Instant, Timer};
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(spawner: Spawner) {
+    embassy_nrf::init(Default::default());
+
+    // Enable flash cache to remove some flash latency jitter
+    compiler_fence(Ordering::SeqCst);
+    embassy_nrf::pac::NVMC.icachecnf().write(|w| {
+        w.set_cacheen(true);
+    });
+    compiler_fence(Ordering::SeqCst);
+
+    //
+    // Baseline system load tunables
+    //
+
+    // how many load tasks? More load tasks means more tasks contending
+    // for the runqueue
+    let tasks = 32;
+    // how long should each task work for? The longer the working time,
+    // the longer the max jitter possible, even when a task is prioritized,
+    // as EDF is still cooperative and not pre-emptive
+    //
+    // 33 ticks ~= 1ms
+    let work_time_ticks = 33;
+    // what fraction, 1/denominator, should the system be busy?
+    // bigger number means **less** busy
+    //
+    // 2  => 50%
+    // 4  => 25%
+    // 10 => 10%
+    let denominator = 2;
+
+    // Total time window, so each worker is working 1/denominator
+    // amount of the total time
+    let time_window = work_time_ticks * u64::from(tasks) * denominator;
+
+    // Spawn all of our load workers!
+    for i in 0..tasks {
+        spawner.spawn(unwrap!(load_task(i, work_time_ticks, time_window)));
+    }
+
+    // Let all the tasks spin up
+    defmt::println!("Spinning up load tasks...");
+    Timer::after_secs(1).await;
+
+    //
+    // Trial task worker tunables
+    //
+
+    // How many steps should the workers under test run?
+    // More steps means more chances to have to wait for other tasks
+    // in line ahead of us.
+    let num_steps = 100;
+
+    // How many ticks should the worker take working on each step?
+    //
+    // 33 ticks ~= 1ms
+    let work_ticks = 33;
+    // How many ticks should the worker wait on each step?
+    //
+    // 66 ticks ~= 2ms
+    let idle_ticks = 66;
+
+    // How many times to repeat each trial?
+    let trials = 3;
+
+    // The total time a trial would take, in a perfect unloaded system
+    let theoretical = (num_steps * work_ticks) + (num_steps * idle_ticks);
+
+    defmt::println!("");
+    defmt::println!("Starting UNPRIORITIZED worker trials");
+    for _ in 0..trials {
+        //
+        // UNPRIORITIZED worker
+        //
+        defmt::println!("");
+        defmt::println!("Starting unprioritized worker");
+        let start = Instant::now();
+        for _ in 0..num_steps {
+            let now = Instant::now();
+            while now.elapsed().as_ticks() < work_ticks {}
+            Timer::after_ticks(idle_ticks).await;
+        }
+        let elapsed = start.elapsed().as_ticks();
+        defmt::println!(
+            "Trial complete, theoretical ticks: {=u64}, actual ticks: {=u64}",
+            theoretical,
+            elapsed
+        );
+        let ratio = ((elapsed as f32) / (theoretical as f32)) * 100.0;
+        defmt::println!("Took {=f32}% of ideal time", ratio);
+        Timer::after_millis(500).await;
+    }
+
+    Timer::after_secs(1).await;
+
+    defmt::println!("");
+    defmt::println!("Starting PRIORITIZED worker trials");
+    for _ in 0..trials {
+        //
+        // PRIORITIZED worker
+        //
+        defmt::println!("");
+        defmt::println!("Starting prioritized worker");
+        let start = Instant::now();
+        // Set the deadline to ~2x the theoretical time. In practice, setting any deadline
+        // here elevates the current task above all other worker tasks.
+        let meta = embassy_executor::Metadata::for_current_task().await;
+        meta.set_deadline_after(theoretical * 2);
+
+        // Perform the trial
+        for _ in 0..num_steps {
+            let now = Instant::now();
+            while now.elapsed().as_ticks() < work_ticks {}
+            Timer::after_ticks(idle_ticks).await;
+        }
+
+        let elapsed = start.elapsed().as_ticks();
+        defmt::println!(
+            "Trial complete, theoretical ticks: {=u64}, actual ticks: {=u64}",
+            theoretical,
+            elapsed
+        );
+        let ratio = ((elapsed as f32) / (theoretical as f32)) * 100.0;
+        defmt::println!("Took {=f32}% of ideal time", ratio);
+
+        // Unset the deadline, deadlines are not automatically cleared, and if our
+        // deadline is in the past, then we get very high priority!
+        meta.unset_deadline();
+
+        Timer::after_millis(500).await;
+    }
+
+    defmt::println!("");
+    defmt::println!("Trials Complete.");
+}
+
+#[embassy_executor::task(pool_size = 32)]
+async fn load_task(id: u32, ticks_on: u64, ttl_ticks: u64) {
+    let mut last_print = Instant::now();
+    let mut last_tick = last_print;
+    let mut variance = 0;
+    let mut max_variance = 0;
+    loop {
+        let tgt = last_tick + Duration::from_ticks(ttl_ticks);
+        assert!(tgt > Instant::now(), "fell too behind!");
+
+        Timer::at(tgt).await;
+        let now = Instant::now();
+        // How late are we from the target?
+        let var = now.duration_since(tgt).as_ticks();
+        max_variance = max_variance.max(var);
+        variance += var;
+
+        // blocking work
+        while now.elapsed().as_ticks() < ticks_on {}
+
+        if last_print.elapsed() >= Duration::from_secs(1) {
+            defmt::trace!(
+                "Task {=u32} variance ticks (1s): {=u64}, max: {=u64}, act: {=u64}",
+                id,
+                variance,
+                max_variance,
+                ticks_on,
+            );
+            max_variance = 0;
+            variance = 0;
+            last_print = Instant::now();
+        }
+
+        last_tick = tgt;
+    }
+}
diff --git a/examples/nrf52840-rtic/src/bin/blinky.rs b/examples/nrf52840-rtic/src/bin/blinky.rs
index 719e22729..2adac7e0a 100644
--- a/examples/nrf52840-rtic/src/bin/blinky.rs
+++ b/examples/nrf52840-rtic/src/bin/blinky.rs
@@ -1,6 +1,5 @@
 #![no_std]
 #![no_main]
-#![feature(type_alias_impl_trait)]
 
 use {defmt_rtt as _, panic_probe as _};
 
diff --git a/examples/nrf52840/Cargo.toml b/examples/nrf52840/Cargo.toml
index a9339bcd3..452e83b7e 100644
--- a/examples/nrf52840/Cargo.toml
+++ b/examples/nrf52840/Cargo.toml
@@ -10,8 +10,8 @@ embassy-futures = { version = "0.1.2", path = "../../embassy-futures" }
 embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
-embassy-nrf = { version = "0.7.0", path = "../../embassy-nrf", features = ["defmt", "nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
-embassy-net = { version = "0.7.1", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet"] }
+embassy-nrf = { version = "0.7.0", path = "../../embassy-nrf", features = ["defmt", "nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac", "time", "net-driver"] }
+embassy-net = { version = "0.7.1", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet","udp", "medium-ieee802154", "proto-ipv6"] }
 embassy-usb = { version = "0.5.1", path = "../../embassy-usb", features = ["defmt"] }
 embedded-io = { version = "0.6.0", features = ["defmt-03"]  }
 embedded-io-async = { version = "0.6.1", features = ["defmt-03"] }
diff --git a/examples/nrf52840/src/bin/nfct.rs b/examples/nrf52840/src/bin/nfct.rs
index d559d006a..fafa37f48 100644
--- a/examples/nrf52840/src/bin/nfct.rs
+++ b/examples/nrf52840/src/bin/nfct.rs
@@ -1,11 +1,12 @@
 #![no_std]
 #![no_main]
 
-use defmt::*;
+use defmt::{todo, *};
 use embassy_executor::Spawner;
 use embassy_nrf::config::HfclkSource;
 use embassy_nrf::nfct::{Config as NfcConfig, NfcId, NfcT};
 use embassy_nrf::{bind_interrupts, nfct};
+use iso14443_4::{Card, IsoDep};
 use {defmt_rtt as _, embassy_nrf as _, panic_probe as _};
 
 bind_interrupts!(struct Irqs {
@@ -30,12 +31,28 @@ async fn main(_spawner: Spawner) {
 
     let mut buf = [0u8; 256];
 
+    let cc = &[
+        0x00, 0x0f, /* CCEN_HI, CCEN_LOW */
+        0x20, /* VERSION */
+        0x00, 0x7f, /* MLe_HI, MLe_LOW */
+        0x00, 0x7f, /* MLc_HI, MLc_LOW */
+        /* TLV */
+        0x04, 0x06, 0xe1, 0x04, 0x00, 0x7f, 0x00, 0x00,
+    ];
+
+    let ndef = &[
+        0x00, 0x10, 0xd1, 0x1, 0xc, 0x55, 0x4, 0x65, 0x6d, 0x62, 0x61, 0x73, 0x73, 0x79, 0x2e, 0x64, 0x65, 0x76,
+    ];
+    let mut selected: &[u8] = cc;
+
     loop {
         info!("activating");
         nfc.activate().await;
+        info!("activated!");
+
+        let mut nfc = IsoDep::new(iso14443_3::Logger(&mut nfc));
 
         loop {
-            info!("rxing");
             let n = match nfc.receive(&mut buf).await {
                 Ok(n) => n,
                 Err(e) => {
@@ -44,25 +61,51 @@ async fn main(_spawner: Spawner) {
                 }
             };
             let req = &buf[..n];
-            info!("received frame {:02x}", req);
+            info!("iso-dep rx {:02x}", req);
 
-            let mut deselect = false;
-            let resp = match req {
-                [0xe0, ..] => {
-                    info!("Got RATS, tx'ing ATS");
-                    &[0x06, 0x77, 0x77, 0x81, 0x02, 0x80][..]
+            let Ok(apdu) = Apdu::parse(req) else {
+                error!("apdu parse error");
+                break;
+            };
+
+            info!("apdu: {:?}", apdu);
+
+            let resp = match (apdu.cla, apdu.ins, apdu.p1, apdu.p2) {
+                (0, 0xa4, 4, 0) => {
+                    info!("select app");
+                    &[0x90, 0x00][..]
                 }
-                [0xc2] => {
-                    info!("Got deselect!");
-                    deselect = true;
-                    &[0xc2]
+                (0, 0xa4, 0, 12) => {
+                    info!("select df");
+                    match apdu.data {
+                        [0xe1, 0x03] => {
+                            selected = cc;
+                            &[0x90, 0x00][..]
+                        }
+                        [0xe1, 0x04] => {
+                            selected = ndef;
+                            &[0x90, 0x00][..]
+                        }
+                        _ => todo!(), // return NOT FOUND
+                    }
+                }
+                (0, 0xb0, p1, p2) => {
+                    info!("read");
+                    let offs = u16::from_be_bytes([p1 & 0x7f, p2]) as usize;
+                    let len = if apdu.le == 0 { usize::MAX } else { apdu.le as usize };
+                    let n = len.min(selected.len() - offs);
+                    buf[..n].copy_from_slice(&selected[offs..][..n]);
+                    buf[n..][..2].copy_from_slice(&[0x90, 0x00]);
+                    &buf[..n + 2]
                 }
                 _ => {
                     info!("Got unknown command!");
-                    &[0xFF]
+                    &[0xFF, 0xFF]
                 }
             };
 
+            info!("iso-dep tx {:02x}", resp);
+
             match nfc.transmit(resp).await {
                 Ok(()) => {}
                 Err(e) => {
@@ -70,10 +113,211 @@ async fn main(_spawner: Spawner) {
                     break;
                 }
             }
+        }
+    }
+}
 
-            if deselect {
-                break;
+#[derive(Debug, Clone, defmt::Format)]
+struct Apdu<'a> {
+    pub cla: u8,
+    pub ins: u8,
+    pub p1: u8,
+    pub p2: u8,
+    pub data: &'a [u8],
+    pub le: u16,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, defmt::Format)]
+struct ApduParseError;
+
+impl<'a> Apdu<'a> {
+    pub fn parse(apdu: &'a [u8]) -> Result<Self, ApduParseError> {
+        if apdu.len() < 4 {
+            return Err(ApduParseError);
+        }
+
+        let (data, le) = match apdu.len() - 4 {
+            0 => (&[][..], 0),
+            1 => (&[][..], apdu[4]),
+            n if n == 1 + apdu[4] as usize && apdu[4] != 0 => (&apdu[5..][..apdu[4] as usize], 0),
+            n if n == 2 + apdu[4] as usize && apdu[4] != 0 => (&apdu[5..][..apdu[4] as usize], apdu[apdu.len() - 1]),
+            _ => return Err(ApduParseError),
+        };
+
+        Ok(Apdu {
+            cla: apdu[0],
+            ins: apdu[1],
+            p1: apdu[2],
+            p2: apdu[3],
+            data,
+            le: le as _,
+        })
+    }
+}
+
+mod iso14443_3 {
+    use core::future::Future;
+
+    use defmt::info;
+    use embassy_nrf::nfct::{Error, NfcT};
+
+    pub trait Card {
+        type Error;
+        async fn receive(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error>;
+        async fn transmit(&mut self, buf: &[u8]) -> Result<(), Self::Error>;
+    }
+
+    impl<'a, T: Card> Card for &'a mut T {
+        type Error = T::Error;
+
+        fn receive(&mut self, buf: &mut [u8]) -> impl Future<Output = Result<usize, Self::Error>> {
+            T::receive(self, buf)
+        }
+
+        fn transmit(&mut self, buf: &[u8]) -> impl Future<Output = Result<(), Self::Error>> {
+            T::transmit(self, buf)
+        }
+    }
+
+    impl<'a> Card for NfcT<'a> {
+        type Error = Error;
+
+        fn receive(&mut self, buf: &mut [u8]) -> impl Future<Output = Result<usize, Self::Error>> {
+            self.receive(buf)
+        }
+
+        fn transmit(&mut self, buf: &[u8]) -> impl Future<Output = Result<(), Self::Error>> {
+            self.transmit(buf)
+        }
+    }
+
+    pub struct Logger<T: Card>(pub T);
+
+    impl<T: Card> Card for Logger<T> {
+        type Error = T::Error;
+
+        async fn receive(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
+            let n = T::receive(&mut self.0, buf).await?;
+            info!("<- {:02x}", &buf[..n]);
+            Ok(n)
+        }
+
+        fn transmit(&mut self, buf: &[u8]) -> impl Future<Output = Result<(), Self::Error>> {
+            info!("-> {:02x}", buf);
+            T::transmit(&mut self.0, buf)
+        }
+    }
+}
+
+mod iso14443_4 {
+    use defmt::info;
+
+    use crate::iso14443_3;
+
+    #[derive(defmt::Format)]
+    pub enum Error<T> {
+        Deselected,
+        Protocol,
+        Lower(T),
+    }
+
+    pub trait Card {
+        type Error;
+        async fn receive(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error>;
+        async fn transmit(&mut self, buf: &[u8]) -> Result<(), Self::Error>;
+    }
+
+    pub struct IsoDep<T: iso14443_3::Card> {
+        nfc: T,
+
+        /// Block count spin bit: 0 or 1
+        block_num: u8,
+
+        /// true if deselected. This is permanent, you must create another IsoDep
+        /// instance if we get selected again.
+        deselected: bool,
+
+        /// last response, in case we need to retransmit.
+        resp: [u8; 256],
+        resp_len: usize,
+    }
+
+    impl<T: iso14443_3::Card> IsoDep<T> {
+        pub fn new(nfc: T) -> Self {
+            Self {
+                nfc,
+                block_num: 1,
+                deselected: false,
+                resp: [0u8; 256],
+                resp_len: 0,
             }
         }
     }
+
+    impl<T: iso14443_3::Card> Card for IsoDep<T> {
+        type Error = Error<T::Error>;
+
+        async fn receive(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
+            if self.deselected {
+                return Err(Error::Deselected);
+            }
+
+            let mut temp = [0u8; 256];
+
+            loop {
+                let n = self.nfc.receive(&mut temp).await.map_err(Error::Lower)?;
+                assert!(n != 0);
+                match temp[0] {
+                    0x02 | 0x03 => {
+                        self.block_num ^= 0x01;
+                        assert!(temp[0] == 0x02 | self.block_num);
+                        buf[..n - 1].copy_from_slice(&temp[1..n]);
+                        return Ok(n - 1);
+                    }
+                    0xb2 | 0xb3 => {
+                        if temp[0] & 0x01 != self.block_num {
+                            info!("Got NAK, transmitting ACK.");
+                            let resp = &[0xA2 | self.block_num];
+                            self.nfc.transmit(resp).await.map_err(Error::Lower)?;
+                        } else {
+                            info!("Got NAK, retransmitting.");
+                            let resp: &[u8] = &self.resp[..self.resp_len];
+                            self.nfc.transmit(resp).await.map_err(Error::Lower)?;
+                        }
+                    }
+                    0xe0 => {
+                        info!("Got RATS, tx'ing ATS");
+                        let resp = &[0x06, 0x77, 0x77, 0x81, 0x02, 0x80];
+                        self.nfc.transmit(resp).await.map_err(Error::Lower)?;
+                    }
+                    0xc2 => {
+                        info!("Got deselect!");
+                        self.deselected = true;
+                        let resp = &[0xC2];
+                        self.nfc.transmit(resp).await.map_err(Error::Lower)?;
+                        return Err(Error::Deselected);
+                    }
+                    _ => {
+                        info!("Got unknown command {:02x}!", temp[0]);
+                        return Err(Error::Protocol);
+                    }
+                };
+            }
+        }
+
+        async fn transmit(&mut self, buf: &[u8]) -> Result<(), Self::Error> {
+            if self.deselected {
+                return Err(Error::Deselected);
+            }
+
+            self.resp[0] = 0x02 | self.block_num;
+            self.resp[1..][..buf.len()].copy_from_slice(buf);
+            self.resp_len = 1 + buf.len();
+
+            let resp: &[u8] = &self.resp[..self.resp_len];
+            self.nfc.transmit(resp).await.map_err(Error::Lower)?;
+
+            Ok(())
+        }
+    }
 }
diff --git a/examples/nrf52840/src/bin/sixlowpan.rs b/examples/nrf52840/src/bin/sixlowpan.rs
new file mode 100644
index 000000000..00a597366
--- /dev/null
+++ b/examples/nrf52840/src/bin/sixlowpan.rs
@@ -0,0 +1,120 @@
+#![no_std]
+#![no_main]
+
+use core::net::Ipv6Addr;
+
+use defmt::{info, unwrap, warn};
+use embassy_executor::Spawner;
+use embassy_net::udp::{PacketMetadata, UdpMetadata, UdpSocket};
+use embassy_net::{IpAddress, IpEndpoint, IpListenEndpoint, Ipv6Cidr, StackResources, StaticConfigV6};
+use embassy_nrf::config::{Config, HfclkSource};
+use embassy_nrf::rng::Rng;
+use embassy_nrf::{bind_interrupts, embassy_net_802154_driver as net, peripherals, radio};
+use embassy_time::Delay;
+use embedded_hal_async::delay::DelayNs;
+use static_cell::StaticCell;
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    RADIO => radio::InterruptHandler<peripherals::RADIO>;
+    RNG => embassy_nrf::rng::InterruptHandler<peripherals::RNG>;
+});
+
+#[embassy_executor::task]
+async fn ieee802154_task(runner: net::Runner<'static, peripherals::RADIO>) -> ! {
+    runner.run().await
+}
+
+#[embassy_executor::task]
+async fn net_task(mut runner: embassy_net::Runner<'static, net::Device<'static>>) -> ! {
+    runner.run().await
+}
+
+#[embassy_executor::main]
+async fn main(spawner: Spawner) {
+    let mut config = Config::default();
+    // Necessary to run the radio nrf52840 v1.11 5.4.1
+    config.hfclk_source = HfclkSource::ExternalXtal;
+    let p = embassy_nrf::init(config);
+
+    let mac_addr: [u8; 8] = [2, 3, 4, 5, 6, 7, 8, 9];
+    static NRF802154_STATE: StaticCell<net::State<20, 20>> = StaticCell::new();
+    let (device, runner) = net::new(mac_addr, p.RADIO, Irqs, NRF802154_STATE.init(net::State::new()))
+        .await
+        .unwrap();
+
+    spawner.spawn(unwrap!(ieee802154_task(runner)));
+
+    // Swap these when flashing a second board
+    let peer = Ipv6Addr::new(0xfe80, 0, 0, 0, 0xd701, 0xda3f, 0x3955, 0x82a4);
+    let local = Ipv6Addr::new(0xfe80, 0, 0, 0, 0xd701, 0xda3f, 0x3955, 0x82a5);
+
+    let config = embassy_net::Config::ipv6_static(StaticConfigV6 {
+        address: Ipv6Cidr::new(local, 64),
+        gateway: None,
+        dns_servers: Default::default(),
+    });
+
+    // Generate random seed
+    let mut rng = Rng::new(p.RNG, Irqs);
+    let mut seed = [0; 8];
+    rng.blocking_fill_bytes(&mut seed);
+    let seed = u64::from_le_bytes(seed);
+
+    // Init network stack
+    static RESOURCES: StaticCell<StackResources<3>> = StaticCell::new();
+    let (stack, runner) = embassy_net::new(device, config, RESOURCES.init(StackResources::new()), seed);
+
+    spawner.spawn(unwrap!(net_task(runner)));
+
+    let mut rx_buffer = [0; 2096];
+    let mut tx_buffer = [0; 2096];
+    let mut tx_m_buffer = [PacketMetadata::EMPTY; 5];
+    let mut rx_m_buffer = [PacketMetadata::EMPTY; 5];
+
+    let mut delay = Delay;
+    loop {
+        let mut socket = UdpSocket::new(
+            stack,
+            &mut tx_m_buffer,
+            &mut rx_buffer,
+            &mut rx_m_buffer,
+            &mut tx_buffer,
+        );
+        socket
+            .bind(IpListenEndpoint {
+                addr: Some(IpAddress::Ipv6(local)),
+                port: 1234,
+            })
+            .unwrap();
+        let rep = UdpMetadata {
+            endpoint: IpEndpoint {
+                addr: IpAddress::Ipv6(peer),
+                port: 1234,
+            },
+            local_address: Some(IpAddress::Ipv6(local)),
+            meta: Default::default(),
+        };
+
+        info!("Listening on {:?} UDP:1234...", local);
+
+        let mut recv_buf = [0; 12];
+        loop {
+            delay.delay_ms(2000).await;
+            if socket.may_recv() {
+                let n = match socket.recv_from(&mut recv_buf).await {
+                    Ok((0, _)) => panic!(),
+                    Ok((n, _)) => n,
+                    Err(e) => {
+                        warn!("read error: {:?}", e);
+                        break;
+                    }
+                };
+                info!("Received {:02x}", &recv_buf[..n]);
+            }
+
+            info!("Sending");
+            socket.send_to(b"Hello World", rep).await.unwrap();
+        }
+    }
+}
diff --git a/examples/rp/src/bin/ethernet_w55rp20_tcp_server.rs b/examples/rp/src/bin/ethernet_w55rp20_tcp_server.rs
new file mode 100644
index 000000000..f51df2df9
--- /dev/null
+++ b/examples/rp/src/bin/ethernet_w55rp20_tcp_server.rs
@@ -0,0 +1,155 @@
+//! This example implements a TCP echo server on port 1234 and using DHCP.
+//! Send it some data, you should see it echoed back and printed in the console.
+//!
+//! Example written for the [`WIZnet W55RP20-EVB-Pico`](https://docs.wiznet.io/Product/ioNIC/W55RP20/w55rp20-evb-pico) board.
+//! Note: the W55RP20 is a single package that contains both a RP2040 and the Wiznet W5500 ethernet
+//! controller
+
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_futures::yield_now;
+use embassy_net::{Stack, StackResources};
+use embassy_net_wiznet::chip::W5500;
+use embassy_net_wiznet::*;
+use embassy_rp::clocks::RoscRng;
+use embassy_rp::gpio::{Input, Level, Output, Pull};
+use embassy_rp::peripherals::PIO0;
+use embassy_rp::pio_programs::spi::Spi;
+use embassy_rp::spi::{Async, Config as SpiConfig};
+use embassy_rp::{bind_interrupts, pio};
+use embassy_time::{Delay, Duration};
+use embedded_hal_bus::spi::ExclusiveDevice;
+use embedded_io_async::Write;
+use static_cell::StaticCell;
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    PIO0_IRQ_0 => pio::InterruptHandler<PIO0>;
+});
+
+#[embassy_executor::task]
+async fn ethernet_task(
+    runner: Runner<
+        'static,
+        W5500,
+        ExclusiveDevice<Spi<'static, PIO0, 0, Async>, Output<'static>, Delay>,
+        Input<'static>,
+        Output<'static>,
+    >,
+) -> ! {
+    runner.run().await
+}
+
+#[embassy_executor::task]
+async fn net_task(mut runner: embassy_net::Runner<'static, Device<'static>>) -> ! {
+    runner.run().await
+}
+
+#[embassy_executor::main]
+async fn main(spawner: Spawner) {
+    let p = embassy_rp::init(Default::default());
+    let mut rng = RoscRng;
+    let mut led = Output::new(p.PIN_19, Level::Low);
+
+    // The W55RP20 uses a PIO unit for SPI communication, once the SPI bus has been formed using a
+    // PIO statemachine everything else is generally unchanged from the other examples that use the W5500
+    let mosi = p.PIN_23;
+    let miso = p.PIN_22;
+    let clk = p.PIN_21;
+
+    let pio::Pio { mut common, sm0, .. } = pio::Pio::new(p.PIO0, Irqs);
+
+    // Construct an SPI driver backed by a PIO state machine
+    let mut spi_cfg = SpiConfig::default();
+    spi_cfg.frequency = 12_500_000; // The PIO SPI program is much less stable than the actual SPI
+                                    // peripheral, use higher speeds at your peril
+    let spi = Spi::new(&mut common, sm0, clk, mosi, miso, p.DMA_CH0, p.DMA_CH1, spi_cfg);
+
+    // Further control pins
+    let cs = Output::new(p.PIN_20, Level::High);
+    let w5500_int = Input::new(p.PIN_24, Pull::Up);
+    let w5500_reset = Output::new(p.PIN_25, Level::High);
+
+    let mac_addr = [0x02, 0x00, 0x00, 0x00, 0x00, 0x00];
+    static STATE: StaticCell<State<8, 8>> = StaticCell::new();
+    let state = STATE.init(State::<8, 8>::new());
+    let (device, runner) = embassy_net_wiznet::new(
+        mac_addr,
+        state,
+        ExclusiveDevice::new(spi, cs, Delay),
+        w5500_int,
+        w5500_reset,
+    )
+    .await
+    .unwrap();
+    spawner.spawn(unwrap!(ethernet_task(runner)));
+
+    // Generate random seed
+    let seed = rng.next_u64();
+
+    // Init network stack
+    static RESOURCES: StaticCell<StackResources<3>> = StaticCell::new();
+    let (stack, runner) = embassy_net::new(
+        device,
+        embassy_net::Config::dhcpv4(Default::default()),
+        RESOURCES.init(StackResources::new()),
+        seed,
+    );
+
+    // Launch network task
+    spawner.spawn(unwrap!(net_task(runner)));
+
+    info!("Waiting for DHCP...");
+    let cfg = wait_for_config(stack).await;
+    let local_addr = cfg.address.address();
+    info!("IP address: {:?}", local_addr);
+
+    let mut rx_buffer = [0; 4096];
+    let mut tx_buffer = [0; 4096];
+    let mut buf = [0; 4096];
+    loop {
+        let mut socket = embassy_net::tcp::TcpSocket::new(stack, &mut rx_buffer, &mut tx_buffer);
+        socket.set_timeout(Some(Duration::from_secs(10)));
+
+        led.set_low();
+        info!("Listening on TCP:1234...");
+        if let Err(e) = socket.accept(1234).await {
+            warn!("accept error: {:?}", e);
+            continue;
+        }
+        info!("Received connection from {:?}", socket.remote_endpoint());
+        led.set_high();
+
+        loop {
+            let n = match socket.read(&mut buf).await {
+                Ok(0) => {
+                    warn!("read EOF");
+                    break;
+                }
+                Ok(n) => n,
+                Err(e) => {
+                    warn!("{:?}", e);
+                    break;
+                }
+            };
+            info!("rxd {}", core::str::from_utf8(&buf[..n]).unwrap());
+
+            if let Err(e) = socket.write_all(&buf[..n]).await {
+                warn!("write error: {:?}", e);
+                break;
+            }
+        }
+    }
+}
+
+async fn wait_for_config(stack: Stack<'static>) -> embassy_net::StaticConfigV4 {
+    loop {
+        if let Some(config) = stack.config_v4() {
+            return config.clone();
+        }
+        yield_now().await;
+    }
+}
diff --git a/examples/rp/src/bin/pio_onewire.rs b/examples/rp/src/bin/pio_onewire.rs
index 379e2b8f9..102f13c45 100644
--- a/examples/rp/src/bin/pio_onewire.rs
+++ b/examples/rp/src/bin/pio_onewire.rs
@@ -1,4 +1,5 @@
 //! This example shows how you can use PIO to read one or more `DS18B20` one-wire temperature sensors.
+//! This uses externally powered sensors. For parasite power, see the pio_onewire_parasite.rs example.
 
 #![no_std]
 #![no_main]
diff --git a/examples/rp/src/bin/pio_onewire_parasite.rs b/examples/rp/src/bin/pio_onewire_parasite.rs
new file mode 100644
index 000000000..fd076dee0
--- /dev/null
+++ b/examples/rp/src/bin/pio_onewire_parasite.rs
@@ -0,0 +1,89 @@
+//! This example shows how you can use PIO to read one or more `DS18B20`
+//! one-wire temperature sensors using parasite power.
+//! It applies a strong pullup during conversion, see "Powering the DS18B20" in the datasheet.
+//! For externally powered sensors, use the pio_onewire.rs example.
+
+#![no_std]
+#![no_main]
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_rp::bind_interrupts;
+use embassy_rp::peripherals::PIO0;
+use embassy_rp::pio::{InterruptHandler, Pio};
+use embassy_rp::pio_programs::onewire::{PioOneWire, PioOneWireProgram, PioOneWireSearch};
+use embassy_time::Duration;
+use heapless::Vec;
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    PIO0_IRQ_0 => InterruptHandler<PIO0>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = embassy_rp::init(Default::default());
+    let mut pio = Pio::new(p.PIO0, Irqs);
+
+    let prg = PioOneWireProgram::new(&mut pio.common);
+    let mut onewire = PioOneWire::new(&mut pio.common, pio.sm0, p.PIN_2, &prg);
+
+    info!("Starting onewire search");
+
+    let mut devices = Vec::<u64, 10>::new();
+    let mut search = PioOneWireSearch::new();
+    for _ in 0..10 {
+        if !search.is_finished() {
+            if let Some(address) = search.next(&mut onewire).await {
+                if crc8(&address.to_le_bytes()) == 0 {
+                    info!("Found address: {:x}", address);
+                    let _ = devices.push(address);
+                } else {
+                    warn!("Found invalid address: {:x}", address);
+                }
+            }
+        }
+    }
+
+    info!("Search done, found {} devices", devices.len());
+
+    loop {
+        // Read all devices one by one
+        for device in &devices {
+            onewire.reset().await;
+            onewire.write_bytes(&[0x55]).await; // Match rom
+            onewire.write_bytes(&device.to_le_bytes()).await;
+            // 750 ms delay required for default 12-bit resolution.
+            onewire.write_bytes_pullup(&[0x44], Duration::from_millis(750)).await;
+
+            onewire.reset().await;
+            onewire.write_bytes(&[0x55]).await; // Match rom
+            onewire.write_bytes(&device.to_le_bytes()).await;
+            onewire.write_bytes(&[0xBE]).await; // Read scratchpad
+
+            let mut data = [0; 9];
+            onewire.read_bytes(&mut data).await;
+            if crc8(&data) == 0 {
+                let temp = ((data[1] as u32) << 8 | data[0] as u32) as f32 / 16.;
+                info!("Read device {:x}: {} deg C", device, temp);
+            } else {
+                warn!("Reading device {:x} failed. {:02x}", device, data);
+            }
+        }
+    }
+}
+
+fn crc8(data: &[u8]) -> u8 {
+    let mut crc = 0;
+    for b in data {
+        let mut data_byte = *b;
+        for _ in 0..8 {
+            let temp = (crc ^ data_byte) & 0x01;
+            crc >>= 1;
+            if temp != 0 {
+                crc ^= 0x8C;
+            }
+            data_byte >>= 1;
+        }
+    }
+    crc
+}
diff --git a/examples/rp/src/bin/pio_spi.rs b/examples/rp/src/bin/pio_spi.rs
new file mode 100644
index 000000000..4218327ec
--- /dev/null
+++ b/examples/rp/src/bin/pio_spi.rs
@@ -0,0 +1,48 @@
+//! This example shows how to use a PIO state machine as an additional SPI
+//! (Serial Peripheral Interface) on the RP2040 chip. No specific hardware is
+//! specified in this example.
+//!
+//! If you connect pin 6 and 7 you should get the same data back.
+
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_rp::peripherals::PIO0;
+use embassy_rp::pio_programs::spi::Spi;
+use embassy_rp::spi::Config;
+use embassy_rp::{bind_interrupts, pio};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    PIO0_IRQ_0 => pio::InterruptHandler<PIO0>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = embassy_rp::init(Default::default());
+    info!("Hello World!");
+
+    // These pins are routed to different hardware SPI peripherals, but we can
+    // use them together regardless
+    let mosi = p.PIN_6; // SPI0 SCLK
+    let miso = p.PIN_7; // SPI0 MOSI
+    let clk = p.PIN_8; // SPI1 MISO
+
+    let pio::Pio { mut common, sm0, .. } = pio::Pio::new(p.PIO0, Irqs);
+
+    // Construct an SPI driver backed by a PIO state machine
+    let mut spi = Spi::new_blocking(&mut common, sm0, clk, mosi, miso, Config::default());
+
+    loop {
+        let tx_buf = [1_u8, 2, 3, 4, 5, 6];
+        let mut rx_buf = [0_u8; 6];
+
+        spi.blocking_transfer(&mut rx_buf, &tx_buf).unwrap();
+        info!("{:?}", rx_buf);
+
+        Timer::after_secs(1).await;
+    }
+}
diff --git a/examples/rp/src/bin/pio_spi_async.rs b/examples/rp/src/bin/pio_spi_async.rs
new file mode 100644
index 000000000..18b57d26e
--- /dev/null
+++ b/examples/rp/src/bin/pio_spi_async.rs
@@ -0,0 +1,57 @@
+//! This example shows how to use a PIO state machine as an additional SPI
+//! (Serial Peripheral Interface) on the RP2040 chip. No specific hardware is
+//! specified in this example.
+//!
+//! If you connect pin 6 and 7 you should get the same data back.
+
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_rp::peripherals::PIO0;
+use embassy_rp::pio_programs::spi::Spi;
+use embassy_rp::spi::Config;
+use embassy_rp::{bind_interrupts, pio};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    PIO0_IRQ_0 => pio::InterruptHandler<PIO0>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = embassy_rp::init(Default::default());
+    info!("Hello World!");
+
+    // These pins are routed to different hardware SPI peripherals, but we can
+    // use them together regardless
+    let mosi = p.PIN_6; // SPI0 SCLK
+    let miso = p.PIN_7; // SPI0 MOSI
+    let clk = p.PIN_8; // SPI1 MISO
+
+    let pio::Pio { mut common, sm0, .. } = pio::Pio::new(p.PIO0, Irqs);
+
+    // Construct an SPI driver backed by a PIO state machine
+    let mut spi = Spi::new(
+        &mut common,
+        sm0,
+        clk,
+        mosi,
+        miso,
+        p.DMA_CH0,
+        p.DMA_CH1,
+        Config::default(),
+    );
+
+    loop {
+        let tx_buf = [1_u8, 2, 3, 4, 5, 6];
+        let mut rx_buf = [0_u8; 6];
+
+        spi.transfer(&mut rx_buf, &tx_buf).await.unwrap();
+        info!("{:?}", rx_buf);
+
+        Timer::after_secs(1).await;
+    }
+}
diff --git a/examples/rp/src/bin/rtc.rs b/examples/rp/src/bin/rtc.rs
index e9a5e43a8..1692bdf36 100644
--- a/examples/rp/src/bin/rtc.rs
+++ b/examples/rp/src/bin/rtc.rs
@@ -5,16 +5,22 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
+use embassy_rp::bind_interrupts;
 use embassy_rp::rtc::{DateTime, DayOfWeek, Rtc};
 use embassy_time::Timer;
 use {defmt_rtt as _, panic_probe as _};
 
+// Bind the RTC interrupt to the handler
+bind_interrupts!(struct Irqs {
+    RTC_IRQ => embassy_rp::rtc::InterruptHandler;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_rp::init(Default::default());
     info!("Wait for 20s");
 
-    let mut rtc = Rtc::new(p.RTC);
+    let mut rtc = Rtc::new(p.RTC, Irqs);
 
     if !rtc.is_running() {
         info!("Start RTC");
diff --git a/examples/rp/src/bin/rtc_alarm.rs b/examples/rp/src/bin/rtc_alarm.rs
new file mode 100644
index 000000000..94b5fbd27
--- /dev/null
+++ b/examples/rp/src/bin/rtc_alarm.rs
@@ -0,0 +1,66 @@
+//! This example shows how to use RTC (Real Time Clock) for scheduling alarms and reacting to them.
+
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_futures::select::{select, Either};
+use embassy_rp::bind_interrupts;
+use embassy_rp::rtc::{DateTime, DateTimeFilter, DayOfWeek, Rtc};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+// Bind the RTC interrupt to the handler
+bind_interrupts!(struct Irqs {
+    RTC_IRQ => embassy_rp::rtc::InterruptHandler;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = embassy_rp::init(Default::default());
+    let mut rtc = Rtc::new(p.RTC, Irqs);
+
+    if !rtc.is_running() {
+        info!("Start RTC");
+        let now = DateTime {
+            year: 2000,
+            month: 1,
+            day: 1,
+            day_of_week: DayOfWeek::Saturday,
+            hour: 0,
+            minute: 0,
+            second: 0,
+        };
+        rtc.set_datetime(now).unwrap();
+    }
+
+    loop {
+        // Wait for 5 seconds or until the alarm is triggered
+        match select(Timer::after_secs(5), rtc.wait_for_alarm()).await {
+            // Timer expired
+            Either::First(_) => {
+                let dt = rtc.now().unwrap();
+                info!(
+                    "Now: {}-{:02}-{:02} {}:{:02}:{:02}",
+                    dt.year, dt.month, dt.day, dt.hour, dt.minute, dt.second,
+                );
+
+                // See if the alarm is already scheduled, if not, schedule it
+                if rtc.alarm_scheduled().is_none() {
+                    info!("Scheduling alarm for 30 seconds from now");
+                    rtc.schedule_alarm(DateTimeFilter::default().second((dt.second + 30) % 60));
+                    info!("Alarm scheduled: {}", rtc.alarm_scheduled().unwrap());
+                }
+            }
+            // Alarm triggered
+            Either::Second(_) => {
+                let dt = rtc.now().unwrap();
+                info!(
+                    "ALARM TRIGGERED! Now: {}-{:02}-{:02} {}:{:02}:{:02}",
+                    dt.year, dt.month, dt.day, dt.hour, dt.minute, dt.second,
+                );
+            }
+        }
+    }
+}
diff --git a/examples/rp235x/src/bin/pio_i2s_rx.rs b/examples/rp235x/src/bin/pio_i2s_rx.rs
new file mode 100644
index 000000000..c3f505b13
--- /dev/null
+++ b/examples/rp235x/src/bin/pio_i2s_rx.rs
@@ -0,0 +1,81 @@
+//! This example shows receiving audio from a connected I2S microphone (or other audio source)
+//! using the PIO module of the RP235x.
+//!
+//!
+//! Connect the i2s microphone as follows:
+//!   bclk : GPIO 18
+//!   lrc  : GPIO 19
+//!   din  : GPIO 20
+//! Then hold down the boot select button to begin receiving audio. Received I2S words will be written to
+//! buffers for the left and right channels for use in your application, whether that's storage or
+//! further processing
+//!
+//!  Note the const USE_ONBOARD_PULLDOWN is by default set to false, meaning an external
+//!  pull-down resistor is being used on the data pin if required by the mic being used.
+
+#![no_std]
+#![no_main]
+use core::mem;
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_rp::bind_interrupts;
+use embassy_rp::peripherals::PIO0;
+use embassy_rp::pio::{InterruptHandler, Pio};
+use embassy_rp::pio_programs::i2s::{PioI2sIn, PioI2sInProgram};
+use static_cell::StaticCell;
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    PIO0_IRQ_0 => InterruptHandler<PIO0>;
+});
+
+const SAMPLE_RATE: u32 = 48_000;
+const BIT_DEPTH: u32 = 16;
+const CHANNELS: u32 = 2;
+const USE_ONBOARD_PULLDOWN: bool = false; // whether or not to use the onboard pull-down resistor,
+                                          // which has documented issues on many RP235x boards
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = embassy_rp::init(Default::default());
+
+    // Setup pio state machine for i2s input
+    let Pio { mut common, sm0, .. } = Pio::new(p.PIO0, Irqs);
+
+    let bit_clock_pin = p.PIN_18;
+    let left_right_clock_pin = p.PIN_19;
+    let data_pin = p.PIN_20;
+
+    let program = PioI2sInProgram::new(&mut common);
+    let mut i2s = PioI2sIn::new(
+        &mut common,
+        sm0,
+        p.DMA_CH0,
+        USE_ONBOARD_PULLDOWN,
+        data_pin,
+        bit_clock_pin,
+        left_right_clock_pin,
+        SAMPLE_RATE,
+        BIT_DEPTH,
+        CHANNELS,
+        &program,
+    );
+
+    // create two audio buffers (back and front) which will take turns being
+    // filled with new audio data from the PIO fifo using DMA
+    const BUFFER_SIZE: usize = 960;
+    static DMA_BUFFER: StaticCell<[u32; BUFFER_SIZE * 2]> = StaticCell::new();
+    let dma_buffer = DMA_BUFFER.init_with(|| [0u32; BUFFER_SIZE * 2]);
+    let (mut back_buffer, mut front_buffer) = dma_buffer.split_at_mut(BUFFER_SIZE);
+
+    loop {
+        // trigger transfer of front buffer data to the pio fifo
+        // but don't await the returned future, yet
+        let dma_future = i2s.read(front_buffer);
+        // now await the dma future. once the dma finishes, the next buffer needs to be queued
+        // within DMA_DEPTH / SAMPLE_RATE = 8 / 48000 seconds = 166us
+        dma_future.await;
+        info!("Received I2S data word: {:?}", &front_buffer);
+        mem::swap(&mut back_buffer, &mut front_buffer);
+    }
+}
diff --git a/examples/rp235x/src/bin/pio_onewire.rs b/examples/rp235x/src/bin/pio_onewire.rs
index 991510851..102f13c45 100644
--- a/examples/rp235x/src/bin/pio_onewire.rs
+++ b/examples/rp235x/src/bin/pio_onewire.rs
@@ -1,4 +1,5 @@
-//! This example shows how you can use PIO to read a `DS18B20` one-wire temperature sensor.
+//! This example shows how you can use PIO to read one or more `DS18B20` one-wire temperature sensors.
+//! This uses externally powered sensors. For parasite power, see the pio_onewire_parasite.rs example.
 
 #![no_std]
 #![no_main]
@@ -6,9 +7,10 @@ use defmt::*;
 use embassy_executor::Spawner;
 use embassy_rp::bind_interrupts;
 use embassy_rp::peripherals::PIO0;
-use embassy_rp::pio::{self, InterruptHandler, Pio};
-use embassy_rp::pio_programs::onewire::{PioOneWire, PioOneWireProgram};
+use embassy_rp::pio::{InterruptHandler, Pio};
+use embassy_rp::pio_programs::onewire::{PioOneWire, PioOneWireProgram, PioOneWireSearch};
 use embassy_time::Timer;
+use heapless::Vec;
 use {defmt_rtt as _, panic_probe as _};
 
 bind_interrupts!(struct Irqs {
@@ -21,63 +23,66 @@ async fn main(_spawner: Spawner) {
     let mut pio = Pio::new(p.PIO0, Irqs);
 
     let prg = PioOneWireProgram::new(&mut pio.common);
-    let onewire = PioOneWire::new(&mut pio.common, pio.sm0, p.PIN_2, &prg);
+    let mut onewire = PioOneWire::new(&mut pio.common, pio.sm0, p.PIN_2, &prg);
 
-    let mut sensor = Ds18b20::new(onewire);
+    info!("Starting onewire search");
 
-    loop {
-        sensor.start().await; // Start a new measurement
-        Timer::after_secs(1).await; // Allow 1s for the measurement to finish
-        match sensor.temperature().await {
-            Ok(temp) => info!("temp = {:?} deg C", temp),
-            _ => error!("sensor error"),
+    let mut devices = Vec::<u64, 10>::new();
+    let mut search = PioOneWireSearch::new();
+    for _ in 0..10 {
+        if !search.is_finished() {
+            if let Some(address) = search.next(&mut onewire).await {
+                if crc8(&address.to_le_bytes()) == 0 {
+                    info!("Found addres: {:x}", address);
+                    let _ = devices.push(address);
+                } else {
+                    warn!("Found invalid address: {:x}", address);
+                }
+            }
         }
-        Timer::after_secs(1).await;
     }
-}
 
-/// DS18B20 temperature sensor driver
-pub struct Ds18b20<'d, PIO: pio::Instance, const SM: usize> {
-    wire: PioOneWire<'d, PIO, SM>,
-}
+    info!("Search done, found {} devices", devices.len());
 
-impl<'d, PIO: pio::Instance, const SM: usize> Ds18b20<'d, PIO, SM> {
-    pub fn new(wire: PioOneWire<'d, PIO, SM>) -> Self {
-        Self { wire }
-    }
+    loop {
+        onewire.reset().await;
+        // Skip rom and trigger conversion, we can trigger all devices on the bus immediately
+        onewire.write_bytes(&[0xCC, 0x44]).await;
 
-    /// Calculate CRC8 of the data
-    fn crc8(data: &[u8]) -> u8 {
-        let mut temp;
-        let mut data_byte;
-        let mut crc = 0;
-        for b in data {
-            data_byte = *b;
-            for _ in 0..8 {
-                temp = (crc ^ data_byte) & 0x01;
-                crc >>= 1;
-                if temp != 0 {
-                    crc ^= 0x8C;
-                }
-                data_byte >>= 1;
+        Timer::after_secs(1).await; // Allow 1s for the measurement to finish
+
+        // Read all devices one by one
+        for device in &devices {
+            onewire.reset().await;
+            onewire.write_bytes(&[0x55]).await; // Match rom
+            onewire.write_bytes(&device.to_le_bytes()).await;
+            onewire.write_bytes(&[0xBE]).await; // Read scratchpad
+
+            let mut data = [0; 9];
+            onewire.read_bytes(&mut data).await;
+            if crc8(&data) == 0 {
+                let temp = ((data[1] as u32) << 8 | data[0] as u32) as f32 / 16.;
+                info!("Read device {:x}: {} deg C", device, temp);
+            } else {
+                warn!("Reading device {:x} failed", device);
             }
         }
-        crc
-    }
-
-    /// Start a new measurement. Allow at least 1000ms before getting `temperature`.
-    pub async fn start(&mut self) {
-        self.wire.write_bytes(&[0xCC, 0x44]).await;
+        Timer::after_secs(1).await;
     }
+}
 
-    /// Read the temperature. Ensure >1000ms has passed since `start` before calling this.
-    pub async fn temperature(&mut self) -> Result<f32, ()> {
-        self.wire.write_bytes(&[0xCC, 0xBE]).await;
-        let mut data = [0; 9];
-        self.wire.read_bytes(&mut data).await;
-        match Self::crc8(&data) == 0 {
-            true => Ok(((data[1] as u32) << 8 | data[0] as u32) as f32 / 16.),
-            false => Err(()),
+fn crc8(data: &[u8]) -> u8 {
+    let mut crc = 0;
+    for b in data {
+        let mut data_byte = *b;
+        for _ in 0..8 {
+            let temp = (crc ^ data_byte) & 0x01;
+            crc >>= 1;
+            if temp != 0 {
+                crc ^= 0x8C;
+            }
+            data_byte >>= 1;
         }
     }
+    crc
 }
diff --git a/examples/rp235x/src/bin/pio_onewire_parasite.rs b/examples/rp235x/src/bin/pio_onewire_parasite.rs
new file mode 100644
index 000000000..fd076dee0
--- /dev/null
+++ b/examples/rp235x/src/bin/pio_onewire_parasite.rs
@@ -0,0 +1,89 @@
+//! This example shows how you can use PIO to read one or more `DS18B20`
+//! one-wire temperature sensors using parasite power.
+//! It applies a strong pullup during conversion, see "Powering the DS18B20" in the datasheet.
+//! For externally powered sensors, use the pio_onewire.rs example.
+
+#![no_std]
+#![no_main]
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_rp::bind_interrupts;
+use embassy_rp::peripherals::PIO0;
+use embassy_rp::pio::{InterruptHandler, Pio};
+use embassy_rp::pio_programs::onewire::{PioOneWire, PioOneWireProgram, PioOneWireSearch};
+use embassy_time::Duration;
+use heapless::Vec;
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    PIO0_IRQ_0 => InterruptHandler<PIO0>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = embassy_rp::init(Default::default());
+    let mut pio = Pio::new(p.PIO0, Irqs);
+
+    let prg = PioOneWireProgram::new(&mut pio.common);
+    let mut onewire = PioOneWire::new(&mut pio.common, pio.sm0, p.PIN_2, &prg);
+
+    info!("Starting onewire search");
+
+    let mut devices = Vec::<u64, 10>::new();
+    let mut search = PioOneWireSearch::new();
+    for _ in 0..10 {
+        if !search.is_finished() {
+            if let Some(address) = search.next(&mut onewire).await {
+                if crc8(&address.to_le_bytes()) == 0 {
+                    info!("Found address: {:x}", address);
+                    let _ = devices.push(address);
+                } else {
+                    warn!("Found invalid address: {:x}", address);
+                }
+            }
+        }
+    }
+
+    info!("Search done, found {} devices", devices.len());
+
+    loop {
+        // Read all devices one by one
+        for device in &devices {
+            onewire.reset().await;
+            onewire.write_bytes(&[0x55]).await; // Match rom
+            onewire.write_bytes(&device.to_le_bytes()).await;
+            // 750 ms delay required for default 12-bit resolution.
+            onewire.write_bytes_pullup(&[0x44], Duration::from_millis(750)).await;
+
+            onewire.reset().await;
+            onewire.write_bytes(&[0x55]).await; // Match rom
+            onewire.write_bytes(&device.to_le_bytes()).await;
+            onewire.write_bytes(&[0xBE]).await; // Read scratchpad
+
+            let mut data = [0; 9];
+            onewire.read_bytes(&mut data).await;
+            if crc8(&data) == 0 {
+                let temp = ((data[1] as u32) << 8 | data[0] as u32) as f32 / 16.;
+                info!("Read device {:x}: {} deg C", device, temp);
+            } else {
+                warn!("Reading device {:x} failed. {:02x}", device, data);
+            }
+        }
+    }
+}
+
+fn crc8(data: &[u8]) -> u8 {
+    let mut crc = 0;
+    for b in data {
+        let mut data_byte = *b;
+        for _ in 0..8 {
+            let temp = (crc ^ data_byte) & 0x01;
+            crc >>= 1;
+            if temp != 0 {
+                crc ^= 0x8C;
+            }
+            data_byte >>= 1;
+        }
+    }
+    crc
+}
diff --git a/examples/rp235x/src/bin/psram.rs b/examples/rp235x/src/bin/psram.rs
new file mode 100644
index 000000000..716ac7695
--- /dev/null
+++ b/examples/rp235x/src/bin/psram.rs
@@ -0,0 +1,49 @@
+//! This example tests an APS6404L PSRAM chip connected to the RP235x
+//! It fills the PSRAM with alternating patterns and reads back a value
+//!
+//! In this example, the PSRAM CS is connected to Pin 0.
+
+#![no_std]
+#![no_main]
+
+use core::slice;
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let config = embassy_rp::config::Config::default();
+    let p = embassy_rp::init(config);
+    let psram_config = embassy_rp::psram::Config::aps6404l();
+    let psram = embassy_rp::psram::Psram::new(embassy_rp::qmi_cs1::QmiCs1::new(p.QMI_CS1, p.PIN_0), psram_config);
+
+    let Ok(psram) = psram else {
+        error!("PSRAM not found");
+        loop {
+            Timer::after_secs(1).await;
+        }
+    };
+
+    let psram_slice = unsafe {
+        let psram_ptr = psram.base_address();
+        let slice: &'static mut [u8] = slice::from_raw_parts_mut(psram_ptr, psram.size() as usize);
+        slice
+    };
+
+    loop {
+        psram_slice.fill(0x55);
+        info!("PSRAM filled with 0x55");
+        let at_addr = psram_slice[0x100];
+        info!("Read from PSRAM at address 0x100: 0x{:02x}", at_addr);
+        Timer::after_secs(1).await;
+
+        psram_slice.fill(0xAA);
+        info!("PSRAM filled with 0xAA");
+        let at_addr = psram_slice[0x100];
+        info!("Read from PSRAM at address 0x100: 0x{:02x}", at_addr);
+        Timer::after_secs(1).await;
+    }
+}
diff --git a/examples/stm32f1/src/bin/input_capture.rs b/examples/stm32f1/src/bin/input_capture.rs
index d747a43c2..b5b26938d 100644
--- a/examples/stm32f1/src/bin/input_capture.rs
+++ b/examples/stm32f1/src/bin/input_capture.rs
@@ -3,7 +3,7 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::gpio::{Level, Output, Pull, Speed};
+use embassy_stm32::gpio::{AfioRemap, Level, Output, Pull, Speed};
 use embassy_stm32::time::khz;
 use embassy_stm32::timer::input_capture::{CapturePin, InputCapture};
 use embassy_stm32::timer::{self, Channel};
@@ -40,7 +40,8 @@ async fn main(spawner: Spawner) {
     spawner.spawn(unwrap!(blinky(p.PC13)));
 
     let ch3 = CapturePin::new(p.PA2, Pull::None);
-    let mut ic = InputCapture::new(p.TIM2, None, None, Some(ch3), None, Irqs, khz(1000), Default::default());
+    let mut ic =
+        InputCapture::new::<AfioRemap<0>>(p.TIM2, None, None, Some(ch3), None, Irqs, khz(1000), Default::default());
 
     loop {
         info!("wait for rising edge");
diff --git a/examples/stm32f1/src/bin/pwm_input.rs b/examples/stm32f1/src/bin/pwm_input.rs
index 63b899767..9ae747018 100644
--- a/examples/stm32f1/src/bin/pwm_input.rs
+++ b/examples/stm32f1/src/bin/pwm_input.rs
@@ -3,7 +3,7 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::gpio::{Level, Output, Pull, Speed};
+use embassy_stm32::gpio::{AfioRemap, Level, Output, Pull, Speed};
 use embassy_stm32::time::khz;
 use embassy_stm32::timer::pwm_input::PwmInput;
 use embassy_stm32::{bind_interrupts, peripherals, timer, Peri};
@@ -38,7 +38,7 @@ async fn main(spawner: Spawner) {
 
     spawner.spawn(unwrap!(blinky(p.PC13)));
 
-    let mut pwm_input = PwmInput::new_ch1(p.TIM2, p.PA0, Pull::None, khz(10));
+    let mut pwm_input = PwmInput::new_ch1::<AfioRemap<0>>(p.TIM2, p.PA0, Pull::None, khz(10));
     pwm_input.enable();
 
     loop {
diff --git a/examples/stm32f7/src/bin/qspi.rs b/examples/stm32f7/src/bin/qspi.rs
index ab29ddeff..80652b865 100644
--- a/examples/stm32f7/src/bin/qspi.rs
+++ b/examples/stm32f7/src/bin/qspi.rs
@@ -273,14 +273,14 @@ async fn main(_spawner: Spawner) -> ! {
     let p = embassy_stm32::init(config);
     info!("Embassy initialized");
 
-    let config = QspiCfg {
-        memory_size: MemorySize::_8MiB,
-        address_size: AddressSize::_24bit,
-        prescaler: 16,
-        cs_high_time: ChipSelectHighTime::_1Cycle,
-        fifo_threshold: FIFOThresholdLevel::_16Bytes,
-        sample_shifting: SampleShifting::None,
-    };
+    let mut config = QspiCfg::default();
+    config.memory_size = MemorySize::_8MiB;
+    config.address_size = AddressSize::_24bit;
+    config.prescaler = 16;
+    config.cs_high_time = ChipSelectHighTime::_1Cycle;
+    config.fifo_threshold = FIFOThresholdLevel::_16Bytes;
+    config.sample_shifting = SampleShifting::None;
+
     let driver = Qspi::new_bank1(
         p.QUADSPI, p.PF8, p.PF9, p.PE2, p.PF6, p.PF10, p.PB10, p.DMA2_CH7, config,
     );
diff --git a/examples/stm32g0/src/bin/adc.rs b/examples/stm32g0/src/bin/adc.rs
index 6c7f3b48a..7d8653ef2 100644
--- a/examples/stm32g0/src/bin/adc.rs
+++ b/examples/stm32g0/src/bin/adc.rs
@@ -3,7 +3,7 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::adc::{Adc, SampleTime};
+use embassy_stm32::adc::{Adc, Clock, Presc, SampleTime};
 use embassy_time::Timer;
 use {defmt_rtt as _, panic_probe as _};
 
@@ -12,7 +12,7 @@ async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Hello World!");
 
-    let mut adc = Adc::new(p.ADC1);
+    let mut adc = Adc::new_with_clock(p.ADC1, Clock::Async { div: Presc::DIV1 });
     adc.set_sample_time(SampleTime::CYCLES79_5);
     let mut pin = p.PA1;
 
diff --git a/examples/stm32g0/src/bin/adc_dma.rs b/examples/stm32g0/src/bin/adc_dma.rs
index d7515933c..8266a6d83 100644
--- a/examples/stm32g0/src/bin/adc_dma.rs
+++ b/examples/stm32g0/src/bin/adc_dma.rs
@@ -3,7 +3,7 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::adc::{Adc, AdcChannel as _, SampleTime};
+use embassy_stm32::adc::{Adc, AdcChannel as _, Clock, Presc, SampleTime};
 use embassy_time::Timer;
 use {defmt_rtt as _, panic_probe as _};
 
@@ -17,7 +17,7 @@ async fn main(_spawner: Spawner) {
 
     info!("Hello World!");
 
-    let mut adc = Adc::new(p.ADC1);
+    let mut adc = Adc::new_with_clock(p.ADC1, Clock::Async { div: Presc::DIV1 });
 
     let mut dma = p.DMA1_CH1;
     let mut vrefint_channel = adc.enable_vrefint().degrade_adc();
diff --git a/examples/stm32g0/src/bin/adc_oversampling.rs b/examples/stm32g0/src/bin/adc_oversampling.rs
index 9c5dd872a..834d1cd4a 100644
--- a/examples/stm32g0/src/bin/adc_oversampling.rs
+++ b/examples/stm32g0/src/bin/adc_oversampling.rs
@@ -7,7 +7,7 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::adc::{Adc, SampleTime};
+use embassy_stm32::adc::{Adc, Clock, Ovsr, Ovss, Presc, SampleTime};
 use embassy_time::Timer;
 use {defmt_rtt as _, panic_probe as _};
 
@@ -16,23 +16,12 @@ async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Adc oversample test");
 
-    let mut adc = Adc::new(p.ADC1);
+    let mut adc = Adc::new_with_clock(p.ADC1, Clock::Async { div: Presc::DIV1 });
     adc.set_sample_time(SampleTime::CYCLES1_5);
     let mut pin = p.PA1;
 
-    // From https://www.st.com/resource/en/reference_manual/rm0444-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
-    // page373 15.8 Oversampler
-    // Table 76. Maximum output results vs N and M. Grayed values indicates truncation
-    // 0x00 oversampling ratio X2
-    // 0x01 oversampling ratio X4
-    // 0x02 oversampling ratio X8
-    // 0x03 oversampling ratio X16
-    // 0x04 oversampling ratio X32
-    // 0x05 oversampling ratio X64
-    // 0x06 oversampling ratio X128
-    // 0x07 oversampling ratio X256
-    adc.set_oversampling_ratio(0x03);
-    adc.set_oversampling_shift(0b0000);
+    adc.set_oversampling_ratio(Ovsr::MUL16);
+    adc.set_oversampling_shift(Ovss::NO_SHIFT);
     adc.oversampling_enable(true);
 
     loop {
diff --git a/examples/stm32h5/src/bin/sai.rs b/examples/stm32h5/src/bin/sai.rs
new file mode 100644
index 000000000..0e182f9cf
--- /dev/null
+++ b/examples/stm32h5/src/bin/sai.rs
@@ -0,0 +1,52 @@
+#![no_std]
+#![no_main]
+
+use defmt::info;
+use embassy_executor::Spawner;
+use embassy_stm32::{sai, Config};
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    info!("Hello world.");
+
+    let mut config = Config::default();
+    {
+        use embassy_stm32::rcc::*;
+
+        config.rcc.pll2 = Some(Pll {
+            source: PllSource::HSI,
+            prediv: PllPreDiv::DIV16,
+            mul: PllMul::MUL32,
+            divp: Some(PllDiv::DIV16), // 8 MHz SAI clock
+            divq: None,
+            divr: None,
+        });
+
+        config.rcc.mux.sai1sel = mux::Saisel::PLL2_P;
+    }
+    let p = embassy_stm32::init(config);
+
+    let mut write_buffer = [0u16; 1024];
+    let (_, sai_b) = sai::split_subblocks(p.SAI1);
+
+    let mut sai_b = sai::Sai::new_asynchronous(
+        sai_b,
+        p.PF8,
+        p.PE3,
+        p.PF9,
+        p.GPDMA1_CH0,
+        &mut write_buffer,
+        Default::default(),
+    );
+
+    // Populate arbitrary data.
+    let mut data = [0u16; 256];
+    for (index, sample) in data.iter_mut().enumerate() {
+        *sample = index as u16;
+    }
+
+    loop {
+        sai_b.write(&data).await.unwrap();
+    }
+}
diff --git a/examples/stm32h7/src/bin/sai.rs b/examples/stm32h7/src/bin/sai.rs
index 01937593a..847b70c85 100644
--- a/examples/stm32h7/src/bin/sai.rs
+++ b/examples/stm32h7/src/bin/sai.rs
@@ -63,7 +63,7 @@ async fn main(_spawner: Spawner) {
     tx_config.tx_rx = TxRx::Transmitter;
     tx_config.sync_output = true;
     tx_config.clock_strobe = ClockStrobe::Falling;
-    tx_config.master_clock_divider = mclk_div;
+    tx_config.master_clock_divider = Some(mclk_div);
     tx_config.stereo_mono = StereoMono::Stereo;
     tx_config.data_size = DataSize::Data24;
     tx_config.bit_order = BitOrder::MsbFirst;
@@ -119,71 +119,7 @@ async fn main(_spawner: Spawner) {
     }
 }
 
-const fn mclk_div_from_u8(v: u8) -> MasterClockDivider {
-    match v {
-        1 => MasterClockDivider::Div1,
-        2 => MasterClockDivider::Div2,
-        3 => MasterClockDivider::Div3,
-        4 => MasterClockDivider::Div4,
-        5 => MasterClockDivider::Div5,
-        6 => MasterClockDivider::Div6,
-        7 => MasterClockDivider::Div7,
-        8 => MasterClockDivider::Div8,
-        9 => MasterClockDivider::Div9,
-        10 => MasterClockDivider::Div10,
-        11 => MasterClockDivider::Div11,
-        12 => MasterClockDivider::Div12,
-        13 => MasterClockDivider::Div13,
-        14 => MasterClockDivider::Div14,
-        15 => MasterClockDivider::Div15,
-        16 => MasterClockDivider::Div16,
-        17 => MasterClockDivider::Div17,
-        18 => MasterClockDivider::Div18,
-        19 => MasterClockDivider::Div19,
-        20 => MasterClockDivider::Div20,
-        21 => MasterClockDivider::Div21,
-        22 => MasterClockDivider::Div22,
-        23 => MasterClockDivider::Div23,
-        24 => MasterClockDivider::Div24,
-        25 => MasterClockDivider::Div25,
-        26 => MasterClockDivider::Div26,
-        27 => MasterClockDivider::Div27,
-        28 => MasterClockDivider::Div28,
-        29 => MasterClockDivider::Div29,
-        30 => MasterClockDivider::Div30,
-        31 => MasterClockDivider::Div31,
-        32 => MasterClockDivider::Div32,
-        33 => MasterClockDivider::Div33,
-        34 => MasterClockDivider::Div34,
-        35 => MasterClockDivider::Div35,
-        36 => MasterClockDivider::Div36,
-        37 => MasterClockDivider::Div37,
-        38 => MasterClockDivider::Div38,
-        39 => MasterClockDivider::Div39,
-        40 => MasterClockDivider::Div40,
-        41 => MasterClockDivider::Div41,
-        42 => MasterClockDivider::Div42,
-        43 => MasterClockDivider::Div43,
-        44 => MasterClockDivider::Div44,
-        45 => MasterClockDivider::Div45,
-        46 => MasterClockDivider::Div46,
-        47 => MasterClockDivider::Div47,
-        48 => MasterClockDivider::Div48,
-        49 => MasterClockDivider::Div49,
-        50 => MasterClockDivider::Div50,
-        51 => MasterClockDivider::Div51,
-        52 => MasterClockDivider::Div52,
-        53 => MasterClockDivider::Div53,
-        54 => MasterClockDivider::Div54,
-        55 => MasterClockDivider::Div55,
-        56 => MasterClockDivider::Div56,
-        57 => MasterClockDivider::Div57,
-        58 => MasterClockDivider::Div58,
-        59 => MasterClockDivider::Div59,
-        60 => MasterClockDivider::Div60,
-        61 => MasterClockDivider::Div61,
-        62 => MasterClockDivider::Div62,
-        63 => MasterClockDivider::Div63,
-        _ => panic!(),
-    }
+fn mclk_div_from_u8(v: u8) -> MasterClockDivider {
+    assert!((1..=63).contains(&v));
+    MasterClockDivider::from_bits(v)
 }
diff --git a/examples/stm32h723/src/bin/spdifrx.rs b/examples/stm32h723/src/bin/spdifrx.rs
index 6d29e8a4d..b75a03ae8 100644
--- a/examples/stm32h723/src/bin/spdifrx.rs
+++ b/examples/stm32h723/src/bin/spdifrx.rs
@@ -168,7 +168,7 @@ fn new_sai_transmitter<'d>(
     sai_config.slot_enable = 0xFFFF; // All slots
     sai_config.data_size = sai::DataSize::Data32;
     sai_config.frame_length = (CHANNEL_COUNT * 32) as u8;
-    sai_config.master_clock_divider = hal::sai::MasterClockDivider::MasterClockDisabled;
+    sai_config.master_clock_divider = None;
 
     let (sub_block_tx, _) = hal::sai::split_subblocks(sai);
     Sai::new_asynchronous(sub_block_tx, sck, sd, fs, dma, buf, sai_config)
diff --git a/examples/stm32h742/src/bin/qspi.rs b/examples/stm32h742/src/bin/qspi.rs
index 50e37ec52..9e79d7089 100644
--- a/examples/stm32h742/src/bin/qspi.rs
+++ b/examples/stm32h742/src/bin/qspi.rs
@@ -266,14 +266,14 @@ async fn main(_spawner: Spawner) -> ! {
     let p = embassy_stm32::init(config);
     info!("Embassy initialized");
 
-    let config = QspiCfg {
-        memory_size: MemorySize::_8MiB,
-        address_size: AddressSize::_24bit,
-        prescaler: 16,
-        cs_high_time: ChipSelectHighTime::_1Cycle,
-        fifo_threshold: FIFOThresholdLevel::_16Bytes,
-        sample_shifting: SampleShifting::None,
-    };
+    let mut config = QspiCfg::default();
+    config.memory_size = MemorySize::_8MiB;
+    config.address_size = AddressSize::_24bit;
+    config.prescaler = 16;
+    config.cs_high_time = ChipSelectHighTime::_1Cycle;
+    config.fifo_threshold = FIFOThresholdLevel::_16Bytes;
+    config.sample_shifting = SampleShifting::None;
+
     let driver = Qspi::new_blocking_bank1(p.QUADSPI, p.PD11, p.PD12, p.PE2, p.PD13, p.PB2, p.PB10, config);
     let mut flash = FlashMemory::new(driver);
     let flash_id = flash.read_id();
diff --git a/examples/stm32l0/Cargo.toml b/examples/stm32l0/Cargo.toml
index 90f57a2d8..d42cdac15 100644
--- a/examples/stm32l0/Cargo.toml
+++ b/examples/stm32l0/Cargo.toml
@@ -11,6 +11,8 @@ embassy-stm32 = { version = "0.4.0", path = "../../embassy-stm32", features = ["
 embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
 embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
+embassy-usb = { version = "0.5.1", path = "../../embassy-usb", features = ["defmt"] }
+embassy-futures = { version = "0.1.2", path = "../../embassy-futures" }
 
 defmt = "1.0.1"
 defmt-rtt = "1.0.0"
diff --git a/examples/stm32l0/src/bin/usb_serial.rs b/examples/stm32l0/src/bin/usb_serial.rs
new file mode 100644
index 000000000..fdb1aeb59
--- /dev/null
+++ b/examples/stm32l0/src/bin/usb_serial.rs
@@ -0,0 +1,95 @@
+#![no_std]
+#![no_main]
+
+use defmt::{panic, *};
+use embassy_executor::Spawner;
+use embassy_futures::join::join;
+use embassy_stm32::usb::{self, Driver, Instance};
+use embassy_stm32::{bind_interrupts, peripherals};
+use embassy_usb::class::cdc_acm::{CdcAcmClass, State};
+use embassy_usb::driver::EndpointError;
+use embassy_usb::Builder;
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    USB => usb::InterruptHandler<peripherals::USB>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut config = embassy_stm32::Config::default();
+    {
+        use embassy_stm32::rcc::*;
+        config.rcc.hsi = true;
+        config.rcc.pll = Some(Pll {
+            source: PllSource::HSI,
+            mul: PllMul::MUL6, // PLLVCO = 16*6 = 96Mhz
+            div: PllDiv::DIV3, // 32Mhz clock (16 * 6 / 3)
+        });
+        config.rcc.sys = Sysclk::PLL1_R;
+    }
+
+    let p = embassy_stm32::init(config);
+
+    info!("Hello World!");
+
+    let driver = Driver::new(p.USB, Irqs, p.PA12, p.PA11);
+
+    let mut config = embassy_usb::Config::new(0xc0de, 0xcafe);
+    config.manufacturer = Some("Embassy");
+    config.product = Some("USB-Serial Example");
+    config.serial_number = Some("123456");
+
+    let mut config_descriptor = [0; 256];
+    let mut bos_descriptor = [0; 256];
+    let mut control_buf = [0; 64];
+
+    let mut state = State::new();
+
+    let mut builder = Builder::new(
+        driver,
+        config,
+        &mut config_descriptor,
+        &mut bos_descriptor,
+        &mut [], // no msos descriptors
+        &mut control_buf,
+    );
+
+    let mut class = CdcAcmClass::new(&mut builder, &mut state, 64);
+
+    let mut usb = builder.build();
+
+    let usb_fut = usb.run();
+
+    let echo_fut = async {
+        loop {
+            class.wait_connection().await;
+            info!("Connected");
+            let _ = echo(&mut class).await;
+            info!("Disconnected");
+        }
+    };
+
+    join(usb_fut, echo_fut).await;
+}
+
+struct Disconnected {}
+
+impl From<EndpointError> for Disconnected {
+    fn from(val: EndpointError) -> Self {
+        match val {
+            EndpointError::BufferOverflow => panic!("Buffer overflow"),
+            EndpointError::Disabled => Disconnected {},
+        }
+    }
+}
+
+async fn echo<'d, T: Instance + 'd>(class: &mut CdcAcmClass<'d, Driver<'d, T>>) -> Result<(), Disconnected> {
+    let mut buf = [0; 64];
+    loop {
+        let n = class.read_packet(&mut buf).await?;
+        let data = &buf[..n];
+        info!("data: {:x}", data);
+        class.write_packet(data).await?;
+    }
+}
diff --git a/examples/stm32l432/src/bin/qspi_mmap.rs b/examples/stm32l432/src/bin/qspi_mmap.rs
index 075458fe5..feabdd532 100644
--- a/examples/stm32l432/src/bin/qspi_mmap.rs
+++ b/examples/stm32l432/src/bin/qspi_mmap.rs
@@ -246,14 +246,14 @@ const MEMORY_ADDR: u32 = 0x00000000 as u32;
 async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
 
-    let config = qspi::Config {
-        memory_size: MemorySize::_16MiB,
-        address_size: AddressSize::_24bit,
-        prescaler: 200,
-        cs_high_time: ChipSelectHighTime::_1Cycle,
-        fifo_threshold: FIFOThresholdLevel::_16Bytes,
-        sample_shifting: SampleShifting::None,
-    };
+    let mut config = qspi::Config::default();
+    config.memory_size = MemorySize::_16MiB;
+    config.address_size = AddressSize::_24bit;
+    config.prescaler = 200;
+    config.cs_high_time = ChipSelectHighTime::_1Cycle;
+    config.fifo_threshold = FIFOThresholdLevel::_16Bytes;
+    config.sample_shifting = SampleShifting::None;
+
     let driver = qspi::Qspi::new_bank1(p.QUADSPI, p.PB1, p.PB0, p.PA7, p.PA6, p.PA3, p.PA2, p.DMA2_CH7, config);
     let mut flash = FlashMemory::new(driver);
     let mut wr_buf = [0u8; 256];
diff --git a/examples/stm32wl/src/bin/adc.rs b/examples/stm32wl/src/bin/adc.rs
new file mode 100644
index 000000000..118f02ae1
--- /dev/null
+++ b/examples/stm32wl/src/bin/adc.rs
@@ -0,0 +1,39 @@
+#![no_std]
+#![no_main]
+
+use core::mem::MaybeUninit;
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::adc::{Adc, CkModePclk, Clock, SampleTime};
+use embassy_stm32::SharedData;
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+static SHARED_DATA: MaybeUninit<SharedData> = MaybeUninit::uninit();
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = embassy_stm32::init_primary(Default::default(), &SHARED_DATA);
+    info!("Hello World!");
+
+    let mut adc = Adc::new_with_clock(p.ADC1, Clock::Sync { div: CkModePclk::DIV1 });
+    adc.set_sample_time(SampleTime::CYCLES79_5);
+    let mut pin = p.PB2;
+
+    let mut vrefint = adc.enable_vrefint();
+    let vrefint_sample = adc.blocking_read(&mut vrefint);
+    let convert_to_millivolts = |sample| {
+        // From https://www.st.com/resource/en/datasheet/stm32g031g8.pdf
+        // 6.3.3 Embedded internal reference voltage
+        const VREFINT_MV: u32 = 1212; // mV
+
+        (u32::from(sample) * VREFINT_MV / u32::from(vrefint_sample)) as u16
+    };
+
+    loop {
+        let v = adc.blocking_read(&mut pin);
+        info!("--> {} - {} mV", v, convert_to_millivolts(v));
+        Timer::after_millis(100).await;
+    }
+}
diff --git a/tests/rp/Cargo.toml b/tests/rp/Cargo.toml
index 809346bed..19461520a 100644
--- a/tests/rp/Cargo.toml
+++ b/tests/rp/Cargo.toml
@@ -64,6 +64,12 @@ name = "float"
 path = "src/bin/float.rs"
 required-features = [ "rp2040",]
 
+# RTC is only available on RP2040
+[[bin]]
+name = "rtc"
+path = "src/bin/rtc.rs"
+required-features = [ "rp2040",]
+
 [profile.dev]
 debug = 2
 debug-assertions = true
diff --git a/tests/rp/src/bin/rtc.rs b/tests/rp/src/bin/rtc.rs
new file mode 100644
index 000000000..c66981d95
--- /dev/null
+++ b/tests/rp/src/bin/rtc.rs
@@ -0,0 +1,125 @@
+#![no_std]
+#![no_main]
+#[cfg(feature = "rp2040")]
+teleprobe_meta::target!(b"rpi-pico");
+
+use defmt::{assert, *};
+use embassy_executor::Spawner;
+use embassy_futures::select::{select, Either};
+use embassy_rp::bind_interrupts;
+use embassy_rp::rtc::{DateTime, DateTimeFilter, DayOfWeek, Rtc};
+use embassy_time::{Duration, Instant, Timer};
+use {defmt_rtt as _, panic_probe as _};
+
+// Bind the RTC interrupt to the handler
+bind_interrupts!(struct Irqs {
+    RTC_IRQ => embassy_rp::rtc::InterruptHandler;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = embassy_rp::init(Default::default());
+    let mut rtc = Rtc::new(p.RTC, Irqs);
+
+    info!("RTC test started");
+
+    // Initialize RTC if not running
+    if !rtc.is_running() {
+        info!("Starting RTC");
+        let now = DateTime {
+            year: 2000,
+            month: 1,
+            day: 1,
+            day_of_week: DayOfWeek::Saturday,
+            hour: 0,
+            minute: 0,
+            second: 0,
+        };
+        rtc.set_datetime(now).unwrap();
+        Timer::after_millis(100).await;
+    }
+
+    // Test 1: Basic RTC functionality - read current time
+    let initial_time = rtc.now().unwrap();
+    info!(
+        "Initial time: {}-{:02}-{:02} {}:{:02}:{:02}",
+        initial_time.year,
+        initial_time.month,
+        initial_time.day,
+        initial_time.hour,
+        initial_time.minute,
+        initial_time.second
+    );
+
+    // Test 2: Schedule and wait for alarm
+    info!("Testing alarm scheduling");
+
+    // Wait until we're at a predictable second, then schedule for a future second
+    loop {
+        let current = rtc.now().unwrap();
+        if current.second <= 55 {
+            break;
+        }
+        Timer::after_millis(100).await;
+    }
+
+    // Now schedule alarm for 3 seconds from current time
+    let current_time = rtc.now().unwrap();
+    let alarm_second = (current_time.second + 3) % 60;
+    let alarm_filter = DateTimeFilter::default().second(alarm_second);
+
+    info!("Scheduling alarm for second: {}", alarm_second);
+    rtc.schedule_alarm(alarm_filter);
+
+    // Verify alarm is scheduled
+    let scheduled = rtc.alarm_scheduled();
+    assert!(scheduled.is_some(), "Alarm should be scheduled");
+    info!("Alarm scheduled successfully: {}", scheduled.unwrap());
+
+    // Wait for alarm with timeout
+    let alarm_start = Instant::now();
+    match select(Timer::after_secs(5), rtc.wait_for_alarm()).await {
+        Either::First(_) => {
+            core::panic!("Alarm timeout - alarm should have triggered by now");
+        }
+        Either::Second(_) => {
+            let alarm_duration = Instant::now() - alarm_start;
+            info!("ALARM TRIGGERED after {:?}", alarm_duration);
+
+            // Verify timing is reasonable (should be around 3 seconds)
+            assert!(
+                alarm_duration >= Duration::from_secs(2) && alarm_duration <= Duration::from_secs(4),
+                "Alarm timing incorrect: {:?}",
+                alarm_duration
+            );
+        }
+    }
+
+    // Test 3: Verify RTC is still running and time has advanced
+    let final_time = rtc.now().unwrap();
+    info!(
+        "Final time: {}-{:02}-{:02} {}:{:02}:{:02}",
+        final_time.year, final_time.month, final_time.day, final_time.hour, final_time.minute, final_time.second
+    );
+
+    // Verify time has advanced (allowing for minute/hour rollover)
+    let time_diff = if final_time.second >= initial_time.second {
+        final_time.second - initial_time.second
+    } else {
+        60 - initial_time.second + final_time.second
+    };
+
+    assert!(time_diff >= 3, "RTC should have advanced by at least 3 seconds");
+    info!("Time advanced by {} seconds", time_diff);
+
+    // Test 4: Verify alarm is no longer scheduled after triggering
+    let post_alarm_scheduled = rtc.alarm_scheduled();
+    assert!(
+        post_alarm_scheduled.is_none(),
+        "Alarm should not be scheduled after triggering"
+    );
+    info!("Alarm correctly cleared after triggering");
+
+    info!("Test OK");
+    cortex_m::asm::bkpt();
+}
diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml
index aeca67659..891ec93fd 100644
--- a/tests/stm32/Cargo.toml
+++ b/tests/stm32/Cargo.toml
@@ -9,7 +9,9 @@ publish = false
 [features]
 stm32c031c6 = ["embassy-stm32/stm32c031c6", "cm0", "not-gpdma"]
 stm32c071rb = ["embassy-stm32/stm32c071rb", "cm0", "not-gpdma"]
-stm32f103c8 = ["embassy-stm32/stm32f103c8", "spi-v1", "not-gpdma"]
+stm32f100rd = ["embassy-stm32/stm32f100rd", "spi-v1", "not-gpdma", "afio", "afio-value-line"]
+stm32f103c8 = ["embassy-stm32/stm32f103c8", "spi-v1", "not-gpdma", "afio"]
+stm32f107vc = ["embassy-stm32/stm32f107vc", "spi-v1", "not-gpdma", "afio", "afio-connectivity-line"]
 stm32f207zg = ["embassy-stm32/stm32f207zg", "spi-v1", "chrono", "not-gpdma", "eth", "rng"]
 stm32f303ze = ["embassy-stm32/stm32f303ze", "chrono", "not-gpdma"]
 stm32f429zi = ["embassy-stm32/stm32f429zi", "spi-v1", "chrono", "eth", "stop", "can", "not-gpdma", "dac", "rng"]
@@ -59,6 +61,9 @@ cordic = ["dep:num-traits"]
 dual-bank = ["embassy-stm32/dual-bank"]
 single-bank = ["embassy-stm32/single-bank"]
 eeprom = []
+afio = []
+afio-connectivity-line = []
+afio-value-line = []
 
 cm0 = ["portable-atomic/unsafe-assume-single-core"]
 
@@ -99,6 +104,11 @@ num-traits = { version="0.2", default-features = false,features = ["libm"], opti
 # BEGIN TESTS
 # Generated by gen_test.py. DO NOT EDIT.
 [[bin]]
+name = "afio"
+path = "src/bin/afio.rs"
+required-features = [ "afio",]
+
+[[bin]]
 name = "can"
 path = "src/bin/can.rs"
 required-features = [ "can",]
diff --git a/tests/stm32/src/bin/afio.rs b/tests/stm32/src/bin/afio.rs
new file mode 100644
index 000000000..cc44dc59c
--- /dev/null
+++ b/tests/stm32/src/bin/afio.rs
@@ -0,0 +1,1156 @@
+// required-features: afio
+#![no_std]
+#![no_main]
+#[path = "../common.rs"]
+mod common;
+
+use common::*;
+use embassy_executor::Spawner;
+use embassy_stm32::gpio::{AfioRemap, OutputType, Pull};
+use embassy_stm32::pac::AFIO;
+use embassy_stm32::time::khz;
+use embassy_stm32::timer::complementary_pwm::{ComplementaryPwm, ComplementaryPwmPin};
+use embassy_stm32::timer::input_capture::{CapturePin, InputCapture};
+use embassy_stm32::timer::pwm_input::PwmInput;
+use embassy_stm32::timer::qei::{Qei, QeiPin};
+use embassy_stm32::timer::simple_pwm::{PwmPin, SimplePwm};
+use embassy_stm32::usart::{Uart, UartRx, UartTx};
+use embassy_stm32::{bind_interrupts, Peripherals};
+
+#[cfg(not(feature = "afio-connectivity-line"))]
+bind_interrupts!(struct Irqs {
+    USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;
+    TIM1_CC => embassy_stm32::timer::CaptureCompareInterruptHandler<embassy_stm32::peripherals::TIM1>;
+});
+
+#[cfg(feature = "afio-connectivity-line")]
+bind_interrupts!(struct Irqs {
+    CAN1_RX0 => embassy_stm32::can::Rx0InterruptHandler<embassy_stm32::peripherals::CAN1>;
+    CAN1_RX1 => embassy_stm32::can::Rx1InterruptHandler<embassy_stm32::peripherals::CAN1>;
+    CAN1_SCE => embassy_stm32::can::SceInterruptHandler<embassy_stm32::peripherals::CAN1>;
+    CAN1_TX => embassy_stm32::can::TxInterruptHandler<embassy_stm32::peripherals::CAN1>;
+
+    CAN2_RX0 => embassy_stm32::can::Rx0InterruptHandler<embassy_stm32::peripherals::CAN2>;
+    CAN2_RX1 => embassy_stm32::can::Rx1InterruptHandler<embassy_stm32::peripherals::CAN2>;
+    CAN2_SCE => embassy_stm32::can::SceInterruptHandler<embassy_stm32::peripherals::CAN2>;
+    CAN2_TX => embassy_stm32::can::TxInterruptHandler<embassy_stm32::peripherals::CAN2>;
+
+    ETH => embassy_stm32::eth::InterruptHandler;
+    USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;
+    TIM1_CC => embassy_stm32::timer::CaptureCompareInterruptHandler<embassy_stm32::peripherals::TIM1>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut p = init();
+    info!("Hello World!");
+
+    // USART3
+    {
+        // no remap RX/TX/RTS/CTS
+        afio_registers_set_remap();
+        Uart::new_blocking_with_rtscts(
+            p.USART3.reborrow(),
+            p.PB11.reborrow(),
+            p.PB10.reborrow(),
+            p.PB14.reborrow(),
+            p.PB13.reborrow(),
+            Default::default(),
+        )
+        .unwrap();
+        defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 0);
+    }
+    {
+        // no remap RX/TX
+        afio_registers_set_remap();
+        Uart::new_blocking(
+            p.USART3.reborrow(),
+            p.PB11.reborrow(),
+            p.PB10.reborrow(),
+            Default::default(),
+        )
+        .unwrap();
+        defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 0);
+    }
+    {
+        // no remap TX
+        afio_registers_set_remap();
+        Uart::new_blocking_half_duplex(
+            p.USART3.reborrow(),
+            p.PB10.reborrow(),
+            Default::default(),
+            embassy_stm32::usart::HalfDuplexReadback::NoReadback,
+        )
+        .unwrap();
+        defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 0);
+    }
+    {
+        // no remap TX async
+        afio_registers_set_remap();
+        UartTx::new(
+            p.USART3.reborrow(),
+            p.PB10.reborrow(),
+            p.DMA1_CH2.reborrow(),
+            Default::default(),
+        )
+        .unwrap();
+        defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 0);
+    }
+    {
+        // no remap TX/CTS async
+        afio_registers_set_remap();
+        UartTx::new_with_cts(
+            p.USART3.reborrow(),
+            p.PB10.reborrow(),
+            p.PB13.reborrow(),
+            p.DMA1_CH2.reborrow(),
+            Default::default(),
+        )
+        .unwrap();
+        defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 0);
+    }
+    {
+        // no remap RX async
+        afio_registers_set_remap();
+        UartRx::new(
+            p.USART3.reborrow(),
+            Irqs,
+            p.PB11.reborrow(),
+            p.DMA1_CH3.reborrow(),
+            Default::default(),
+        )
+        .unwrap();
+        defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 0);
+    }
+    {
+        // no remap RX async
+        afio_registers_set_remap();
+        UartRx::new_with_rts(
+            p.USART3.reborrow(),
+            Irqs,
+            p.PB11.reborrow(),
+            p.PB14.reborrow(),
+            p.DMA1_CH3.reborrow(),
+            Default::default(),
+        )
+        .unwrap();
+        defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 0);
+    }
+    {
+        // no remap RX/TX async
+        afio_registers_set_remap();
+        Uart::new(
+            p.USART3.reborrow(),
+            p.PB11.reborrow(),
+            p.PB10.reborrow(),
+            Irqs,
+            p.DMA1_CH2.reborrow(),
+            p.DMA1_CH3.reborrow(),
+            Default::default(),
+        )
+        .unwrap();
+        defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 0);
+    }
+    {
+        // no remap RX/TX/RTS/CTS async
+        afio_registers_set_remap();
+        Uart::new_with_rtscts(
+            p.USART3.reborrow(),
+            p.PB11.reborrow(),
+            p.PB10.reborrow(),
+            Irqs,
+            p.PB14.reborrow(),
+            p.PB13.reborrow(),
+            p.DMA1_CH2.reborrow(),
+            p.DMA1_CH3.reborrow(),
+            Default::default(),
+        )
+        .unwrap();
+        defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 0);
+    }
+
+    // TIM1
+    {
+        // no remap
+        afio_registers_set_remap();
+        SimplePwm::new::<AfioRemap<0>>(
+            p.TIM1.reborrow(),
+            Some(PwmPin::new(p.PA8.reborrow(), OutputType::PushPull)),
+            Some(PwmPin::new(p.PA9.reborrow(), OutputType::PushPull)),
+            Some(PwmPin::new(p.PA10.reborrow(), OutputType::PushPull)),
+            Some(PwmPin::new(p.PA11.reborrow(), OutputType::PushPull)),
+            khz(10),
+            Default::default(),
+        );
+        defmt::assert_eq!(AFIO.mapr().read().tim1_remap(), 0);
+    }
+    {
+        // no remap
+        afio_registers_set_remap();
+        SimplePwm::new::<AfioRemap<0>>(
+            p.TIM1.reborrow(),
+            Some(PwmPin::new(p.PA8.reborrow(), OutputType::PushPull)),
+            None,
+            None,
+            None,
+            khz(10),
+            Default::default(),
+        );
+        defmt::assert_eq!(AFIO.mapr().read().tim1_remap(), 0);
+    }
+    {
+        // partial remap
+        reset_afio_registers();
+        ComplementaryPwm::new::<AfioRemap<1>>(
+            p.TIM1.reborrow(),
+            Some(PwmPin::new(p.PA8.reborrow(), OutputType::PushPull)),
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            khz(10),
+            Default::default(),
+        );
+        defmt::assert_eq!(AFIO.mapr().read().tim1_remap(), 1);
+    }
+    {
+        // partial remap
+        reset_afio_registers();
+        ComplementaryPwm::new::<AfioRemap<1>>(
+            p.TIM1.reborrow(),
+            Some(PwmPin::new(p.PA8.reborrow(), OutputType::PushPull)),
+            Some(ComplementaryPwmPin::new(p.PA7.reborrow(), OutputType::PushPull)),
+            Some(PwmPin::new(p.PA9.reborrow(), OutputType::PushPull)),
+            Some(ComplementaryPwmPin::new(p.PB0.reborrow(), OutputType::PushPull)),
+            Some(PwmPin::new(p.PA10.reborrow(), OutputType::PushPull)),
+            None, // pin does not exist on medium-density devices
+            Some(PwmPin::new(p.PA11.reborrow(), OutputType::PushPull)),
+            None, // signal does not exist
+            khz(10),
+            Default::default(),
+        );
+        defmt::assert_eq!(AFIO.mapr().read().tim1_remap(), 1);
+    }
+    {
+        // partial remap
+        reset_afio_registers();
+        InputCapture::new::<AfioRemap<1>>(
+            p.TIM1.reborrow(),
+            Some(CapturePin::new(p.PA8.reborrow(), Pull::Down)),
+            None,
+            None,
+            None,
+            Irqs,
+            khz(10),
+            Default::default(),
+        );
+        defmt::assert_eq!(AFIO.mapr().read().tim1_remap(), 1);
+    }
+    {
+        // partial remap
+        reset_afio_registers();
+        PwmInput::new_ch1::<AfioRemap<1>>(p.TIM1.reborrow(), p.PA8.reborrow(), Pull::Down, khz(10));
+        defmt::assert_eq!(AFIO.mapr().read().tim1_remap(), 1);
+    }
+    {
+        // partial remap
+        reset_afio_registers();
+        Qei::new::<AfioRemap<1>>(
+            p.TIM1.reborrow(),
+            QeiPin::new(p.PA8.reborrow()),
+            QeiPin::new(p.PA9.reborrow()),
+        );
+        defmt::assert_eq!(AFIO.mapr().read().tim1_remap(), 1);
+    }
+
+    // TIM2
+    {
+        // no remap
+        afio_registers_set_remap();
+        SimplePwm::new::<AfioRemap<0>>(
+            p.TIM2.reborrow(),
+            Some(PwmPin::new(p.PA0.reborrow(), OutputType::PushPull)),
+            Some(PwmPin::new(p.PA1.reborrow(), OutputType::PushPull)),
+            Some(PwmPin::new(p.PA2.reborrow(), OutputType::PushPull)),
+            Some(PwmPin::new(p.PA3.reborrow(), OutputType::PushPull)),
+            khz(10),
+            Default::default(),
+        );
+        defmt::assert_eq!(AFIO.mapr().read().tim2_remap(), 0);
+    }
+    {
+        // partial remap 1
+        reset_afio_registers();
+        SimplePwm::new::<AfioRemap<1>>(
+            p.TIM2.reborrow(),
+            Some(PwmPin::new(p.PA15.reborrow(), OutputType::PushPull)),
+            Some(PwmPin::new(p.PB3.reborrow(), OutputType::PushPull)),
+            Some(PwmPin::new(p.PA2.reborrow(), OutputType::PushPull)),
+            Some(PwmPin::new(p.PA3.reborrow(), OutputType::PushPull)),
+            khz(10),
+            Default::default(),
+        );
+        defmt::assert_eq!(AFIO.mapr().read().tim2_remap(), 1);
+    }
+    {
+        // partial remap 2
+        reset_afio_registers();
+        SimplePwm::new::<AfioRemap<2>>(
+            p.TIM2.reborrow(),
+            Some(PwmPin::new(p.PA0.reborrow(), OutputType::PushPull)),
+            Some(PwmPin::new(p.PA1.reborrow(), OutputType::PushPull)),
+            Some(PwmPin::new(p.PB10.reborrow(), OutputType::PushPull)),
+            Some(PwmPin::new(p.PB11.reborrow(), OutputType::PushPull)),
+            khz(10),
+            Default::default(),
+        );
+        defmt::assert_eq!(AFIO.mapr().read().tim2_remap(), 2);
+    }
+    {
+        // full remap
+        reset_afio_registers();
+        SimplePwm::new::<AfioRemap<3>>(
+            p.TIM2.reborrow(),
+            Some(PwmPin::new(p.PA15.reborrow(), OutputType::PushPull)),
+            Some(PwmPin::new(p.PB3.reborrow(), OutputType::PushPull)),
+            Some(PwmPin::new(p.PB10.reborrow(), OutputType::PushPull)),
+            Some(PwmPin::new(p.PB11.reborrow(), OutputType::PushPull)),
+            khz(10),
+            Default::default(),
+        );
+        defmt::assert_eq!(AFIO.mapr().read().tim2_remap(), 3);
+    }
+
+    connectivity_line::run(&mut p);
+    value_line::run(&mut p);
+
+    info!("Test OK");
+    cortex_m::asm::bkpt();
+}
+
+#[cfg(feature = "afio-connectivity-line")]
+mod connectivity_line {
+    use embassy_stm32::can::Can;
+    use embassy_stm32::eth::{Ethernet, GenericPhy, PacketQueue};
+    use embassy_stm32::i2s::I2S;
+    use embassy_stm32::spi::Spi;
+
+    use super::*;
+
+    pub fn run(p: &mut Peripherals) {
+        // USART3
+        {
+            // partial remap RX/TX/RTS/CTS
+            reset_afio_registers();
+            Uart::new_blocking_with_rtscts(
+                p.USART3.reborrow(),
+                p.PC11.reborrow(),
+                p.PC10.reborrow(),
+                p.PB14.reborrow(),
+                p.PB13.reborrow(),
+                Default::default(),
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 1);
+        }
+        {
+            // partial remap RX/TX
+            reset_afio_registers();
+            Uart::new_blocking(
+                p.USART3.reborrow(),
+                p.PC11.reborrow(),
+                p.PC10.reborrow(),
+                Default::default(),
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 1);
+        }
+        {
+            // partial remap TX
+            reset_afio_registers();
+            Uart::new_blocking_half_duplex(
+                p.USART3.reborrow(),
+                p.PC10.reborrow(),
+                Default::default(),
+                embassy_stm32::usart::HalfDuplexReadback::NoReadback,
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 1);
+        }
+        {
+            // partial remap TX async
+            reset_afio_registers();
+            UartTx::new(
+                p.USART3.reborrow(),
+                p.PC10.reborrow(),
+                p.DMA1_CH2.reborrow(),
+                Default::default(),
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 1);
+        }
+        {
+            // partial remap TX/CTS async
+            reset_afio_registers();
+            UartTx::new_with_cts(
+                p.USART3.reborrow(),
+                p.PC10.reborrow(),
+                p.PB13.reborrow(),
+                p.DMA1_CH2.reborrow(),
+                Default::default(),
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 1);
+        }
+        {
+            // partial remap RX async
+            reset_afio_registers();
+            UartRx::new(
+                p.USART3.reborrow(),
+                Irqs,
+                p.PC11.reborrow(),
+                p.DMA1_CH3.reborrow(),
+                Default::default(),
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 1);
+        }
+        {
+            // partial remap RX async
+            reset_afio_registers();
+            UartRx::new_with_rts(
+                p.USART3.reborrow(),
+                Irqs,
+                p.PC11.reborrow(),
+                p.PB14.reborrow(),
+                p.DMA1_CH3.reborrow(),
+                Default::default(),
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 1);
+        }
+        {
+            // partial remap RX/TX async
+            reset_afio_registers();
+            Uart::new(
+                p.USART3.reborrow(),
+                p.PC11.reborrow(),
+                p.PC10.reborrow(),
+                Irqs,
+                p.DMA1_CH2.reborrow(),
+                p.DMA1_CH3.reborrow(),
+                Default::default(),
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 1);
+        }
+        {
+            // partial remap RX/TX/RTS/CTS async
+            reset_afio_registers();
+            Uart::new_with_rtscts(
+                p.USART3.reborrow(),
+                p.PC11.reborrow(),
+                p.PC10.reborrow(),
+                Irqs,
+                p.PB14.reborrow(),
+                p.PB13.reborrow(),
+                p.DMA1_CH2.reborrow(),
+                p.DMA1_CH3.reborrow(),
+                Default::default(),
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 1);
+        }
+        {
+            // full remap RX/TX/RTS/CTS
+            reset_afio_registers();
+            Uart::new_blocking_with_rtscts(
+                p.USART3.reborrow(),
+                p.PD9.reborrow(),
+                p.PD8.reborrow(),
+                p.PD12.reborrow(),
+                p.PD11.reborrow(),
+                Default::default(),
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 3);
+        }
+        {
+            // full remap RX/TX
+            reset_afio_registers();
+            Uart::new_blocking(
+                p.USART3.reborrow(),
+                p.PD9.reborrow(),
+                p.PD8.reborrow(),
+                Default::default(),
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 3);
+        }
+        {
+            // full remap TX
+            reset_afio_registers();
+            Uart::new_blocking_half_duplex(
+                p.USART3.reborrow(),
+                p.PD8.reborrow(),
+                Default::default(),
+                embassy_stm32::usart::HalfDuplexReadback::NoReadback,
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 3);
+        }
+        {
+            // full remap TX async
+            reset_afio_registers();
+            UartTx::new(
+                p.USART3.reborrow(),
+                p.PD8.reborrow(),
+                p.DMA1_CH2.reborrow(),
+                Default::default(),
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 3);
+        }
+        {
+            // full remap TX/CTS async
+            reset_afio_registers();
+            UartTx::new_with_cts(
+                p.USART3.reborrow(),
+                p.PD8.reborrow(),
+                p.PD11.reborrow(),
+                p.DMA1_CH2.reborrow(),
+                Default::default(),
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 3);
+        }
+        {
+            // full remap RX async
+            reset_afio_registers();
+            UartRx::new(
+                p.USART3.reborrow(),
+                Irqs,
+                p.PD9.reborrow(),
+                p.DMA1_CH3.reborrow(),
+                Default::default(),
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 3);
+        }
+        {
+            // full remap RX async
+            reset_afio_registers();
+            UartRx::new_with_rts(
+                p.USART3.reborrow(),
+                Irqs,
+                p.PD9.reborrow(),
+                p.PD12.reborrow(),
+                p.DMA1_CH3.reborrow(),
+                Default::default(),
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 3);
+        }
+        {
+            // full remap RX/TX async
+            reset_afio_registers();
+            Uart::new(
+                p.USART3.reborrow(),
+                p.PD9.reborrow(),
+                p.PD8.reborrow(),
+                Irqs,
+                p.DMA1_CH2.reborrow(),
+                p.DMA1_CH3.reborrow(),
+                Default::default(),
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 3);
+        }
+        {
+            // full remap RX/TX/RTS/CTS async
+            reset_afio_registers();
+            Uart::new_with_rtscts(
+                p.USART3.reborrow(),
+                p.PD9.reborrow(),
+                p.PD8.reborrow(),
+                Irqs,
+                p.PD12.reborrow(),
+                p.PD11.reborrow(),
+                p.DMA1_CH2.reborrow(),
+                p.DMA1_CH3.reborrow(),
+                Default::default(),
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart3_remap(), 3);
+        }
+
+        // SPI3
+        {
+            // no remap SCK/MISO/MOSI
+            afio_registers_set_remap();
+            Spi::new_blocking(
+                p.SPI3.reborrow(),
+                p.PB3.reborrow(),
+                p.PB5.reborrow(),
+                p.PB4.reborrow(),
+                Default::default(),
+            );
+            defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), false);
+        }
+        {
+            // no remap SCK/MOSI
+            afio_registers_set_remap();
+            Spi::new_blocking_txonly(
+                p.SPI3.reborrow(),
+                p.PB3.reborrow(),
+                p.PB5.reborrow(),
+                Default::default(),
+            );
+            defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), false);
+        }
+        {
+            // no remap MOSI
+            afio_registers_set_remap();
+            Spi::new_blocking_txonly_nosck(p.SPI3.reborrow(), p.PB5.reborrow(), Default::default());
+            defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), false);
+        }
+        {
+            // no remap SCK/MISO
+            afio_registers_set_remap();
+            Spi::new_blocking_rxonly(
+                p.SPI3.reborrow(),
+                p.PB3.reborrow(),
+                p.PB4.reborrow(),
+                Default::default(),
+            );
+            defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), false);
+        }
+        {
+            // remap SCK/MISO/MOSI
+            reset_afio_registers();
+            Spi::new_blocking(
+                p.SPI3.reborrow(),
+                p.PC10.reborrow(),
+                p.PC12.reborrow(),
+                p.PC11.reborrow(),
+                Default::default(),
+            );
+
+            defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), true);
+        }
+        {
+            // remap SCK/MOSI
+            reset_afio_registers();
+            Spi::new_blocking_txonly(
+                p.SPI3.reborrow(),
+                p.PC10.reborrow(),
+                p.PC12.reborrow(),
+                Default::default(),
+            );
+            defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), true);
+        }
+        {
+            // remap MOSI
+            reset_afio_registers();
+            Spi::new_blocking_txonly_nosck(p.SPI3.reborrow(), p.PB5.reborrow(), Default::default());
+            defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), true);
+        }
+        {
+            // remap SCK/MISO
+            reset_afio_registers();
+            Spi::new_blocking_rxonly(
+                p.SPI3.reborrow(),
+                p.PC10.reborrow(),
+                p.PC11.reborrow(),
+                Default::default(),
+            );
+            defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), true);
+        }
+
+        // I2S3
+        {
+            // no remap SD/WS/CK/MCK
+            afio_registers_set_remap();
+            I2S::new_txonly(
+                p.SPI3.reborrow(),
+                p.PB5.reborrow(),
+                p.PA15.reborrow(),
+                p.PB3.reborrow(),
+                p.PC7.reborrow(),
+                p.DMA2_CH2.reborrow(),
+                &mut [0u16; 0],
+                Default::default(),
+            );
+            defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), false);
+        }
+        {
+            // no remap SD/WS/CK
+            afio_registers_set_remap();
+            I2S::new_txonly_nomck(
+                p.SPI3.reborrow(),
+                p.PB5.reborrow(),
+                p.PA15.reborrow(),
+                p.PB3.reborrow(),
+                p.DMA2_CH2.reborrow(),
+                &mut [0u16; 0],
+                Default::default(),
+            );
+            defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), false);
+        }
+        {
+            // no remap SD/WS/CK/MCK
+            afio_registers_set_remap();
+            I2S::new_rxonly(
+                p.SPI3.reborrow(),
+                p.PB4.reborrow(),
+                p.PA15.reborrow(),
+                p.PB3.reborrow(),
+                p.PC7.reborrow(),
+                p.DMA2_CH1.reborrow(),
+                &mut [0u16; 0],
+                Default::default(),
+            );
+            defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), true);
+        }
+        {
+            // remap SD/WS/CK/MCK
+            reset_afio_registers();
+            I2S::new_txonly(
+                p.SPI3.reborrow(),
+                p.PC12.reborrow(),
+                p.PA4.reborrow(),
+                p.PC10.reborrow(),
+                p.PC7.reborrow(),
+                p.DMA2_CH2.reborrow(),
+                &mut [0u16; 0],
+                Default::default(),
+            );
+            defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), true);
+        }
+        {
+            // remap SD/WS/CK
+            reset_afio_registers();
+            I2S::new_txonly_nomck(
+                p.SPI3.reborrow(),
+                p.PC12.reborrow(),
+                p.PA4.reborrow(),
+                p.PC10.reborrow(),
+                p.DMA2_CH2.reborrow(),
+                &mut [0u16; 0],
+                Default::default(),
+            );
+            defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), true);
+        }
+        {
+            // remap SD/WS/CK/MCK
+            reset_afio_registers();
+            I2S::new_rxonly(
+                p.SPI3.reborrow(),
+                p.PC11.reborrow(),
+                p.PA4.reborrow(),
+                p.PC10.reborrow(),
+                p.PC7.reborrow(),
+                p.DMA2_CH1.reborrow(),
+                &mut [0u16; 0],
+                Default::default(),
+            );
+            defmt::assert_eq!(AFIO.mapr().read().spi3_remap(), true);
+        }
+
+        // CAN2
+        {
+            // no remap
+            afio_registers_set_remap();
+            Can::new(p.CAN2.reborrow(), p.PB12.reborrow(), p.PB13.reborrow(), Irqs);
+            defmt::assert_eq!(AFIO.mapr().read().can2_remap(), false);
+        }
+        {
+            // remap
+            reset_afio_registers();
+            Can::new(p.CAN2.reborrow(), p.PB5.reborrow(), p.PB6.reborrow(), Irqs);
+            defmt::assert_eq!(AFIO.mapr().read().can2_remap(), true);
+        }
+
+        // Ethernet
+        {
+            // no remap RMII
+            afio_registers_set_remap();
+            Ethernet::new(
+                &mut PacketQueue::<1, 1>::new(),
+                p.ETH.reborrow(),
+                Irqs,
+                p.PA1.reborrow(),
+                p.PA2.reborrow(),
+                p.PC1.reborrow(),
+                p.PA7.reborrow(),
+                p.PC4.reborrow(),
+                p.PC5.reborrow(),
+                p.PB12.reborrow(),
+                p.PB13.reborrow(),
+                p.PB11.reborrow(),
+                GenericPhy::new_auto(),
+                Default::default(),
+            );
+            defmt::assert_eq!(AFIO.mapr().read().eth_remap(), false);
+        }
+        {
+            // no remap MII
+            afio_registers_set_remap();
+            Ethernet::new_mii(
+                &mut PacketQueue::<1, 1>::new(),
+                p.ETH.reborrow(),
+                Irqs,
+                p.PA1.reborrow(),
+                p.PC3.reborrow(),
+                p.PA2.reborrow(),
+                p.PC1.reborrow(),
+                p.PA7.reborrow(),
+                p.PC4.reborrow(),
+                p.PC5.reborrow(),
+                p.PB0.reborrow(),
+                p.PB1.reborrow(),
+                p.PB12.reborrow(),
+                p.PB13.reborrow(),
+                p.PC2.reborrow(),
+                p.PB8.reborrow(),
+                p.PB11.reborrow(),
+                GenericPhy::new_auto(),
+                Default::default(),
+            );
+            defmt::assert_eq!(AFIO.mapr().read().eth_remap(), false);
+        }
+        {
+            // remap RMII
+            reset_afio_registers();
+            Ethernet::new(
+                &mut PacketQueue::<1, 1>::new(),
+                p.ETH.reborrow(),
+                Irqs,
+                p.PA1.reborrow(),
+                p.PA2.reborrow(),
+                p.PC1.reborrow(),
+                p.PD8.reborrow(),
+                p.PD9.reborrow(),
+                p.PD10.reborrow(),
+                p.PB12.reborrow(),
+                p.PB13.reborrow(),
+                p.PB11.reborrow(),
+                GenericPhy::new_auto(),
+                Default::default(),
+            );
+            defmt::assert_eq!(AFIO.mapr().read().eth_remap(), true);
+        }
+        {
+            // remap MII
+            reset_afio_registers();
+            Ethernet::new_mii(
+                &mut PacketQueue::<1, 1>::new(),
+                p.ETH.reborrow(),
+                Irqs,
+                p.PA1.reborrow(),
+                p.PC3.reborrow(),
+                p.PA2.reborrow(),
+                p.PC1.reborrow(),
+                p.PD8.reborrow(),
+                p.PD9.reborrow(),
+                p.PD10.reborrow(),
+                p.PD11.reborrow(),
+                p.PD12.reborrow(),
+                p.PB12.reborrow(),
+                p.PB13.reborrow(),
+                p.PC2.reborrow(),
+                p.PB8.reborrow(),
+                p.PB11.reborrow(),
+                GenericPhy::new_auto(),
+                Default::default(),
+            );
+            defmt::assert_eq!(AFIO.mapr().read().eth_remap(), true);
+        }
+
+        // CAN1
+        {
+            // no remap
+            afio_registers_set_remap();
+            Can::new(p.CAN1.reborrow(), p.PA11.reborrow(), p.PA12.reborrow(), Irqs);
+            defmt::assert_eq!(AFIO.mapr().read().can1_remap(), 0);
+        }
+        {
+            // partial remap
+            reset_afio_registers();
+            Can::new(p.CAN1.reborrow(), p.PB8.reborrow(), p.PB9.reborrow(), Irqs);
+            defmt::assert_eq!(AFIO.mapr().read().can1_remap(), 2);
+        }
+        {
+            // full remap
+            reset_afio_registers();
+            Can::new(p.CAN1.reborrow(), p.PD0.reborrow(), p.PD1.reborrow(), Irqs);
+            defmt::assert_eq!(AFIO.mapr().read().can1_remap(), 3);
+        }
+
+        // USART2
+        {
+            // no remap RX/TX/RTS/CTS
+            afio_registers_set_remap();
+            Uart::new_blocking_with_rtscts(
+                p.USART2.reborrow(),
+                p.PA3.reborrow(),
+                p.PA2.reborrow(),
+                p.PA1.reborrow(),
+                p.PA0.reborrow(),
+                Default::default(),
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart2_remap(), false);
+        }
+        {
+            // no remap RX/TX
+            afio_registers_set_remap();
+            Uart::new_blocking(
+                p.USART2.reborrow(),
+                p.PA3.reborrow(),
+                p.PA2.reborrow(),
+                Default::default(),
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart2_remap(), false);
+        }
+        {
+            // no remap TX
+            afio_registers_set_remap();
+            Uart::new_blocking_half_duplex(
+                p.USART2.reborrow(),
+                p.PA2.reborrow(),
+                Default::default(),
+                embassy_stm32::usart::HalfDuplexReadback::NoReadback,
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart2_remap(), false);
+        }
+        {
+            // full remap RX/TX/RTS/CTS
+            reset_afio_registers();
+            Uart::new_blocking_with_rtscts(
+                p.USART2.reborrow(),
+                p.PD6.reborrow(),
+                p.PD5.reborrow(),
+                p.PD4.reborrow(),
+                p.PD3.reborrow(),
+                Default::default(),
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart2_remap(), false);
+        }
+        {
+            // full remap RX/TX
+            reset_afio_registers();
+            Uart::new_blocking(
+                p.USART2.reborrow(),
+                p.PD6.reborrow(),
+                p.PD5.reborrow(),
+                Default::default(),
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart2_remap(), false);
+        }
+        {
+            // full remap TX
+            reset_afio_registers();
+            Uart::new_blocking_half_duplex(
+                p.USART2.reborrow(),
+                p.PD5.reborrow(),
+                Default::default(),
+                embassy_stm32::usart::HalfDuplexReadback::NoReadback,
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart2_remap(), true);
+        }
+
+        // USART1
+        {
+            // no remap RX/TX/RTS/CTS
+            afio_registers_set_remap();
+            Uart::new_blocking_with_rtscts(
+                p.USART1.reborrow(),
+                p.PA10.reborrow(),
+                p.PA9.reborrow(),
+                p.PA12.reborrow(),
+                p.PA11.reborrow(),
+                Default::default(),
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart1_remap(), false);
+        }
+        {
+            // no remap RX/TX
+            afio_registers_set_remap();
+            Uart::new_blocking(
+                p.USART1.reborrow(),
+                p.PA10.reborrow(),
+                p.PA9.reborrow(),
+                Default::default(),
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart1_remap(), false);
+        }
+        {
+            // no remap TX
+            afio_registers_set_remap();
+            Uart::new_blocking_half_duplex(
+                p.USART1.reborrow(),
+                p.PA9.reborrow(),
+                Default::default(),
+                embassy_stm32::usart::HalfDuplexReadback::NoReadback,
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart1_remap(), false);
+        }
+        {
+            // remap RX/TX/RTS/CTS
+            reset_afio_registers();
+            Uart::new_blocking_with_rtscts(
+                p.USART1.reborrow(),
+                p.PB7.reborrow(),
+                p.PB6.reborrow(),
+                p.PA12.reborrow(),
+                p.PA11.reborrow(),
+                Default::default(),
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart1_remap(), true);
+        }
+        {
+            // remap RX/TX
+            reset_afio_registers();
+            Uart::new_blocking(
+                p.USART1.reborrow(),
+                p.PB7.reborrow(),
+                p.PB6.reborrow(),
+                Default::default(),
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart1_remap(), true);
+        }
+        {
+            // remap TX
+            reset_afio_registers();
+            Uart::new_blocking_half_duplex(
+                p.USART1.reborrow(),
+                p.PB6.reborrow(),
+                Default::default(),
+                embassy_stm32::usart::HalfDuplexReadback::NoReadback,
+            )
+            .unwrap();
+            defmt::assert_eq!(AFIO.mapr().read().usart1_remap(), true);
+        }
+
+        // TIM1
+        {
+            // full remap
+            reset_afio_registers();
+            SimplePwm::new(
+                p.TIM1.reborrow(),
+                Some(PwmPin::new(p.PE9.reborrow(), OutputType::PushPull)),
+                Some(PwmPin::new(p.PE11.reborrow(), OutputType::PushPull)),
+                None,
+                None,
+                khz(10),
+                Default::default(),
+            );
+            defmt::assert_eq!(AFIO.mapr().read().tim1_remap(), 3);
+        }
+    }
+}
+
+#[cfg(feature = "afio-value-line")]
+mod value_line {
+    use super::*;
+
+    pub fn run(p: &mut Peripherals) {
+        // TIM13
+        {
+            // no remap
+            reset_afio_registers();
+            SimplePwm::new(
+                p.TIM13.reborrow(),
+                Some(PwmPin::new(p.PC8.reborrow(), OutputType::PushPull)),
+                None,
+                None,
+                None,
+                khz(10),
+                Default::default(),
+            );
+            defmt::assert_eq!(AFIO.mapr2().read().tim13_remap(), false);
+        }
+        {
+            // remap
+            reset_afio_registers();
+            SimplePwm::new(
+                p.TIM13.reborrow(),
+                Some(PwmPin::new(p.PB0.reborrow(), OutputType::PushPull)),
+                None,
+                None,
+                None,
+                khz(10),
+                Default::default(),
+            );
+            defmt::assert_eq!(AFIO.mapr2().read().tim13_remap(), true);
+        }
+    }
+}
+
+#[cfg(not(feature = "afio-connectivity-line"))]
+mod connectivity_line {
+    use super::*;
+
+    pub fn run(_: &mut Peripherals) {}
+}
+
+#[cfg(not(feature = "afio-value-line"))]
+mod value_line {
+    use super::*;
+
+    pub fn run(_: &mut Peripherals) {}
+}
+
+fn reset_afio_registers() {
+    set_afio_registers(false, 0);
+}
+
+fn afio_registers_set_remap() {
+    set_afio_registers(true, 1);
+}
+
+fn set_afio_registers(bool_val: bool, num_val: u8) {
+    AFIO.mapr().modify(|w| {
+        w.set_swj_cfg(embassy_stm32::pac::afio::vals::SwjCfg::NO_OP);
+        w.set_can1_remap(num_val);
+        w.set_can2_remap(bool_val);
+        w.set_eth_remap(bool_val);
+        w.set_i2c1_remap(bool_val);
+        w.set_spi1_remap(bool_val);
+        w.set_spi3_remap(bool_val);
+        w.set_tim1_remap(num_val);
+        w.set_tim2_remap(num_val);
+        w.set_tim3_remap(num_val);
+        w.set_tim4_remap(bool_val);
+        w.set_usart1_remap(bool_val);
+        w.set_usart2_remap(bool_val);
+        w.set_usart3_remap(num_val);
+    });
+
+    AFIO.mapr2().modify(|w| {
+        w.set_cec_remap(bool_val);
+        w.set_tim9_remap(bool_val);
+        w.set_tim10_remap(bool_val);
+        w.set_tim11_remap(bool_val);
+        w.set_tim12_remap(bool_val);
+        w.set_tim13_remap(bool_val);
+        w.set_tim14_remap(bool_val);
+        w.set_tim15_remap(bool_val);
+        w.set_tim16_remap(bool_val);
+        w.set_tim17_remap(bool_val);
+    });
+}
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index cb63b3374..f800769ab 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -103,7 +103,7 @@ define_peris!(
     SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2,
     @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
 );
-#[cfg(feature = "stm32f103c8")]
+#[cfg(any(feature = "stm32f100rd", feature = "stm32f103c8", feature = "stm32f107vc"))]
 define_peris!(
     UART = USART1, UART_TX = PA9, UART_RX = PA10, UART_TX_DMA = DMA1_CH4, UART_RX_DMA = DMA1_CH5,
     SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2,