2 files changed, 28 insertions, 13 deletions

diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs
index 06cc0e41d..86f56eb7c 100644
--- a/embassy-stm32/src/usart/buffered.rs
+++ b/embassy-stm32/src/usart/buffered.rs
@@ -12,8 +12,8 @@ use embassy_sync::waitqueue::AtomicWaker;
 #[cfg(not(any(usart_v1, usart_v2)))]
 use super::DePin;
 use super::{
-    clear_interrupt_flags, configure, rdr, reconfigure, sr, tdr, Config, ConfigError, CtsPin, Error, Info, Instance,
-    Regs, RtsPin, RxPin, TxPin,
+    clear_interrupt_flags, configure, rdr, reconfigure, send_break, sr, tdr, Config, ConfigError, CtsPin, Error, Info,
+    Instance, Regs, RtsPin, RxPin, TxPin,
 };
 use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed};
 use crate::interrupt::{self, InterruptExt};
@@ -359,6 +359,11 @@ impl<'d> BufferedUart<'d> {
 
         Ok(())
     }
+
+    /// Send break character
+    pub fn send_break(&self) {
+        self.tx.send_break()
+    }
 }
 
 impl<'d> BufferedUartRx<'d> {
@@ -538,6 +543,11 @@ impl<'d> BufferedUartTx<'d> {
 
         Ok(())
     }
+
+    /// Send break character
+    pub fn send_break(&self) {
+        send_break(&self.info.regs);
+    }
 }
 
 impl<'d> Drop for BufferedUartRx<'d> {
diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs
index cbd4ac3bc..e7f2f890a 100644
--- a/embassy-stm32/src/usart/mod.rs
+++ b/embassy-stm32/src/usart/mod.rs
@@ -523,17 +523,7 @@ impl<'d, M: Mode> UartTx<'d, M> {
 
     /// Send break character
     pub fn send_break(&self) {
-        // Busy wait until previous break has been sent
-        #[cfg(any(usart_v1, usart_v2))]
-        while self.info.regs.cr1().read().sbk() {}
-        #[cfg(any(usart_v3, usart_v4))]
-        while self.info.regs.isr().read().sbkf() {}
-
-        // Send break right after completing the current character transmission
-        #[cfg(any(usart_v1, usart_v2))]
-        self.info.regs.cr1().modify(|w| w.set_sbk(true));
-        #[cfg(any(usart_v3, usart_v4))]
-        self.info.regs.rqr().write(|w| w.set_sbkrq(true));
+        send_break(&self.info.regs);
     }
 }
 
@@ -549,6 +539,21 @@ fn blocking_flush(info: &Info) -> Result<(), Error> {
     Ok(())
 }
 
+/// Send break character
+pub fn send_break(regs: &Regs) {
+    // Busy wait until previous break has been sent
+    #[cfg(any(usart_v1, usart_v2))]
+    while regs.cr1().read().sbk() {}
+    #[cfg(any(usart_v3, usart_v4))]
+    while regs.isr().read().sbkf() {}
+
+    // Send break right after completing the current character transmission
+    #[cfg(any(usart_v1, usart_v2))]
+    regs.cr1().modify(|w| w.set_sbk(true));
+    #[cfg(any(usart_v3, usart_v4))]
+    regs.rqr().write(|w| w.set_sbkrq(true));
+}
+
 impl<'d> UartRx<'d, Async> {
     /// Create a new rx-only UART with no hardware flow control.
     ///