3 files changed, 20 insertions, 24 deletions

diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs
index 9a56a41fb..90ba196fc 100644
--- a/embassy-stm32/src/timer/complementary_pwm.rs
+++ b/embassy-stm32/src/timer/complementary_pwm.rs
@@ -160,15 +160,17 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
 
     /// Set PWM frequency.
     ///
-    /// Note: when you call this, the max duty value changes, so you will have to
-    /// call `set_duty` on all channels with the duty calculated based on the new max duty.
-    pub fn set_frequency(&mut self, freq: Hertz) {
+    /// Returns the applied ARR value which can be used to calculate CCR values.
+    ///
+    /// Note: that the frequency will not be applied in the timer until an update event
+    /// occurs. Reading the `max_duty` before the update event will return the old value
+    pub fn set_frequency(&mut self, freq: Hertz) -> u32 {
         let multiplier = if self.inner.get_counting_mode().is_center_aligned() {
             2u8
         } else {
             1u8
         };
-        self.inner.set_frequency_internal(freq * multiplier, 16);
+        self.inner.set_frequency_internal(freq * multiplier, 16)
     }
 
     /// Get max duty value.
diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs
index 0122fe4f7..f6af8be8c 100644
--- a/embassy-stm32/src/timer/low_level.rs
+++ b/embassy-stm32/src/timer/low_level.rs
@@ -293,19 +293,17 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
     /// the timer counter will wrap around at the same frequency as is being set.
     /// In center-aligned mode (which not all timers support), the wrap-around frequency is effectively halved
     /// because it needs to count up and down.
-    pub fn set_frequency(&self, frequency: Hertz) {
+    pub fn set_frequency(&self, frequency: Hertz) -> u32 {
         match T::BITS {
-            TimerBits::Bits16 => {
-                self.set_frequency_internal(frequency, 16);
-            }
+            TimerBits::Bits16 => self.set_frequency_internal(frequency, 16),
             #[cfg(not(stm32l0))]
-            TimerBits::Bits32 => {
-                self.set_frequency_internal(frequency, 32);
-            }
+            TimerBits::Bits32 => self.set_frequency_internal(frequency, 32),
         }
     }
 
-    pub(crate) fn set_frequency_internal(&self, frequency: Hertz, max_divide_by_bits: u8) {
+    /// Calculate ARR based on desired frequency
+    /// Returns actual value written to the register as u32
+    pub(crate) fn set_frequency_internal(&self, frequency: Hertz, max_divide_by_bits: u8) -> u32 {
         let f = frequency.0;
         assert!(f > 0);
         let timer_f = T::frequency().0;
@@ -322,10 +320,7 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
                 let regs = self.regs_core();
                 regs.psc().write_value(psc);
                 regs.arr().write(|r| r.set_arr(arr));
-
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
-                regs.egr().write(|r| r.set_ug(true));
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
+                arr as u32
             }
             #[cfg(not(stm32l0))]
             TimerBits::Bits32 => {
@@ -335,10 +330,7 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
                 let regs = self.regs_gp32_unchecked();
                 regs.psc().write_value(psc);
                 regs.arr().write_value(arr);
-
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
-                regs.egr().write(|r| r.set_ug(true));
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
+                arr
             }
         }
     }
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index c338b0fd4..01996c969 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -285,16 +285,18 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
 
     /// Set PWM frequency.
     ///
-    /// Note: when you call this, the max duty value changes, so you will have to
-    /// call `set_duty` on all channels with the duty calculated based on the new max duty.
-    pub fn set_frequency(&mut self, freq: Hertz) {
+    /// Returns the applied ARR value which can be used to calculate CCR values.
+    ///
+    /// Note: that the frequency will not be applied in the timer until an update event
+    /// occurs. Reading the `max_duty` before the update event will return the old value
+    pub fn set_frequency(&mut self, freq: Hertz) -> u32 {
         // TODO: prevent ARR = u16::MAX?
         let multiplier = if self.inner.get_counting_mode().is_center_aligned() {
             2u8
         } else {
             1u8
         };
-        self.inner.set_frequency_internal(freq * multiplier, 16);
+        self.inner.set_frequency_internal(freq * multiplier, 16)
     }
 
     /// Get max duty value.