14 files changed, 37 insertions, 49 deletions

diff --git a/embassy-rp/src/adc.rs b/embassy-rp/src/adc.rs
index 21360bf66..4c01fe195 100644
--- a/embassy-rp/src/adc.rs
+++ b/embassy-rp/src/adc.rs
@@ -19,14 +19,9 @@ static WAKER: AtomicWaker = AtomicWaker::new();
 
 /// ADC config.
 #[non_exhaustive]
+#[derive(Default)]
 pub struct Config {}
 
-impl Default for Config {
-    fn default() -> Self {
-        Self {}
-    }
-}
-
 enum Source<'p> {
     Pin(PeripheralRef<'p, AnyPin>),
     TempSensor(PeripheralRef<'p, ADC_TEMP_SENSOR>),
@@ -175,7 +170,7 @@ impl<'d, M: Mode> Adc<'d, M> {
         while !r.cs().read().ready() {}
         match r.cs().read().err() {
             true => Err(Error::ConversionFailed),
-            false => Ok(r.result().read().result().into()),
+            false => Ok(r.result().read().result()),
         }
     }
 }
@@ -221,7 +216,7 @@ impl<'d> Adc<'d, Async> {
         Self::wait_for_ready().await;
         match r.cs().read().err() {
             true => Err(Error::ConversionFailed),
-            false => Ok(r.result().read().result().into()),
+            false => Ok(r.result().read().result()),
         }
     }
 
diff --git a/embassy-rp/src/clocks.rs b/embassy-rp/src/clocks.rs
index 19232b801..b02f3796f 100644
--- a/embassy-rp/src/clocks.rs
+++ b/embassy-rp/src/clocks.rs
@@ -1,5 +1,4 @@
 //! Clock configuration for the RP2040
-use core::arch::asm;
 use core::marker::PhantomData;
 use core::sync::atomic::{AtomicU16, AtomicU32, Ordering};
 
@@ -8,7 +7,6 @@ use pac::clocks::vals::*;
 
 use crate::gpio::sealed::Pin;
 use crate::gpio::AnyPin;
-use crate::pac::common::{Reg, RW};
 use crate::{pac, reset, Peripheral};
 
 // NOTE: all gpin handling is commented out for future reference.
@@ -737,7 +735,7 @@ fn configure_pll(p: pac::pll::Pll, input_freq: u32, config: PllConfig) -> u32 {
     assert!(config.refdiv >= 1 && config.refdiv <= 63);
     assert!(ref_freq >= 5_000_000 && ref_freq <= 800_000_000);
     let vco_freq = ref_freq.saturating_mul(config.fbdiv as u32);
-    assert!(vco_freq >= 750_000_000 && vco_freq <= 1800_000_000);
+    assert!(vco_freq >= 750_000_000 && vco_freq <= 1_800_000_000);
 
     // Load VCO-related dividers before starting VCO
     p.cs().write(|w| w.set_refdiv(config.refdiv as _));
diff --git a/embassy-rp/src/flash.rs b/embassy-rp/src/flash.rs
index 2d673cf6c..8bac93684 100644
--- a/embassy-rp/src/flash.rs
+++ b/embassy-rp/src/flash.rs
@@ -326,9 +326,9 @@ impl<'d, T: Instance, const FLASH_SIZE: usize> Flash<'d, T, Async, FLASH_SIZE> {
         // If the destination address is already aligned, then we can just DMA directly
         if (bytes.as_ptr() as u32) % 4 == 0 {
             // Safety: alignment and size have been checked for compatibility
-            let mut buf: &mut [u32] =
+            let buf: &mut [u32] =
                 unsafe { core::slice::from_raw_parts_mut(bytes.as_mut_ptr() as *mut u32, bytes.len() / 4) };
-            self.background_read(offset, &mut buf)?.await;
+            self.background_read(offset, buf)?.await;
             return Ok(());
         }
 
diff --git a/embassy-rp/src/gpio.rs b/embassy-rp/src/gpio.rs
index 62eeb4cf6..405bddfd8 100644
--- a/embassy-rp/src/gpio.rs
+++ b/embassy-rp/src/gpio.rs
@@ -225,8 +225,8 @@ fn irq_handler<const N: usize>(bank: pac::io::Io, wakers: &[AtomicWaker; N]) {
         // The status register is divided into groups of four, one group for
         // each pin. Each group consists of four trigger levels LEVEL_LOW,
         // LEVEL_HIGH, EDGE_LOW, and EDGE_HIGH for each pin.
-        let pin_group = (pin % 8) as usize;
-        let event = (intsx.read().0 >> pin_group * 4) & 0xf as u32;
+        let pin_group = pin % 8;
+        let event = (intsx.read().0 >> (pin_group * 4)) & 0xf;
 
         // no more than one event can be awaited per pin at any given time, so
         // we can just clear all interrupt enables for that pin without having
@@ -238,7 +238,7 @@ fn irq_handler<const N: usize>(bank: pac::io::Io, wakers: &[AtomicWaker; N]) {
                 w.set_level_high(pin_group, true);
                 w.set_level_low(pin_group, true);
             });
-            wakers[pin as usize].wake();
+            wakers[pin].wake();
         }
     }
 }
diff --git a/embassy-rp/src/i2c.rs b/embassy-rp/src/i2c.rs
index ac0eac96d..26a819b25 100644
--- a/embassy-rp/src/i2c.rs
+++ b/embassy-rp/src/i2c.rs
@@ -352,7 +352,7 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
     }
 }
 
-pub(crate) fn set_up_i2c_pin<'d, P, T>(pin: &P)
+pub(crate) fn set_up_i2c_pin<P, T>(pin: &P)
 where
     P: core::ops::Deref<Target = T>,
     T: crate::gpio::Pin,
@@ -749,7 +749,7 @@ where
 
         let addr: u16 = address.into();
 
-        if operations.len() > 0 {
+        if !operations.is_empty() {
             Self::setup(addr)?;
         }
         let mut iterator = operations.iter_mut();
@@ -762,7 +762,7 @@ where
                     self.read_async_internal(buffer, false, last).await?;
                 }
                 Operation::Write(buffer) => {
-                    self.write_async_internal(buffer.into_iter().cloned(), last).await?;
+                    self.write_async_internal(buffer.iter().cloned(), last).await?;
                 }
             }
         }
diff --git a/embassy-rp/src/i2c_slave.rs b/embassy-rp/src/i2c_slave.rs
index 97ca17295..e2d4fbac0 100644
--- a/embassy-rp/src/i2c_slave.rs
+++ b/embassy-rp/src/i2c_slave.rs
@@ -289,7 +289,7 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
     pub async fn respond_to_read(&mut self, buffer: &[u8]) -> Result<ReadStatus, Error> {
         let p = T::regs();
 
-        if buffer.len() == 0 {
+        if buffer.is_empty() {
             return Err(Error::InvalidResponseBufferLength);
         }
 
@@ -318,15 +318,13 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
                     }
 
                     Poll::Pending
+                } else if stat.rx_done() {
+                    p.ic_clr_rx_done().read();
+                    Poll::Ready(Ok(ReadStatus::Done))
+                } else if stat.rd_req() && stat.tx_empty() {
+                    Poll::Ready(Ok(ReadStatus::NeedMoreBytes))
                 } else {
-                    if stat.rx_done() {
-                        p.ic_clr_rx_done().read();
-                        Poll::Ready(Ok(ReadStatus::Done))
-                    } else if stat.rd_req() && stat.tx_empty() {
-                        Poll::Ready(Ok(ReadStatus::NeedMoreBytes))
-                    } else {
-                        Poll::Pending
-                    }
+                    Poll::Pending
                 }
             },
             |_me| {
diff --git a/embassy-rp/src/lib.rs b/embassy-rp/src/lib.rs
index 46973fdc8..7092b3fab 100644
--- a/embassy-rp/src/lib.rs
+++ b/embassy-rp/src/lib.rs
@@ -238,8 +238,8 @@ select_bootloader! {
 }
 
 /// Installs a stack guard for the CORE0 stack in MPU region 0.
-/// Will fail if the MPU is already confgigured. This function requires
-/// a `_stack_end` symbol to be defined by the linker script, and expexcts
+/// Will fail if the MPU is already configured. This function requires
+/// a `_stack_end` symbol to be defined by the linker script, and expects
 /// `_stack_end` to be located at the lowest address (largest depth) of
 /// the stack.
 ///
diff --git a/embassy-rp/src/multicore.rs b/embassy-rp/src/multicore.rs
index 252f30dc1..d9d65694a 100644
--- a/embassy-rp/src/multicore.rs
+++ b/embassy-rp/src/multicore.rs
@@ -59,7 +59,7 @@ static IS_CORE1_INIT: AtomicBool = AtomicBool::new(false);
 
 #[inline(always)]
 fn core1_setup(stack_bottom: *mut usize) {
-    if let Err(_) = install_stack_guard(stack_bottom) {
+    if install_stack_guard(stack_bottom).is_err() {
         // currently only happens if the MPU was already set up, which
         // would indicate that the core is already in use from outside
         // embassy, somehow. trap if so since we can't deal with that.
diff --git a/embassy-rp/src/pio/mod.rs b/embassy-rp/src/pio/mod.rs
index ca9795024..804a7636d 100644
--- a/embassy-rp/src/pio/mod.rs
+++ b/embassy-rp/src/pio/mod.rs
@@ -268,7 +268,7 @@ impl<'l, PIO: Instance> Pin<'l, PIO> {
     }
 
     /// Set the pin's input sync bypass.
-    pub fn set_input_sync_bypass<'a>(&mut self, bypass: bool) {
+    pub fn set_input_sync_bypass(&mut self, bypass: bool) {
         let mask = 1 << self.pin();
         if bypass {
             PIO::PIO.input_sync_bypass().write_set(|w| *w = mask);
@@ -463,7 +463,7 @@ impl<'d, PIO: Instance, const SM: usize> Drop for StateMachine<'d, PIO, SM> {
     }
 }
 
-fn assert_consecutive<'d, PIO: Instance>(pins: &[&Pin<'d, PIO>]) {
+fn assert_consecutive<PIO: Instance>(pins: &[&Pin<PIO>]) {
     for (p1, p2) in pins.iter().zip(pins.iter().skip(1)) {
         // purposely does not allow wrap-around because we can't claim pins 30 and 31.
         assert!(p1.pin() + 1 == p2.pin(), "pins must be consecutive");
@@ -749,7 +749,7 @@ impl<'d, PIO: Instance + 'd, const SM: usize> StateMachine<'d, PIO, SM> {
                     w.set_set_count(1);
                 });
                 // SET PINDIRS, (dir)
-                unsafe { sm.exec_instr(0b111_00000_100_00000 | dir as u16) };
+                unsafe { sm.exec_instr(0b1110_0000_1000_0000 | dir as u16) };
             }
         });
     }
@@ -764,7 +764,7 @@ impl<'d, PIO: Instance + 'd, const SM: usize> StateMachine<'d, PIO, SM> {
                     w.set_set_count(1);
                 });
                 // SET PINS, (dir)
-                unsafe { sm.exec_instr(0b111_00000_000_00000 | level as u16) };
+                unsafe { sm.exec_instr(0b1110_0000_0000_0000 | level as u16) };
             }
         });
     }
@@ -867,9 +867,7 @@ impl<'d, PIO: Instance> Common<'d, PIO> {
         prog: &Program<SIZE>,
     ) -> Result<LoadedProgram<'d, PIO>, LoadError> {
         match prog.origin {
-            Some(origin) => self
-                .try_load_program_at(prog, origin)
-                .map_err(|a| LoadError::AddressInUse(a)),
+            Some(origin) => self.try_load_program_at(prog, origin).map_err(LoadError::AddressInUse),
             None => {
                 // naively search for free space, allowing wraparound since
                 // PIO does support that. with only 32 instruction slots it
diff --git a/embassy-rp/src/pwm.rs b/embassy-rp/src/pwm.rs
index 784a05f92..e6f3b2aa2 100644
--- a/embassy-rp/src/pwm.rs
+++ b/embassy-rp/src/pwm.rs
@@ -114,8 +114,8 @@ impl<'d, T: Channel> Pwm<'d, T> {
         }
         Self {
             inner,
-            pin_a: a.into(),
-            pin_b: b.into(),
+            pin_a: a,
+            pin_b: b,
         }
     }
 
@@ -190,7 +190,7 @@ impl<'d, T: Channel> Pwm<'d, T> {
     }
 
     fn configure(p: pac::pwm::Channel, config: &Config) {
-        if config.divider > FixedU16::<fixed::types::extra::U4>::from_bits(0xFF_F) {
+        if config.divider > FixedU16::<fixed::types::extra::U4>::from_bits(0xFFF) {
             panic!("Requested divider is too large");
         }
 
diff --git a/embassy-rp/src/relocate.rs b/embassy-rp/src/relocate.rs
index b35b4ed72..40cb2667b 100644
--- a/embassy-rp/src/relocate.rs
+++ b/embassy-rp/src/relocate.rs
@@ -22,15 +22,15 @@ where
 {
     type Item = u16;
     fn next(&mut self) -> Option<Self::Item> {
-        self.iter.next().and_then(|&instr| {
-            Some(if instr & 0b1110_0000_0000_0000 == 0 {
+        self.iter.next().map(|&instr| {
+            if instr & 0b1110_0000_0000_0000 == 0 {
                 // this is a JMP instruction -> add offset to address
                 let address = (instr & 0b1_1111) as u8;
                 let address = address.wrapping_add(self.offset) % 32;
                 instr & (!0b11111) | address as u16
             } else {
                 instr
-            })
+            }
         })
     }
 }
diff --git a/embassy-rp/src/rtc/mod.rs b/embassy-rp/src/rtc/mod.rs
index b696989f5..c8691bdc2 100644
--- a/embassy-rp/src/rtc/mod.rs
+++ b/embassy-rp/src/rtc/mod.rs
@@ -29,8 +29,7 @@ impl<'d, T: Instance> Rtc<'d, T> {
         // Set the RTC divider
         inner.regs().clkdiv_m1().write(|w| w.set_clkdiv_m1(clk_rtc_freq() - 1));
 
-        let result = Self { inner };
-        result
+        Self { inner }
     }
 
     /// Enable or disable the leap year check. The rp2040 chip will always add a Feb 29th on every year that is divisable by 4, but this may be incorrect (e.g. on century years). This function allows you to disable this check.
diff --git a/embassy-rp/src/uart/buffered.rs b/embassy-rp/src/uart/buffered.rs
index 99c958129..7622539f1 100644
--- a/embassy-rp/src/uart/buffered.rs
+++ b/embassy-rp/src/uart/buffered.rs
@@ -467,7 +467,7 @@ impl<'d, T: Instance> Drop for BufferedUartRx<'d, T> {
 
         // TX is inactive if the the buffer is not available.
         // We can now unregister the interrupt handler
-        if state.tx_buf.len() == 0 {
+        if state.tx_buf.is_empty() {
             T::Interrupt::disable();
         }
     }
@@ -480,7 +480,7 @@ impl<'d, T: Instance> Drop for BufferedUartTx<'d, T> {
 
         // RX is inactive if the the buffer is not available.
         // We can now unregister the interrupt handler
-        if state.rx_buf.len() == 0 {
+        if state.rx_buf.is_empty() {
             T::Interrupt::disable();
         }
     }
diff --git a/embassy-rp/src/uart/mod.rs b/embassy-rp/src/uart/mod.rs
index f372cb640..65dcf4eb4 100644
--- a/embassy-rp/src/uart/mod.rs
+++ b/embassy-rp/src/uart/mod.rs
@@ -322,7 +322,7 @@ impl<'d, T: Instance, M: Mode> UartRx<'d, T, M> {
 
 impl<'d, T: Instance, M: Mode> Drop for UartRx<'d, T, M> {
     fn drop(&mut self) {
-        if let Some(_) = self.rx_dma {
+        if self.rx_dma.is_some() {
             T::Interrupt::disable();
             // clear dma flags. irq handlers use these to disambiguate among themselves.
             T::regs().uartdmacr().write_clear(|reg| {