229 files changed, 9774 insertions, 5762 deletions

diff --git a/.vscode/settings.json b/.vscode/settings.json
index c504f3ccd..73dfa53a4 100644
--- a/.vscode/settings.json
+++ b/.vscode/settings.json
@@ -5,6 +5,9 @@
   "[markdown]": {
     "editor.formatOnSave": false
   },
+  "rust-analyzer.rustfmt.extraArgs": [
+    "+nightly"
+  ],
   "rust-analyzer.check.allTargets": false,
   "rust-analyzer.check.noDefaultFeatures": true,
   "rust-analyzer.cargo.noDefaultFeatures": true,
@@ -61,4 +64,4 @@
     // "examples/stm32wl/Cargo.toml",
     // "examples/wasm/Cargo.toml",
   ],
-}
+}
\ No newline at end of file
diff --git a/ci.sh b/ci.sh
index 6cc2a031d..b4ed0dc18 100755
--- a/ci.sh
+++ b/ci.sh
@@ -35,7 +35,7 @@ rm -rf out/tests/nrf5340-dk
 # disabled because these boards are not on the shelf
 rm -rf out/tests/mspm0g3507
 
-rm out/tests/stm32wb55rg/wpan_mac
+# rm out/tests/stm32wb55rg/wpan_mac
 rm out/tests/stm32wb55rg/wpan_ble
 
 # unstable, I think it's running out of RAM?
diff --git a/docs/examples/layer-by-layer/blinky-async/src/main.rs b/docs/examples/layer-by-layer/blinky-async/src/main.rs
index 004602816..007f7da46 100644
--- a/docs/examples/layer-by-layer/blinky-async/src/main.rs
+++ b/docs/examples/layer-by-layer/blinky-async/src/main.rs
@@ -2,15 +2,21 @@
 #![no_main]
 
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::gpio::{Level, Output, Pull, Speed};
+use embassy_stm32::{bind_interrupts, interrupt};
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI15_10  => exti::InterruptHandler<interrupt::typelevel::EXTI15_10 >;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     let mut led = Output::new(p.PB14, Level::Low, Speed::VeryHigh);
-    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up);
+    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up, Irqs);
 
     loop {
         button.wait_for_any_edge().await;
diff --git a/docs/pages/bootloader.adoc b/docs/pages/bootloader.adoc
index b0f0331aa..c010b0622 100644
--- a/docs/pages/bootloader.adoc
+++ b/docs/pages/bootloader.adoc
@@ -43,14 +43,14 @@ Partition Size~dfu~= Partition Size~active~+ Page Size~active~
 +
 All values are specified in bytes.
 
-* BOOTLOADER STATE - Where the bootloader stores the current state describing if the active and dfu partitions need to be swapped. When the new firmware has been written to the DFU partition, a magic field is written to instruct the bootloader that the partitions should be swapped. This partition must be able to store a magic field as well as the partition swap progress. The partition size given by:
+* BOOTLOADER STATE - Where the bootloader stores the current state describing if the active and dfu partitions need to be swapped. When the new firmware has been written to the DFU partition, a magic field is written to instruct the bootloader that the partitions should be swapped. This partition must be able to store a magic field as well as the partition swap progress. The partition size is given by:
 +
-Partition Size~state~ = Write Size~state~ + (2 × Partition Size~active~ / Page Size~active~)
+Partition Size~state~ = (2 × Write Size~state~) + (4 × Write Size~state~ × Partition Size~active~ / Page Size~active~)
 +
 All values are specified in bytes.
 
 The partitions for ACTIVE (+BOOTLOADER), DFU and BOOTLOADER_STATE may be placed in separate flash. The page size used by the bootloader is determined by the lowest common multiple of the ACTIVE and DFU page sizes.
-The BOOTLOADER_STATE partition must be big enough to store one word per page in the ACTIVE and DFU partitions combined.
+The BOOTLOADER_STATE partition must be big enough to store two words, plus four words per page in the ACTIVE partition.
 
 The bootloader has a platform-agnostic part, which implements the power fail safe swapping algorithm given the boundaries set by the partitions. The platform-specific part is a minimal shim that provides additional functionality such as watchdogs or supporting the nRF52 softdevice.
 
diff --git a/docs/pages/faq.adoc b/docs/pages/faq.adoc
index 8098e12ac..e59ef7b46 100644
--- a/docs/pages/faq.adoc
+++ b/docs/pages/faq.adoc
@@ -171,7 +171,11 @@ Note that the git revision should match any other embassy patches or git depende
 
 == Can I use manual ISRs alongside Embassy?
 
-Yes! This can be useful if you need to respond to an event as fast as possible, and the latency caused by the usual “ISR, wake, return from ISR, context switch to woken task” flow is too much for your application. Simply define a `#[interrupt] fn INTERRUPT_NAME() {}` handler as you would link:https://docs.rust-embedded.org/book/start/interrupts.html[in any other embedded rust project].
+Yes! This can be useful if you need to respond to an event as fast as possible, and the latency caused by the usual “ISR, wake, return from ISR, context switch to woken task” flow is too much for your application. 
+
+You may simply define a `#[interrupt] fn INTERRUPT_NAME() {}` handler as you would link:https://docs.rust-embedded.org/book/start/interrupts.html[in any other embedded rust project].
+
+Or you may define a struct implementing the `embassy-[family]::interrupt::typelevel::Handler` trait with an on_interrupt() method, and bind it to the interrupt vector via the `bind_interrupts!` macro, which introduces only a single indirection. This allows the mixing of manual ISRs with Embassy driver-defined ISRs; handlers will be called directly in the order they appear in the macro.
 
 == How can I measure resource usage (CPU, RAM, etc.)?
 
diff --git a/docs/pages/layer_by_layer.adoc b/docs/pages/layer_by_layer.adoc
index 0692ee4fa..f554e642a 100644
--- a/docs/pages/layer_by_layer.adoc
+++ b/docs/pages/layer_by_layer.adoc
@@ -76,7 +76,7 @@ The async version looks very similar to the HAL version, apart from a few minor
 * The peripheral initialization is done by the main macro, and is handed to the main task.
 * Before checking the button state, the application is awaiting a transition in the pin state (low -> high or high -> low).
 
-When `button.wait_for_any_edge().await` is called, the executor will pause the main task and put the microcontroller in sleep mode, unless there are other tasks that can run. Internally, the Embassy HAL has configured the interrupt handler for the button (in `ExtiInput`), so that whenever an interrupt is raised, the task awaiting the button will be woken up.
+When `button.wait_for_any_edge().await` is called, the executor will pause the main task and put the microcontroller in sleep mode, unless there are other tasks that can run. On this chip, interrupt signals on EXTI lines 10-15 (including the button on EXTI line 13) raise the hardware interrupt EXTI15_10. This interrupt handler has been bound (using `bind_interrupts!`) to call the `InterruptHandler` provided by the exti module, so that whenever an interrupt is raised, the task awaiting the button via `wait_for_any_edge()` will be woken up.
 
 The minimal overhead of the executor and the ability to run multiple tasks "concurrently" combined with the enormous simplification of the application, makes `async` a great fit for embedded.
 
diff --git a/embassy-boot/CHANGELOG.md b/embassy-boot/CHANGELOG.md
index 8d6395357..1d41043cb 100644
--- a/embassy-boot/CHANGELOG.md
+++ b/embassy-boot/CHANGELOG.md
@@ -8,6 +8,9 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 <!-- next-header -->
 ## Unreleased - ReleaseDate
 
+- Fixed documentation and assertion of STATE partition size requirements
+- Added documentation for package features
+
 ## 0.6.1 - 2025-08-26
 
 - First release with changelog.
diff --git a/embassy-boot/Cargo.toml b/embassy-boot/Cargo.toml
index 8c5c1f633..754c6e5f1 100644
--- a/embassy-boot/Cargo.toml
+++ b/embassy-boot/Cargo.toml
@@ -26,6 +26,7 @@ features = ["defmt"]
 [dependencies]
 defmt = { version = "1.0.1", optional = true }
 digest = "0.10"
+document-features = "0.2.7"
 log = { version = "0.4", optional = true }
 ed25519-dalek = { version = "2", default-features = false, features = ["digest"], optional = true }
 embassy-embedded-hal = { version = "0.5.0", path = "../embassy-embedded-hal" }
@@ -45,11 +46,22 @@ critical-section = { version = "1.1.1", features = ["std"] }
 ed25519-dalek = { version = "2", default-features = false, features = ["std", "rand_core", "digest"]  }
 
 [features]
+## Use [`defmt`](https://docs.rs/defmt/latest/defmt/) for logging
 defmt = ["dep:defmt"]
+## Use log for logging
 log = ["dep:log"]
+
+## Enable for devices that set erased flash bytes to `0x00` instead of the usual `0xFF`
+flash-erase-zero = []
+
+#! ## Firmware Signing
+#! Enable one of these features to allow verification of DFU signatures with
+#! `FirmwareUpdater::verify_and_mark_updated`.
+
+## Use the `ed25519-dalek` package to verify DFU signatures.
 ed25519-dalek = ["dep:ed25519-dalek", "_verify"]
+## Use the `salty` package to verify DFU signatures.
 ed25519-salty = ["dep:salty", "_verify"]
-flash-erase-zero = []
 
 #Internal features
 _verify = []
diff --git a/embassy-boot/src/boot_loader.rs b/embassy-boot/src/boot_loader.rs
index c38940d6e..a3a307051 100644
--- a/embassy-boot/src/boot_loader.rs
+++ b/embassy-boot/src/boot_loader.rs
@@ -135,10 +135,12 @@ pub struct BootLoader<ACTIVE: NorFlash, DFU: NorFlash, STATE: NorFlash> {
     dfu: DFU,
     /// The state partition has the following format:
     /// All ranges are in multiples of WRITE_SIZE bytes.
-    /// | Range    | Description                                                                      |
-    /// | 0..1     | Magic indicating bootloader state. BOOT_MAGIC means boot, SWAP_MAGIC means swap. |
-    /// | 1..2     | Progress validity. ERASE_VALUE means valid, !ERASE_VALUE means invalid.          |
-    /// | 2..2 + N | Progress index used while swapping or reverting      
+    /// N = Active partition size divided by WRITE_SIZE.
+    /// | Range              | Description                                                                      |
+    /// | 0..1               | Magic indicating bootloader state. BOOT_MAGIC means boot, SWAP_MAGIC means swap. |
+    /// | 1..2               | Progress validity. ERASE_VALUE means valid, !ERASE_VALUE means invalid.          |
+    /// | 2..(2 + 2N)        | Progress index used while swapping                                               |
+    /// | (2 + 2N)..(2 + 4N) | Progress index used while reverting
     state: STATE,
 }
 
@@ -429,7 +431,7 @@ fn assert_partitions<ACTIVE: NorFlash, DFU: NorFlash, STATE: NorFlash>(
     assert_eq!(dfu.capacity() as u32 % page_size, 0);
     // DFU partition has to be bigger than ACTIVE partition to handle swap algorithm
     assert!(dfu.capacity() as u32 - active.capacity() as u32 >= page_size);
-    assert!(2 + 2 * (active.capacity() as u32 / page_size) <= state.capacity() as u32 / STATE::WRITE_SIZE as u32);
+    assert!(2 + 4 * (active.capacity() as u32 / page_size) <= state.capacity() as u32 / STATE::WRITE_SIZE as u32);
 }
 
 #[cfg(test)]
diff --git a/embassy-boot/src/lib.rs b/embassy-boot/src/lib.rs
index 7dc811f66..3e61d6036 100644
--- a/embassy-boot/src/lib.rs
+++ b/embassy-boot/src/lib.rs
@@ -3,6 +3,10 @@
 #![allow(unsafe_op_in_unsafe_fn)]
 #![warn(missing_docs)]
 #![doc = include_str!("../README.md")]
+
+//! ## Feature flags
+#![doc = document_features::document_features!(feature_label = r#"<span class="stab portability"><code>{feature}</code></span>"#)]
+
 mod fmt;
 
 mod boot_loader;
diff --git a/embassy-mspm0/CHANGELOG.md b/embassy-mspm0/CHANGELOG.md
index f0b5868f4..6972a8472 100644
--- a/embassy-mspm0/CHANGELOG.md
+++ b/embassy-mspm0/CHANGELOG.md
@@ -19,3 +19,4 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - feat: Add i2c target implementation (#4605)
 - fix: group irq handlers must check for NO_INTR (#4785)
 - feat: Add read_reset_cause function
+- feat: Add module Mathacl & example for mspm0g3507 (#4897)
\ No newline at end of file
diff --git a/embassy-mspm0/Cargo.toml b/embassy-mspm0/Cargo.toml
index b76bc7e41..254e0209b 100644
--- a/embassy-mspm0/Cargo.toml
+++ b/embassy-mspm0/Cargo.toml
@@ -70,9 +70,10 @@ log = { version = "0.4.14", optional = true }
 cortex-m-rt = ">=0.6.15,<0.8"
 cortex-m = "0.7.6"
 critical-section = "1.2.0"
+micromath = "2.0.0"
 
 # mspm0-metapac = { version = "" }
-mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-8542f260cc89645a983b7f1a874c87b21822279e" }
+mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-f21b04e9de074af4965bf67ec3646cb9fe1b9852" }
 
 [build-dependencies]
 proc-macro2 = "1.0.94"
@@ -80,7 +81,7 @@ quote = "1.0.40"
 cfg_aliases = "0.2.1"
 
 # mspm0-metapac = { version = "", default-features = false, features = ["metadata"] }
-mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-8542f260cc89645a983b7f1a874c87b21822279e", default-features = false, features = ["metadata"] }
+mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-f21b04e9de074af4965bf67ec3646cb9fe1b9852", default-features = false, features = ["metadata"] }
 
 [features]
 default = ["rt"]
diff --git a/embassy-mspm0/build.rs b/embassy-mspm0/build.rs
index 4942364aa..0fe056c4e 100644
--- a/embassy-mspm0/build.rs
+++ b/embassy-mspm0/build.rs
@@ -591,6 +591,7 @@ fn generate_peripheral_instances() -> TokenStream {
             "i2c" => Some(quote! { impl_i2c_instance!(#peri, #fifo_size); }),
             "wwdt" => Some(quote! { impl_wwdt_instance!(#peri); }),
             "adc" => Some(quote! { impl_adc_instance!(#peri); }),
+            "mathacl" => Some(quote! { impl_mathacl_instance!(#peri); }),
             _ => None,
         };
 
diff --git a/embassy-mspm0/src/lib.rs b/embassy-mspm0/src/lib.rs
index 9f3e4d5e8..c43c81853 100644
--- a/embassy-mspm0/src/lib.rs
+++ b/embassy-mspm0/src/lib.rs
@@ -19,6 +19,8 @@ pub mod dma;
 pub mod gpio;
 pub mod i2c;
 pub mod i2c_target;
+#[cfg(any(mspm0g150x, mspm0g151x, mspm0g350x, mspm0g351x))]
+pub mod mathacl;
 pub mod timer;
 pub mod uart;
 pub mod wwdt;
diff --git a/embassy-mspm0/src/mathacl.rs b/embassy-mspm0/src/mathacl.rs
new file mode 100644
index 000000000..e29f4a59e
--- /dev/null
+++ b/embassy-mspm0/src/mathacl.rs
@@ -0,0 +1,255 @@
+//! MATHACL
+//!
+//! This HAL implements mathematical calculations performed by the CPU.
+
+#![macro_use]
+
+use core::f32::consts::PI;
+use core::marker::PhantomData;
+
+use embassy_hal_internal::PeripheralType;
+use micromath::F32Ext;
+
+use crate::Peri;
+use crate::pac::mathacl::{Mathacl as Regs, vals};
+
+pub enum Precision {
+    High = 31,
+    Medium = 15,
+    Low = 1,
+}
+
+/// Serial error
+#[derive(Debug, Eq, PartialEq, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[non_exhaustive]
+pub enum Error {
+    ValueInWrongRange,
+    NBitsTooBig,
+}
+
+pub struct Mathacl<'d> {
+    regs: &'static Regs,
+    _phantom: PhantomData<&'d mut ()>,
+}
+
+impl<'d> Mathacl<'d> {
+    /// Mathacl initialization.
+    pub fn new<T: Instance>(_instance: Peri<'d, T>) -> Self {
+        // Init power
+        T::regs().gprcm(0).rstctl().write(|w| {
+            w.set_resetstkyclr(vals::Resetstkyclr::CLR);
+            w.set_resetassert(vals::Resetassert::ASSERT);
+            w.set_key(vals::ResetKey::KEY);
+        });
+
+        // Enable power
+        T::regs().gprcm(0).pwren().write(|w| {
+            w.set_enable(true);
+            w.set_key(vals::PwrenKey::KEY);
+        });
+
+        // init delay, 16 cycles
+        cortex_m::asm::delay(16);
+
+        Self {
+            regs: T::regs(),
+            _phantom: PhantomData,
+        }
+    }
+
+    /// Internal helper SINCOS function.
+    fn sincos(&mut self, rad: f32, precision: Precision, sin: bool) -> Result<f32, Error> {
+        self.regs.ctl().write(|w| {
+            w.set_func(vals::Func::SINCOS);
+            w.set_numiter(precision as u8);
+        });
+
+        if rad > PI || rad < -PI {
+            return Err(Error::ValueInWrongRange);
+        }
+
+        // TODO: make f32 division on CPU
+        let native = rad / PI;
+
+        match signed_f32_to_register(native, 0) {
+            Ok(val) => self.regs.op1().write(|w| {
+                w.set_data(val);
+            }),
+            Err(er) => return Err(er),
+        };
+
+        // check if done
+        while self.regs.status().read().busy() == vals::Busy::NOTDONE {}
+
+        match sin {
+            true => register_to_signed_f32(self.regs.res2().read().data(), 0),
+            false => register_to_signed_f32(self.regs.res1().read().data(), 0),
+        }
+    }
+
+    /// Calsulates trigonometric sine operation in the range [-1,1) with a give precision.
+    pub fn sin(&mut self, rad: f32, precision: Precision) -> Result<f32, Error> {
+        self.sincos(rad, precision, true)
+    }
+
+    /// Calsulates trigonometric cosine operation in the range [-1,1) with a give precision.
+    pub fn cos(&mut self, rad: f32, precision: Precision) -> Result<f32, Error> {
+        self.sincos(rad, precision, false)
+    }
+}
+
+pub(crate) trait SealedInstance {
+    fn regs() -> &'static Regs;
+}
+
+/// Mathacl instance trait
+#[allow(private_bounds)]
+pub trait Instance: SealedInstance + PeripheralType {}
+
+macro_rules! impl_mathacl_instance {
+    ($instance: ident) => {
+        impl crate::mathacl::SealedInstance for crate::peripherals::$instance {
+            fn regs() -> &'static crate::pac::mathacl::Mathacl {
+                &crate::pac::$instance
+            }
+        }
+
+        impl crate::mathacl::Instance for crate::peripherals::$instance {}
+    };
+}
+
+/// Convert f32 data to understandable by M0 format.
+fn signed_f32_to_register(data: f32, n_bits: u8) -> Result<u32, Error> {
+    let mut res: u32 = 0;
+    // check if negative
+    let negative = data < 0.0;
+
+    // absolute value for extraction
+    let abs = data.abs();
+
+    // total integer bit count
+    let total_bits = 31;
+
+    // Validate n_bits
+    if n_bits > 31 {
+        return Err(Error::NBitsTooBig);
+    }
+
+    // number of fractional bits
+    let shift = total_bits - n_bits;
+
+    // Compute masks
+    let (n_mask, m_mask) = if n_bits == 0 {
+        (0, 0x7FFFFFFF)
+    } else if n_bits == 31 {
+        (0x7FFFFFFF, 0)
+    } else {
+        ((1u32 << n_bits) - 1, (1u32 << shift) - 1)
+    };
+
+    // calc. integer(n) & fractional(m) parts
+    let n = abs.floor() as u32;
+    let mut m = ((abs - abs.floor()) * (1u32 << shift) as f32).round() as u32;
+
+    // Handle trimming integer part
+    if n_bits == 0 && n > 0 {
+        m = 0x7FFFFFFF;
+    }
+
+    // calculate result
+    if n_bits > 0 {
+        res = n << shift & n_mask;
+    }
+    if shift > 0 {
+        res = res | m & m_mask;
+    }
+
+    // if negative, do 2’s compliment
+    if negative {
+        res = !res + 1;
+    }
+    Ok(res)
+}
+
+/// Reversely converts M0-register format to native f32.
+fn register_to_signed_f32(data: u32, n_bits: u8) -> Result<f32, Error> {
+    // Validate n_bits
+    if n_bits > 31 {
+        return Err(Error::NBitsTooBig);
+    }
+
+    // total integer bit count
+    let total_bits = 31;
+
+    let negative = (data >> 31) == 1;
+
+    // number of fractional bits
+    let shift = total_bits - n_bits;
+
+    // Compute masks
+    let (n_mask, m_mask) = if n_bits == 0 {
+        (0, 0x7FFFFFFF)
+    } else if n_bits == 31 {
+        (0x7FFFFFFF, 0)
+    } else {
+        ((1u32 << n_bits) - 1, (1u32 << shift) - 1)
+    };
+
+    // Compute n and m
+    let mut n = if n_bits == 0 {
+        0
+    } else if shift >= 32 {
+        data & n_mask
+    } else {
+        (data >> shift) & n_mask
+    };
+    let mut m = data & m_mask;
+
+    // if negative, do 2’s compliment
+    if negative {
+        n = !n & n_mask;
+        m = (!m & m_mask) + 1;
+    }
+
+    let mut value = (n as f32) + (m as f32) / (1u32 << shift) as f32;
+    if negative {
+        value = -value;
+    }
+    return Ok(value);
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn mathacl_convert_func_errors() {
+        assert_eq!(signed_f32_to_register(0.0, 32), Err(Error::NBitsTooBig));
+        assert_eq!(register_to_signed_f32(0, 32), Err(Error::NBitsTooBig));
+    }
+
+    #[test]
+    fn mathacl_signed_f32_to_register() {
+        let mut test_float = 1.0;
+        assert_eq!(signed_f32_to_register(test_float, 0).unwrap(), 0x7FFFFFFF);
+
+        test_float = 0.0;
+        assert_eq!(signed_f32_to_register(test_float, 0).unwrap(), 0x0);
+
+        test_float = -1.0;
+        assert_eq!(signed_f32_to_register(test_float, 0).unwrap(), 0x80000001);
+    }
+
+    #[test]
+    fn mathacl_register_to_signed_f32() {
+        let mut test_u32: u32 = 0x7FFFFFFF;
+        assert_eq!(register_to_signed_f32(test_u32, 0u8).unwrap(), 1.0);
+
+        test_u32 = 0x0;
+        assert_eq!(register_to_signed_f32(test_u32, 0u8).unwrap(), 0.0);
+
+        test_u32 = 0x80000001;
+        assert_eq!(register_to_signed_f32(test_u32, 0u8).unwrap(), -1.0);
+    }
+}
diff --git a/embassy-nrf/CHANGELOG.md b/embassy-nrf/CHANGELOG.md
index 72ecb116a..cfb040ef5 100644
--- a/embassy-nrf/CHANGELOG.md
+++ b/embassy-nrf/CHANGELOG.md
@@ -23,6 +23,12 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - bugfix: Do not write to UICR from non-secure code on nrf53
 - bugfix: Add delay to uart init anomaly fix
 - changed: `BufferedUarte::read_ready` now uses the same definition for 'empty' so following read calls will not block when true is returned
+- added: add `gpiote::InputChannel::wait_for_high()` and `wait_for_low()` to wait for specific signal level
+- changed: `gpiote::InputChannel::wait()` now takes a mutable reference to `self` to avoid interference from concurrent calls
+- changed: `gpiote::InputChannel::wait()` now ensures events are seen as soon as the function is called, even if the future is not polled
+- bugfix: use correct flash size for nRF54l
+- changed: add workaround for anomaly 66 on nrf52
+- added: expose PPI events available on SPIS peripheral
 
 ## 0.8.0 - 2025-09-30
 
diff --git a/embassy-nrf/src/chips/nrf54l15_app.rs b/embassy-nrf/src/chips/nrf54l15_app.rs
index 0724f2ff6..8846717db 100644
--- a/embassy-nrf/src/chips/nrf54l15_app.rs
+++ b/embassy-nrf/src/chips/nrf54l15_app.rs
@@ -204,7 +204,7 @@ pub const FORCE_COPY_BUFFER_SIZE: usize = 1024;
 
 // 1.5 MB NVM
 #[allow(unused)]
-pub const FLASH_SIZE: usize = 1536 * 1024;
+pub const FLASH_SIZE: usize = 1524 * 1024;
 
 embassy_hal_internal::peripherals! {
     // PPI
diff --git a/embassy-nrf/src/gpiote.rs b/embassy-nrf/src/gpiote.rs
index 91944d8cd..d4f6668f3 100644
--- a/embassy-nrf/src/gpiote.rs
+++ b/embassy-nrf/src/gpiote.rs
@@ -349,16 +349,73 @@ impl<'d> InputChannel<'d> {
     }
 
     /// Asynchronously wait for an event in this channel.
-    pub async fn wait(&self) {
-        let g = self.ch.regs();
-        let num = self.ch.number();
-        let waker = self.ch.waker();
+    ///
+    /// It is possible to call this function and await the returned future later.
+    /// If an even occurs in the mean time, the future will immediately report ready.
+    pub fn wait(&mut self) -> impl Future<Output = ()> {
+        // NOTE: This is `-> impl Future` and not an `async fn` on purpose.
+        // Otherwise, events will only be detected starting at the first poll of the returned future.
+        Self::wait_internal(&mut self.ch)
+    }
+
+    /// Asynchronously wait for the pin to become high.
+    ///
+    /// The channel must be configured with [`InputChannelPolarity::LoToHi`] or [`InputChannelPolarity::Toggle`].
+    /// If the channel is not configured to detect rising edges, it is unspecified when the returned future completes.
+    ///
+    /// It is possible to call this function and await the returned future later.
+    /// If an even occurs in the mean time, the future will immediately report ready.
+    pub fn wait_for_high(&mut self) -> impl Future<Output = ()> {
+        // NOTE: This is `-> impl Future` and not an `async fn` on purpose.
+        // Otherwise, events will only be detected starting at the first poll of the returned future.
+
+        // Subscribe to the event before checking the pin level.
+        let wait = Self::wait_internal(&mut self.ch);
+        let pin = &self.pin;
+        async move {
+            if pin.is_high() {
+                return;
+            }
+            wait.await;
+        }
+    }
+
+    /// Asynchronously wait for the pin to become low.
+    ///
+    /// The channel must be configured with [`InputChannelPolarity::HiToLo`] or [`InputChannelPolarity::Toggle`].
+    /// If the channel is not configured to detect falling edges, it is unspecified when the returned future completes.
+    ///
+    /// It is possible to call this function and await the returned future later.
+    /// If an even occurs in the mean time, the future will immediately report ready.
+    pub fn wait_for_low(&mut self) -> impl Future<Output = ()> {
+        // NOTE: This is `-> impl Future` and not an `async fn` on purpose.
+        // Otherwise, events will only be detected starting at the first poll of the returned future.
+
+        // Subscribe to the event before checking the pin level.
+        let wait = Self::wait_internal(&mut self.ch);
+        let pin = &self.pin;
+        async move {
+            if pin.is_low() {
+                return;
+            }
+            wait.await;
+        }
+    }
+
+    /// Internal implementation for `wait()` and friends.
+    fn wait_internal(channel: &mut Peri<'_, AnyChannel>) -> impl Future<Output = ()> {
+        // NOTE: This is `-> impl Future` and not an `async fn` on purpose.
+        // Otherwise, events will only be detected starting at the first poll of the returned future.
+
+        let g = channel.regs();
+        let num = channel.number();
+        let waker = channel.waker();
 
         // Enable interrupt
         g.events_in(num).write_value(0);
         g.intenset(INTNUM).write(|w| w.0 = 1 << num);
 
-        poll_fn(|cx| {
+        poll_fn(move |cx| {
             CHANNEL_WAKERS[waker].register(cx.waker());
 
             if g.events_in(num).read() != 0 {
@@ -367,7 +424,6 @@ impl<'d> InputChannel<'d> {
                 Poll::Pending
             }
         })
-        .await;
     }
 
     /// Get the associated input pin.
diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index 2f5ad352f..28d2119ae 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -776,6 +776,30 @@ pub fn init(config: config::Config) -> Peripherals {
         }
     }
 
+    // Workaround for anomaly 66
+    #[cfg(feature = "_nrf52")]
+    {
+        let ficr = pac::FICR;
+        let temp = pac::TEMP;
+        temp.a(0).write_value(ficr.temp().a0().read().0);
+        temp.a(1).write_value(ficr.temp().a1().read().0);
+        temp.a(2).write_value(ficr.temp().a2().read().0);
+        temp.a(3).write_value(ficr.temp().a3().read().0);
+        temp.a(4).write_value(ficr.temp().a4().read().0);
+        temp.a(5).write_value(ficr.temp().a5().read().0);
+        temp.b(0).write_value(ficr.temp().b0().read().0);
+        temp.b(1).write_value(ficr.temp().b1().read().0);
+        temp.b(2).write_value(ficr.temp().b2().read().0);
+        temp.b(3).write_value(ficr.temp().b3().read().0);
+        temp.b(4).write_value(ficr.temp().b4().read().0);
+        temp.b(5).write_value(ficr.temp().b5().read().0);
+        temp.t(0).write_value(ficr.temp().t0().read().0);
+        temp.t(1).write_value(ficr.temp().t1().read().0);
+        temp.t(2).write_value(ficr.temp().t2().read().0);
+        temp.t(3).write_value(ficr.temp().t3().read().0);
+        temp.t(4).write_value(ficr.temp().t4().read().0);
+    }
+
     // GLITCHDET is only accessible for secure code
     #[cfg(all(feature = "_nrf54l", feature = "_s"))]
     {
diff --git a/embassy-nrf/src/spis.rs b/embassy-nrf/src/spis.rs
index 96a9c0ae0..6f837c317 100644
--- a/embassy-nrf/src/spis.rs
+++ b/embassy-nrf/src/spis.rs
@@ -17,6 +17,7 @@ use crate::gpio::{self, AnyPin, OutputDrive, Pin as GpioPin, SealedPin as _, con
 use crate::interrupt::typelevel::Interrupt;
 use crate::pac::gpio::vals as gpiovals;
 use crate::pac::spis::vals;
+use crate::ppi::Event;
 use crate::util::slice_in_ram_or;
 use crate::{interrupt, pac};
 
@@ -334,6 +335,20 @@ impl<'d> Spis<'d> {
         Ok((n_rx, n_tx))
     }
 
+    /// Returns the ACQUIRED event, for use with PPI.
+    ///
+    /// This event will fire when the semaphore is acquired.
+    pub fn event_acquired(&self) -> Event<'d> {
+        Event::from_reg(self.r.events_acquired())
+    }
+
+    /// Returns the END event, for use with PPI.
+    ///
+    /// This event will fire when the slave transaction is complete.
+    pub fn event_end(&self) -> Event<'d> {
+        Event::from_reg(self.r.events_end())
+    }
+
     async fn async_inner(&mut self, rx: &mut [u8], tx: &[u8]) -> Result<(usize, usize), Error> {
         match self.async_inner_from_ram(rx, tx).await {
             Ok(n) => Ok(n),
diff --git a/embassy-nxp/CHANGELOG.md b/embassy-nxp/CHANGELOG.md
index 39f5c75bd..e6f117da4 100644
--- a/embassy-nxp/CHANGELOG.md
+++ b/embassy-nxp/CHANGELOG.md
@@ -7,6 +7,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 <!-- next-header -->
 ## Unreleased - ReleaseDate
+- Codegen using `nxp-pac` metadata
 - LPC55: PWM simple
 - LPC55: Move ALT definitions for USART to TX/RX pin impls. 
 - LPC55: Remove internal match_iocon macro
diff --git a/embassy-nxp/Cargo.toml b/embassy-nxp/Cargo.toml
index f8c63ba29..b78c26c77 100644
--- a/embassy-nxp/Cargo.toml
+++ b/embassy-nxp/Cargo.toml
@@ -38,13 +38,13 @@ embassy-time-queue-utils = { version = "0.3.0", path = "../embassy-time-queue-ut
 embedded-io = "0.6.1"
 embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
 ## Chip dependencies
-nxp-pac = { version = "0.1.0", optional = true, git = "https://github.com/i509VCB/nxp-pac", rev = "477dfdbfd5e6c75c0730c56494b601c1b2257263"}
+nxp-pac = { version = "0.1.0", optional = true, git = "https://github.com/i509VCB/nxp-pac", rev = "af5122e1cbe1483833c5d2e5af96b26a34ed5d62"}
 
 imxrt-rt = { version = "0.1.7", optional = true, features = ["device"] }
 
 [build-dependencies]
 cfg_aliases = "0.2.1"
-nxp-pac = { version = "0.1.0", git = "https://github.com/i509VCB/nxp-pac", rev = "477dfdbfd5e6c75c0730c56494b601c1b2257263", features = ["metadata"], optional = true }
+nxp-pac = { version = "0.1.0", git = "https://github.com/i509VCB/nxp-pac", rev = "af5122e1cbe1483833c5d2e5af96b26a34ed5d62", features = ["metadata"], optional = true }
 proc-macro2 = "1.0.95"
 quote = "1.0.15"
 
diff --git a/embassy-nxp/build.rs b/embassy-nxp/build.rs
index f3c062c87..f53c29161 100644
--- a/embassy-nxp/build.rs
+++ b/embassy-nxp/build.rs
@@ -4,10 +4,12 @@ use std::process::Command;
 use std::{env, fs};
 
 use cfg_aliases::cfg_aliases;
-#[cfg(feature = "_rt1xxx")]
 use nxp_pac::metadata;
+use nxp_pac::metadata::{METADATA, Peripheral};
 #[allow(unused)]
 use proc_macro2::TokenStream;
+use proc_macro2::{Ident, Literal, Span};
+use quote::format_ident;
 #[allow(unused)]
 use quote::quote;
 
@@ -31,56 +33,188 @@ fn main() {
     .unwrap()
     .to_ascii_lowercase();
 
+    let singletons = singletons(&mut cfgs);
+
     cfg_aliases! {
         rt1xxx: { any(feature = "mimxrt1011", feature = "mimxrt1062") },
-        gpio1: { any(feature = "mimxrt1011", feature = "mimxrt1062") },
-        gpio2: { any(feature = "mimxrt1011", feature = "mimxrt1062") },
-        gpio3: { feature = "mimxrt1062" },
-        gpio4: { feature = "mimxrt1062" },
-        gpio5: { any(feature = "mimxrt1011", feature = "mimxrt1062") },
     }
 
     eprintln!("chip: {chip_name}");
 
-    generate_code();
+    generate_code(&mut cfgs, &singletons);
 }
 
-#[cfg(feature = "_rt1xxx")]
-fn generate_iomuxc() -> TokenStream {
-    use proc_macro2::{Ident, Span};
+/// A peripheral singleton returned by `embassy_nxp::init`.
+struct Singleton {
+    name: String,
 
-    let pads = metadata::iomuxc::IOMUXC_REGISTERS.iter().map(|registers| {
-        let name = Ident::new(&registers.name, Span::call_site());
-        let address = registers.pad_ctl;
+    /// A cfg guard which indicates whether the `Peripherals` struct will give the user this singleton.
+    cfg: Option<TokenStream>,
+}
 
-        quote! {
-            pub const #name: u32 = #address;
+fn singletons(cfgs: &mut common::CfgSet) -> Vec<Singleton> {
+    let mut singletons = Vec::new();
+
+    for peripheral in METADATA.peripherals {
+        // GPIO and DMA are generated in a 2nd pass.
+        let skip_singleton = if peripheral.name.starts_with("GPIO") || peripheral.name.starts_with("DMA") {
+            true
+        } else {
+            false
+        };
+
+        if !skip_singleton {
+            singletons.push(Singleton {
+                name: peripheral.name.into(),
+                cfg: None,
+            });
         }
-    });
+    }
 
-    let muxes = metadata::iomuxc::IOMUXC_REGISTERS.iter().map(|registers| {
-        let name = Ident::new(&registers.name, Span::call_site());
-        let address = registers.mux_ctl;
+    cfgs.declare_all(&[
+        "gpio1",
+        "gpio1_hi",
+        "gpio2",
+        "gpio2_hi",
+        "gpio3",
+        "gpio3_hi",
+        "gpio4",
+        "gpio4_hi",
+        "gpio5",
+        "gpio5_hi",
+        "gpio10",
+        "gpio10_hi",
+    ]);
 
-        quote! {
-            pub const #name: u32 = #address;
+    for peripheral in METADATA.peripherals.iter().filter(|p| p.name.starts_with("GPIO")) {
+        let number = peripheral.name.strip_prefix("GPIO").unwrap();
+        assert!(number.parse::<u8>().is_ok());
+        cfgs.enable(format!("gpio{}", number));
+
+        for signal in peripheral.signals.iter() {
+            let pin_number = signal.name.parse::<u8>().unwrap();
+
+            if pin_number > 15 {
+                cfgs.enable(format!("gpio{}_hi", number));
+            }
+
+            // GPIO signals only defined a single signal, on a single pin.
+            assert_eq!(signal.pins.len(), 1);
+
+            singletons.push(Singleton {
+                name: signal.pins[0].pin.into(),
+                cfg: None,
+            });
+        }
+    }
+
+    for peripheral in METADATA.peripherals.iter().filter(|p| p.name.starts_with("DMA")) {
+        let instance = peripheral.name.strip_prefix("DMA").unwrap();
+        assert!(instance.parse::<u8>().is_ok());
+
+        for signal in peripheral.signals.iter() {
+            let channel_number = signal.name.parse::<u8>().unwrap();
+            let name = format!("DMA{instance}_CH{channel_number}");
+
+            // DMA has no pins.
+            assert!(signal.pins.is_empty());
+
+            singletons.push(Singleton { name, cfg: None });
+        }
+    }
+
+    for peripheral in METADATA.peripherals.iter().filter(|p| p.name.starts_with("SCT")) {
+        let instance = peripheral.name.strip_prefix("SCT").unwrap();
+        assert!(instance.parse::<u8>().is_ok());
+
+        for signal in peripheral.signals.iter() {
+            if !signal.name.starts_with("OUT") {
+                continue;
+            }
+
+            let channel_number = signal.name.strip_prefix("OUT").unwrap().parse::<u8>().unwrap();
+            let name = format!("SCT{instance}_OUT{channel_number}");
+
+            singletons.push(Singleton { name, cfg: None });
         }
+    }
+
+    singletons
+}
+
+#[cfg(feature = "_rt1xxx")]
+fn generate_iomuxc() -> TokenStream {
+    let iomuxc_pad_impls = metadata::METADATA
+        .pins
+        .iter()
+        .filter(|p| p.iomuxc.as_ref().filter(|i| i.mux.is_some()).is_some())
+        .map(|pin| {
+            let Some(ref iomuxc) = pin.iomuxc else {
+                panic!("Pin {} has no IOMUXC definitions", pin.name);
+            };
+
+            let name = Ident::new(pin.name, Span::call_site());
+            let mux = iomuxc.mux.unwrap();
+            let pad = iomuxc.pad;
+
+            quote! {
+                impl_iomuxc_pad!(#name, #pad, #mux);
+            }
+        });
+
+    let base_match_arms = metadata::METADATA
+        .peripherals
+        .iter()
+        .filter(|p| p.name.starts_with("GPIO"))
+        .map(|peripheral| {
+            peripheral.signals.iter().map(|signal| {
+                // All GPIO signals have a single pin.
+                let pin = &signal.pins[0];
+                let instance = peripheral.name.strip_prefix("GPIO").unwrap();
+                let bank_match = format_ident!("Gpio{}", instance);
+                let pin_number = signal.name.parse::<u8>().unwrap();
+                let pin_ident = Ident::new(pin.pin, Span::call_site());
+
+                quote! {
+                    (Bank::#bank_match, #pin_number) => <crate::peripherals::#pin_ident as crate::iomuxc::SealedPad>
+                }
+            })
+        })
+        .flatten()
+        .collect::<Vec<_>>();
+
+    let pad_match_arms = base_match_arms.iter().map(|arm| {
+        quote! { #arm::PAD }
+    });
+
+    let mux_match_arms = base_match_arms.iter().map(|arm| {
+        quote! { #arm::MUX }
     });
 
     quote! {
-        pub mod iomuxc {
-            pub mod pads {
-                #(#pads)*
+        #(#iomuxc_pad_impls)*
+
+        pub(crate) fn iomuxc_pad(bank: crate::gpio::Bank, pin: u8) -> *mut () {
+            use crate::gpio::Bank;
+
+            match (bank, pin) {
+                #(#pad_match_arms),*,
+                _ => unreachable!()
             }
+        }
+
+        pub(crate) fn iomuxc_mux(bank: crate::gpio::Bank, pin: u8) -> Option<*mut ()> {
+            use crate::gpio::Bank;
 
-            pub mod muxes {
-                #(#muxes)*
+            match (bank, pin) {
+                #(#mux_match_arms),*,
+                _ => unreachable!()
             }
         }
     }
 }
 
-fn generate_code() {
+fn generate_code(cfgs: &mut common::CfgSet, singletons: &[Singleton]) {
     #[allow(unused)]
     use std::fmt::Write;
 
@@ -88,14 +222,179 @@ fn generate_code() {
     #[allow(unused_mut)]
     let mut output = String::new();
 
+    writeln!(&mut output, "{}", peripherals(singletons)).unwrap();
+
     #[cfg(feature = "_rt1xxx")]
     writeln!(&mut output, "{}", generate_iomuxc()).unwrap();
 
+    writeln!(&mut output, "{}", interrupts()).unwrap();
+    writeln!(&mut output, "{}", impl_peripherals(cfgs, singletons)).unwrap();
+
     let out_file = out_dir.join("_generated.rs").to_string_lossy().to_string();
     fs::write(&out_file, output).unwrap();
     rustfmt(&out_file);
 }
 
+fn interrupts() -> TokenStream {
+    let interrupts = METADATA.interrupts.iter().map(|interrupt| format_ident!("{interrupt}"));
+
+    quote! {
+        embassy_hal_internal::interrupt_mod!(#(#interrupts),*);
+    }
+}
+
+fn peripherals(singletons: &[Singleton]) -> TokenStream {
+    let defs = singletons.iter().map(|s| {
+        let ident = Ident::new(&s.name, Span::call_site());
+        quote! { #ident }
+    });
+
+    let peripherals = singletons.iter().map(|s| {
+        let ident = Ident::new(&s.name, Span::call_site());
+        let cfg = s.cfg.clone().unwrap_or_else(|| quote! {});
+        quote! {
+            #cfg
+            #ident
+        }
+    });
+
+    quote! {
+        embassy_hal_internal::peripherals_definition!(#(#defs),*);
+        embassy_hal_internal::peripherals_struct!(#(#peripherals),*);
+    }
+}
+
+fn impl_gpio_pin(impls: &mut Vec<TokenStream>, peripheral: &Peripheral) {
+    let instance = peripheral.name.strip_prefix("GPIO").unwrap();
+    let bank = format_ident!("Gpio{}", instance);
+    // let pin =
+
+    for signal in peripheral.signals.iter() {
+        let pin_number = signal.name.parse::<u8>().unwrap();
+        let pin = Ident::new(signal.pins[0].pin, Span::call_site());
+
+        impls.push(quote! {
+            impl_pin!(#pin, #bank, #pin_number);
+        });
+    }
+}
+
+fn impl_dma_channel(impls: &mut Vec<TokenStream>, peripheral: &Peripheral) {
+    let instance = Ident::new(peripheral.name, Span::call_site());
+
+    for signal in peripheral.signals.iter() {
+        let channel_number = signal.name.parse::<u8>().unwrap();
+        let channel_name = format_ident!("{instance}_CH{channel_number}");
+
+        impls.push(quote! {
+            impl_dma_channel!(#instance, #channel_name, #channel_number);
+        });
+    }
+}
+
+fn impl_usart(impls: &mut Vec<TokenStream>, peripheral: &Peripheral) {
+    let instance = Ident::new(peripheral.name, Span::call_site());
+    let flexcomm = Ident::new(
+        peripheral.flexcomm.expect("LPC55 must specify FLEXCOMM instance"),
+        Span::call_site(),
+    );
+    let number = Literal::u8_unsuffixed(peripheral.name.strip_prefix("USART").unwrap().parse::<u8>().unwrap());
+
+    impls.push(quote! {
+        impl_usart_instance!(#instance, #flexcomm, #number);
+    });
+
+    for signal in peripheral.signals {
+        let r#macro = match signal.name {
+            "TXD" => format_ident!("impl_usart_txd_pin"),
+            "RXD" => format_ident!("impl_usart_rxd_pin"),
+            _ => unreachable!(),
+        };
+
+        for pin in signal.pins {
+            let alt = format_ident!("ALT{}", pin.alt);
+            let pin = format_ident!("{}", pin.pin);
+
+            impls.push(quote! {
+                #r#macro!(#pin, #instance, #alt);
+            });
+        }
+    }
+
+    for dma_mux in peripheral.dma_muxing {
+        assert_eq!(dma_mux.mux, "DMA0", "TODO: USART for more than LPC55");
+
+        let r#macro = match dma_mux.signal {
+            "TX" => format_ident!("impl_usart_tx_channel"),
+            "RX" => format_ident!("impl_usart_rx_channel"),
+            _ => unreachable!(),
+        };
+
+        let channel = format_ident!("DMA0_CH{}", dma_mux.request);
+
+        impls.push(quote! {
+            #r#macro!(#instance, #channel);
+        });
+    }
+}
+
+fn impl_sct(impls: &mut Vec<TokenStream>, peripheral: &Peripheral) {
+    let instance = Ident::new(peripheral.name, Span::call_site());
+
+    impls.push(quote! {
+        impl_sct_instance!(#instance);
+    });
+
+    for signal in peripheral.signals.iter() {
+        if signal.name.starts_with("OUT") {
+            let channel_number = signal.name.strip_prefix("OUT").unwrap().parse::<u8>().unwrap();
+
+            let channel_name = format_ident!("{instance}_OUT{channel_number}");
+
+            impls.push(quote! {
+                impl_sct_output_instance!(#instance, #channel_name, #channel_number);
+            });
+
+            if signal.name.starts_with("OUT") {
+                for pin in signal.pins {
+                    let pin_name = format_ident!("{}", pin.pin);
+                    let alt = format_ident!("ALT{}", pin.alt);
+
+                    impls.push(quote! {
+                        impl_sct_output_pin!(#instance, #channel_name, #pin_name, #alt);
+                    });
+                }
+            }
+        }
+    }
+}
+
+fn impl_peripherals(_cfgs: &mut common::CfgSet, _singletons: &[Singleton]) -> TokenStream {
+    let mut impls = Vec::new();
+
+    for peripheral in metadata::METADATA.peripherals.iter() {
+        if peripheral.name.starts_with("GPIO") {
+            impl_gpio_pin(&mut impls, peripheral);
+        }
+
+        if peripheral.name.starts_with("DMA") {
+            impl_dma_channel(&mut impls, peripheral);
+        }
+
+        if peripheral.name.starts_with("USART") {
+            impl_usart(&mut impls, peripheral);
+        }
+
+        if peripheral.name.starts_with("SCT") {
+            impl_sct(&mut impls, peripheral);
+        }
+    }
+
+    quote! {
+        #(#impls)*
+    }
+}
+
 /// rustfmt a given path.
 /// Failures are logged to stderr and ignored.
 fn rustfmt(path: impl AsRef<Path>) {
diff --git a/embassy-nxp/src/chips/lpc55.rs b/embassy-nxp/src/chips/lpc55.rs
index e9addddb6..7967e07d1 100644
--- a/embassy-nxp/src/chips/lpc55.rs
+++ b/embassy-nxp/src/chips/lpc55.rs
@@ -1,121 +1,10 @@
-pub use nxp_pac as pac;
+pub(crate) mod _generated {
+    #![allow(dead_code)]
+    #![allow(unused_imports)]
+    #![allow(non_snake_case)]
+    #![allow(missing_docs)]
 
-embassy_hal_internal::interrupt_mod!(
-    FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7
-);
-
-embassy_hal_internal::peripherals! {
-    // External pins. These are not only GPIOs, they are multi-purpose pins and can be used by other
-    // peripheral types (e.g. I2C).
-    PIO0_0,
-    PIO0_1,
-    PIO0_2,
-    PIO0_3,
-    PIO0_4,
-    PIO0_5,
-    PIO0_6,
-    PIO0_7,
-    PIO0_8,
-    PIO0_9,
-    PIO0_10,
-    PIO0_11,
-    PIO0_12,
-    PIO0_13,
-    PIO0_14,
-    PIO0_15,
-    PIO0_16,
-    PIO0_17,
-    PIO0_18,
-    PIO0_19,
-    PIO0_20,
-    PIO0_21,
-    PIO0_22,
-    PIO0_23,
-    PIO0_24,
-    PIO0_25,
-    PIO0_26,
-    PIO0_27,
-    PIO0_28,
-    PIO0_29,
-    PIO0_30,
-    PIO0_31,
-    PIO1_0,
-    PIO1_1,
-    PIO1_2,
-    PIO1_3,
-    PIO1_4,
-    PIO1_5,
-    PIO1_6,
-    PIO1_7,
-    PIO1_8,
-    PIO1_9,
-    PIO1_10,
-    PIO1_11,
-    PIO1_12,
-    PIO1_13,
-    PIO1_14,
-    PIO1_15,
-    PIO1_16,
-    PIO1_17,
-    PIO1_18,
-    PIO1_19,
-    PIO1_20,
-    PIO1_21,
-    PIO1_22,
-    PIO1_23,
-    PIO1_24,
-    PIO1_25,
-    PIO1_26,
-    PIO1_27,
-    PIO1_28,
-    PIO1_29,
-    PIO1_30,
-    PIO1_31,
-
-    // Direct Memory Access (DMA) channels. They are used for asynchronous modes of peripherals.
-    DMA_CH0,
-    DMA_CH1,
-    DMA_CH2,
-    DMA_CH3,
-    DMA_CH4,
-    DMA_CH5,
-    DMA_CH6,
-    DMA_CH7,
-    DMA_CH8,
-    DMA_CH9,
-    DMA_CH10,
-    DMA_CH11,
-    DMA_CH12,
-    DMA_CH13,
-    DMA_CH14,
-    DMA_CH15,
-    DMA_CH16,
-    DMA_CH17,
-    DMA_CH18,
-    DMA_CH19,
-    DMA_CH20,
-    DMA_CH21,
-    DMA_CH22,
-
-    // Pulse-Width Modulation Outputs.
-    PWM_OUTPUT0,
-    PWM_OUTPUT1,
-    PWM_OUTPUT2,
-    PWM_OUTPUT3,
-    PWM_OUTPUT4,
-    PWM_OUTPUT5,
-    PWM_OUTPUT6,
-    PWM_OUTPUT7,
-    PWM_OUTPUT8,
-    PWM_OUTPUT9,
-
-    // Universal Synchronous/Asynchronous Receiver/Transmitter (USART) instances.
-    USART0,
-    USART1,
-    USART2,
-    USART3,
-    USART4,
-    USART5,
-    USART6,
-    USART7
+    include!(concat!(env!("OUT_DIR"), "/_generated.rs"));
 }
+
+pub use _generated::*;
diff --git a/embassy-nxp/src/chips/mimxrt1011.rs b/embassy-nxp/src/chips/mimxrt1011.rs
index a74d953fc..d5969a24b 100644
--- a/embassy-nxp/src/chips/mimxrt1011.rs
+++ b/embassy-nxp/src/chips/mimxrt1011.rs
@@ -1,107 +1,5 @@
 // This must be imported so that __preinit is defined.
 use imxrt_rt as _;
-pub use nxp_pac as pac;
-
-embassy_hal_internal::peripherals! {
-    // External pins. These are not only GPIOs, they are multi-purpose pins and can be used by other
-    // peripheral types (e.g. I2C).
-    GPIO_00,
-    GPIO_01,
-    GPIO_02,
-    GPIO_03,
-    GPIO_04,
-    GPIO_05,
-    GPIO_06,
-    GPIO_07,
-    GPIO_08,
-    GPIO_09,
-    GPIO_10,
-    GPIO_11,
-    GPIO_12,
-    GPIO_13,
-    GPIO_AD_00,
-    GPIO_AD_01,
-    GPIO_AD_02,
-    GPIO_AD_03,
-    GPIO_AD_04,
-    GPIO_AD_05,
-    GPIO_AD_06,
-    GPIO_AD_07,
-    GPIO_AD_08,
-    GPIO_AD_09,
-    GPIO_AD_10,
-    GPIO_AD_11,
-    GPIO_AD_12,
-    GPIO_AD_13,
-    GPIO_AD_14,
-    GPIO_SD_00,
-    GPIO_SD_01,
-    GPIO_SD_02,
-    GPIO_SD_03,
-    GPIO_SD_04,
-    GPIO_SD_05,
-    GPIO_SD_06,
-    GPIO_SD_07,
-    GPIO_SD_08,
-    GPIO_SD_09,
-    GPIO_SD_10,
-    GPIO_SD_11,
-    GPIO_SD_12,
-    GPIO_SD_13,
-    PMIC_ON_REQ,
-}
-
-impl_gpio! {
-    // GPIO Bank 1
-    GPIO_00(Gpio1, 0);
-    GPIO_01(Gpio1, 1);
-    GPIO_02(Gpio1, 2);
-    GPIO_03(Gpio1, 3);
-    GPIO_04(Gpio1, 4);
-    GPIO_05(Gpio1, 5);
-    GPIO_06(Gpio1, 6);
-    GPIO_07(Gpio1, 7);
-    GPIO_08(Gpio1, 8);
-    GPIO_09(Gpio1, 9);
-    GPIO_10(Gpio1, 10);
-    GPIO_11(Gpio1, 11);
-    GPIO_12(Gpio1, 12);
-    GPIO_13(Gpio1, 13);
-    GPIO_AD_00(Gpio1, 14);
-    GPIO_AD_01(Gpio1, 15);
-    GPIO_AD_02(Gpio1, 16);
-    GPIO_AD_03(Gpio1, 17);
-    GPIO_AD_04(Gpio1, 18);
-    GPIO_AD_05(Gpio1, 19);
-    GPIO_AD_06(Gpio1, 20);
-    GPIO_AD_07(Gpio1, 21);
-    GPIO_AD_08(Gpio1, 22);
-    GPIO_AD_09(Gpio1, 23);
-    GPIO_AD_10(Gpio1, 24);
-    GPIO_AD_11(Gpio1, 25);
-    GPIO_AD_12(Gpio1, 26);
-    GPIO_AD_13(Gpio1, 27);
-    GPIO_AD_14(Gpio1, 28);
-
-    // GPIO Bank 2
-    GPIO_SD_00(Gpio2, 0);
-    GPIO_SD_01(Gpio2, 1);
-    GPIO_SD_02(Gpio2, 2);
-    GPIO_SD_03(Gpio2, 3);
-    GPIO_SD_04(Gpio2, 4);
-    GPIO_SD_05(Gpio2, 5);
-    GPIO_SD_06(Gpio2, 6);
-    GPIO_SD_07(Gpio2, 7);
-    GPIO_SD_08(Gpio2, 8);
-    GPIO_SD_09(Gpio2, 9);
-    GPIO_SD_10(Gpio2, 10);
-    GPIO_SD_11(Gpio2, 11);
-    GPIO_SD_12(Gpio2, 12);
-    GPIO_SD_13(Gpio2, 13);
-
-    // GPIO Bank 5
-    PMIC_ON_REQ(Gpio5, 0);
-}
 
 pub(crate) mod _generated {
     #![allow(dead_code)]
@@ -111,3 +9,5 @@ pub(crate) mod _generated {
 
     include!(concat!(env!("OUT_DIR"), "/_generated.rs"));
 }
+
+pub use _generated::*;
diff --git a/embassy-nxp/src/chips/mimxrt1062.rs b/embassy-nxp/src/chips/mimxrt1062.rs
index ef153bd66..d5969a24b 100644
--- a/embassy-nxp/src/chips/mimxrt1062.rs
+++ b/embassy-nxp/src/chips/mimxrt1062.rs
@@ -1,276 +1,5 @@
 // This must be imported so that __preinit is defined.
 use imxrt_rt as _;
-pub use nxp_pac as pac;
-
-embassy_hal_internal::peripherals! {
-    // External pins. These are not only GPIOs, they are multi-purpose pins and can be used by other
-    // peripheral types (e.g. I2C).
-    GPIO_AD_B0_00,
-    GPIO_AD_B0_01,
-    GPIO_AD_B0_02,
-    GPIO_AD_B0_03,
-    GPIO_AD_B0_04,
-    GPIO_AD_B0_05,
-    GPIO_AD_B0_06,
-    GPIO_AD_B0_07,
-    GPIO_AD_B0_08,
-    GPIO_AD_B0_09,
-    GPIO_AD_B0_10,
-    GPIO_AD_B0_11,
-    GPIO_AD_B0_12,
-    GPIO_AD_B0_13,
-    GPIO_AD_B0_14,
-    GPIO_AD_B0_15,
-    GPIO_AD_B1_00,
-    GPIO_AD_B1_01,
-    GPIO_AD_B1_02,
-    GPIO_AD_B1_03,
-    GPIO_AD_B1_04,
-    GPIO_AD_B1_05,
-    GPIO_AD_B1_06,
-    GPIO_AD_B1_07,
-    GPIO_AD_B1_08,
-    GPIO_AD_B1_09,
-    GPIO_AD_B1_10,
-    GPIO_AD_B1_11,
-    GPIO_AD_B1_12,
-    GPIO_AD_B1_13,
-    GPIO_AD_B1_14,
-    GPIO_AD_B1_15,
-    GPIO_B0_00,
-    GPIO_B0_01,
-    GPIO_B0_02,
-    GPIO_B0_03,
-    GPIO_B0_04,
-    GPIO_B0_05,
-    GPIO_B0_06,
-    GPIO_B0_07,
-    GPIO_B0_08,
-    GPIO_B0_09,
-    GPIO_B0_10,
-    GPIO_B0_11,
-    GPIO_B0_12,
-    GPIO_B0_13,
-    GPIO_B0_14,
-    GPIO_B0_15,
-    GPIO_B1_00,
-    GPIO_B1_01,
-    GPIO_B1_02,
-    GPIO_B1_03,
-    GPIO_B1_04,
-    GPIO_B1_05,
-    GPIO_B1_06,
-    GPIO_B1_07,
-    GPIO_B1_08,
-    GPIO_B1_09,
-    GPIO_B1_10,
-    GPIO_B1_11,
-    GPIO_B1_12,
-    GPIO_B1_13,
-    GPIO_B1_14,
-    GPIO_B1_15,
-    GPIO_EMC_00,
-    GPIO_EMC_01,
-    GPIO_EMC_02,
-    GPIO_EMC_03,
-    GPIO_EMC_04,
-    GPIO_EMC_05,
-    GPIO_EMC_06,
-    GPIO_EMC_07,
-    GPIO_EMC_08,
-    GPIO_EMC_09,
-    GPIO_EMC_10,
-    GPIO_EMC_11,
-    GPIO_EMC_12,
-    GPIO_EMC_13,
-    GPIO_EMC_14,
-    GPIO_EMC_15,
-    GPIO_EMC_16,
-    GPIO_EMC_17,
-    GPIO_EMC_18,
-    GPIO_EMC_19,
-    GPIO_EMC_20,
-    GPIO_EMC_21,
-    GPIO_EMC_22,
-    GPIO_EMC_23,
-    GPIO_EMC_24,
-    GPIO_EMC_25,
-    GPIO_EMC_26,
-    GPIO_EMC_27,
-    GPIO_EMC_28,
-    GPIO_EMC_29,
-    GPIO_EMC_30,
-    GPIO_EMC_31,
-    GPIO_EMC_32,
-    GPIO_EMC_33,
-    GPIO_EMC_34,
-    GPIO_EMC_35,
-    GPIO_EMC_36,
-    GPIO_EMC_37,
-    GPIO_EMC_38,
-    GPIO_EMC_39,
-    GPIO_EMC_40,
-    GPIO_EMC_41,
-    GPIO_SD_B0_00,
-    GPIO_SD_B0_01,
-    GPIO_SD_B0_02,
-    GPIO_SD_B0_03,
-    GPIO_SD_B0_04,
-    GPIO_SD_B0_05,
-    GPIO_SD_B1_00,
-    GPIO_SD_B1_01,
-    GPIO_SD_B1_02,
-    GPIO_SD_B1_03,
-    GPIO_SD_B1_04,
-    GPIO_SD_B1_05,
-    GPIO_SD_B1_06,
-    GPIO_SD_B1_07,
-    GPIO_SD_B1_08,
-    GPIO_SD_B1_09,
-    GPIO_SD_B1_10,
-    GPIO_SD_B1_11,
-    WAKEUP,
-    PMIC_ON_REQ,
-    PMIC_STBY_REQ,
-}
-
-impl_gpio! {
-    // GPIO Bank 1
-    GPIO_AD_B0_00(Gpio1, 0);
-    GPIO_AD_B0_01(Gpio1, 1);
-    GPIO_AD_B0_02(Gpio1, 2);
-    GPIO_AD_B0_03(Gpio1, 3);
-    GPIO_AD_B0_04(Gpio1, 4);
-    GPIO_AD_B0_05(Gpio1, 5);
-    GPIO_AD_B0_06(Gpio1, 6);
-    GPIO_AD_B0_07(Gpio1, 7);
-    GPIO_AD_B0_08(Gpio1, 8);
-    GPIO_AD_B0_09(Gpio1, 9);
-    GPIO_AD_B0_10(Gpio1, 10);
-    GPIO_AD_B0_11(Gpio1, 11);
-    GPIO_AD_B0_12(Gpio1, 12);
-    GPIO_AD_B0_13(Gpio1, 13);
-    GPIO_AD_B0_14(Gpio1, 14);
-    GPIO_AD_B0_15(Gpio1, 15);
-    GPIO_AD_B1_00(Gpio1, 16);
-    GPIO_AD_B1_01(Gpio1, 17);
-    GPIO_AD_B1_02(Gpio1, 18);
-    GPIO_AD_B1_03(Gpio1, 19);
-    GPIO_AD_B1_04(Gpio1, 20);
-    GPIO_AD_B1_05(Gpio1, 21);
-    GPIO_AD_B1_06(Gpio1, 22);
-    GPIO_AD_B1_07(Gpio1, 23);
-    GPIO_AD_B1_08(Gpio1, 24);
-    GPIO_AD_B1_09(Gpio1, 25);
-    GPIO_AD_B1_10(Gpio1, 26);
-    GPIO_AD_B1_11(Gpio1, 27);
-    GPIO_AD_B1_12(Gpio1, 28);
-    GPIO_AD_B1_13(Gpio1, 29);
-    GPIO_AD_B1_14(Gpio1, 30);
-    GPIO_AD_B1_15(Gpio1, 31);
-
-    // GPIO Bank 2
-    GPIO_B0_00(Gpio2, 0);
-    GPIO_B0_01(Gpio2, 1);
-    GPIO_B0_02(Gpio2, 2);
-    GPIO_B0_03(Gpio2, 3);
-    GPIO_B0_04(Gpio2, 4);
-    GPIO_B0_05(Gpio2, 5);
-    GPIO_B0_06(Gpio2, 6);
-    GPIO_B0_07(Gpio2, 7);
-    GPIO_B0_08(Gpio2, 8);
-    GPIO_B0_09(Gpio2, 9);
-    GPIO_B0_10(Gpio2, 10);
-    GPIO_B0_11(Gpio2, 11);
-    GPIO_B0_12(Gpio2, 12);
-    GPIO_B0_13(Gpio2, 13);
-    GPIO_B0_14(Gpio2, 14);
-    GPIO_B0_15(Gpio2, 15);
-    GPIO_B1_00(Gpio2, 16);
-    GPIO_B1_01(Gpio2, 17);
-    GPIO_B1_02(Gpio2, 18);
-    GPIO_B1_03(Gpio2, 19);
-    GPIO_B1_04(Gpio2, 20);
-    GPIO_B1_05(Gpio2, 21);
-    GPIO_B1_06(Gpio2, 22);
-    GPIO_B1_07(Gpio2, 23);
-    GPIO_B1_08(Gpio2, 24);
-    GPIO_B1_09(Gpio2, 25);
-    GPIO_B1_10(Gpio2, 26);
-    GPIO_B1_11(Gpio2, 27);
-    GPIO_B1_12(Gpio2, 28);
-    GPIO_B1_13(Gpio2, 29);
-    GPIO_B1_14(Gpio2, 30);
-    GPIO_B1_15(Gpio2, 31);
-
-    // GPIO Bank 4 (EMC is 4, then 3)
-    GPIO_EMC_00(Gpio4, 0);
-    GPIO_EMC_01(Gpio4, 1);
-    GPIO_EMC_02(Gpio4, 2);
-    GPIO_EMC_03(Gpio4, 3);
-    GPIO_EMC_04(Gpio4, 4);
-    GPIO_EMC_05(Gpio4, 5);
-    GPIO_EMC_06(Gpio4, 6);
-    GPIO_EMC_07(Gpio4, 7);
-    GPIO_EMC_08(Gpio4, 8);
-    GPIO_EMC_09(Gpio4, 9);
-    GPIO_EMC_10(Gpio4, 10);
-    GPIO_EMC_11(Gpio4, 11);
-    GPIO_EMC_12(Gpio4, 12);
-    GPIO_EMC_13(Gpio4, 13);
-    GPIO_EMC_14(Gpio4, 14);
-    GPIO_EMC_15(Gpio4, 15);
-    GPIO_EMC_16(Gpio4, 16);
-    GPIO_EMC_17(Gpio4, 17);
-    GPIO_EMC_18(Gpio4, 18);
-    GPIO_EMC_19(Gpio4, 19);
-    GPIO_EMC_20(Gpio4, 20);
-    GPIO_EMC_21(Gpio4, 21);
-    GPIO_EMC_22(Gpio4, 22);
-    GPIO_EMC_23(Gpio4, 23);
-    GPIO_EMC_24(Gpio4, 24);
-    GPIO_EMC_25(Gpio4, 25);
-    GPIO_EMC_26(Gpio4, 26);
-    GPIO_EMC_27(Gpio4, 27);
-    GPIO_EMC_28(Gpio4, 28);
-    GPIO_EMC_29(Gpio4, 29);
-    GPIO_EMC_30(Gpio4, 30);
-    GPIO_EMC_31(Gpio4, 31);
-
-    // GPIO Bank 3
-    GPIO_EMC_32(Gpio3, 18);
-    GPIO_EMC_33(Gpio3, 19);
-    GPIO_EMC_34(Gpio3, 20);
-    GPIO_EMC_35(Gpio3, 21);
-    GPIO_EMC_36(Gpio3, 22);
-    GPIO_EMC_37(Gpio3, 23);
-    GPIO_EMC_38(Gpio3, 24);
-    GPIO_EMC_39(Gpio3, 25);
-    GPIO_EMC_40(Gpio3, 26);
-    GPIO_EMC_41(Gpio3, 27);
-    GPIO_SD_B0_00(Gpio3, 12);
-    GPIO_SD_B0_01(Gpio3, 13);
-    GPIO_SD_B0_02(Gpio3, 14);
-    GPIO_SD_B0_03(Gpio3, 15);
-    GPIO_SD_B0_04(Gpio3, 16);
-    GPIO_SD_B0_05(Gpio3, 17);
-    GPIO_SD_B1_00(Gpio3, 0);
-    GPIO_SD_B1_01(Gpio3, 1);
-    GPIO_SD_B1_02(Gpio3, 2);
-    GPIO_SD_B1_03(Gpio3, 3);
-    GPIO_SD_B1_04(Gpio3, 4);
-    GPIO_SD_B1_05(Gpio3, 5);
-    GPIO_SD_B1_06(Gpio3, 6);
-    GPIO_SD_B1_07(Gpio3, 7);
-    GPIO_SD_B1_08(Gpio3, 8);
-    GPIO_SD_B1_09(Gpio3, 9);
-    GPIO_SD_B1_10(Gpio3, 10);
-    GPIO_SD_B1_11(Gpio3, 11);
-
-    WAKEUP(Gpio5, 0);
-    PMIC_ON_REQ(Gpio5, 1);
-    PMIC_STBY_REQ(Gpio5, 2);
-}
 
 pub(crate) mod _generated {
     #![allow(dead_code)]
@@ -280,3 +9,5 @@ pub(crate) mod _generated {
 
     include!(concat!(env!("OUT_DIR"), "/_generated.rs"));
 }
+
+pub use _generated::*;
diff --git a/embassy-nxp/src/dma.rs b/embassy-nxp/src/dma.rs
index e2df65fc9..1f479122d 100644
--- a/embassy-nxp/src/dma.rs
+++ b/embassy-nxp/src/dma.rs
@@ -1,3 +1,4 @@
+#![macro_use]
 //! Direct Memory Access (DMA) driver.
 
 #[cfg_attr(feature = "lpc55-core0", path = "./dma/lpc55.rs")]
diff --git a/embassy-nxp/src/dma/lpc55.rs b/embassy-nxp/src/dma/lpc55.rs
index 5bd763f03..623644bf1 100644
--- a/embassy-nxp/src/dma/lpc55.rs
+++ b/embassy-nxp/src/dma/lpc55.rs
@@ -1,3 +1,5 @@
+#![macro_use]
+
 use core::cell::RefCell;
 use core::future::Future;
 use core::pin::Pin;
@@ -9,9 +11,12 @@ use embassy_hal_internal::interrupt::InterruptExt;
 use embassy_hal_internal::{PeripheralType, impl_peripheral};
 use embassy_sync::waitqueue::AtomicWaker;
 
-use crate::pac::{DMA0, SYSCON, *};
-use crate::{Peri, peripherals};
+use crate::Peri;
+#[cfg(feature = "rt")]
+use crate::pac::interrupt;
+use crate::pac::{SYSCON, *};
 
+#[cfg(feature = "rt")]
 #[interrupt]
 fn DMA0() {
     let inta = DMA0.inta0().read().ia();
@@ -278,7 +283,7 @@ static DMA_DESCRIPTORS: Mutex<RefCell<DmaDescriptorTable>> = Mutex::new(RefCell:
     }; CHANNEL_COUNT],
 }));
 
-trait SealedChannel {}
+pub(crate) trait SealedChannel {}
 trait SealedWord {}
 
 /// DMA channel interface.
@@ -323,7 +328,7 @@ impl Word for u32 {
 
 /// Type erased DMA channel.
 pub struct AnyChannel {
-    number: u8,
+    pub(crate) number: u8,
 }
 
 impl_peripheral!(AnyChannel);
@@ -335,10 +340,10 @@ impl Channel for AnyChannel {
     }
 }
 
-macro_rules! channel {
-    ($name:ident, $num:expr) => {
-        impl SealedChannel for peripherals::$name {}
-        impl Channel for peripherals::$name {
+macro_rules! impl_dma_channel {
+    ($instance:ident, $name:ident, $num:expr) => {
+        impl crate::dma::SealedChannel for crate::peripherals::$name {}
+        impl crate::dma::Channel for crate::peripherals::$name {
             fn number(&self) -> u8 {
                 $num
             }
@@ -346,32 +351,10 @@ macro_rules! channel {
 
         impl From<peripherals::$name> for crate::dma::AnyChannel {
             fn from(val: peripherals::$name) -> Self {
+                use crate::dma::Channel;
+
                 Self { number: val.number() }
             }
         }
     };
 }
-
-channel!(DMA_CH0, 0);
-channel!(DMA_CH1, 1);
-channel!(DMA_CH2, 2);
-channel!(DMA_CH3, 3);
-channel!(DMA_CH4, 4);
-channel!(DMA_CH5, 5);
-channel!(DMA_CH6, 6);
-channel!(DMA_CH7, 7);
-channel!(DMA_CH8, 8);
-channel!(DMA_CH9, 9);
-channel!(DMA_CH10, 10);
-channel!(DMA_CH11, 11);
-channel!(DMA_CH12, 12);
-channel!(DMA_CH13, 13);
-channel!(DMA_CH14, 14);
-channel!(DMA_CH15, 15);
-channel!(DMA_CH16, 16);
-channel!(DMA_CH17, 17);
-channel!(DMA_CH18, 18);
-channel!(DMA_CH19, 19);
-channel!(DMA_CH20, 20);
-channel!(DMA_CH21, 21);
-channel!(DMA_CH22, 22);
diff --git a/embassy-nxp/src/gpio/lpc55.rs b/embassy-nxp/src/gpio/lpc55.rs
index 6039d8ca8..6be405463 100644
--- a/embassy-nxp/src/gpio/lpc55.rs
+++ b/embassy-nxp/src/gpio/lpc55.rs
@@ -1,9 +1,11 @@
+#![macro_use]
+
 use embassy_hal_internal::{PeripheralType, impl_peripheral};
 
+use crate::Peri;
 use crate::pac::common::{RW, Reg};
 use crate::pac::iocon::vals::{PioDigimode, PioMode};
 use crate::pac::{GPIO, IOCON, SYSCON, iocon};
-use crate::{Peri, peripherals};
 
 pub(crate) fn init() {
     // Enable clocks for GPIO, PINT, and IOCON
@@ -39,8 +41,8 @@ pub enum Pull {
 /// The LPC55 boards have two GPIO banks, each with 32 pins. This enum represents the two banks.
 #[derive(Debug, Eq, PartialEq, Clone, Copy)]
 pub enum Bank {
-    Bank0 = 0,
-    Bank1 = 1,
+    Gpio0 = 0,
+    Gpio1 = 1,
 }
 
 /// GPIO output driver. Internally, this is a specialized [Flex] pin.
@@ -228,8 +230,8 @@ pub(crate) trait SealedPin: Sized {
     #[inline]
     fn pio(&self) -> Reg<iocon::regs::Pio, RW> {
         match self.pin_bank() {
-            Bank::Bank0 => IOCON.pio0(self.pin_number() as usize),
-            Bank::Bank1 => IOCON.pio1(self.pin_number() as usize),
+            Bank::Gpio0 => IOCON.pio0(self.pin_number() as usize),
+            Bank::Gpio1 => IOCON.pio1(self.pin_number() as usize),
         }
     }
 }
@@ -254,8 +256,8 @@ pub trait Pin: PeripheralType + Into<AnyPin> + SealedPin + Sized + 'static {
 
 /// Type-erased GPIO pin.
 pub struct AnyPin {
-    pin_bank: Bank,
-    pin_number: u8,
+    pub(crate) pin_bank: Bank,
+    pub(crate) pin_number: u8,
 }
 
 impl AnyPin {
@@ -285,12 +287,12 @@ impl SealedPin for AnyPin {
 }
 
 macro_rules! impl_pin {
-    ($name:ident, $bank:expr, $pin_num:expr) => {
-        impl Pin for peripherals::$name {}
-        impl SealedPin for peripherals::$name {
+    ($name:ident, $bank:ident, $pin_num:expr) => {
+        impl crate::gpio::Pin for peripherals::$name {}
+        impl crate::gpio::SealedPin for peripherals::$name {
             #[inline]
-            fn pin_bank(&self) -> Bank {
-                $bank
+            fn pin_bank(&self) -> crate::gpio::Bank {
+                crate::gpio::Bank::$bank
             }
 
             #[inline]
@@ -301,6 +303,8 @@ macro_rules! impl_pin {
 
         impl From<peripherals::$name> for crate::gpio::AnyPin {
             fn from(val: peripherals::$name) -> Self {
+                use crate::gpio::SealedPin;
+
                 Self {
                     pin_bank: val.pin_bank(),
                     pin_number: val.pin_number(),
@@ -309,68 +313,3 @@ macro_rules! impl_pin {
         }
     };
 }
-
-impl_pin!(PIO0_0, Bank::Bank0, 0);
-impl_pin!(PIO0_1, Bank::Bank0, 1);
-impl_pin!(PIO0_2, Bank::Bank0, 2);
-impl_pin!(PIO0_3, Bank::Bank0, 3);
-impl_pin!(PIO0_4, Bank::Bank0, 4);
-impl_pin!(PIO0_5, Bank::Bank0, 5);
-impl_pin!(PIO0_6, Bank::Bank0, 6);
-impl_pin!(PIO0_7, Bank::Bank0, 7);
-impl_pin!(PIO0_8, Bank::Bank0, 8);
-impl_pin!(PIO0_9, Bank::Bank0, 9);
-impl_pin!(PIO0_10, Bank::Bank0, 10);
-impl_pin!(PIO0_11, Bank::Bank0, 11);
-impl_pin!(PIO0_12, Bank::Bank0, 12);
-impl_pin!(PIO0_13, Bank::Bank0, 13);
-impl_pin!(PIO0_14, Bank::Bank0, 14);
-impl_pin!(PIO0_15, Bank::Bank0, 15);
-impl_pin!(PIO0_16, Bank::Bank0, 16);
-impl_pin!(PIO0_17, Bank::Bank0, 17);
-impl_pin!(PIO0_18, Bank::Bank0, 18);
-impl_pin!(PIO0_19, Bank::Bank0, 19);
-impl_pin!(PIO0_20, Bank::Bank0, 20);
-impl_pin!(PIO0_21, Bank::Bank0, 21);
-impl_pin!(PIO0_22, Bank::Bank0, 22);
-impl_pin!(PIO0_23, Bank::Bank0, 23);
-impl_pin!(PIO0_24, Bank::Bank0, 24);
-impl_pin!(PIO0_25, Bank::Bank0, 25);
-impl_pin!(PIO0_26, Bank::Bank0, 26);
-impl_pin!(PIO0_27, Bank::Bank0, 27);
-impl_pin!(PIO0_28, Bank::Bank0, 28);
-impl_pin!(PIO0_29, Bank::Bank0, 29);
-impl_pin!(PIO0_30, Bank::Bank0, 30);
-impl_pin!(PIO0_31, Bank::Bank0, 31);
-impl_pin!(PIO1_0, Bank::Bank1, 0);
-impl_pin!(PIO1_1, Bank::Bank1, 1);
-impl_pin!(PIO1_2, Bank::Bank1, 2);
-impl_pin!(PIO1_3, Bank::Bank1, 3);
-impl_pin!(PIO1_4, Bank::Bank1, 4);
-impl_pin!(PIO1_5, Bank::Bank1, 5);
-impl_pin!(PIO1_6, Bank::Bank1, 6);
-impl_pin!(PIO1_7, Bank::Bank1, 7);
-impl_pin!(PIO1_8, Bank::Bank1, 8);
-impl_pin!(PIO1_9, Bank::Bank1, 9);
-impl_pin!(PIO1_10, Bank::Bank1, 10);
-impl_pin!(PIO1_11, Bank::Bank1, 11);
-impl_pin!(PIO1_12, Bank::Bank1, 12);
-impl_pin!(PIO1_13, Bank::Bank1, 13);
-impl_pin!(PIO1_14, Bank::Bank1, 14);
-impl_pin!(PIO1_15, Bank::Bank1, 15);
-impl_pin!(PIO1_16, Bank::Bank1, 16);
-impl_pin!(PIO1_17, Bank::Bank1, 17);
-impl_pin!(PIO1_18, Bank::Bank1, 18);
-impl_pin!(PIO1_19, Bank::Bank1, 19);
-impl_pin!(PIO1_20, Bank::Bank1, 20);
-impl_pin!(PIO1_21, Bank::Bank1, 21);
-impl_pin!(PIO1_22, Bank::Bank1, 22);
-impl_pin!(PIO1_23, Bank::Bank1, 23);
-impl_pin!(PIO1_24, Bank::Bank1, 24);
-impl_pin!(PIO1_25, Bank::Bank1, 25);
-impl_pin!(PIO1_26, Bank::Bank1, 26);
-impl_pin!(PIO1_27, Bank::Bank1, 27);
-impl_pin!(PIO1_28, Bank::Bank1, 28);
-impl_pin!(PIO1_29, Bank::Bank1, 29);
-impl_pin!(PIO1_30, Bank::Bank1, 30);
-impl_pin!(PIO1_31, Bank::Bank1, 31);
diff --git a/embassy-nxp/src/gpio/rt1xxx.rs b/embassy-nxp/src/gpio/rt1xxx.rs
index c4dc110ff..8a560310c 100644
--- a/embassy-nxp/src/gpio/rt1xxx.rs
+++ b/embassy-nxp/src/gpio/rt1xxx.rs
@@ -10,7 +10,7 @@ use embassy_sync::waitqueue::AtomicWaker;
 use nxp_pac::gpio::vals::Icr;
 use nxp_pac::iomuxc::vals::Pus;
 
-use crate::chip::{mux_address, pad_address};
+use crate::chip::{iomuxc_mux, iomuxc_pad};
 use crate::pac::common::{RW, Reg};
 use crate::pac::gpio::Gpio;
 #[cfg(feature = "rt")]
@@ -121,6 +121,10 @@ pub enum Bank {
     /// Bank 5
     #[cfg(gpio5)]
     Gpio5,
+
+    #[cfg(gpio10)]
+    /// Bank 10
+    Gpio10,
 }
 
 /// GPIO flexible pin.
@@ -656,6 +660,8 @@ static GPIO3_WAKERS: [AtomicWaker; 32] = [const { AtomicWaker::new() }; 32];
 static GPIO4_WAKERS: [AtomicWaker; 32] = [const { AtomicWaker::new() }; 32];
 #[cfg(gpio5)]
 static GPIO5_WAKERS: [AtomicWaker; 32] = [const { AtomicWaker::new() }; 32];
+#[cfg(gpio10)]
+static GPIO10_WAKERS: [AtomicWaker; 32] = [const { AtomicWaker::new() }; 32];
 
 /// Sealed trait for pins. This trait is sealed and cannot be implemented outside of this crate.
 pub(crate) trait SealedPin: Sized {
@@ -676,13 +682,15 @@ pub(crate) trait SealedPin: Sized {
             Bank::Gpio4 => pac::GPIO4,
             #[cfg(gpio5)]
             Bank::Gpio5 => pac::GPIO5,
+            #[cfg(gpio10)]
+            Bank::Gpio10 => pac::GPIO10,
         }
     }
 
     #[inline]
     fn mux(&self) -> Reg<MuxCtl, RW> {
         // SAFETY: The generated mux address table is valid since it is generated from the SVD files.
-        let address = unsafe { mux_address(self._bank(), self.pin_number()).unwrap_unchecked() };
+        let address = unsafe { iomuxc_mux(self._bank(), self.pin_number()).unwrap_unchecked() };
 
         // SAFETY: The register at the address is an instance of MuxCtl.
         unsafe { Reg::from_ptr(address as *mut _) }
@@ -690,8 +698,7 @@ pub(crate) trait SealedPin: Sized {
 
     #[inline]
     fn pad(&self) -> Reg<Ctl, RW> {
-        // SAFETY: The generated pad address table is valid since it is generated from the SVD files.
-        let address = unsafe { pad_address(self._bank(), self.pin_number()).unwrap_unchecked() };
+        let address = iomuxc_pad(self._bank(), self.pin_number());
 
         // SAFETY: The register at the address is an instance of Ctl.
         unsafe { Reg::from_ptr(address as *mut _) }
@@ -709,6 +716,8 @@ pub(crate) trait SealedPin: Sized {
             Bank::Gpio4 => &GPIO4_WAKERS[self.pin_number() as usize],
             #[cfg(gpio5)]
             Bank::Gpio5 => &GPIO5_WAKERS[self.pin_number() as usize],
+            #[cfg(gpio10)]
+            Bank::Gpio10 => &GPIO10_WAKERS[self.pin_number() as usize],
         }
     }
 }
@@ -793,39 +802,6 @@ impl<'d> Future for InputFuture<'d> {
     }
 }
 
-/// A macro to generate all GPIO pins.
-///
-/// This generates a lookup table for IOMUX register addresses.
-macro_rules! impl_gpio {
-    (
-        $($name: ident($bank: ident, $pin_number: expr);)*
-    ) => {
-        #[inline]
-        pub(crate) const fn pad_address(bank: crate::gpio::Bank, pin: u8) -> Option<u32> {
-            match (bank, pin) {
-                $(
-                    (crate::gpio::Bank::$bank, $pin_number) => Some(crate::chip::_generated::iomuxc::pads::$name),
-                )*
-                _ => None
-            }
-        }
-
-        #[inline]
-        pub(crate) const fn mux_address(bank: crate::gpio::Bank, pin: u8) -> Option<u32> {
-            match (bank, pin) {
-                $(
-                    (crate::gpio::Bank::$bank, $pin_number) => Some(crate::chip::_generated::iomuxc::muxes::$name),
-                )*
-                _ => None
-            }
-        }
-
-        $(
-            impl_pin!($name, $bank, $pin_number);
-        )*
-    };
-}
-
 macro_rules! impl_pin {
     ($name: ident, $bank: ident, $pin_num: expr) => {
         impl crate::gpio::Pin for crate::peripherals::$name {}
diff --git a/embassy-nxp/src/iomuxc.rs b/embassy-nxp/src/iomuxc.rs
new file mode 100644
index 000000000..c015ecbc2
--- /dev/null
+++ b/embassy-nxp/src/iomuxc.rs
@@ -0,0 +1,29 @@
+#![macro_use]
+
+/// An IOMUXC pad.
+///
+/// This trait does not imply that GPIO can be used with this pad. [`Pin`](crate::gpio::Pin) must
+/// also be implemented for GPIO.
+#[allow(private_bounds)]
+pub trait Pad: SealedPad {}
+
+pub(crate) trait SealedPad {
+    /// Address of the pad register for this pad.
+    const PAD: *mut ();
+
+    /// Address of the mux register for this pad.
+    ///
+    /// Some pads do not allow muxing (e.g. ONOFF).
+    const MUX: Option<*mut ()>;
+}
+
+macro_rules! impl_iomuxc_pad {
+    ($name: ident, $pad: expr, $mux: expr) => {
+        impl crate::iomuxc::SealedPad for crate::peripherals::$name {
+            const PAD: *mut () = $pad as *mut ();
+            const MUX: Option<*mut ()> = Some($mux as *mut ());
+        }
+
+        impl crate::iomuxc::Pad for crate::peripherals::$name {}
+    };
+}
diff --git a/embassy-nxp/src/lib.rs b/embassy-nxp/src/lib.rs
index 4058881a5..4c3dbebb9 100644
--- a/embassy-nxp/src/lib.rs
+++ b/embassy-nxp/src/lib.rs
@@ -12,8 +12,13 @@ pub mod pint;
 #[cfg(feature = "lpc55-core0")]
 pub mod pwm;
 #[cfg(feature = "lpc55-core0")]
+pub mod sct;
+#[cfg(feature = "lpc55-core0")]
 pub mod usart;
 
+#[cfg(rt1xxx)]
+mod iomuxc;
+
 #[cfg(feature = "_time_driver")]
 #[cfg_attr(feature = "time-driver-pit", path = "time_driver/pit.rs")]
 #[cfg_attr(feature = "time-driver-rtc", path = "time_driver/rtc.rs")]
@@ -25,15 +30,12 @@ mod time_driver;
 #[cfg_attr(feature = "mimxrt1062", path = "chips/mimxrt1062.rs")]
 mod chip;
 
-// TODO: Remove when this module is implemented for other chips
-#[cfg(feature = "lpc55-core0")]
-pub use chip::interrupt;
+pub use chip::{Peripherals, interrupt, peripherals};
+pub use embassy_hal_internal::{Peri, PeripheralType};
 #[cfg(feature = "unstable-pac")]
-pub use chip::pac;
+pub use nxp_pac as pac;
 #[cfg(not(feature = "unstable-pac"))]
-pub(crate) use chip::pac;
-pub use chip::{Peripherals, peripherals};
-pub use embassy_hal_internal::{Peri, PeripheralType};
+pub(crate) use nxp_pac as pac;
 
 /// Macro to bind interrupts to handlers.
 /// (Copied from `embassy-rp`)
diff --git a/embassy-nxp/src/pwm.rs b/embassy-nxp/src/pwm.rs
index 68980924a..c87a39c34 100644
--- a/embassy-nxp/src/pwm.rs
+++ b/embassy-nxp/src/pwm.rs
@@ -1,3 +1,5 @@
+#![macro_use]
+
 //! Pulse-Width Modulation (PWM) driver.
 
 #[cfg_attr(feature = "lpc55-core0", path = "./pwm/lpc55.rs")]
diff --git a/embassy-nxp/src/pwm/lpc55.rs b/embassy-nxp/src/pwm/lpc55.rs
index 197184ad6..4cdbd8526 100644
--- a/embassy-nxp/src/pwm/lpc55.rs
+++ b/embassy-nxp/src/pwm/lpc55.rs
@@ -1,12 +1,15 @@
+#![macro_use]
+
 use core::sync::atomic::{AtomicU8, AtomicU32, Ordering};
 
-use embassy_hal_internal::{Peri, PeripheralType};
+use embassy_hal_internal::Peri;
 
 use crate::gpio::AnyPin;
-use crate::pac::iocon::vals::{PioDigimode, PioFunc, PioMode, PioOd, PioSlew};
+use crate::pac::iocon::vals::{PioDigimode, PioMode, PioOd, PioSlew};
 use crate::pac::sct0::vals;
 use crate::pac::syscon::vals::{SctRst, SctclkselSel};
 use crate::pac::{SCT0, SYSCON};
+use crate::sct;
 
 // Since for now the counter is shared, the TOP value has to be kept.
 static TOP_VALUE: AtomicU32 = AtomicU32::new(0);
@@ -75,7 +78,11 @@ impl<'d> Pwm<'d> {
         SYSCON.presetctrl1().modify(|w| w.set_sct_rst(SctRst::ASSERTED));
         SYSCON.presetctrl1().modify(|w| w.set_sct_rst(SctRst::RELEASED));
     }
-    fn new_inner<T: Output>(output: usize, channel: Peri<'d, impl OutputChannelPin<T>>, config: Config) -> Self {
+    fn new_inner<T: sct::Instance, O: sct::Output<T>>(
+        output: usize,
+        channel: Peri<'d, impl sct::OutputPin<T, O>>,
+        config: Config,
+    ) -> Self {
         // Enable clocks (Syscon is enabled by default)
         critical_section::with(|_cs| {
             if !SYSCON.ahbclkctrl0().read().iocon() {
@@ -109,12 +116,12 @@ impl<'d> Pwm<'d> {
 
     /// Create PWM driver with a single 'a' pin as output.
     #[inline]
-    pub fn new_output<T: Output>(
-        output: Peri<'d, T>,
-        channel: Peri<'d, impl OutputChannelPin<T>>,
+    pub fn new_output<T: sct::Instance, O: sct::Output<T>>(
+        output: Peri<'d, O>,
+        channel: Peri<'d, impl sct::OutputPin<T, O>>,
         config: Config,
     ) -> Self {
-        Self::new_inner(output.number(), channel, config)
+        Self::new_inner::<T, O>(output.number(), channel, config)
     }
 
     /// Set the PWM config.
@@ -196,18 +203,18 @@ impl<'d> Pwm<'d> {
         // TODO(frihetselsker): optimize nxp-pac so that `set_clr` and `set_set` are turned into a bit array.
         if config.invert {
             // Low when event 0 is active
-            SCT0.out(output_number).out_clr().modify(|w| w.set_clr(1 << 0));
+            SCT0.out(output_number).out_clr().modify(|w| w.set_clr(0, true));
             // High when event `output_number + 1` is active
             SCT0.out(output_number)
                 .out_set()
-                .modify(|w| w.set_set(1 << (output_number + 1)));
+                .modify(|w| w.set_set(output_number, true));
         } else {
             // High when event 0 is active
-            SCT0.out(output_number).out_set().modify(|w| w.set_set(1 << 0));
+            SCT0.out(output_number).out_set().modify(|w| w.set_set(0, true));
             // Low when event `output_number + 1` is active
             SCT0.out(output_number)
                 .out_clr()
-                .modify(|w| w.set_clr(1 << (output_number + 1)));
+                .modify(|w| w.set_clr(output_number, true));
         }
 
         if config.phase_correct {
@@ -239,87 +246,3 @@ impl<'d> Drop for Pwm<'d> {
         }
     }
 }
-
-trait SealedOutput {
-    /// Output number.
-    fn number(&self) -> usize;
-}
-
-/// PWM Output.
-#[allow(private_bounds)]
-pub trait Output: PeripheralType + SealedOutput {}
-
-macro_rules! output {
-    ($name:ident, $num:expr) => {
-        impl SealedOutput for crate::peripherals::$name {
-            fn number(&self) -> usize {
-                $num
-            }
-        }
-        impl Output for crate::peripherals::$name {}
-    };
-}
-
-output!(PWM_OUTPUT0, 0);
-output!(PWM_OUTPUT1, 1);
-output!(PWM_OUTPUT2, 2);
-output!(PWM_OUTPUT3, 3);
-output!(PWM_OUTPUT4, 4);
-output!(PWM_OUTPUT5, 5);
-output!(PWM_OUTPUT6, 6);
-output!(PWM_OUTPUT7, 7);
-output!(PWM_OUTPUT8, 8);
-output!(PWM_OUTPUT9, 9);
-
-/// PWM Output Channel.
-pub trait OutputChannelPin<T: Output>: crate::gpio::Pin {
-    fn pin_func(&self) -> PioFunc;
-}
-
-macro_rules! impl_pin {
-    ($pin:ident, $output:ident, $func:ident) => {
-        impl crate::pwm::inner::OutputChannelPin<crate::peripherals::$output> for crate::peripherals::$pin {
-            fn pin_func(&self) -> PioFunc {
-                PioFunc::$func
-            }
-        }
-    };
-}
-
-impl_pin!(PIO0_2, PWM_OUTPUT0, ALT3);
-impl_pin!(PIO0_17, PWM_OUTPUT0, ALT4);
-impl_pin!(PIO1_4, PWM_OUTPUT0, ALT4);
-impl_pin!(PIO1_23, PWM_OUTPUT0, ALT2);
-
-impl_pin!(PIO0_3, PWM_OUTPUT1, ALT3);
-impl_pin!(PIO0_18, PWM_OUTPUT1, ALT4);
-impl_pin!(PIO1_8, PWM_OUTPUT1, ALT4);
-impl_pin!(PIO1_24, PWM_OUTPUT1, ALT2);
-
-impl_pin!(PIO0_10, PWM_OUTPUT2, ALT5);
-impl_pin!(PIO0_15, PWM_OUTPUT2, ALT4);
-impl_pin!(PIO0_19, PWM_OUTPUT2, ALT4);
-impl_pin!(PIO1_9, PWM_OUTPUT2, ALT4);
-impl_pin!(PIO1_25, PWM_OUTPUT2, ALT2);
-
-impl_pin!(PIO0_22, PWM_OUTPUT3, ALT4);
-impl_pin!(PIO0_31, PWM_OUTPUT3, ALT4);
-impl_pin!(PIO1_10, PWM_OUTPUT3, ALT4);
-impl_pin!(PIO1_26, PWM_OUTPUT3, ALT2);
-
-impl_pin!(PIO0_23, PWM_OUTPUT4, ALT4);
-impl_pin!(PIO1_3, PWM_OUTPUT4, ALT4);
-impl_pin!(PIO1_17, PWM_OUTPUT4, ALT4);
-
-impl_pin!(PIO0_26, PWM_OUTPUT5, ALT4);
-impl_pin!(PIO1_18, PWM_OUTPUT5, ALT4);
-
-impl_pin!(PIO0_27, PWM_OUTPUT6, ALT4);
-impl_pin!(PIO1_31, PWM_OUTPUT6, ALT4);
-
-impl_pin!(PIO0_28, PWM_OUTPUT7, ALT4);
-impl_pin!(PIO1_19, PWM_OUTPUT7, ALT2);
-
-impl_pin!(PIO0_29, PWM_OUTPUT8, ALT4);
-
-impl_pin!(PIO0_30, PWM_OUTPUT9, ALT4);
diff --git a/embassy-nxp/src/sct.rs b/embassy-nxp/src/sct.rs
new file mode 100644
index 000000000..b6b0e35a9
--- /dev/null
+++ b/embassy-nxp/src/sct.rs
@@ -0,0 +1,56 @@
+#![macro_use]
+
+use embassy_hal_internal::PeripheralType;
+use nxp_pac::iocon::vals::PioFunc;
+
+use crate::gpio;
+
+/// SCT instance.
+#[allow(private_bounds)]
+pub trait Instance: SealedInstance + PeripheralType {}
+
+pub(crate) trait SealedInstance {}
+
+/// An SCT output.
+#[allow(private_bounds)]
+pub trait Output<T: Instance>: SealedOutput + PeripheralType {}
+
+pub(crate) trait SealedOutput {
+    /// Output number.
+    fn number(&self) -> usize;
+}
+
+/// An SCT output capable pin.
+pub trait OutputPin<T: Instance, O: Output<T>>: gpio::Pin {
+    fn pin_func(&self) -> PioFunc;
+}
+
+macro_rules! impl_sct_instance {
+    ($instance: ident) => {
+        impl crate::sct::SealedInstance for crate::peripherals::$instance {}
+        impl crate::sct::Instance for crate::peripherals::$instance {}
+    };
+}
+
+macro_rules! impl_sct_output_instance {
+    ($instance: ident, $name: ident, $num: expr) => {
+        impl crate::sct::SealedOutput for crate::peripherals::$name {
+            fn number(&self) -> usize {
+                $num as usize
+            }
+        }
+        impl crate::sct::Output<crate::peripherals::$instance> for crate::peripherals::$name {}
+    };
+}
+
+macro_rules! impl_sct_output_pin {
+    ($instance: ident, $output_instance: ident, $pin: ident, $alt: ident) => {
+        impl crate::sct::OutputPin<crate::peripherals::$instance, crate::peripherals::$output_instance>
+            for crate::peripherals::$pin
+        {
+            fn pin_func(&self) -> crate::pac::iocon::vals::PioFunc {
+                crate::pac::iocon::vals::PioFunc::$alt
+            }
+        }
+    };
+}
diff --git a/embassy-nxp/src/usart.rs b/embassy-nxp/src/usart.rs
index 1d8886f24..af039dee4 100644
--- a/embassy-nxp/src/usart.rs
+++ b/embassy-nxp/src/usart.rs
@@ -1,3 +1,5 @@
+#![macro_use]
+
 //! Universal Synchronous/Asynchronous Receiver/Transmitter (USART) driver.
 
 #[cfg_attr(feature = "lpc55-core0", path = "./usart/lpc55.rs")]
diff --git a/embassy-nxp/src/usart/lpc55.rs b/embassy-nxp/src/usart/lpc55.rs
index d54927b25..d77f08fd8 100644
--- a/embassy-nxp/src/usart/lpc55.rs
+++ b/embassy-nxp/src/usart/lpc55.rs
@@ -1,3 +1,5 @@
+#![macro_use]
+
 use core::fmt::Debug;
 use core::future::poll_fn;
 use core::marker::PhantomData;
@@ -13,7 +15,7 @@ use embedded_io::{self, ErrorKind};
 use crate::dma::{AnyChannel, Channel};
 use crate::gpio::{AnyPin, SealedPin};
 use crate::interrupt::Interrupt;
-use crate::interrupt::typelevel::{Binding, Interrupt as _};
+use crate::interrupt::typelevel::Binding;
 use crate::pac::flexcomm::Flexcomm as FlexcommReg;
 use crate::pac::iocon::vals::PioFunc;
 use crate::pac::usart::Usart as UsartReg;
@@ -113,8 +115,8 @@ impl Default for Config {
 
 /// Internal DMA state of UART RX.
 pub struct DmaState {
-    rx_err_waker: AtomicWaker,
-    rx_err: AtomicBool,
+    pub(crate) rx_err_waker: AtomicWaker,
+    pub(crate) rx_err: AtomicBool,
 }
 
 /// # Type parameters
@@ -818,13 +820,13 @@ impl<'d> embedded_io::Read for Usart<'d, Blocking> {
     }
 }
 
-struct Info {
-    usart_reg: UsartReg,
-    fc_reg: FlexcommReg,
-    interrupt: Interrupt,
+pub(crate) struct Info {
+    pub(crate) usart_reg: UsartReg,
+    pub(crate) fc_reg: FlexcommReg,
+    pub(crate) interrupt: Interrupt,
 }
 
-trait SealedInstance {
+pub(crate) trait SealedInstance {
     fn info() -> &'static Info;
     fn dma_state() -> &'static DmaState;
     fn instance_number() -> usize;
@@ -837,10 +839,13 @@ pub trait Instance: SealedInstance + PeripheralType {
     type Interrupt: crate::interrupt::typelevel::Interrupt;
 }
 
-macro_rules! impl_instance {
+macro_rules! impl_usart_instance {
     ($inst:ident, $fc:ident, $fc_num:expr) => {
-        impl $crate::usart::inner::SealedInstance for $crate::peripherals::$inst {
-            fn info() -> &'static Info {
+        impl crate::usart::SealedInstance for $crate::peripherals::$inst {
+            fn info() -> &'static crate::usart::Info {
+                use crate::interrupt::typelevel::Interrupt;
+                use crate::usart::Info;
+
                 static INFO: Info = Info {
                     usart_reg: crate::pac::$inst,
                     fc_reg: crate::pac::$fc,
@@ -849,7 +854,13 @@ macro_rules! impl_instance {
                 &INFO
             }
 
-            fn dma_state() -> &'static DmaState {
+            fn dma_state() -> &'static crate::usart::DmaState {
+                use core::sync::atomic::AtomicBool;
+
+                use embassy_sync::waitqueue::AtomicWaker;
+
+                use crate::usart::DmaState;
+
                 static STATE: DmaState = DmaState {
                     rx_err_waker: AtomicWaker::new(),
                     rx_err: AtomicBool::new(false),
@@ -867,15 +878,6 @@ macro_rules! impl_instance {
     };
 }
 
-impl_instance!(USART0, FLEXCOMM0, 0);
-impl_instance!(USART1, FLEXCOMM1, 1);
-impl_instance!(USART2, FLEXCOMM2, 2);
-impl_instance!(USART3, FLEXCOMM3, 3);
-impl_instance!(USART4, FLEXCOMM4, 4);
-impl_instance!(USART5, FLEXCOMM5, 5);
-impl_instance!(USART6, FLEXCOMM6, 6);
-impl_instance!(USART7, FLEXCOMM7, 7);
-
 pub(crate) trait SealedTxPin<T: Instance>: crate::gpio::Pin {
     fn pin_func(&self) -> PioFunc;
 }
@@ -892,75 +894,46 @@ pub trait TxPin<T: Instance>: SealedTxPin<T> + crate::gpio::Pin {}
 #[allow(private_bounds)]
 pub trait RxPin<T: Instance>: SealedRxPin<T> + crate::gpio::Pin {}
 
-macro_rules! impl_tx_pin {
+macro_rules! impl_usart_txd_pin {
     ($pin:ident, $instance:ident, $func: ident) => {
-        impl SealedTxPin<crate::peripherals::$instance> for crate::peripherals::$pin {
-            fn pin_func(&self) -> PioFunc {
+        impl crate::usart::SealedTxPin<crate::peripherals::$instance> for crate::peripherals::$pin {
+            fn pin_func(&self) -> crate::pac::iocon::vals::PioFunc {
+                use crate::pac::iocon::vals::PioFunc;
                 PioFunc::$func
             }
         }
 
-        impl TxPin<crate::peripherals::$instance> for crate::peripherals::$pin {}
+        impl crate::usart::TxPin<crate::peripherals::$instance> for crate::peripherals::$pin {}
     };
 }
 
-macro_rules! impl_rx_pin {
+macro_rules! impl_usart_rxd_pin {
     ($pin:ident, $instance:ident, $func: ident) => {
-        impl SealedRxPin<crate::peripherals::$instance> for crate::peripherals::$pin {
-            fn pin_func(&self) -> PioFunc {
+        impl crate::usart::SealedRxPin<crate::peripherals::$instance> for crate::peripherals::$pin {
+            fn pin_func(&self) -> crate::pac::iocon::vals::PioFunc {
+                use crate::pac::iocon::vals::PioFunc;
                 PioFunc::$func
             }
         }
 
-        impl RxPin<crate::peripherals::$instance> for crate::peripherals::$pin {}
+        impl crate::usart::RxPin<crate::peripherals::$instance> for crate::peripherals::$pin {}
     };
 }
 
-impl_tx_pin!(PIO1_6, USART0, ALT1);
-impl_tx_pin!(PIO1_11, USART1, ALT2);
-impl_tx_pin!(PIO0_27, USART2, ALT1);
-impl_tx_pin!(PIO0_2, USART3, ALT1);
-impl_tx_pin!(PIO0_16, USART4, ALT1);
-impl_tx_pin!(PIO0_9, USART5, ALT3);
-impl_tx_pin!(PIO1_16, USART6, ALT2);
-impl_tx_pin!(PIO0_19, USART7, ALT7);
-
-impl_rx_pin!(PIO1_5, USART0, ALT1);
-impl_rx_pin!(PIO1_10, USART1, ALT2);
-impl_rx_pin!(PIO1_24, USART2, ALT1);
-impl_rx_pin!(PIO0_3, USART3, ALT1);
-impl_rx_pin!(PIO0_5, USART4, ALT2);
-impl_rx_pin!(PIO0_8, USART5, ALT3);
-impl_rx_pin!(PIO1_13, USART6, ALT2);
-impl_rx_pin!(PIO0_20, USART7, ALT7);
-
-/// Trait for TX DMA channels.
+/// Marker trait indicating a DMA channel may be used for USART transmit.
 pub trait TxChannel<T: Instance>: crate::dma::Channel {}
-/// Trait for RX DMA channels.
+
+/// Marker trait indicating a DMA channel may be used for USART recieve.
 pub trait RxChannel<T: Instance>: crate::dma::Channel {}
 
-macro_rules! impl_channel {
-    ($dma:ident, $instance:ident, Tx) => {
-        impl TxChannel<crate::peripherals::$instance> for crate::peripherals::$dma {}
-    };
-    ($dma:ident, $instance:ident, Rx) => {
-        impl RxChannel<crate::peripherals::$instance> for crate::peripherals::$dma {}
+macro_rules! impl_usart_tx_channel {
+    ($instance: ident, $channel: ident) => {
+        impl crate::usart::TxChannel<crate::peripherals::$instance> for crate::peripherals::$channel {}
     };
 }
 
-impl_channel!(DMA_CH4, USART0, Rx);
-impl_channel!(DMA_CH5, USART0, Tx);
-impl_channel!(DMA_CH6, USART1, Rx);
-impl_channel!(DMA_CH7, USART1, Tx);
-impl_channel!(DMA_CH10, USART2, Rx);
-impl_channel!(DMA_CH11, USART2, Tx);
-impl_channel!(DMA_CH8, USART3, Rx);
-impl_channel!(DMA_CH9, USART3, Tx);
-impl_channel!(DMA_CH12, USART4, Rx);
-impl_channel!(DMA_CH13, USART4, Tx);
-impl_channel!(DMA_CH14, USART5, Rx);
-impl_channel!(DMA_CH15, USART5, Tx);
-impl_channel!(DMA_CH16, USART6, Rx);
-impl_channel!(DMA_CH17, USART6, Tx);
-impl_channel!(DMA_CH18, USART7, Rx);
-impl_channel!(DMA_CH19, USART7, Tx);
+macro_rules! impl_usart_rx_channel {
+    ($instance: ident, $channel: ident) => {
+        impl crate::usart::RxChannel<crate::peripherals::$instance> for crate::peripherals::$channel {}
+    };
+}
diff --git a/embassy-rp/CHANGELOG.md b/embassy-rp/CHANGELOG.md
index 3b3cb5351..fa8609bbf 100644
--- a/embassy-rp/CHANGELOG.md
+++ b/embassy-rp/CHANGELOG.md
@@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 <!-- next-header -->
 ## Unreleased - ReleaseDate
 
+- Add documentation for pio `get_x` about autopush.
 - Fix several minor typos in documentation
 - Add PIO SPI
 - Add PIO I2S input
@@ -17,6 +18,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Add reset_to_usb_boot for rp235x ([#4705](https://github.com/embassy-rs/embassy/pull/4705))
 - Add fix #4822 in PIO onewire. Change to disable the state machine before setting y register ([#4824](https://github.com/embassy-rs/embassy/pull/4824))
 - Add PIO::Ws2812 color order support
+- Add TX-only, no SCK SPI support
 
 ## 0.8.0 - 2025-08-26
 
@@ -114,3 +116,4 @@ Small release fixing a few gnarly bugs, upgrading is strongly recommended.
 - rename the Channel trait to Slice and the PwmPin to PwmChannel
 - i2c: Fix race condition that appears on fast repeated transfers.
 - Add a basic "read to break" function
+
diff --git a/embassy-rp/src/pio/instr.rs b/embassy-rp/src/pio/instr.rs
index b15d507de..304ddb20a 100644
--- a/embassy-rp/src/pio/instr.rs
+++ b/embassy-rp/src/pio/instr.rs
@@ -5,6 +5,10 @@ use crate::pio::{Instance, StateMachine};
 
 impl<'d, PIO: Instance, const SM: usize> StateMachine<'d, PIO, SM> {
     /// Set value of scratch register X.
+    ///
+    /// SAFETY: autopull enabled else it will write undefined data.
+    /// Make sure to have setup the according configuration see
+    /// [shift_out](crate::pio::Config::shift_out) and [auto_fill](crate::pio::ShiftConfig::auto_fill).
     pub unsafe fn set_x(&mut self, value: u32) {
         const OUT: u16 = InstructionOperands::OUT {
             destination: OutDestination::X,
@@ -16,6 +20,10 @@ impl<'d, PIO: Instance, const SM: usize> StateMachine<'d, PIO, SM> {
     }
 
     /// Get value of scratch register X.
+    ///
+    /// SAFETY: autopush enabled else it will read undefined data.
+    /// Make sure to have setup the according configurations see
+    /// [shift_in](crate::pio::Config::shift_in) and [auto_fill](crate::pio::ShiftConfig::auto_fill).
     pub unsafe fn get_x(&mut self) -> u32 {
         const IN: u16 = InstructionOperands::IN {
             source: InSource::X,
@@ -27,6 +35,10 @@ impl<'d, PIO: Instance, const SM: usize> StateMachine<'d, PIO, SM> {
     }
 
     /// Set value of scratch register Y.
+    ///
+    /// SAFETY: autopull enabled else it will write undefined data.
+    /// Make sure to have setup the according configuration see
+    /// [shift_out](crate::pio::Config::shift_out) and [auto_fill](crate::pio::ShiftConfig::auto_fill).
     pub unsafe fn set_y(&mut self, value: u32) {
         const OUT: u16 = InstructionOperands::OUT {
             destination: OutDestination::Y,
@@ -38,6 +50,10 @@ impl<'d, PIO: Instance, const SM: usize> StateMachine<'d, PIO, SM> {
     }
 
     /// Get value of scratch register Y.
+    ///
+    /// SAFETY: autopush enabled else it will read undefined data.
+    /// Make sure to have setup the according configurations see
+    /// [shift_in](crate::pio::Config::shift_in) and [auto_fill](crate::pio::ShiftConfig::auto_fill).
     pub unsafe fn get_y(&mut self) -> u32 {
         const IN: u16 = InstructionOperands::IN {
             source: InSource::Y,
diff --git a/embassy-rp/src/spi.rs b/embassy-rp/src/spi.rs
index d9410e78d..39f128214 100644
--- a/embassy-rp/src/spi.rs
+++ b/embassy-rp/src/spi.rs
@@ -308,6 +308,11 @@ impl<'d, T: Instance> Spi<'d, T, Blocking> {
         )
     }
 
+    /// Create an SPI driver in blocking mode supporting writes only, without SCK pin.
+    pub fn new_blocking_txonly_nosck(inner: Peri<'d, T>, mosi: Peri<'d, impl MosiPin<T> + 'd>, config: Config) -> Self {
+        Self::new_inner(inner, None, Some(mosi.into()), None, None, None, None, config)
+    }
+
     /// Create an SPI driver in blocking mode supporting reads only.
     pub fn new_blocking_rxonly(
         inner: Peri<'d, T>,
@@ -371,6 +376,26 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
         )
     }
 
+    /// Create an SPI driver in async mode supporting DMA write operations only,
+    /// without SCK pin.
+    pub fn new_txonly_nosck(
+        inner: Peri<'d, T>,
+        mosi: Peri<'d, impl MosiPin<T> + 'd>,
+        tx_dma: Peri<'d, impl Channel>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(
+            inner,
+            None,
+            Some(mosi.into()),
+            None,
+            None,
+            Some(tx_dma.into()),
+            None,
+            config,
+        )
+    }
+
     /// Create an SPI driver in async mode supporting DMA read operations only.
     pub fn new_rxonly(
         inner: Peri<'d, T>,
diff --git a/embassy-stm32-wpan/CHANGELOG.md b/embassy-stm32-wpan/CHANGELOG.md
index 7042ad14c..eb17856fc 100644
--- a/embassy-stm32-wpan/CHANGELOG.md
+++ b/embassy-stm32-wpan/CHANGELOG.md
@@ -8,4 +8,6 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 <!-- next-header -->
 ## Unreleased - ReleaseDate
 
+- wpan: restructure hil and test wpan mac
+- restructure to allow embassy net driver to work.
 - First release with changelog.
diff --git a/embassy-stm32-wpan/Cargo.toml b/embassy-stm32-wpan/Cargo.toml
index 0802b7328..05d76f4a6 100644
--- a/embassy-stm32-wpan/Cargo.toml
+++ b/embassy-stm32-wpan/Cargo.toml
@@ -33,6 +33,7 @@ embassy-futures = { version = "0.1.2", path = "../embassy-futures" }
 embassy-hal-internal = { version = "0.3.0", path = "../embassy-hal-internal" }
 embassy-embedded-hal = { version = "0.5.0", path = "../embassy-embedded-hal" }
 embassy-net-driver = { version = "0.2.0", path = "../embassy-net-driver", optional=true }
+smoltcp = { version = "0.12.0", optional=true, default-features = false }
 
 defmt = { version = "1.0.1", optional = true }
 log = { version = "0.4.17", optional = true }
@@ -40,6 +41,7 @@ log = { version = "0.4.17", optional = true }
 cortex-m = "0.7.6"
 heapless = "0.8"
 aligned = "0.4.1"
+critical-section = "1.1"
 
 bit_field = "0.10.2"
 stm32-device-signature = { version = "0.3.3", features = ["stm32wb5x"] }
@@ -51,7 +53,7 @@ bitflags = { version = "2.3.3", optional = true }
 defmt = ["dep:defmt", "embassy-sync/defmt", "embassy-embedded-hal/defmt", "embassy-hal-internal/defmt", "stm32wb-hci?/defmt"]
 
 ble = ["dep:stm32wb-hci"]
-mac = ["dep:bitflags", "dep:embassy-net-driver" ]
+mac = ["dep:bitflags", "dep:embassy-net-driver", "dep:smoltcp", "smoltcp/medium-ieee802154"]
 
 extended = []
 
diff --git a/embassy-stm32-wpan/src/channels.rs b/embassy-stm32-wpan/src/channels.rs
index 9a2be1cfa..58f857136 100644
--- a/embassy-stm32-wpan/src/channels.rs
+++ b/embassy-stm32-wpan/src/channels.rs
@@ -48,9 +48,20 @@
 //!  |<----HW_IPCC_TRACES_CHANNEL----------------------|
 //!  |                                                 |
 //!
+//!
+
+#[repr(u8)]
+pub enum IpccChannel {
+    Channel1 = 1,
+    Channel2 = 2,
+    Channel3 = 3,
+    Channel4 = 4,
+    Channel5 = 5,
+    Channel6 = 6,
+}
 
 pub mod cpu1 {
-    use embassy_stm32::ipcc::IpccChannel;
+    use super::IpccChannel;
 
     pub const IPCC_BLE_CMD_CHANNEL: IpccChannel = IpccChannel::Channel1;
     pub const IPCC_SYSTEM_CMD_RSP_CHANNEL: IpccChannel = IpccChannel::Channel2;
@@ -70,7 +81,7 @@ pub mod cpu1 {
 }
 
 pub mod cpu2 {
-    use embassy_stm32::ipcc::IpccChannel;
+    use super::IpccChannel;
 
     pub const IPCC_BLE_EVENT_CHANNEL: IpccChannel = IpccChannel::Channel1;
     pub const IPCC_SYSTEM_EVENT_CHANNEL: IpccChannel = IpccChannel::Channel2;
diff --git a/embassy-stm32-wpan/src/cmd.rs b/embassy-stm32-wpan/src/cmd.rs
index 5c81a4aa7..787c22c4b 100644
--- a/embassy-stm32-wpan/src/cmd.rs
+++ b/embassy-stm32-wpan/src/cmd.rs
@@ -1,4 +1,5 @@
 use core::ptr;
+use core::sync::atomic::{Ordering, compiler_fence};
 
 use crate::PacketHeader;
 use crate::consts::TlPacketType;
@@ -45,11 +46,11 @@ pub struct CmdPacket {
 
 impl CmdPacket {
     pub unsafe fn write_into(cmd_buf: *mut CmdPacket, packet_type: TlPacketType, cmd_code: u16, payload: &[u8]) {
-        let p_cmd_serial = &mut (*cmd_buf).cmdserial as *mut _ as *mut CmdSerialStub;
-        let p_payload = &mut (*cmd_buf).cmdserial.cmd.payload as *mut _;
+        let p_cmd_serial = (cmd_buf as *mut u8).add(size_of::<PacketHeader>());
+        let p_payload = p_cmd_serial.add(size_of::<CmdSerialStub>());
 
-        ptr::write_volatile(
-            p_cmd_serial,
+        ptr::write_unaligned(
+            p_cmd_serial as *mut _,
             CmdSerialStub {
                 ty: packet_type as u8,
                 cmd_code,
@@ -58,6 +59,8 @@ impl CmdPacket {
         );
 
         ptr::copy_nonoverlapping(payload as *const _ as *const u8, p_payload, payload.len());
+
+        compiler_fence(Ordering::Release);
     }
 }
 
@@ -87,11 +90,11 @@ pub struct AclDataPacket {
 
 impl AclDataPacket {
     pub unsafe fn write_into(cmd_buf: *mut AclDataPacket, packet_type: TlPacketType, handle: u16, payload: &[u8]) {
-        let p_cmd_serial = &mut (*cmd_buf).acl_data_serial as *mut _ as *mut AclDataSerialStub;
-        let p_payload = &mut (*cmd_buf).acl_data_serial.acl_data as *mut _;
+        let p_cmd_serial = (cmd_buf as *mut u8).add(size_of::<PacketHeader>());
+        let p_payload = p_cmd_serial.add(size_of::<AclDataSerialStub>());
 
-        ptr::write_volatile(
-            p_cmd_serial,
+        ptr::write_unaligned(
+            p_cmd_serial as *mut _,
             AclDataSerialStub {
                 ty: packet_type as u8,
                 handle: handle,
@@ -100,5 +103,7 @@ impl AclDataPacket {
         );
 
         ptr::copy_nonoverlapping(payload as *const _ as *const u8, p_payload, payload.len());
+
+        compiler_fence(Ordering::Release);
     }
 }
diff --git a/embassy-stm32-wpan/src/evt.rs b/embassy-stm32-wpan/src/evt.rs
index c6528413d..f32821269 100644
--- a/embassy-stm32-wpan/src/evt.rs
+++ b/embassy-stm32-wpan/src/evt.rs
@@ -67,6 +67,7 @@ pub struct EvtSerial {
 pub struct EvtStub {
     pub kind: u8,
     pub evt_code: u8,
+    pub payload_len: u8,
 }
 
 /// This format shall be used for all events (asynchronous and command response) reported
diff --git a/embassy-stm32-wpan/src/lib.rs b/embassy-stm32-wpan/src/lib.rs
index f6b1f6021..18b0feada 100644
--- a/embassy-stm32-wpan/src/lib.rs
+++ b/embassy-stm32-wpan/src/lib.rs
@@ -26,7 +26,7 @@ use core::sync::atomic::{Ordering, compiler_fence};
 
 use embassy_hal_internal::Peri;
 use embassy_stm32::interrupt;
-use embassy_stm32::ipcc::{Config, Ipcc, ReceiveInterruptHandler, TransmitInterruptHandler};
+use embassy_stm32::ipcc::{Config, Ipcc, IpccRxChannel, ReceiveInterruptHandler, TransmitInterruptHandler};
 use embassy_stm32::peripherals::IPCC;
 use sub::mm::MemoryManager;
 use sub::sys::Sys;
@@ -53,14 +53,13 @@ type PacketHeader = LinkedListNode;
 
 /// Transport Layer for the Mailbox interface
 pub struct TlMbox<'d> {
-    _ipcc: Peri<'d, IPCC>,
-
-    pub sys_subsystem: Sys,
-    pub mm_subsystem: MemoryManager,
+    pub sys_subsystem: Sys<'d>,
+    pub mm_subsystem: MemoryManager<'d>,
     #[cfg(feature = "ble")]
-    pub ble_subsystem: sub::ble::Ble,
+    pub ble_subsystem: sub::ble::Ble<'d>,
     #[cfg(feature = "mac")]
-    pub mac_subsystem: sub::mac::Mac,
+    pub mac_subsystem: sub::mac::Mac<'d>,
+    pub traces: IpccRxChannel<'d>,
 }
 
 impl<'d> TlMbox<'d> {
@@ -92,7 +91,7 @@ impl<'d> TlMbox<'d> {
     /// be handled by `TL_BLE_Init`; see Figure 66). This completes the procedure laid out in
     /// Figure 66.
     // TODO: document what the user should do after calling init to use the mac_802_15_4 subsystem
-    pub fn init(
+    pub async fn init(
         ipcc: Peri<'d, IPCC>,
         _irqs: impl interrupt::typelevel::Binding<interrupt::typelevel::IPCC_C1_RX, ReceiveInterruptHandler>
         + interrupt::typelevel::Binding<interrupt::typelevel::IPCC_C1_TX, TransmitInterruptHandler>,
@@ -185,16 +184,35 @@ impl<'d> TlMbox<'d> {
         compiler_fence(Ordering::SeqCst);
 
         // this is equivalent to `HW_IPCC_Enable`, which is called by `TL_Enable`
-        Ipcc::enable(config);
+        let [
+            (_hw_ipcc_ble_cmd_channel, _ipcc_ble_event_channel),
+            (ipcc_system_cmd_rsp_channel, ipcc_system_event_channel),
+            (_ipcc_mac_802_15_4_cmd_rsp_channel, _ipcc_mac_802_15_4_notification_ack_channel),
+            (ipcc_mm_release_buffer_channel, _ipcc_traces_channel),
+            (_ipcc_ble_lld_cmd_channel, _ipcc_ble_lld_rsp_channel),
+            (_ipcc_hci_acl_data_channel, _),
+        ] = Ipcc::new(ipcc, _irqs, config).split();
+
+        let mm = sub::mm::MemoryManager::new(ipcc_mm_release_buffer_channel);
+        let mut sys = sub::sys::Sys::new(ipcc_system_cmd_rsp_channel, ipcc_system_event_channel);
+
+        debug!("sys event: {}", sys.read().await.payload());
 
         Self {
-            _ipcc: ipcc,
-            sys_subsystem: sub::sys::Sys::new(),
+            sys_subsystem: sys,
             #[cfg(feature = "ble")]
-            ble_subsystem: sub::ble::Ble::new(),
+            ble_subsystem: sub::ble::Ble::new(
+                _hw_ipcc_ble_cmd_channel,
+                _ipcc_ble_event_channel,
+                _ipcc_hci_acl_data_channel,
+            ),
             #[cfg(feature = "mac")]
-            mac_subsystem: sub::mac::Mac::new(),
-            mm_subsystem: sub::mm::MemoryManager::new(),
+            mac_subsystem: sub::mac::Mac::new(
+                _ipcc_mac_802_15_4_cmd_rsp_channel,
+                _ipcc_mac_802_15_4_notification_ack_channel,
+            ),
+            mm_subsystem: mm,
+            traces: _ipcc_traces_channel,
         }
     }
 }
diff --git a/embassy-stm32-wpan/src/mac/commands.rs b/embassy-stm32-wpan/src/mac/commands.rs
index 82b9d2772..d96f0094a 100644
--- a/embassy-stm32-wpan/src/mac/commands.rs
+++ b/embassy-stm32-wpan/src/mac/commands.rs
@@ -2,6 +2,8 @@
 
 use core::{mem, slice};
 
+use smoltcp::wire::ieee802154::Frame;
+
 use super::opcodes::OpcodeM4ToM0;
 use super::typedefs::{
     AddressMode, Capabilities, DisassociationReason, GtsCharacteristics, KeyIdMode, MacAddress, MacChannel, MacStatus,
@@ -379,6 +381,35 @@ impl DataRequest {
     }
 }
 
+impl<'a, T: AsRef<[u8]>> TryFrom<Frame<&'a T>> for DataRequest {
+    type Error = ();
+
+    fn try_from(frame: Frame<&'a T>) -> Result<Self, Self::Error> {
+        // TODO: map the rest of these
+
+        let mut request = DataRequest {
+            src_addr_mode: frame.src_addressing_mode().try_into()?,
+            dst_addr_mode: frame.dst_addressing_mode().try_into()?,
+            dst_pan_id: frame.dst_pan_id().ok_or(())?.into(),
+            dst_address: frame.dst_addr().ok_or(())?.into(),
+            msdu_handle: frame.sequence_number().ok_or(())?,
+            key_source: frame.key_source().unwrap_or_default().try_into().unwrap_or_default(),
+            ack_tx: frame.ack_request() as u8,
+            gts_tx: false,
+            security_level: if frame.security_enabled() {
+                SecurityLevel::Secured
+            } else {
+                SecurityLevel::Unsecure
+            },
+            ..Default::default()
+        };
+
+        request.set_buffer(frame.payload().ok_or(())?);
+
+        Ok(request)
+    }
+}
+
 impl Default for DataRequest {
     fn default() -> Self {
         Self {
diff --git a/embassy-stm32-wpan/src/mac/control.rs b/embassy-stm32-wpan/src/mac/control.rs
index e8d2f9f7b..14c6fdd2b 100644
--- a/embassy-stm32-wpan/src/mac/control.rs
+++ b/embassy-stm32-wpan/src/mac/control.rs
@@ -1,65 +1,186 @@
+use core::cell::RefCell;
 use core::future::Future;
+use core::sync::atomic::{Ordering, compiler_fence};
 use core::task;
 use core::task::Poll;
 
+use embassy_net_driver::LinkState;
+use embassy_sync::blocking_mutex;
 use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
-use embassy_sync::mutex::MutexGuard;
+use embassy_sync::mutex::Mutex;
 use embassy_sync::signal::Signal;
 use futures_util::FutureExt;
 
-use super::commands::MacCommand;
-use super::event::MacEvent;
-use super::typedefs::MacError;
-use crate::mac::runner::Runner;
+use crate::mac::commands::*;
+use crate::mac::driver::NetworkState;
+use crate::mac::event::MacEvent;
+use crate::mac::runner::ZeroCopyPubSub;
+use crate::mac::typedefs::*;
+use crate::sub::mac::MacTx;
 
 pub struct Control<'a> {
-    runner: &'a Runner<'a>,
+    rx_event_channel: &'a ZeroCopyPubSub<CriticalSectionRawMutex, MacEvent<'a>>,
+    mac_tx: &'a Mutex<CriticalSectionRawMutex, MacTx<'a>>,
+    #[allow(unused)]
+    network_state: &'a blocking_mutex::Mutex<CriticalSectionRawMutex, RefCell<NetworkState>>,
 }
 
 impl<'a> Control<'a> {
-    pub(crate) fn new(runner: &'a Runner<'a>) -> Self {
-        Self { runner: runner }
+    pub(crate) fn new(
+        rx_event_channel: &'a ZeroCopyPubSub<CriticalSectionRawMutex, MacEvent<'a>>,
+        mac_tx: &'a Mutex<CriticalSectionRawMutex, MacTx<'a>>,
+        network_state: &'a blocking_mutex::Mutex<CriticalSectionRawMutex, RefCell<NetworkState>>,
+    ) -> Self {
+        Self {
+            rx_event_channel,
+            mac_tx,
+            network_state,
+        }
+    }
+
+    pub async fn init_link(&mut self, pan_id: [u8; 2]) {
+        debug!("resetting");
+
+        debug!(
+            "{:#x}",
+            self.send_command_and_get_response(&ResetRequest {
+                set_default_pib: true,
+                ..Default::default()
+            })
+            .await
+            .unwrap()
+            .await
+        );
+
+        let (short_address, mac_address) = critical_section::with(|cs| {
+            let mut network_state = self.network_state.borrow(cs).borrow_mut();
+
+            network_state.pan_id = pan_id;
+
+            (network_state.short_addr, network_state.mac_addr)
+        });
+
+        debug!("setting extended address");
+        debug!(
+            "{:#x}",
+            self.send_command_and_get_response(&SetRequest {
+                pib_attribute_ptr: &u64::from_be_bytes(mac_address) as *const _ as *const u8,
+                pib_attribute: PibId::ExtendedAddress,
+            })
+            .await
+            .unwrap()
+            .await
+        );
+
+        debug!("setting short address");
+        debug!(
+            "{:#x}",
+            self.send_command_and_get_response(&SetRequest {
+                pib_attribute_ptr: &u16::from_be_bytes(short_address) as *const _ as *const u8,
+                pib_attribute: PibId::ShortAddress,
+            })
+            .await
+            .unwrap()
+            .await
+        );
+
+        debug!("setting association permit");
+        let association_permit: bool = true;
+        debug!(
+            "{:#x}",
+            self.send_command_and_get_response(&SetRequest {
+                pib_attribute_ptr: &association_permit as *const _ as *const u8,
+                pib_attribute: PibId::AssociationPermit,
+            })
+            .await
+            .unwrap()
+            .await
+        );
+
+        debug!("setting TX power");
+        let transmit_power: i8 = 2;
+        debug!(
+            "{:#x}",
+            self.send_command_and_get_response(&SetRequest {
+                pib_attribute_ptr: &transmit_power as *const _ as *const u8,
+                pib_attribute: PibId::TransmitPower,
+            })
+            .await
+            .unwrap()
+            .await
+        );
+
+        debug!("starting FFD device");
+        debug!(
+            "{:#x}",
+            self.send_command_and_get_response(&StartRequest {
+                pan_id: PanId(pan_id),
+                channel_number: MacChannel::Channel16,
+                beacon_order: 0x0F,
+                superframe_order: 0x0F,
+                pan_coordinator: true,
+                battery_life_extension: false,
+                ..Default::default()
+            })
+            .await
+            .unwrap()
+            .await
+        );
+
+        debug!("setting RX on when idle");
+        let rx_on_while_idle: bool = true;
+        debug!(
+            "{:#x}",
+            self.send_command_and_get_response(&SetRequest {
+                pib_attribute_ptr: &rx_on_while_idle as *const _ as *const u8,
+                pib_attribute: PibId::RxOnWhenIdle,
+            })
+            .await
+            .unwrap()
+            .await
+        );
+
+        critical_section::with(|cs| {
+            let mut network_state = self.network_state.borrow(cs).borrow_mut();
+
+            network_state.link_state = LinkState::Up;
+            network_state.link_waker.wake();
+        });
     }
 
     pub async fn send_command<T>(&self, cmd: &T) -> Result<(), MacError>
     where
         T: MacCommand,
     {
-        let _wm = self.runner.write_mutex.lock().await;
-
-        self.runner.mac_subsystem.send_command(cmd).await
+        self.mac_tx.lock().await.send_command(cmd).await
     }
 
     pub async fn send_command_and_get_response<T>(&self, cmd: &T) -> Result<EventToken<'a>, MacError>
     where
         T: MacCommand,
     {
-        let rm = self.runner.read_mutex.lock().await;
-        let _wm = self.runner.write_mutex.lock().await;
-        let token = EventToken::new(self.runner, rm);
+        let token = EventToken::new(self.rx_event_channel);
 
-        self.runner.mac_subsystem.send_command(cmd).await?;
+        compiler_fence(Ordering::Release);
+
+        self.mac_tx.lock().await.send_command(cmd).await?;
 
         Ok(token)
     }
 }
 
 pub struct EventToken<'a> {
-    runner: &'a Runner<'a>,
-    _mutex_guard: MutexGuard<'a, CriticalSectionRawMutex, ()>,
+    rx_event_channel: &'a ZeroCopyPubSub<CriticalSectionRawMutex, MacEvent<'a>>,
 }
 
 impl<'a> EventToken<'a> {
-    pub(crate) fn new(runner: &'a Runner<'a>, mutex_guard: MutexGuard<'a, CriticalSectionRawMutex, ()>) -> Self {
+    pub(crate) fn new(rx_event_channel: &'a ZeroCopyPubSub<CriticalSectionRawMutex, MacEvent<'a>>) -> Self {
         // Enable event receiving
-        runner.rx_event_channel.lock(|s| {
+        rx_event_channel.lock(|s| {
             *s.borrow_mut() = Some(Signal::new());
         });
 
-        Self {
-            runner: runner,
-            _mutex_guard: mutex_guard,
-        }
+        Self { rx_event_channel }
     }
 }
 
@@ -67,20 +188,8 @@ impl<'a> Future for EventToken<'a> {
     type Output = MacEvent<'a>;
 
     fn poll(self: core::pin::Pin<&mut Self>, cx: &mut task::Context<'_>) -> Poll<Self::Output> {
-        self.get_mut().runner.rx_event_channel.lock(|s| {
-            let signal = s.borrow_mut();
-            let signal = match &*signal {
-                Some(s) => s,
-                _ => unreachable!(),
-            };
-
-            let result = match signal.wait().poll_unpin(cx) {
-                Poll::Ready(mac_event) => Poll::Ready(mac_event),
-                Poll::Pending => Poll::Pending,
-            };
-
-            result
-        })
+        self.rx_event_channel
+            .lock(|s| s.borrow_mut().as_mut().unwrap().wait().poll_unpin(cx))
     }
 }
 
@@ -88,7 +197,7 @@ impl<'a> Drop for EventToken<'a> {
     fn drop(&mut self) {
         // Disable event receiving
         // This will also drop the contained event, if it exists, and will free up receiving the next event
-        self.runner.rx_event_channel.lock(|s| {
+        self.rx_event_channel.lock(|s| {
             *s.borrow_mut() = None;
         });
     }
diff --git a/embassy-stm32-wpan/src/mac/driver.rs b/embassy-stm32-wpan/src/mac/driver.rs
index 480ac3790..41171ce3d 100644
--- a/embassy-stm32-wpan/src/mac/driver.rs
+++ b/embassy-stm32-wpan/src/mac/driver.rs
@@ -1,22 +1,108 @@
 #![deny(unused_must_use)]
 
+use core::cell::RefCell;
 use core::task::Context;
 
 use embassy_net_driver::{Capabilities, HardwareAddress, LinkState};
+use embassy_sync::blocking_mutex;
 use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_sync::channel::Channel;
+use embassy_sync::mutex::Mutex;
+use embassy_sync::waitqueue::AtomicWaker;
 
-use crate::mac::MTU;
 use crate::mac::event::MacEvent;
-use crate::mac::runner::Runner;
+use crate::mac::indications::{write_frame_from_beacon_indication, write_frame_from_data_indication};
+use crate::mac::runner::{BUF_SIZE, ZeroCopyPubSub};
+use crate::mac::{Control, MTU, Runner};
+use crate::sub::mac::{Mac, MacRx, MacTx};
+
+pub struct NetworkState {
+    pub mac_addr: [u8; 8],
+    pub short_addr: [u8; 2],
+    pub pan_id: [u8; 2],
+    pub link_state: LinkState,
+    pub link_waker: AtomicWaker,
+}
+
+impl NetworkState {
+    pub const fn new() -> Self {
+        Self {
+            mac_addr: [0u8; 8],
+            short_addr: [0u8; 2],
+            pan_id: [0u8; 2],
+            link_state: LinkState::Down,
+            link_waker: AtomicWaker::new(),
+        }
+    }
+}
+
+pub struct DriverState<'d> {
+    pub mac_tx: Mutex<CriticalSectionRawMutex, MacTx<'d>>,
+    pub mac_rx: MacRx<'d>,
+    pub rx_event_channel: ZeroCopyPubSub<CriticalSectionRawMutex, MacEvent<'d>>,
+    pub rx_data_channel: Channel<CriticalSectionRawMutex, MacEvent<'d>, 1>,
+    pub tx_data_channel: Channel<CriticalSectionRawMutex, (&'d mut [u8; MTU], usize), BUF_SIZE>,
+    pub tx_buf_channel: Channel<CriticalSectionRawMutex, &'d mut [u8; MTU], BUF_SIZE>,
+    pub tx_buf_queue: [[u8; MTU]; BUF_SIZE],
+    pub network_state: blocking_mutex::Mutex<CriticalSectionRawMutex, RefCell<NetworkState>>,
+}
+
+impl<'d> DriverState<'d> {
+    pub const fn new(mac: Mac<'d>) -> Self {
+        let (mac_rx, mac_tx) = mac.split();
+        let mac_tx = Mutex::new(mac_tx);
+
+        Self {
+            mac_tx,
+            mac_rx,
+            rx_event_channel: ZeroCopyPubSub::new(RefCell::new(None)),
+            rx_data_channel: Channel::new(),
+            tx_data_channel: Channel::new(),
+            tx_buf_channel: Channel::new(),
+            tx_buf_queue: [[0u8; MTU]; BUF_SIZE],
+            network_state: blocking_mutex::Mutex::new(RefCell::new(NetworkState::new())),
+        }
+    }
+}
 
 pub struct Driver<'d> {
-    runner: &'d Runner<'d>,
+    tx_data_channel: &'d Channel<CriticalSectionRawMutex, (&'d mut [u8; MTU], usize), BUF_SIZE>,
+    tx_buf_channel: &'d Channel<CriticalSectionRawMutex, &'d mut [u8; MTU], BUF_SIZE>,
+    rx_data_channel: &'d Channel<CriticalSectionRawMutex, MacEvent<'d>, 1>,
+    network_state: &'d blocking_mutex::Mutex<CriticalSectionRawMutex, RefCell<NetworkState>>,
 }
 
 impl<'d> Driver<'d> {
-    pub(crate) fn new(runner: &'d Runner<'d>) -> Self {
-        Self { runner: runner }
+    pub fn new(
+        driver_state: &'d mut DriverState<'d>,
+        short_address: [u8; 2],
+        mac_address: [u8; 8],
+    ) -> (Self, Runner<'d>, Control<'d>) {
+        (
+            Self {
+                tx_data_channel: &driver_state.tx_data_channel,
+                tx_buf_channel: &driver_state.tx_buf_channel,
+                rx_data_channel: &driver_state.rx_data_channel,
+                network_state: &driver_state.network_state,
+            },
+            Runner::new(
+                &driver_state.rx_event_channel,
+                &driver_state.rx_data_channel,
+                &mut driver_state.mac_rx,
+                &driver_state.tx_data_channel,
+                &driver_state.tx_buf_channel,
+                &driver_state.mac_tx,
+                &mut driver_state.tx_buf_queue,
+                &driver_state.network_state,
+                short_address,
+                mac_address,
+            ),
+            Control::new(
+                &driver_state.rx_event_channel,
+                &driver_state.mac_tx,
+                &driver_state.network_state,
+            ),
+        )
     }
 }
 
@@ -33,16 +119,16 @@ impl<'d> embassy_net_driver::Driver for Driver<'d> {
         Self: 'a;
 
     fn receive(&mut self, cx: &mut Context) -> Option<(Self::RxToken<'_>, Self::TxToken<'_>)> {
-        if self.runner.rx_channel.poll_ready_to_receive(cx).is_ready()
-            && self.runner.tx_buf_channel.poll_ready_to_receive(cx).is_ready()
+        if self.rx_data_channel.poll_ready_to_receive(cx).is_ready()
+            && self.tx_buf_channel.poll_ready_to_receive(cx).is_ready()
         {
             Some((
                 RxToken {
-                    rx: &self.runner.rx_channel,
+                    rx: self.rx_data_channel,
                 },
                 TxToken {
-                    tx: &self.runner.tx_channel,
-                    tx_buf: &self.runner.tx_buf_channel,
+                    tx: self.tx_data_channel,
+                    tx_buf: self.tx_buf_channel,
                 },
             ))
         } else {
@@ -51,10 +137,10 @@ impl<'d> embassy_net_driver::Driver for Driver<'d> {
     }
 
     fn transmit(&mut self, cx: &mut Context) -> Option<Self::TxToken<'_>> {
-        if self.runner.tx_buf_channel.poll_ready_to_receive(cx).is_ready() {
+        if self.tx_buf_channel.poll_ready_to_receive(cx).is_ready() {
             Some(TxToken {
-                tx: &self.runner.tx_channel,
-                tx_buf: &self.runner.tx_buf_channel,
+                tx: self.tx_data_channel,
+                tx_buf: self.tx_buf_channel,
             })
         } else {
             None
@@ -68,13 +154,20 @@ impl<'d> embassy_net_driver::Driver for Driver<'d> {
         caps
     }
 
-    fn link_state(&mut self, _cx: &mut Context) -> LinkState {
-        LinkState::Down
+    fn link_state(&mut self, cx: &mut Context) -> LinkState {
+        critical_section::with(|cs| {
+            let network_state = self.network_state.borrow(cs).borrow_mut();
+
+            // Unconditionally register the waker to avoid a race
+            network_state.link_waker.register(cx.waker());
+            network_state.link_state
+        })
     }
 
     fn hardware_address(&self) -> HardwareAddress {
-        // self.mac_addr
-        HardwareAddress::Ieee802154([0; 8])
+        HardwareAddress::Ieee802154(critical_section::with(|cs| {
+            self.network_state.borrow(cs).borrow().mac_addr
+        }))
     }
 }
 
@@ -87,20 +180,20 @@ impl<'d> embassy_net_driver::RxToken for RxToken<'d> {
     where
         F: FnOnce(&mut [u8]) -> R,
     {
-        // Only valid data events should be put into the queue
-
-        let data_event = match self.rx.try_receive().unwrap() {
-            MacEvent::McpsDataInd(data_event) => data_event,
-            _ => unreachable!(),
+        let mut buffer = [0u8; MTU];
+        match self.rx.try_receive().unwrap() {
+            MacEvent::McpsDataInd(data_event) => write_frame_from_data_indication(data_event, &mut buffer),
+            MacEvent::MlmeBeaconNotifyInd(data_event) => write_frame_from_beacon_indication(data_event, &mut buffer),
+            _ => {}
         };
 
-        f(&mut data_event.payload())
+        f(&mut buffer[..])
     }
 }
 
 pub struct TxToken<'d> {
-    tx: &'d Channel<CriticalSectionRawMutex, (&'d mut [u8; MTU], usize), 5>,
-    tx_buf: &'d Channel<CriticalSectionRawMutex, &'d mut [u8; MTU], 5>,
+    tx: &'d Channel<CriticalSectionRawMutex, (&'d mut [u8; MTU], usize), BUF_SIZE>,
+    tx_buf: &'d Channel<CriticalSectionRawMutex, &'d mut [u8; MTU], BUF_SIZE>,
 }
 
 impl<'d> embassy_net_driver::TxToken for TxToken<'d> {
diff --git a/embassy-stm32-wpan/src/mac/event.rs b/embassy-stm32-wpan/src/mac/event.rs
index 9ca4f5a2a..39856e185 100644
--- a/embassy-stm32-wpan/src/mac/event.rs
+++ b/embassy-stm32-wpan/src/mac/event.rs
@@ -10,7 +10,7 @@ use super::responses::{
 };
 use crate::evt::{EvtBox, MemoryManager};
 use crate::mac::opcodes::OpcodeM0ToM4;
-use crate::sub::mac::{self, Mac};
+use crate::sub::mac::{self, MacRx};
 
 pub(crate) trait ParseableMacEvent: Sized {
     fn from_buffer<'a>(buf: &'a [u8]) -> Result<&'a Self, ()> {
@@ -53,7 +53,7 @@ pub enum MacEvent<'a> {
 }
 
 impl<'a> MacEvent<'a> {
-    pub(crate) fn new(event_box: EvtBox<Mac>) -> Result<Self, ()> {
+    pub(crate) fn new(event_box: EvtBox<MacRx>) -> Result<Self, ()> {
         let payload = event_box.payload();
         let opcode = u16::from_le_bytes(payload[0..2].try_into().unwrap());
 
@@ -148,6 +148,6 @@ unsafe impl<'a> Send for MacEvent<'a> {}
 
 impl<'a> Drop for MacEvent<'a> {
     fn drop(&mut self) {
-        unsafe { mac::Mac::drop_event_packet(ptr::null_mut()) };
+        unsafe { mac::MacRx::drop_event_packet(ptr::null_mut()) };
     }
 }
diff --git a/embassy-stm32-wpan/src/mac/indications.rs b/embassy-stm32-wpan/src/mac/indications.rs
index c0b86d745..5673514c9 100644
--- a/embassy-stm32-wpan/src/mac/indications.rs
+++ b/embassy-stm32-wpan/src/mac/indications.rs
@@ -1,11 +1,15 @@
 use core::slice;
 
+use smoltcp::wire::Ieee802154FrameType;
+use smoltcp::wire::ieee802154::Frame;
+
 use super::consts::MAX_PENDING_ADDRESS;
 use super::event::ParseableMacEvent;
 use super::typedefs::{
     AddressMode, Capabilities, DisassociationReason, KeyIdMode, MacAddress, MacChannel, MacStatus, PanDescriptor,
     PanId, SecurityLevel,
 };
+use crate::mac::typedefs::MacAddressAndMode;
 
 /// MLME ASSOCIATE Indication which will be used by the MAC
 /// to indicate the reception of an association request command
@@ -74,6 +78,22 @@ pub struct BeaconNotifyIndication {
 
 impl ParseableMacEvent for BeaconNotifyIndication {}
 
+impl BeaconNotifyIndication {
+    pub fn payload<'a>(&'a self) -> &'a mut [u8] {
+        unsafe { slice::from_raw_parts_mut(self.sdu_ptr as *mut _, self.sdu_length as usize) }
+    }
+}
+
+pub fn write_frame_from_beacon_indication<'a, T: AsRef<[u8]> + AsMut<[u8]>>(
+    data: &'a BeaconNotifyIndication,
+    buffer: &'a mut T,
+) {
+    let mut frame = Frame::new_unchecked(buffer);
+
+    frame.set_frame_type(Ieee802154FrameType::Beacon);
+    frame.set_sequence_number(data.bsn);
+}
+
 /// MLME COMM STATUS Indication which is used by the MAC to indicate a communications status
 #[repr(C)]
 #[derive(Debug)]
@@ -250,6 +270,21 @@ impl DataIndication {
     }
 }
 
+pub fn write_frame_from_data_indication<'a, T: AsRef<[u8]> + AsMut<[u8]>>(data: &'a DataIndication, buffer: &'a mut T) {
+    let mut frame = Frame::new_unchecked(buffer);
+
+    frame.set_frame_type(Ieee802154FrameType::Data);
+    frame.set_src_addr(MacAddressAndMode(data.src_address, data.src_addr_mode).into());
+    frame.set_dst_addr(MacAddressAndMode(data.dst_address, data.dst_addr_mode).into());
+    frame.set_dst_pan_id(data.dst_pan_id.into());
+    frame.set_src_pan_id(data.src_pan_id.into());
+    frame.set_sequence_number(data.dsn);
+    frame.set_security_enabled(data.security_level == SecurityLevel::Secured);
+
+    // No way around the copy with the current API
+    frame.payload_mut().unwrap().copy_from_slice(data.payload());
+}
+
 /// MLME POLL Indication which will be used for indicating the Data Request
 /// reception to upper layer as defined in Zigbee r22 - D.8.2
 #[repr(C)]
diff --git a/embassy-stm32-wpan/src/mac/mod.rs b/embassy-stm32-wpan/src/mac/mod.rs
index c847a5cca..ac50a6b29 100644
--- a/embassy-stm32-wpan/src/mac/mod.rs
+++ b/embassy-stm32-wpan/src/mac/mod.rs
@@ -11,11 +11,7 @@ pub mod runner;
 pub mod typedefs;
 
 pub use crate::mac::control::Control;
-use crate::mac::driver::Driver;
+pub use crate::mac::driver::{Driver, DriverState};
 pub use crate::mac::runner::Runner;
 
 const MTU: usize = 127;
-
-pub async fn new<'a>(runner: &'a Runner<'a>) -> (Control<'a>, Driver<'a>) {
-    (Control::new(runner), Driver::new(runner))
-}
diff --git a/embassy-stm32-wpan/src/mac/runner.rs b/embassy-stm32-wpan/src/mac/runner.rs
index 2409f994d..3b7d895df 100644
--- a/embassy-stm32-wpan/src/mac/runner.rs
+++ b/embassy-stm32-wpan/src/mac/runner.rs
@@ -6,96 +6,138 @@ use embassy_sync::blocking_mutex::raw::{CriticalSectionRawMutex, NoopRawMutex};
 use embassy_sync::channel::Channel;
 use embassy_sync::mutex::Mutex;
 use embassy_sync::signal::Signal;
+use smoltcp::wire::Ieee802154FrameType;
+use smoltcp::wire::ieee802154::Frame;
 
 use crate::mac::MTU;
-use crate::mac::commands::DataRequest;
+use crate::mac::commands::*;
+use crate::mac::driver::NetworkState;
 use crate::mac::event::MacEvent;
-use crate::mac::typedefs::{AddressMode, MacAddress, PanId, SecurityLevel};
-use crate::sub::mac::Mac;
+use crate::sub::mac::{MacRx, MacTx};
 
-type ZeroCopyPubSub<M, T> = blocking_mutex::Mutex<M, RefCell<Option<Signal<NoopRawMutex, T>>>>;
+pub type ZeroCopyPubSub<M, T> = blocking_mutex::Mutex<M, RefCell<Option<Signal<NoopRawMutex, T>>>>;
+
+pub const BUF_SIZE: usize = 3;
 
 pub struct Runner<'a> {
-    pub(crate) mac_subsystem: Mac,
     // rx event backpressure is already provided through the MacEvent drop mechanism
     // therefore, we don't need to worry about overwriting events
-    pub(crate) rx_event_channel: ZeroCopyPubSub<CriticalSectionRawMutex, MacEvent<'a>>,
-    pub(crate) read_mutex: Mutex<CriticalSectionRawMutex, ()>,
-    pub(crate) write_mutex: Mutex<CriticalSectionRawMutex, ()>,
-    pub(crate) rx_channel: Channel<CriticalSectionRawMutex, MacEvent<'a>, 1>,
-    pub(crate) tx_channel: Channel<CriticalSectionRawMutex, (&'a mut [u8; MTU], usize), 5>,
-    pub(crate) tx_buf_channel: Channel<CriticalSectionRawMutex, &'a mut [u8; MTU], 5>,
+    rx_event_channel: &'a ZeroCopyPubSub<CriticalSectionRawMutex, MacEvent<'a>>,
+    rx_data_channel: &'a Channel<CriticalSectionRawMutex, MacEvent<'a>, 1>,
+    mac_rx: Mutex<NoopRawMutex, &'a mut MacRx<'a>>,
+
+    tx_data_channel: &'a Channel<CriticalSectionRawMutex, (&'a mut [u8; MTU], usize), BUF_SIZE>,
+    tx_buf_channel: &'a Channel<CriticalSectionRawMutex, &'a mut [u8; MTU], BUF_SIZE>,
+    mac_tx: &'a Mutex<CriticalSectionRawMutex, MacTx<'a>>,
+
+    #[allow(unused)]
+    network_state: &'a blocking_mutex::Mutex<CriticalSectionRawMutex, RefCell<NetworkState>>,
 }
 
 impl<'a> Runner<'a> {
-    pub fn new(mac: Mac, tx_buf_queue: [&'a mut [u8; MTU]; 5]) -> Self {
-        let this = Self {
-            mac_subsystem: mac,
-            rx_event_channel: blocking_mutex::Mutex::new(RefCell::new(None)),
-            read_mutex: Mutex::new(()),
-            write_mutex: Mutex::new(()),
-            rx_channel: Channel::new(),
-            tx_channel: Channel::new(),
-            tx_buf_channel: Channel::new(),
-        };
-
+    pub(crate) fn new(
+        rx_event_channel: &'a ZeroCopyPubSub<CriticalSectionRawMutex, MacEvent<'a>>,
+        rx_data_channel: &'a Channel<CriticalSectionRawMutex, MacEvent<'a>, 1>,
+        mac_rx: &'a mut MacRx<'a>,
+        tx_data_channel: &'a Channel<CriticalSectionRawMutex, (&'a mut [u8; MTU], usize), BUF_SIZE>,
+        tx_buf_channel: &'a Channel<CriticalSectionRawMutex, &'a mut [u8; MTU], BUF_SIZE>,
+        mac_tx: &'a Mutex<CriticalSectionRawMutex, MacTx<'a>>,
+        tx_buf_queue: &'a mut [[u8; MTU]; BUF_SIZE],
+        network_state: &'a blocking_mutex::Mutex<CriticalSectionRawMutex, RefCell<NetworkState>>,
+        short_address: [u8; 2],
+        mac_address: [u8; 8],
+    ) -> Self {
         for buf in tx_buf_queue {
-            this.tx_buf_channel.try_send(buf).unwrap();
+            tx_buf_channel.try_send(buf).unwrap();
+        }
+
+        critical_section::with(|cs| {
+            let mut network_state = network_state.borrow(cs).borrow_mut();
+
+            network_state.mac_addr = mac_address;
+            network_state.short_addr = short_address;
+        });
+
+        Self {
+            rx_event_channel,
+            rx_data_channel,
+            mac_rx: Mutex::new(mac_rx),
+            tx_data_channel,
+            tx_buf_channel,
+            mac_tx,
+            network_state,
         }
+    }
+
+    async fn send_request<T: MacCommand, U: TryInto<T>>(&self, frame: U) -> Result<(), ()>
+    where
+        (): From<<U as TryInto<T>>::Error>,
+    {
+        let request: T = frame.try_into()?;
+        self.mac_tx.lock().await.send_command(&request).await.map_err(|_| ())?;
 
-        this
+        Ok(())
     }
 
     pub async fn run(&'a self) -> ! {
         join::join(
             async {
                 loop {
-                    if let Ok(mac_event) = self.mac_subsystem.read().await {
+                    if let Ok(mac_event) = self.mac_rx.try_lock().unwrap().read().await {
                         match mac_event {
+                            MacEvent::MlmeAssociateCnf(_)
+                            | MacEvent::MlmeDisassociateCnf(_)
+                            | MacEvent::MlmeGetCnf(_)
+                            | MacEvent::MlmeGtsCnf(_)
+                            | MacEvent::MlmeResetCnf(_)
+                            | MacEvent::MlmeRxEnableCnf(_)
+                            | MacEvent::MlmeScanCnf(_)
+                            | MacEvent::MlmeSetCnf(_)
+                            | MacEvent::MlmeStartCnf(_)
+                            | MacEvent::MlmePollCnf(_)
+                            | MacEvent::MlmeDpsCnf(_)
+                            | MacEvent::MlmeSoundingCnf(_)
+                            | MacEvent::MlmeCalibrateCnf(_)
+                            | MacEvent::McpsDataCnf(_)
+                            | MacEvent::McpsPurgeCnf(_) => {
+                                self.rx_event_channel.lock(|s| {
+                                    s.borrow().as_ref().map(|signal| signal.signal(mac_event));
+                                });
+                            }
                             MacEvent::McpsDataInd(_) => {
-                                self.rx_channel.send(mac_event).await;
+                                // Pattern should match driver
+                                self.rx_data_channel.send(mac_event).await;
                             }
                             _ => {
-                                self.rx_event_channel.lock(|s| {
-                                    match &*s.borrow() {
-                                        Some(signal) => {
-                                            signal.signal(mac_event);
-                                        }
-                                        None => {}
-                                    };
-                                });
+                                debug!("unhandled mac event: {:#x}", mac_event);
                             }
                         }
                     }
                 }
             },
             async {
-                let mut msdu_handle = 0x02;
-
                 loop {
-                    let (buf, len) = self.tx_channel.receive().await;
-                    let _wm = self.write_mutex.lock().await;
-
-                    // The mutex should be dropped on the next loop iteration
-                    self.mac_subsystem
-                        .send_command(
-                            DataRequest {
-                                src_addr_mode: AddressMode::Short,
-                                dst_addr_mode: AddressMode::Short,
-                                dst_pan_id: PanId([0x1A, 0xAA]),
-                                dst_address: MacAddress::BROADCAST,
-                                msdu_handle: msdu_handle,
-                                ack_tx: 0x00,
-                                gts_tx: false,
-                                security_level: SecurityLevel::Unsecure,
-                                ..Default::default()
-                            }
-                            .set_buffer(&buf[..len]),
-                        )
-                        .await
-                        .unwrap();
+                    let (buf, _) = self.tx_data_channel.receive().await;
+
+                    // Smoltcp has created this frame, so there's no need to reparse it.
+                    let frame = Frame::new_unchecked(&buf);
 
-                    msdu_handle = msdu_handle.wrapping_add(1);
+                    let result: Result<(), ()> = match frame.frame_type() {
+                        Ieee802154FrameType::Beacon => Err(()),
+                        Ieee802154FrameType::Data => self.send_request::<DataRequest, _>(frame).await,
+                        Ieee802154FrameType::Acknowledgement => Err(()),
+                        Ieee802154FrameType::MacCommand => Err(()),
+                        Ieee802154FrameType::Multipurpose => Err(()),
+                        Ieee802154FrameType::FragmentOrFrak => Err(()),
+                        Ieee802154FrameType::Extended => Err(()),
+                        _ => Err(()),
+                    };
+
+                    if result.is_err() {
+                        debug!("failed to parse mac frame");
+                    } else {
+                        trace!("data frame sent!");
+                    }
 
                     // The tx channel should always be of equal capacity to the tx_buf channel
                     self.tx_buf_channel.try_send(buf).unwrap();
diff --git a/embassy-stm32-wpan/src/mac/typedefs.rs b/embassy-stm32-wpan/src/mac/typedefs.rs
index 0552b8ea1..175d4a37d 100644
--- a/embassy-stm32-wpan/src/mac/typedefs.rs
+++ b/embassy-stm32-wpan/src/mac/typedefs.rs
@@ -1,5 +1,7 @@
 use core::fmt::Debug;
 
+use smoltcp::wire::ieee802154::{Address, AddressingMode, Pan};
+
 use crate::numeric_enum;
 
 #[derive(Debug)]
@@ -109,12 +111,51 @@ numeric_enum! {
 }
 }
 
+impl TryFrom<AddressingMode> for AddressMode {
+    type Error = ();
+
+    fn try_from(value: AddressingMode) -> Result<Self, Self::Error> {
+        match value {
+            AddressingMode::Absent => Ok(Self::NoAddress),
+            AddressingMode::Extended => Ok(Self::Extended),
+            AddressingMode::Short => Ok(Self::Short),
+            AddressingMode::Unknown(_) => Err(()),
+        }
+    }
+}
+
 #[derive(Clone, Copy)]
 pub union MacAddress {
     pub short: [u8; 2],
     pub extended: [u8; 8],
 }
 
+impl From<Address> for MacAddress {
+    fn from(value: Address) -> Self {
+        match value {
+            Address::Short(addr) => Self { short: addr },
+            Address::Extended(addr) => Self { extended: addr },
+            Address::Absent => Self { short: [0u8; 2] },
+        }
+    }
+}
+
+pub struct MacAddressAndMode(pub MacAddress, pub AddressMode);
+
+impl From<MacAddressAndMode> for Address {
+    fn from(mac_address_and_mode: MacAddressAndMode) -> Self {
+        let address = mac_address_and_mode.0;
+        let mode = mac_address_and_mode.1;
+
+        match mode {
+            AddressMode::Short => Address::Short(unsafe { address.short }),
+            AddressMode::Extended => Address::Extended(unsafe { address.extended }),
+            AddressMode::NoAddress => Address::Absent,
+            AddressMode::Reserved => Address::Absent,
+        }
+    }
+}
+
 impl Debug for MacAddress {
     fn fmt(&self, fmt: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
         unsafe {
@@ -346,7 +387,7 @@ numeric_enum! {
 
 numeric_enum! {
     #[repr(u8)]
-    #[derive(Default, Clone, Copy, Debug)]
+    #[derive(Default, Clone, Copy, Debug, PartialEq)]
     #[cfg_attr(feature = "defmt", derive(defmt::Format))]
     pub enum SecurityLevel {
         /// MAC Unsecured Mode Security
@@ -379,3 +420,15 @@ pub struct PanId(pub [u8; 2]);
 impl PanId {
     pub const BROADCAST: Self = Self([0xFF, 0xFF]);
 }
+
+impl From<Pan> for PanId {
+    fn from(value: Pan) -> Self {
+        Self(value.0.to_be_bytes())
+    }
+}
+
+impl From<PanId> for Pan {
+    fn from(value: PanId) -> Self {
+        Self(u16::from_be_bytes(value.0))
+    }
+}
diff --git a/embassy-stm32-wpan/src/shci.rs b/embassy-stm32-wpan/src/shci.rs
index 30d689716..2d94a9cda 100644
--- a/embassy-stm32-wpan/src/shci.rs
+++ b/embassy-stm32-wpan/src/shci.rs
@@ -1,6 +1,10 @@
-use core::{mem, slice};
+use core::sync::atomic::{Ordering, compiler_fence};
+use core::{mem, ptr, slice};
 
+use crate::PacketHeader;
+use crate::cmd::CmdPacket;
 use crate::consts::{TL_CS_EVT_SIZE, TL_EVT_HEADER_SIZE, TL_PACKET_HEADER_SIZE};
+use crate::evt::{CcEvt, EvtStub};
 
 const SHCI_OGF: u16 = 0x3F;
 
@@ -21,6 +25,18 @@ pub enum SchiCommandStatus {
     ShciFusCmdNotSupported = 0xFF,
 }
 
+impl SchiCommandStatus {
+    pub unsafe fn from_packet(cmd_buf: *const CmdPacket) -> Result<Self, ()> {
+        let p_cmd_serial = (cmd_buf as *mut u8).add(size_of::<PacketHeader>());
+        let p_evt_payload = p_cmd_serial.add(size_of::<EvtStub>());
+
+        compiler_fence(Ordering::Acquire);
+        let cc_evt = ptr::read_unaligned(p_evt_payload as *const CcEvt);
+
+        cc_evt.payload[0].try_into()
+    }
+}
+
 impl TryFrom<u8> for SchiCommandStatus {
     type Error = ();
 
@@ -274,69 +290,64 @@ pub struct ShciBleInitCmdParam {
     pub options: u8,
     /// Reserved for future use - shall be set to 0
     pub hw_version: u8,
-    //    /**
-    //     * Maximum number of connection-oriented channels in initiator mode.
-    //     * Range: 0 .. 64
-    //     */
-    //    pub max_coc_initiator_nbr: u8,
-    //
-    //    /**
-    //     * Minimum transmit power in dBm supported by the Controller.
-    //     * Range: -127 .. 20
-    //     */
-    //    pub min_tx_power: i8,
-    //
-    //    /**
-    //     * Maximum transmit power in dBm supported by the Controller.
-    //     * Range: -127 .. 20
-    //     */
-    //    pub max_tx_power: i8,
-    //
-    //    /**
-    //     * RX model configuration
-    //     * - bit 0:   1: agc_rssi model improved vs RF blockers    0: Legacy agc_rssi model
-    //     * - other bits: reserved ( shall be set to 0)
-    //     */
-    //    pub rx_model_config: u8,
-    //
-    //    /* Maximum number of advertising sets.
-    //     * Range: 1 .. 8 with limitation:
-    //     * This parameter is linked to max_adv_data_len such as both compliant with allocated Total memory computed with BLE_EXT_ADV_BUFFER_SIZE based
-    //     * on Max Extended advertising configuration supported.
-    //     * This parameter is considered by the CPU2 when Options has SHCI_C2_BLE_INIT_OPTIONS_EXT_ADV flag set
-    //     */
-    //    pub max_adv_set_nbr: u8,
-    //
-    //    /* Maximum advertising data length (in bytes)
-    //     * Range: 31 .. 1650 with limitation:
-    //     * This parameter is linked to max_adv_set_nbr such as both compliant with allocated Total memory computed with BLE_EXT_ADV_BUFFER_SIZE based
-    //     * on Max Extended advertising configuration supported.
-    //     * This parameter is considered by the CPU2 when Options has SHCI_C2_BLE_INIT_OPTIONS_EXT_ADV flag set
-    //     */
-    //    pub max_adv_data_len: u16,
-    //
-    //    /* RF TX Path Compensation Value (16-bit signed integer). Units: 0.1 dB.
-    //     * Range: -1280 .. 1280
-    //     */
-    //    pub tx_path_compens: i16,
-    //
-    //    /* RF RX Path Compensation Value (16-bit signed integer). Units: 0.1 dB.
-    //     * Range: -1280 .. 1280
-    //     */
-    //    pub rx_path_compens: i16,
-    //
-    //    /* BLE core specification version (8-bit unsigned integer).
-    //     * values as: 11(5.2), 12(5.3)
-    //     */
-    //    pub ble_core_version: u8,
-    //
-    //    /**
-    //     * Options flags extension
-    //     * - bit 0:   1: appearance Writable              0: appearance Read-Only
-    //     * - bit 1:   1: Enhanced ATT supported           0: Enhanced ATT not supported
-    //     * - other bits: reserved ( shall be set to 0)
-    //     */
-    //    pub options_extension: u8,
+    ///
+    /// Maximum number of connection-oriented channels in initiator mode.
+    /// Range: 0 .. 64
+    pub max_coc_initiator_nbr: u8,
+
+    ///
+    /// Minimum transmit power in dBm supported by the Controller.
+    /// Range: -127 .. 20
+    pub min_tx_power: i8,
+
+    ///
+    /// Maximum transmit power in dBm supported by the Controller.
+    /// Range: -127 .. 20
+    pub max_tx_power: i8,
+
+    ///
+    /// RX model configuration
+    /// - bit 0:   1: agc_rssi model improved vs RF blockers    0: Legacy agc_rssi model
+    /// - other bits: reserved ( shall be set to 0)
+    pub rx_model_config: u8,
+
+    /// Maximum number of advertising sets.
+    /// Range: 1 .. 8 with limitation:
+    /// This parameter is linked to max_adv_data_len such as both compliant with allocated Total memory computed with BLE_EXT_ADV_BUFFER_SIZE based
+    /// on Max Extended advertising configuration supported.
+    /// This parameter is considered by the CPU2 when Options has SHCI_C2_BLE_INIT_OPTIONS_EXT_ADV flag set
+    pub max_adv_set_nbr: u8,
+
+    /// Maximum advertising data length (in bytes)
+    /// Range: 31 .. 1650 with limitation:
+    /// This parameter is linked to max_adv_set_nbr such as both compliant with allocated Total memory computed with BLE_EXT_ADV_BUFFER_SIZE based
+    /// on Max Extended advertising configuration supported.
+    /// This parameter is considered by the CPU2 when Options has SHCI_C2_BLE_INIT_OPTIONS_EXT_ADV flag set
+    pub max_adv_data_len: u16,
+
+    /// RF TX Path Compensation Value (16-bit signed integer). Units: 0.1 dB.
+    /// Range: -1280 .. 1280
+    pub tx_path_compens: i16,
+
+    //// RF RX Path Compensation Value (16-bit signed integer). Units: 0.1 dB.
+    /// Range: -1280 .. 1280
+    pub rx_path_compens: i16,
+
+    /// BLE core specification version (8-bit unsigned integer).
+    /// values as: 11(5.2), 12(5.3)
+    pub ble_core_version: u8,
+
+    /// Options flags extension
+    /// - bit 0:   1: appearance Writable              0: appearance Read-Only
+    /// - bit 1:   1: Enhanced ATT supported           0: Enhanced ATT not supported
+    /// - other bits: reserved ( shall be set to 0)
+    pub options_extension: u8,
+
+    /// MaxAddEattBearers
+    /// Maximum number of bearers that can be created for Enhanced ATT
+    /// in addition to the number of links
+    ///     - Range: 0 .. 4
+    pub max_add_eatt_bearers: u8,
 }
 
 impl ShciBleInitCmdParam {
@@ -351,7 +362,7 @@ impl Default for ShciBleInitCmdParam {
             p_ble_buffer_address: 0,
             ble_buffer_size: 0,
             num_attr_record: 68,
-            num_attr_serv: 8,
+            num_attr_serv: 4,
             attr_value_arr_size: 1344,
             num_of_links: 2,
             extended_packet_length_enable: 1,
@@ -366,6 +377,17 @@ impl Default for ShciBleInitCmdParam {
             viterbi_enable: 1,
             options: 0,
             hw_version: 0,
+            max_coc_initiator_nbr: 32,
+            min_tx_power: -40,
+            max_tx_power: 6,
+            rx_model_config: 0,
+            max_adv_set_nbr: 2,
+            max_adv_data_len: 1650,
+            tx_path_compens: 0,
+            rx_path_compens: 0,
+            ble_core_version: 11,
+            options_extension: 0,
+            max_add_eatt_bearers: 4,
         }
     }
 }
diff --git a/embassy-stm32-wpan/src/sub/ble.rs b/embassy-stm32-wpan/src/sub/ble.rs
index cd69a0479..afc4a510a 100644
--- a/embassy-stm32-wpan/src/sub/ble.rs
+++ b/embassy-stm32-wpan/src/sub/ble.rs
@@ -1,15 +1,15 @@
 use core::ptr;
 
-use embassy_stm32::ipcc::Ipcc;
+use embassy_stm32::ipcc::{IpccRxChannel, IpccTxChannel};
 use hci::Opcode;
 
 use crate::cmd::CmdPacket;
 use crate::consts::{TL_BLEEVT_CC_OPCODE, TL_BLEEVT_CS_OPCODE, TlPacketType};
+use crate::evt;
 use crate::evt::{EvtBox, EvtPacket, EvtStub};
 use crate::sub::mm;
 use crate::tables::{BLE_CMD_BUFFER, BleTable, CS_BUFFER, EVT_QUEUE, HCI_ACL_DATA_BUFFER, TL_BLE_TABLE};
 use crate::unsafe_linked_list::LinkedListNode;
-use crate::{channels, evt};
 
 /// A guard that, once constructed, may be used to send BLE commands to CPU2.
 ///
@@ -36,15 +36,21 @@ use crate::{channels, evt};
 /// # mbox.ble_subsystem.reset().await;
 /// # let _reset_response = mbox.ble_subsystem.read().await;
 /// ```
-pub struct Ble {
-    _private: (),
+pub struct Ble<'a> {
+    hw_ipcc_ble_cmd_channel: IpccTxChannel<'a>,
+    ipcc_ble_event_channel: IpccRxChannel<'a>,
+    ipcc_hci_acl_data_channel: IpccTxChannel<'a>,
 }
 
-impl Ble {
+impl<'a> Ble<'a> {
     /// Constructs a guard that allows for BLE commands to be sent to CPU2.
     ///
     /// This takes the place of `TL_BLE_Init`, completing that step as laid out in AN5289, Fig 66.
-    pub(crate) fn new() -> Self {
+    pub(crate) fn new(
+        hw_ipcc_ble_cmd_channel: IpccTxChannel<'a>,
+        ipcc_ble_event_channel: IpccRxChannel<'a>,
+        ipcc_hci_acl_data_channel: IpccTxChannel<'a>,
+    ) -> Self {
         unsafe {
             LinkedListNode::init_head(EVT_QUEUE.as_mut_ptr());
 
@@ -56,44 +62,51 @@ impl Ble {
             });
         }
 
-        Self { _private: () }
+        Self {
+            hw_ipcc_ble_cmd_channel,
+            ipcc_ble_event_channel,
+            ipcc_hci_acl_data_channel,
+        }
     }
 
     /// `HW_IPCC_BLE_EvtNot`
-    pub async fn tl_read(&self) -> EvtBox<Self> {
-        Ipcc::receive(channels::cpu2::IPCC_BLE_EVENT_CHANNEL, || unsafe {
-            if let Some(node_ptr) = LinkedListNode::remove_head(EVT_QUEUE.as_mut_ptr()) {
-                Some(EvtBox::new(node_ptr.cast()))
-            } else {
-                None
-            }
-        })
-        .await
+    pub async fn tl_read(&mut self) -> EvtBox<Self> {
+        self.ipcc_ble_event_channel
+            .receive(|| unsafe {
+                if let Some(node_ptr) = LinkedListNode::remove_head(EVT_QUEUE.as_mut_ptr()) {
+                    Some(EvtBox::new(node_ptr.cast()))
+                } else {
+                    None
+                }
+            })
+            .await
     }
 
     /// `TL_BLE_SendCmd`
-    pub async fn tl_write(&self, opcode: u16, payload: &[u8]) {
-        Ipcc::send(channels::cpu1::IPCC_BLE_CMD_CHANNEL, || unsafe {
-            CmdPacket::write_into(BLE_CMD_BUFFER.as_mut_ptr(), TlPacketType::BleCmd, opcode, payload);
-        })
-        .await;
+    pub async fn tl_write(&mut self, opcode: u16, payload: &[u8]) {
+        self.hw_ipcc_ble_cmd_channel
+            .send(|| unsafe {
+                CmdPacket::write_into(BLE_CMD_BUFFER.as_mut_ptr(), TlPacketType::BleCmd, opcode, payload);
+            })
+            .await;
     }
 
     /// `TL_BLE_SendAclData`
-    pub async fn acl_write(&self, handle: u16, payload: &[u8]) {
-        Ipcc::send(channels::cpu1::IPCC_HCI_ACL_DATA_CHANNEL, || unsafe {
-            CmdPacket::write_into(
-                HCI_ACL_DATA_BUFFER.as_mut_ptr() as *mut _,
-                TlPacketType::AclData,
-                handle,
-                payload,
-            );
-        })
-        .await;
+    pub async fn acl_write(&mut self, handle: u16, payload: &[u8]) {
+        self.ipcc_hci_acl_data_channel
+            .send(|| unsafe {
+                CmdPacket::write_into(
+                    HCI_ACL_DATA_BUFFER.as_mut_ptr() as *mut _,
+                    TlPacketType::AclData,
+                    handle,
+                    payload,
+                );
+            })
+            .await;
     }
 }
 
-impl evt::MemoryManager for Ble {
+impl<'a> evt::MemoryManager for Ble<'a> {
     /// SAFETY: passing a pointer to something other than a managed event packet is UB
     unsafe fn drop_event_packet(evt: *mut EvtPacket) {
         let stub = unsafe {
@@ -110,13 +123,17 @@ impl evt::MemoryManager for Ble {
 
 pub extern crate stm32wb_hci as hci;
 
-impl hci::Controller for Ble {
+impl<'a> hci::Controller for Ble<'a> {
     async fn controller_write(&mut self, opcode: Opcode, payload: &[u8]) {
         self.tl_write(opcode.0, payload).await;
     }
 
+    #[allow(invalid_reference_casting)]
     async fn controller_read_into(&self, buf: &mut [u8]) {
-        let evt_box = self.tl_read().await;
+        // A complete hack since I cannot update the trait
+        let s = unsafe { &mut *(self as *const _ as *mut Ble) };
+
+        let evt_box = s.tl_read().await;
         let evt_serial = evt_box.serial();
 
         buf[..evt_serial.len()].copy_from_slice(evt_serial);
diff --git a/embassy-stm32-wpan/src/sub/mac.rs b/embassy-stm32-wpan/src/sub/mac.rs
index baf4da979..ce2903e61 100644
--- a/embassy-stm32-wpan/src/sub/mac.rs
+++ b/embassy-stm32-wpan/src/sub/mac.rs
@@ -4,60 +4,78 @@ use core::sync::atomic::{AtomicBool, Ordering};
 use core::task::Poll;
 
 use embassy_futures::poll_once;
-use embassy_stm32::ipcc::Ipcc;
+use embassy_stm32::ipcc::{Ipcc, IpccRxChannel, IpccTxChannel};
 use embassy_sync::waitqueue::AtomicWaker;
 
 use crate::cmd::CmdPacket;
 use crate::consts::TlPacketType;
+use crate::evt;
 use crate::evt::{EvtBox, EvtPacket};
 use crate::mac::commands::MacCommand;
 use crate::mac::event::MacEvent;
 use crate::mac::typedefs::MacError;
 use crate::tables::{MAC_802_15_4_CMD_BUFFER, MAC_802_15_4_NOTIF_RSP_EVT_BUFFER};
-use crate::{channels, evt};
+use crate::unsafe_linked_list::LinkedListNode;
 
 static MAC_WAKER: AtomicWaker = AtomicWaker::new();
 static MAC_EVT_OUT: AtomicBool = AtomicBool::new(false);
 
-pub struct Mac {
-    _private: (),
+pub struct Mac<'a> {
+    ipcc_mac_802_15_4_cmd_rsp_channel: IpccTxChannel<'a>,
+    ipcc_mac_802_15_4_notification_ack_channel: IpccRxChannel<'a>,
 }
 
-impl Mac {
-    pub(crate) fn new() -> Self {
-        Self { _private: () }
-    }
-
-    /// `HW_IPCC_MAC_802_15_4_EvtNot`
-    ///
-    /// This function will stall if the previous `EvtBox` has not been dropped
-    pub async fn tl_read(&self) -> EvtBox<Self> {
-        // Wait for the last event box to be dropped
-        poll_fn(|cx| {
-            MAC_WAKER.register(cx.waker());
-            if MAC_EVT_OUT.load(Ordering::SeqCst) {
-                Poll::Pending
-            } else {
-                Poll::Ready(())
-            }
-        })
-        .await;
+impl<'a> Mac<'a> {
+    pub(crate) fn new(
+        ipcc_mac_802_15_4_cmd_rsp_channel: IpccTxChannel<'a>,
+        ipcc_mac_802_15_4_notification_ack_channel: IpccRxChannel<'a>,
+    ) -> Self {
+        use crate::tables::{
+            MAC_802_15_4_CMD_BUFFER, MAC_802_15_4_NOTIF_RSP_EVT_BUFFER, Mac802_15_4Table, TL_MAC_802_15_4_TABLE,
+            TL_TRACES_TABLE, TRACES_EVT_QUEUE, TracesTable,
+        };
 
-        // Return a new event box
-        Ipcc::receive(channels::cpu2::IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL, || unsafe {
-            // The closure is not async, therefore the closure must execute to completion (cannot be dropped)
-            // Therefore, the event box is guaranteed to be cleaned up if it's not leaked
-            MAC_EVT_OUT.store(true, Ordering::SeqCst);
+        unsafe {
+            LinkedListNode::init_head(TRACES_EVT_QUEUE.as_mut_ptr() as *mut _);
+
+            TL_TRACES_TABLE.as_mut_ptr().write_volatile(TracesTable {
+                traces_queue: TRACES_EVT_QUEUE.as_ptr() as *const _,
+            });
+
+            TL_MAC_802_15_4_TABLE.as_mut_ptr().write_volatile(Mac802_15_4Table {
+                p_cmdrsp_buffer: MAC_802_15_4_CMD_BUFFER.as_mut_ptr().cast(),
+                p_notack_buffer: MAC_802_15_4_NOTIF_RSP_EVT_BUFFER.as_mut_ptr().cast(),
+                evt_queue: core::ptr::null_mut(),
+            });
+        };
+
+        Self {
+            ipcc_mac_802_15_4_cmd_rsp_channel,
+            ipcc_mac_802_15_4_notification_ack_channel,
+        }
+    }
 
-            Some(EvtBox::new(MAC_802_15_4_NOTIF_RSP_EVT_BUFFER.as_mut_ptr() as *mut _))
-        })
-        .await
+    pub const fn split(self) -> (MacRx<'a>, MacTx<'a>) {
+        (
+            MacRx {
+                ipcc_mac_802_15_4_notification_ack_channel: self.ipcc_mac_802_15_4_notification_ack_channel,
+            },
+            MacTx {
+                ipcc_mac_802_15_4_cmd_rsp_channel: self.ipcc_mac_802_15_4_cmd_rsp_channel,
+            },
+        )
     }
+}
+
+pub struct MacTx<'a> {
+    ipcc_mac_802_15_4_cmd_rsp_channel: IpccTxChannel<'a>,
+}
 
+impl<'a> MacTx<'a> {
     /// `HW_IPCC_MAC_802_15_4_CmdEvtNot`
-    pub async fn tl_write_and_get_response(&self, opcode: u16, payload: &[u8]) -> u8 {
+    pub async fn tl_write_and_get_response(&mut self, opcode: u16, payload: &[u8]) -> u8 {
         self.tl_write(opcode, payload).await;
-        Ipcc::flush(channels::cpu1::IPCC_MAC_802_15_4_CMD_RSP_CHANNEL).await;
+        self.ipcc_mac_802_15_4_cmd_rsp_channel.flush().await;
 
         unsafe {
             let p_event_packet = MAC_802_15_4_CMD_BUFFER.as_ptr() as *const EvtPacket;
@@ -68,19 +86,20 @@ impl Mac {
     }
 
     /// `TL_MAC_802_15_4_SendCmd`
-    pub async fn tl_write(&self, opcode: u16, payload: &[u8]) {
-        Ipcc::send(channels::cpu1::IPCC_MAC_802_15_4_CMD_RSP_CHANNEL, || unsafe {
-            CmdPacket::write_into(
-                MAC_802_15_4_CMD_BUFFER.as_mut_ptr(),
-                TlPacketType::MacCmd,
-                opcode,
-                payload,
-            );
-        })
-        .await;
+    pub async fn tl_write(&mut self, opcode: u16, payload: &[u8]) {
+        self.ipcc_mac_802_15_4_cmd_rsp_channel
+            .send(|| unsafe {
+                CmdPacket::write_into(
+                    MAC_802_15_4_CMD_BUFFER.as_mut_ptr(),
+                    TlPacketType::MacCmd,
+                    opcode,
+                    payload,
+                );
+            })
+            .await;
     }
 
-    pub async fn send_command<T>(&self, cmd: &T) -> Result<(), MacError>
+    pub async fn send_command<T>(&mut self, cmd: &T) -> Result<(), MacError>
     where
         T: MacCommand,
     {
@@ -92,13 +111,46 @@ impl Mac {
             Err(MacError::from(response))
         }
     }
+}
+
+pub struct MacRx<'a> {
+    ipcc_mac_802_15_4_notification_ack_channel: IpccRxChannel<'a>,
+}
+
+impl<'a> MacRx<'a> {
+    /// `HW_IPCC_MAC_802_15_4_EvtNot`
+    ///
+    /// This function will stall if the previous `EvtBox` has not been dropped
+    pub async fn tl_read(&mut self) -> EvtBox<MacRx<'a>> {
+        // Wait for the last event box to be dropped
+        poll_fn(|cx| {
+            MAC_WAKER.register(cx.waker());
+            if MAC_EVT_OUT.load(Ordering::Acquire) {
+                Poll::Pending
+            } else {
+                Poll::Ready(())
+            }
+        })
+        .await;
+
+        // Return a new event box
+        self.ipcc_mac_802_15_4_notification_ack_channel
+            .receive(|| unsafe {
+                // The closure is not async, therefore the closure must execute to completion (cannot be dropped)
+                // Therefore, the event box is guaranteed to be cleaned up if it's not leaked
+                MAC_EVT_OUT.store(true, Ordering::SeqCst);
+
+                Some(EvtBox::new(MAC_802_15_4_NOTIF_RSP_EVT_BUFFER.as_mut_ptr() as *mut _))
+            })
+            .await
+    }
 
-    pub async fn read(&self) -> Result<MacEvent<'_>, ()> {
+    pub async fn read<'b>(&mut self) -> Result<MacEvent<'b>, ()> {
         MacEvent::new(self.tl_read().await)
     }
 }
 
-impl evt::MemoryManager for Mac {
+impl<'a> evt::MemoryManager for MacRx<'a> {
     /// SAFETY: passing a pointer to something other than a managed event packet is UB
     unsafe fn drop_event_packet(_: *mut EvtPacket) {
         trace!("mac drop event");
@@ -112,13 +164,10 @@ impl evt::MemoryManager for Mac {
         );
 
         // Clear the rx flag
-        let _ = poll_once(Ipcc::receive::<()>(
-            channels::cpu2::IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL,
-            || None,
-        ));
+        let _ = poll_once(Ipcc::receive::<()>(3, || None));
 
         // Allow a new read call
-        MAC_EVT_OUT.store(false, Ordering::SeqCst);
+        MAC_EVT_OUT.store(false, Ordering::Release);
         MAC_WAKER.wake();
     }
 }
diff --git a/embassy-stm32-wpan/src/sub/mm.rs b/embassy-stm32-wpan/src/sub/mm.rs
index 62d0de8bd..aac252929 100644
--- a/embassy-stm32-wpan/src/sub/mm.rs
+++ b/embassy-stm32-wpan/src/sub/mm.rs
@@ -5,26 +5,26 @@ use core::task::Poll;
 
 use aligned::{A4, Aligned};
 use cortex_m::interrupt;
-use embassy_stm32::ipcc::Ipcc;
+use embassy_stm32::ipcc::IpccTxChannel;
 use embassy_sync::waitqueue::AtomicWaker;
 
 use crate::consts::POOL_SIZE;
+use crate::evt;
 use crate::evt::EvtPacket;
 #[cfg(feature = "ble")]
 use crate::tables::BLE_SPARE_EVT_BUF;
 use crate::tables::{EVT_POOL, FREE_BUF_QUEUE, MemManagerTable, SYS_SPARE_EVT_BUF, TL_MEM_MANAGER_TABLE};
 use crate::unsafe_linked_list::LinkedListNode;
-use crate::{channels, evt};
 
 static MM_WAKER: AtomicWaker = AtomicWaker::new();
 static mut LOCAL_FREE_BUF_QUEUE: Aligned<A4, MaybeUninit<LinkedListNode>> = Aligned(MaybeUninit::uninit());
 
-pub struct MemoryManager {
-    _private: (),
+pub struct MemoryManager<'a> {
+    ipcc_mm_release_buffer_channel: IpccTxChannel<'a>,
 }
 
-impl MemoryManager {
-    pub(crate) fn new() -> Self {
+impl<'a> MemoryManager<'a> {
+    pub(crate) fn new(ipcc_mm_release_buffer_channel: IpccTxChannel<'a>) -> Self {
         unsafe {
             LinkedListNode::init_head(FREE_BUF_QUEUE.as_mut_ptr());
             LinkedListNode::init_head(LOCAL_FREE_BUF_QUEUE.as_mut_ptr());
@@ -43,10 +43,12 @@ impl MemoryManager {
             });
         }
 
-        Self { _private: () }
+        Self {
+            ipcc_mm_release_buffer_channel,
+        }
     }
 
-    pub async fn run_queue(&self) {
+    pub async fn run_queue(&mut self) -> ! {
         loop {
             poll_fn(|cx| unsafe {
                 MM_WAKER.register(cx.waker());
@@ -58,20 +60,21 @@ impl MemoryManager {
             })
             .await;
 
-            Ipcc::send(channels::cpu1::IPCC_MM_RELEASE_BUFFER_CHANNEL, || {
-                interrupt::free(|_| unsafe {
-                    // CS required while moving nodes
-                    while let Some(node_ptr) = LinkedListNode::remove_head(LOCAL_FREE_BUF_QUEUE.as_mut_ptr()) {
-                        LinkedListNode::insert_head(FREE_BUF_QUEUE.as_mut_ptr(), node_ptr);
-                    }
+            self.ipcc_mm_release_buffer_channel
+                .send(|| {
+                    interrupt::free(|_| unsafe {
+                        // CS required while moving nodes
+                        while let Some(node_ptr) = LinkedListNode::remove_head(LOCAL_FREE_BUF_QUEUE.as_mut_ptr()) {
+                            LinkedListNode::insert_head(FREE_BUF_QUEUE.as_mut_ptr(), node_ptr);
+                        }
+                    })
                 })
-            })
-            .await;
+                .await;
         }
     }
 }
 
-impl evt::MemoryManager for MemoryManager {
+impl<'a> evt::MemoryManager for MemoryManager<'a> {
     /// SAFETY: passing a pointer to something other than a managed event packet is UB
     unsafe fn drop_event_packet(evt: *mut EvtPacket) {
         interrupt::free(|_| unsafe {
diff --git a/embassy-stm32-wpan/src/sub/sys.rs b/embassy-stm32-wpan/src/sub/sys.rs
index 8a3382f86..3ee539bb9 100644
--- a/embassy-stm32-wpan/src/sub/sys.rs
+++ b/embassy-stm32-wpan/src/sub/sys.rs
@@ -1,23 +1,28 @@
-use core::ptr;
+use embassy_stm32::ipcc::{IpccRxChannel, IpccTxChannel};
 
 use crate::cmd::CmdPacket;
 use crate::consts::TlPacketType;
-use crate::evt::{CcEvt, EvtBox, EvtPacket};
-#[allow(unused_imports)]
-use crate::shci::{SchiCommandStatus, ShciBleInitCmdParam, ShciOpcode};
+use crate::evt::EvtBox;
+#[cfg(feature = "ble")]
+use crate::shci::ShciBleInitCmdParam;
+use crate::shci::{SchiCommandStatus, ShciOpcode};
 use crate::sub::mm;
 use crate::tables::{SysTable, WirelessFwInfoTable};
 use crate::unsafe_linked_list::LinkedListNode;
-use crate::{Ipcc, SYS_CMD_BUF, SYSTEM_EVT_QUEUE, TL_DEVICE_INFO_TABLE, TL_SYS_TABLE, channels};
+use crate::{SYS_CMD_BUF, SYSTEM_EVT_QUEUE, TL_DEVICE_INFO_TABLE, TL_SYS_TABLE};
 
 /// A guard that, once constructed, allows for sys commands to be sent to CPU2.
-pub struct Sys {
-    _private: (),
+pub struct Sys<'a> {
+    ipcc_system_cmd_rsp_channel: IpccTxChannel<'a>,
+    ipcc_system_event_channel: IpccRxChannel<'a>,
 }
 
-impl Sys {
+impl<'a> Sys<'a> {
     /// TL_Sys_Init
-    pub(crate) fn new() -> Self {
+    pub(crate) fn new(
+        ipcc_system_cmd_rsp_channel: IpccTxChannel<'a>,
+        ipcc_system_event_channel: IpccRxChannel<'a>,
+    ) -> Self {
         unsafe {
             LinkedListNode::init_head(SYSTEM_EVT_QUEUE.as_mut_ptr());
 
@@ -27,7 +32,10 @@ impl Sys {
             });
         }
 
-        Self { _private: () }
+        Self {
+            ipcc_system_cmd_rsp_channel,
+            ipcc_system_event_channel,
+        }
     }
 
     /// Returns CPU2 wireless firmware information (if present).
@@ -38,48 +46,28 @@ impl Sys {
         if info.version != 0 { Some(info) } else { None }
     }
 
-    pub async fn write(&self, opcode: ShciOpcode, payload: &[u8]) {
-        Ipcc::send(channels::cpu1::IPCC_SYSTEM_CMD_RSP_CHANNEL, || unsafe {
-            CmdPacket::write_into(SYS_CMD_BUF.as_mut_ptr(), TlPacketType::SysCmd, opcode as u16, payload);
-        })
-        .await;
+    pub async fn write(&mut self, opcode: ShciOpcode, payload: &[u8]) {
+        self.ipcc_system_cmd_rsp_channel
+            .send(|| unsafe {
+                CmdPacket::write_into(SYS_CMD_BUF.as_mut_ptr(), TlPacketType::SysCmd, opcode as u16, payload);
+            })
+            .await;
     }
 
     /// `HW_IPCC_SYS_CmdEvtNot`
-    pub async fn write_and_get_response(&self, opcode: ShciOpcode, payload: &[u8]) -> Result<SchiCommandStatus, ()> {
+    pub async fn write_and_get_response(
+        &mut self,
+        opcode: ShciOpcode,
+        payload: &[u8],
+    ) -> Result<SchiCommandStatus, ()> {
         self.write(opcode, payload).await;
-        Ipcc::flush(channels::cpu1::IPCC_SYSTEM_CMD_RSP_CHANNEL).await;
-
-        unsafe {
-            let p_event_packet = SYS_CMD_BUF.as_ptr() as *const EvtPacket;
-            let p_command_event = &((*p_event_packet).evt_serial.evt.payload) as *const _ as *const CcEvt;
-            let p_payload = &((*p_command_event).payload) as *const u8;
+        self.ipcc_system_cmd_rsp_channel.flush().await;
 
-            ptr::read_volatile(p_payload).try_into()
-        }
+        unsafe { SchiCommandStatus::from_packet(SYS_CMD_BUF.as_ptr()) }
     }
 
     #[cfg(feature = "mac")]
-    pub async fn shci_c2_mac_802_15_4_init(&self) -> Result<SchiCommandStatus, ()> {
-        use crate::tables::{
-            MAC_802_15_4_CMD_BUFFER, MAC_802_15_4_NOTIF_RSP_EVT_BUFFER, Mac802_15_4Table, TL_MAC_802_15_4_TABLE,
-            TL_TRACES_TABLE, TRACES_EVT_QUEUE, TracesTable,
-        };
-
-        unsafe {
-            LinkedListNode::init_head(TRACES_EVT_QUEUE.as_mut_ptr() as *mut _);
-
-            TL_TRACES_TABLE.as_mut_ptr().write_volatile(TracesTable {
-                traces_queue: TRACES_EVT_QUEUE.as_ptr() as *const _,
-            });
-
-            TL_MAC_802_15_4_TABLE.as_mut_ptr().write_volatile(Mac802_15_4Table {
-                p_cmdrsp_buffer: MAC_802_15_4_CMD_BUFFER.as_mut_ptr().cast(),
-                p_notack_buffer: MAC_802_15_4_NOTIF_RSP_EVT_BUFFER.as_mut_ptr().cast(),
-                evt_queue: core::ptr::null_mut(),
-            });
-        };
-
+    pub async fn shci_c2_mac_802_15_4_init(&mut self) -> Result<SchiCommandStatus, ()> {
         self.write_and_get_response(ShciOpcode::Mac802_15_4Init, &[]).await
     }
 
@@ -90,7 +78,7 @@ impl Sys {
     /// `HW_IPCC_SYS_EvtNot`, aka `IoBusCallBackUserEvt` (as detailed in Figure 65), aka
     /// [crate::sub::ble::hci::host::uart::UartHci::read].
     #[cfg(feature = "ble")]
-    pub async fn shci_c2_ble_init(&self, param: ShciBleInitCmdParam) -> Result<SchiCommandStatus, ()> {
+    pub async fn shci_c2_ble_init(&mut self, param: ShciBleInitCmdParam) -> Result<SchiCommandStatus, ()> {
         self.write_and_get_response(ShciOpcode::BleInit, param.payload()).await
     }
 
@@ -99,14 +87,15 @@ impl Sys {
     /// This method takes the place of the `HW_IPCC_SYS_EvtNot`/`SysUserEvtRx`/`APPE_SysUserEvtRx`,
     /// as the embassy implementation avoids the need to call C public bindings, and instead
     /// handles the event channels directly.
-    pub async fn read(&self) -> EvtBox<mm::MemoryManager> {
-        Ipcc::receive(channels::cpu2::IPCC_SYSTEM_EVENT_CHANNEL, || unsafe {
-            if let Some(node_ptr) = LinkedListNode::remove_head(SYSTEM_EVT_QUEUE.as_mut_ptr()) {
-                Some(EvtBox::new(node_ptr.cast()))
-            } else {
-                None
-            }
-        })
-        .await
+    pub async fn read<'b>(&mut self) -> EvtBox<mm::MemoryManager<'b>> {
+        self.ipcc_system_event_channel
+            .receive(|| unsafe {
+                if let Some(node_ptr) = LinkedListNode::remove_head(SYSTEM_EVT_QUEUE.as_mut_ptr()) {
+                    Some(EvtBox::new(node_ptr.cast()))
+                } else {
+                    None
+                }
+            })
+            .await
     }
 }
diff --git a/embassy-stm32-wpan/src/tables.rs b/embassy-stm32-wpan/src/tables.rs
index 1dafed159..20d2c190f 100644
--- a/embassy-stm32-wpan/src/tables.rs
+++ b/embassy-stm32-wpan/src/tables.rs
@@ -191,93 +191,93 @@ pub struct RefTable {
 
 // --------------------- ref table ---------------------
 #[unsafe(link_section = "TL_REF_TABLE")]
-pub static mut TL_REF_TABLE: MaybeUninit<RefTable> = MaybeUninit::uninit();
+pub static mut TL_REF_TABLE: MaybeUninit<RefTable> = MaybeUninit::zeroed();
 
 #[unsafe(link_section = "MB_MEM1")]
-pub static mut TL_DEVICE_INFO_TABLE: Aligned<A4, MaybeUninit<DeviceInfoTable>> = Aligned(MaybeUninit::uninit());
+pub static mut TL_DEVICE_INFO_TABLE: Aligned<A4, MaybeUninit<DeviceInfoTable>> = Aligned(MaybeUninit::zeroed());
 
 #[unsafe(link_section = "MB_MEM1")]
-pub static mut TL_BLE_TABLE: Aligned<A4, MaybeUninit<BleTable>> = Aligned(MaybeUninit::uninit());
+pub static mut TL_BLE_TABLE: Aligned<A4, MaybeUninit<BleTable>> = Aligned(MaybeUninit::zeroed());
 
 #[unsafe(link_section = "MB_MEM1")]
-pub static mut TL_THREAD_TABLE: Aligned<A4, MaybeUninit<ThreadTable>> = Aligned(MaybeUninit::uninit());
+pub static mut TL_THREAD_TABLE: Aligned<A4, MaybeUninit<ThreadTable>> = Aligned(MaybeUninit::zeroed());
 
 #[unsafe(link_section = "MB_MEM1")]
-pub static mut TL_LLD_TESTS_TABLE: Aligned<A4, MaybeUninit<LldTestsTable>> = Aligned(MaybeUninit::uninit());
+pub static mut TL_LLD_TESTS_TABLE: Aligned<A4, MaybeUninit<LldTestsTable>> = Aligned(MaybeUninit::zeroed());
 
 #[unsafe(link_section = "MB_MEM1")]
-pub static mut TL_BLE_LLD_TABLE: Aligned<A4, MaybeUninit<BleLldTable>> = Aligned(MaybeUninit::uninit());
+pub static mut TL_BLE_LLD_TABLE: Aligned<A4, MaybeUninit<BleLldTable>> = Aligned(MaybeUninit::zeroed());
 
 #[unsafe(link_section = "MB_MEM1")]
-pub static mut TL_SYS_TABLE: Aligned<A4, MaybeUninit<SysTable>> = Aligned(MaybeUninit::uninit());
+pub static mut TL_SYS_TABLE: Aligned<A4, MaybeUninit<SysTable>> = Aligned(MaybeUninit::zeroed());
 
 #[unsafe(link_section = "MB_MEM1")]
-pub static mut TL_MEM_MANAGER_TABLE: Aligned<A4, MaybeUninit<MemManagerTable>> = Aligned(MaybeUninit::uninit());
+pub static mut TL_MEM_MANAGER_TABLE: Aligned<A4, MaybeUninit<MemManagerTable>> = Aligned(MaybeUninit::zeroed());
 
 #[unsafe(link_section = "MB_MEM1")]
-pub static mut TL_TRACES_TABLE: Aligned<A4, MaybeUninit<TracesTable>> = Aligned(MaybeUninit::uninit());
+pub static mut TL_TRACES_TABLE: Aligned<A4, MaybeUninit<TracesTable>> = Aligned(MaybeUninit::zeroed());
 
 #[unsafe(link_section = "MB_MEM1")]
-pub static mut TL_MAC_802_15_4_TABLE: Aligned<A4, MaybeUninit<Mac802_15_4Table>> = Aligned(MaybeUninit::uninit());
+pub static mut TL_MAC_802_15_4_TABLE: Aligned<A4, MaybeUninit<Mac802_15_4Table>> = Aligned(MaybeUninit::zeroed());
 
 #[unsafe(link_section = "MB_MEM1")]
-pub static mut TL_ZIGBEE_TABLE: Aligned<A4, MaybeUninit<ZigbeeTable>> = Aligned(MaybeUninit::uninit());
+pub static mut TL_ZIGBEE_TABLE: Aligned<A4, MaybeUninit<ZigbeeTable>> = Aligned(MaybeUninit::zeroed());
 
 // --------------------- tables ---------------------
 #[unsafe(link_section = "MB_MEM1")]
-pub static mut FREE_BUF_QUEUE: Aligned<A4, MaybeUninit<LinkedListNode>> = Aligned(MaybeUninit::uninit());
+pub static mut FREE_BUF_QUEUE: Aligned<A4, MaybeUninit<LinkedListNode>> = Aligned(MaybeUninit::zeroed());
 
 #[allow(dead_code)]
 #[unsafe(link_section = "MB_MEM1")]
-pub static mut TRACES_EVT_QUEUE: Aligned<A4, MaybeUninit<LinkedListNode>> = Aligned(MaybeUninit::uninit());
+pub static mut TRACES_EVT_QUEUE: Aligned<A4, MaybeUninit<LinkedListNode>> = Aligned(MaybeUninit::zeroed());
 
 #[unsafe(link_section = "MB_MEM2")]
 pub static mut CS_BUFFER: Aligned<A4, MaybeUninit<[u8; TL_PACKET_HEADER_SIZE + TL_EVT_HEADER_SIZE + TL_CS_EVT_SIZE]>> =
-    Aligned(MaybeUninit::uninit());
+    Aligned(MaybeUninit::zeroed());
 
 #[unsafe(link_section = "MB_MEM2")]
-pub static mut EVT_QUEUE: Aligned<A4, MaybeUninit<LinkedListNode>> = Aligned(MaybeUninit::uninit());
+pub static mut EVT_QUEUE: Aligned<A4, MaybeUninit<LinkedListNode>> = Aligned(MaybeUninit::zeroed());
 
 #[unsafe(link_section = "MB_MEM2")]
-pub static mut SYSTEM_EVT_QUEUE: Aligned<A4, MaybeUninit<LinkedListNode>> = Aligned(MaybeUninit::uninit());
+pub static mut SYSTEM_EVT_QUEUE: Aligned<A4, MaybeUninit<LinkedListNode>> = Aligned(MaybeUninit::zeroed());
 
 // --------------------- app tables ---------------------
 #[cfg(feature = "mac")]
 #[unsafe(link_section = "MB_MEM2")]
-pub static mut MAC_802_15_4_CMD_BUFFER: Aligned<A4, MaybeUninit<CmdPacket>> = Aligned(MaybeUninit::uninit());
+pub static mut MAC_802_15_4_CMD_BUFFER: Aligned<A4, MaybeUninit<CmdPacket>> = Aligned(MaybeUninit::zeroed());
 
 #[cfg(feature = "mac")]
 #[unsafe(link_section = "MB_MEM2")]
 pub static mut MAC_802_15_4_NOTIF_RSP_EVT_BUFFER: MaybeUninit<
     Aligned<A4, [u8; TL_PACKET_HEADER_SIZE + TL_EVT_HEADER_SIZE + 255]>,
-> = MaybeUninit::uninit();
+> = MaybeUninit::zeroed();
 
 #[unsafe(link_section = "MB_MEM2")]
-pub static mut EVT_POOL: Aligned<A4, MaybeUninit<[u8; POOL_SIZE]>> = Aligned(MaybeUninit::uninit());
+pub static mut EVT_POOL: Aligned<A4, MaybeUninit<[u8; POOL_SIZE]>> = Aligned(MaybeUninit::zeroed());
 
 #[unsafe(link_section = "MB_MEM2")]
-pub static mut SYS_CMD_BUF: Aligned<A4, MaybeUninit<CmdPacket>> = Aligned(MaybeUninit::uninit());
+pub static mut SYS_CMD_BUF: Aligned<A4, MaybeUninit<CmdPacket>> = Aligned(MaybeUninit::zeroed());
 
 #[unsafe(link_section = "MB_MEM2")]
 pub static mut SYS_SPARE_EVT_BUF: Aligned<A4, MaybeUninit<[u8; TL_PACKET_HEADER_SIZE + TL_EVT_HEADER_SIZE + 255]>> =
-    Aligned(MaybeUninit::uninit());
+    Aligned(MaybeUninit::zeroed());
 
 #[cfg(feature = "mac")]
 #[unsafe(link_section = "MB_MEM2")]
 pub static mut MAC_802_15_4_CNFINDNOT: Aligned<A4, MaybeUninit<[u8; C_SIZE_CMD_STRING]>> =
-    Aligned(MaybeUninit::uninit());
+    Aligned(MaybeUninit::zeroed());
 
 #[cfg(feature = "ble")]
 #[unsafe(link_section = "MB_MEM1")]
-pub static mut BLE_CMD_BUFFER: Aligned<A4, MaybeUninit<CmdPacket>> = Aligned(MaybeUninit::uninit());
+pub static mut BLE_CMD_BUFFER: Aligned<A4, MaybeUninit<CmdPacket>> = Aligned(MaybeUninit::zeroed());
 
 #[cfg(feature = "ble")]
 #[unsafe(link_section = "MB_MEM2")]
 pub static mut BLE_SPARE_EVT_BUF: Aligned<A4, MaybeUninit<[u8; TL_PACKET_HEADER_SIZE + TL_EVT_HEADER_SIZE + 255]>> =
-    Aligned(MaybeUninit::uninit());
+    Aligned(MaybeUninit::zeroed());
 
 #[cfg(feature = "ble")]
 #[unsafe(link_section = "MB_MEM2")]
 //                                                 fuck these "magic" numbers from ST ---v---v
 pub static mut HCI_ACL_DATA_BUFFER: Aligned<A4, MaybeUninit<[u8; TL_PACKET_HEADER_SIZE + 5 + 251]>> =
-    Aligned(MaybeUninit::uninit());
+    Aligned(MaybeUninit::zeroed());
diff --git a/embassy-stm32/CHANGELOG.md b/embassy-stm32/CHANGELOG.md
index 3431848d3..d3e5ba48d 100644
--- a/embassy-stm32/CHANGELOG.md
+++ b/embassy-stm32/CHANGELOG.md
@@ -7,6 +7,22 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ## Unreleased - ReleaseDate
 
+- feat: Add continuous waveform method to SimplePWM
+- change: remove waveform timer method
+- change: low power: store stop mode for dma channels
+- fix: Fixed ADC4 enable() for WBA
+- feat: allow use of anyadcchannel for adc4
+- fix: fix incorrect logic for buffered usart transmission complete.
+- feat: add poll_for methods to exti
+- feat: implement stop for stm32wb.
+- change: rework hsem and add HIL test for some chips.
+- change: stm32/eth: ethernet no longer has a hard dependency on station management, and station management can be used independently ([#4871](https://github.com/embassy-rs/embassy/pull/4871))
+- feat: allow embassy_executor::main for low power
+- feat: Add waveform methods to ComplementaryPwm
+- fix: Avoid generating timer update events when updating the frequency ([#4890](https://github.com/embassy-rs/embassy/pull/4890))
+- chore: cleanup low-power add time
+- fix: Allow setting SAI peripheral `frame_length` to `256`
+- fix: flash erase on dual-bank STM32Gxxx
 - feat: Add support for STM32N657X0
 - feat: timer: Add 32-bit timer support to SimplePwm waveform_up method following waveform pattern ([#4717](https://github.com/embassy-rs/embassy/pull/4717))
 - feat: Add support for injected ADC measurements for g4 ([#4840](https://github.com/embassy-rs/embassy/pull/4840))
@@ -26,7 +42,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - feat: Configurable gpio speed for QSPI
 - feat: derive Clone, Copy and defmt::Format for all *SPI-related configs
 - fix: handle address and data-length errors in OSPI
-- feat: Allow OSPI DMA writes larger than 64kB using chunking
+- feat: Allow OSPI/HSPI/XSPI DMA writes larger than 64kB using chunking
 - feat: More ADC enums for g0 PAC, API change for oversampling, allow separate sample times
 - feat: Add USB CRS sync support for STM32C071
 - fix: RTC register definition for STM32L4P5 and L4Q5 as they use v3 register map.
@@ -37,13 +53,16 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - feat: stm32/usart: add `eager_reads` option to control if buffered readers return as soon as possible or after more data is available ([#4668](https://github.com/embassy-rs/embassy/pull/4668))
 - feat: stm32/usart: add `de_assertion_time` and `de_deassertion_time` config options
 - change: stm32/uart: BufferedUartRx now returns all available bytes from the internal buffer
+- fix: Properly set the transfer size for OSPI/HSPI/XSPI transfers with word sizes other than 8 bits.
+- fix: stm32/adc: Calculate the ADC prescaler in a way that it allows for the max frequency to be reached
 - fix: Prevent a HardFault crash on STM32H5 devices by changing `uid()` to return `[u8; 12]` by value instead of a reference. (Fixes #2696)
 - change: timer: added output compare values
 - feat: timer: add ability to set master mode
 - fix: sdmmc: don't wait for DBCKEND flag on sdmmc_v2 devices as it never fires (Fixes #4723)
 - fix: usart: fix race condition in ringbuffered usart
 - feat: Add backup_sram::init() for H5 devices to access BKPSRAM
-- feat: Add I2C MultiMaster (Slave) support for I2C v1
+- feat: stm32/i2c v1: Add I2C MultiMaster (Slave) support
+- feat: stm32/i2c v2: Add transaction() and blocking_transaction() methods with contract-compliant operation merging
 - feat: stm32/fdcan: add ability to control automatic recovery from bus off ([#4821](https://github.com/embassy-rs/embassy/pull/4821))
 - low-power: update rtc api to allow reconfig
 - adc: consolidate ringbuffer
@@ -55,6 +74,14 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - chore: Updated stm32-metapac and stm32-data dependencies
 - adc: reogranize and cleanup somewhat. require sample_time to be passed on conversion
 - fix: stm32/i2c v2 slave: prevent misaligned reads, error false positives, and incorrect counts of bytes read/written
+- feat: add flash support for c0 family ([#4874](https://github.com/embassy-rs/embassy/pull/4874))
+- fix: fixing channel numbers on vbat and vddcore for adc on adc
+- adc: adding disable to vbat
+- feat: stm32/flash: add async support for h7 family
+- feat: exti brought in line with other drivers' interrupt rebinding system ([#4922](https://github.com/embassy-rs/embassy/pull/4922))
+- removal: ExtiInput no longer accepts AnyPin/AnyChannel; AnyChannel removed entirely
+- fix: build script ensures EXTI2_TSC is listed as the IRQ of EXTI2 even if the PAC doesn't
+- feat: stm32/lcd: added implementation
 
 ## 0.4.0 - 2025-08-26
 
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index a722d2379..e10409112 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -139,6 +139,7 @@ flavors = [
     { regex_feature = "stm32wb.*", target = "thumbv7em-none-eabi" },
     { regex_feature = "stm32wba.*", target = "thumbv8m.main-none-eabihf" },
     { regex_feature = "stm32wl.*", target = "thumbv7em-none-eabi" },
+    { regex_feature = "stm32n6.*", target = "thumbv8m.main-none-eabihf" },
 ]
 
 [package.metadata.docs.rs]
@@ -187,6 +188,7 @@ embedded-io = { version = "0.6.0" }
 embedded-io-async = { version = "0.6.1" }
 chrono = { version = "^0.4", default-features = false, optional = true }
 bit_field = "0.10.2"
+trait-set = "0.3.0"
 document-features = "0.2.7"
 
 static_assertions = { version = "1.1" }
@@ -198,11 +200,11 @@ aligned = "0.4.1"
 heapless = "0.9.1"
 
 #stm32-metapac = { version = "18" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-b77c8d968f53b18d6bdcd052e354b5070ec2bbc2" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-f61ed017ef12ec84ff04c49e3147694bda3b29cb" }
 
 [build-dependencies]
 #stm32-metapac = { version = "18", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-b77c8d968f53b18d6bdcd052e354b5070ec2bbc2", default-features = false, features = ["metadata"] }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-f61ed017ef12ec84ff04c49e3147694bda3b29cb", default-features = false, features = ["metadata"] }
 
 proc-macro2 = "1.0.36"
 quote = "1.0.15"
@@ -1642,7 +1644,30 @@ stm32l562qe = [ "stm32-metapac/stm32l562qe" ]
 stm32l562re = [ "stm32-metapac/stm32l562re" ]
 stm32l562ve = [ "stm32-metapac/stm32l562ve" ]
 stm32l562ze = [ "stm32-metapac/stm32l562ze" ]
+stm32n645a0 = [ "stm32-metapac/stm32n645a0" ]
+stm32n645b0 = [ "stm32-metapac/stm32n645b0" ]
+stm32n645i0 = [ "stm32-metapac/stm32n645i0" ]
+stm32n645l0 = [ "stm32-metapac/stm32n645l0" ]
+stm32n645x0 = [ "stm32-metapac/stm32n645x0" ]
+stm32n645z0 = [ "stm32-metapac/stm32n645z0" ]
+stm32n647a0 = [ "stm32-metapac/stm32n647a0" ]
+stm32n647b0 = [ "stm32-metapac/stm32n647b0" ]
+stm32n647i0 = [ "stm32-metapac/stm32n647i0" ]
+stm32n647l0 = [ "stm32-metapac/stm32n647l0" ]
+stm32n647x0 = [ "stm32-metapac/stm32n647x0" ]
+stm32n647z0 = [ "stm32-metapac/stm32n647z0" ]
+stm32n655a0 = [ "stm32-metapac/stm32n655a0" ]
+stm32n655b0 = [ "stm32-metapac/stm32n655b0" ]
+stm32n655i0 = [ "stm32-metapac/stm32n655i0" ]
+stm32n655l0 = [ "stm32-metapac/stm32n655l0" ]
+stm32n655x0 = [ "stm32-metapac/stm32n655x0" ]
+stm32n655z0 = [ "stm32-metapac/stm32n655z0" ]
+stm32n657a0 = [ "stm32-metapac/stm32n657a0" ]
+stm32n657b0 = [ "stm32-metapac/stm32n657b0" ]
+stm32n657i0 = [ "stm32-metapac/stm32n657i0" ]
+stm32n657l0 = [ "stm32-metapac/stm32n657l0" ]
 stm32n657x0 = [ "stm32-metapac/stm32n657x0" ]
+stm32n657z0 = [ "stm32-metapac/stm32n657z0" ]
 stm32u031c6 = [ "stm32-metapac/stm32u031c6" ]
 stm32u031c8 = [ "stm32-metapac/stm32u031c8" ]
 stm32u031f4 = [ "stm32-metapac/stm32u031f4" ]
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 48da475df..109571e8f 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -170,6 +170,11 @@ fn main() {
                     }
                     singletons.push(p.name.to_string());
                 }
+
+                "eth" => {
+                    singletons.push(p.name.to_string());
+                    singletons.push("ETH_SMA".to_string());
+                }
                 //"dbgmcu" => {}
                 //"syscfg" => {}
                 //"dma" => {}
@@ -348,8 +353,13 @@ fn main() {
     // ========
     // Generate interrupt declarations
 
+    let mut exti2_tsc_shared_int_present: Option<stm32_metapac::metadata::Interrupt> = None;
     let mut irqs = Vec::new();
     for irq in METADATA.interrupts {
+        // The PAC doesn't ensure this is listed as the IRQ of EXTI2, so we must do so
+        if irq.name == "EXTI2_TSC" {
+            exti2_tsc_shared_int_present = Some(irq.clone())
+        }
         irqs.push(format_ident!("{}", irq.name));
     }
 
@@ -1347,6 +1357,9 @@ fn main() {
         (("tsc", "G8_IO2"), quote!(crate::tsc::G8IO2Pin)),
         (("tsc", "G8_IO3"), quote!(crate::tsc::G8IO3Pin)),
         (("tsc", "G8_IO4"), quote!(crate::tsc::G8IO4Pin)),
+        (("lcd", "SEG"), quote!(crate::lcd::SegPin)),
+        (("lcd", "COM"), quote!(crate::lcd::ComPin)),
+        (("lcd", "VLCD"), quote!(crate::lcd::VlcdPin)),
         (("dac", "OUT1"), quote!(crate::dac::DacPin<Ch1>)),
         (("dac", "OUT2"), quote!(crate::dac::DacPin<Ch2>)),
     ].into();
@@ -1354,9 +1367,22 @@ fn main() {
     for p in METADATA.peripherals {
         if let Some(regs) = &p.registers {
             let mut adc_pairs: BTreeMap<u8, (Option<Ident>, Option<Ident>)> = BTreeMap::new();
+            let mut seen_lcd_seg_pins = HashSet::new();
 
             for pin in p.pins {
-                let key = (regs.kind, pin.signal);
+                let mut key = (regs.kind, pin.signal);
+
+                // LCD is special. There are so many pins!
+                if regs.kind == "lcd" {
+                    key.1 = pin.signal.trim_end_matches(char::is_numeric);
+
+                    if key.1 == "SEG" && !seen_lcd_seg_pins.insert(pin.pin) {
+                        // LCD has SEG pins multiplexed in the peripheral
+                        // This means we can see them twice. We need to skip those so we're not impl'ing the trait twice
+                        continue;
+                    }
+                }
+
                 if let Some(tr) = signals.get(&key) {
                     let mut peri = format_ident!("{}", p.name);
 
@@ -1399,6 +1425,11 @@ fn main() {
                         }
                     }
 
+                    // MDIO and MDC are special
+                    if pin.signal == "MDIO" || pin.signal == "MDC" {
+                        peri = format_ident!("{}", "ETH_SMA");
+                    }
+
                     // XSPI NCS pin to CSSEL mapping
                     if pin.signal.ends_with("NCS1") {
                         g.extend(quote! {
@@ -1602,13 +1633,13 @@ fn main() {
     .into();
 
     if chip_name.starts_with("stm32u5") {
-        signals.insert(("adc", "ADC4"), quote!(crate::adc::RxDma4));
+        signals.insert(("adc", "ADC4"), quote!(crate::adc::RxDma));
     } else {
         signals.insert(("adc", "ADC4"), quote!(crate::adc::RxDma));
     }
 
     if chip_name.starts_with("stm32wba") {
-        signals.insert(("adc", "ADC4"), quote!(crate::adc::RxDma4));
+        signals.insert(("adc", "ADC4"), quote!(crate::adc::RxDma));
     }
 
     if chip_name.starts_with("stm32g4") {
@@ -1695,70 +1726,88 @@ fn main() {
     }
 
     // ========
-    // Generate Div/Mul impls for RCC prescalers/dividers/multipliers.
-    for e in rcc_registers.ir.enums {
-        fn is_rcc_name(e: &str) -> bool {
-            match e {
-                "Pllp" | "Pllq" | "Pllr" | "Plldivst" | "Pllm" | "Plln" | "Prediv1" | "Prediv2" | "Hpre5" => true,
-                "Timpre" | "Pllrclkpre" => false,
-                e if e.ends_with("pre") || e.ends_with("pres") || e.ends_with("div") || e.ends_with("mul") => true,
-                _ => false,
+    // Generate Div/Mul impls for RCC and ADC prescalers/dividers/multipliers.
+    for (kind, psc_enums) in ["rcc", "adc", "adccommon"].iter().filter_map(|kind| {
+        METADATA
+            .peripherals
+            .iter()
+            .filter_map(|p| p.registers.as_ref())
+            .find(|r| r.kind == *kind)
+            .map(|r| (*kind, r.ir.enums))
+    }) {
+        for e in psc_enums.iter() {
+            fn is_adc_name(e: &str) -> bool {
+                match e {
+                    "Presc" | "Adc4Presc" | "Adcpre" => true,
+                    _ => false,
+                }
             }
-        }
 
-        fn parse_num(n: &str) -> Result<Frac, ()> {
-            for prefix in ["DIV", "MUL"] {
-                if let Some(n) = n.strip_prefix(prefix) {
-                    let exponent = n.find('_').map(|e| n.len() - 1 - e).unwrap_or(0) as u32;
-                    let mantissa = n.replace('_', "").parse().map_err(|_| ())?;
-                    let f = Frac {
-                        num: mantissa,
-                        denom: 10u32.pow(exponent),
-                    };
-                    return Ok(f.simplify());
+            fn is_rcc_name(e: &str) -> bool {
+                match e {
+                    "Pllp" | "Pllq" | "Pllr" | "Plldivst" | "Pllm" | "Plln" | "Prediv1" | "Prediv2" | "Hpre5" => true,
+                    "Timpre" | "Pllrclkpre" => false,
+                    e if e.ends_with("pre") || e.ends_with("pres") || e.ends_with("div") || e.ends_with("mul") => true,
+                    _ => false,
                 }
             }
-            Err(())
-        }
 
-        if is_rcc_name(e.name) {
-            let enum_name = format_ident!("{}", e.name);
-            let mut muls = Vec::new();
-            let mut divs = Vec::new();
-            for v in e.variants {
-                let Ok(val) = parse_num(v.name) else {
-                    panic!("could not parse mul/div. enum={} variant={}", e.name, v.name)
-                };
-                let variant_name = format_ident!("{}", v.name);
-                let variant = quote!(crate::pac::rcc::vals::#enum_name::#variant_name);
-                let num = val.num;
-                let denom = val.denom;
-                muls.push(quote!(#variant => self * #num / #denom,));
-                divs.push(quote!(#variant => self * #denom / #num,));
+            fn parse_num(n: &str) -> Result<Frac, ()> {
+                for prefix in ["DIV", "MUL"] {
+                    if let Some(n) = n.strip_prefix(prefix) {
+                        let exponent = n.find('_').map(|e| n.len() - 1 - e).unwrap_or(0) as u32;
+                        let mantissa = n.replace('_', "").parse().map_err(|_| ())?;
+                        let f = Frac {
+                            num: mantissa,
+                            denom: 10u32.pow(exponent),
+                        };
+                        return Ok(f.simplify());
+                    }
+                }
+                Err(())
             }
 
-            g.extend(quote! {
-                impl core::ops::Div<crate::pac::rcc::vals::#enum_name> for crate::time::Hertz {
-                    type Output = crate::time::Hertz;
-                    fn div(self, rhs: crate::pac::rcc::vals::#enum_name) -> Self::Output {
-                        match rhs {
-                            #(#divs)*
-                            #[allow(unreachable_patterns)]
-                            _ => unreachable!(),
+            if (kind == "rcc" && is_rcc_name(e.name)) || ((kind == "adccommon" || kind == "adc") && is_adc_name(e.name))
+            {
+                let kind = format_ident!("{}", kind);
+                let enum_name = format_ident!("{}", e.name);
+                let mut muls = Vec::new();
+                let mut divs = Vec::new();
+                for v in e.variants {
+                    let Ok(val) = parse_num(v.name) else {
+                        panic!("could not parse mul/div. enum={} variant={}", e.name, v.name)
+                    };
+                    let variant_name = format_ident!("{}", v.name);
+                    let variant = quote!(crate::pac::#kind::vals::#enum_name::#variant_name);
+                    let num = val.num;
+                    let denom = val.denom;
+                    muls.push(quote!(#variant => self * #num / #denom,));
+                    divs.push(quote!(#variant => self * #denom / #num,));
+                }
+
+                g.extend(quote! {
+                    impl core::ops::Div<crate::pac::#kind::vals::#enum_name> for crate::time::Hertz {
+                        type Output = crate::time::Hertz;
+                        fn div(self, rhs: crate::pac::#kind::vals::#enum_name) -> Self::Output {
+                            match rhs {
+                                #(#divs)*
+                                #[allow(unreachable_patterns)]
+                                _ => unreachable!(),
+                            }
                         }
                     }
-                }
-                impl core::ops::Mul<crate::pac::rcc::vals::#enum_name> for crate::time::Hertz {
-                    type Output = crate::time::Hertz;
-                    fn mul(self, rhs: crate::pac::rcc::vals::#enum_name) -> Self::Output {
-                        match rhs {
-                            #(#muls)*
-                            #[allow(unreachable_patterns)]
-                            _ => unreachable!(),
+                    impl core::ops::Mul<crate::pac::#kind::vals::#enum_name> for crate::time::Hertz {
+                        type Output = crate::time::Hertz;
+                        fn mul(self, rhs: crate::pac::#kind::vals::#enum_name) -> Self::Output {
+                            match rhs {
+                                #(#muls)*
+                                #[allow(unreachable_patterns)]
+                                _ => unreachable!(),
+                            }
                         }
                     }
-                }
-            });
+                });
+            }
         }
     }
 
@@ -1768,7 +1817,19 @@ fn main() {
     for p in METADATA.peripherals {
         let mut pt = TokenStream::new();
 
+        let mut exti2_tsc_injected = false;
+        if let Some(ref irq) = exti2_tsc_shared_int_present
+            && p.name == "EXTI"
+        {
+            exti2_tsc_injected = true;
+            let iname = format_ident!("{}", irq.name);
+            let sname = format_ident!("{}", "EXTI2");
+            pt.extend(quote!(pub type #sname = crate::interrupt::typelevel::#iname;));
+        }
         for irq in p.interrupts {
+            if exti2_tsc_injected && irq.signal == "EXTI2" {
+                continue;
+            }
             let iname = format_ident!("{}", irq.interrupt);
             let sname = format_ident!("{}", irq.signal);
             pt.extend(quote!(pub type #sname = crate::interrupt::typelevel::#iname;));
@@ -1919,6 +1980,19 @@ fn main() {
             continue;
         }
 
+        let stop_mode = METADATA
+            .peripherals
+            .iter()
+            .find(|p| p.name == ch.dma)
+            .map(|p| p.rcc.as_ref().map(|rcc| rcc.stop_mode.clone()).unwrap_or_default())
+            .unwrap_or_default();
+
+        let stop_mode = match stop_mode {
+            StopMode::Standby => quote! { Standby },
+            StopMode::Stop2 => quote! { Stop2 },
+            StopMode::Stop1 => quote! { Stop1 },
+        };
+
         let name = format_ident!("{}", ch.name);
         let idx = ch_idx as u8;
         #[cfg(feature = "_dual-core")]
@@ -1931,7 +2005,7 @@ fn main() {
             quote!(crate::pac::Interrupt::#irq_name)
         };
 
-        g.extend(quote!(dma_channel_impl!(#name, #idx);));
+        g.extend(quote!(dma_channel_impl!(#name, #idx, #stop_mode);));
 
         let dma = format_ident!("{}", ch.dma);
         let ch_num = ch.channel as usize;
diff --git a/embassy-stm32/src/adc/adc4.rs b/embassy-stm32/src/adc/adc4.rs
index befa8ed4a..453513309 100644
--- a/embassy-stm32/src/adc/adc4.rs
+++ b/embassy-stm32/src/adc/adc4.rs
@@ -4,8 +4,8 @@ use pac::adc::vals::{Adc4Dmacfg as Dmacfg, Adc4Exten as Exten, Adc4OversamplingR
 #[cfg(stm32wba)]
 use pac::adc::vals::{Chselrmod, Cont, Dmacfg, Exten, OversamplingRatio, Ovss, Smpsel};
 
-use super::{AdcChannel, AnyAdcChannel, RxDma4, SealedAdcChannel, blocking_delay_us};
-use crate::dma::Transfer;
+use super::blocking_delay_us;
+use crate::adc::ConversionMode;
 #[cfg(stm32u5)]
 pub use crate::pac::adc::regs::Adc4Chselrmod0 as Chselr;
 #[cfg(stm32wba)]
@@ -24,56 +24,24 @@ pub const VREF_DEFAULT_MV: u32 = 3300;
 /// VREF voltage used for factory calibration of VREFINTCAL register.
 pub const VREF_CALIB_MV: u32 = 3300;
 
-const VREF_CHANNEL: u8 = 0;
-const VCORE_CHANNEL: u8 = 12;
-const TEMP_CHANNEL: u8 = 13;
-const VBAT_CHANNEL: u8 = 14;
-const DAC_CHANNEL: u8 = 21;
-
-// NOTE: Vrefint/Temperature/Vbat are not available on all ADCs, this currently cannot be modeled with stm32-data, so these are available from the software on all ADCs
-/// Internal voltage reference channel.
-pub struct VrefInt;
-impl<T: Instance> AdcChannel<T> for VrefInt {}
-impl<T: Instance> SealedAdcChannel<T> for VrefInt {
-    fn channel(&self) -> u8 {
-        VREF_CHANNEL
-    }
+impl<'d, T: Instance> super::SealedSpecialConverter<super::VrefInt> for Adc4<'d, T> {
+    const CHANNEL: u8 = 0;
 }
 
-/// Internal temperature channel.
-pub struct Temperature;
-impl<T: Instance> AdcChannel<T> for Temperature {}
-impl<T: Instance> SealedAdcChannel<T> for Temperature {
-    fn channel(&self) -> u8 {
-        TEMP_CHANNEL
-    }
+impl<'d, T: Instance> super::SealedSpecialConverter<super::Temperature> for Adc4<'d, T> {
+    const CHANNEL: u8 = 13;
 }
 
-/// Internal battery voltage channel.
-pub struct Vbat;
-impl<T: Instance> AdcChannel<T> for Vbat {}
-impl<T: Instance> SealedAdcChannel<T> for Vbat {
-    fn channel(&self) -> u8 {
-        VBAT_CHANNEL
-    }
+impl<'d, T: Instance> super::SealedSpecialConverter<super::Vcore> for Adc4<'d, T> {
+    const CHANNEL: u8 = 12;
 }
 
-/// Internal DAC channel.
-pub struct Dac;
-impl<T: Instance> AdcChannel<T> for Dac {}
-impl<T: Instance> SealedAdcChannel<T> for Dac {
-    fn channel(&self) -> u8 {
-        DAC_CHANNEL
-    }
+impl<'d, T: Instance> super::SealedSpecialConverter<super::Vbat> for Adc4<'d, T> {
+    const CHANNEL: u8 = 14;
 }
 
-/// Internal Vcore channel.
-pub struct Vcore;
-impl<T: Instance> AdcChannel<T> for Vcore {}
-impl<T: Instance> SealedAdcChannel<T> for Vcore {
-    fn channel(&self) -> u8 {
-        VCORE_CHANNEL
-    }
+impl<'d, T: Instance> super::SealedSpecialConverter<super::Dac> for Adc4<'d, T> {
+    const CHANNEL: u8 = 21;
 }
 
 #[derive(Copy, Clone)]
@@ -108,71 +76,17 @@ pub const fn resolution_to_max_count(res: Resolution) -> u32 {
     }
 }
 
-// NOTE (unused): The prescaler enum closely copies the hardware capabilities,
-// but high prescaling doesn't make a lot of sense in the current implementation and is ommited.
-#[allow(unused)]
-enum Prescaler {
-    NotDivided,
-    DividedBy2,
-    DividedBy4,
-    DividedBy6,
-    DividedBy8,
-    DividedBy10,
-    DividedBy12,
-    DividedBy16,
-    DividedBy32,
-    DividedBy64,
-    DividedBy128,
-    DividedBy256,
-}
-
-impl Prescaler {
-    fn from_ker_ck(frequency: Hertz) -> Self {
-        let raw_prescaler = frequency.0 / MAX_ADC_CLK_FREQ.0;
-        match raw_prescaler {
-            0 => Self::NotDivided,
-            1 => Self::DividedBy2,
-            2..=3 => Self::DividedBy4,
-            4..=5 => Self::DividedBy6,
-            6..=7 => Self::DividedBy8,
-            8..=9 => Self::DividedBy10,
-            10..=11 => Self::DividedBy12,
-            _ => unimplemented!(),
-        }
-    }
-
-    fn divisor(&self) -> u32 {
-        match self {
-            Prescaler::NotDivided => 1,
-            Prescaler::DividedBy2 => 2,
-            Prescaler::DividedBy4 => 4,
-            Prescaler::DividedBy6 => 6,
-            Prescaler::DividedBy8 => 8,
-            Prescaler::DividedBy10 => 10,
-            Prescaler::DividedBy12 => 12,
-            Prescaler::DividedBy16 => 16,
-            Prescaler::DividedBy32 => 32,
-            Prescaler::DividedBy64 => 64,
-            Prescaler::DividedBy128 => 128,
-            Prescaler::DividedBy256 => 256,
-        }
-    }
-
-    fn presc(&self) -> Presc {
-        match self {
-            Prescaler::NotDivided => Presc::DIV1,
-            Prescaler::DividedBy2 => Presc::DIV2,
-            Prescaler::DividedBy4 => Presc::DIV4,
-            Prescaler::DividedBy6 => Presc::DIV6,
-            Prescaler::DividedBy8 => Presc::DIV8,
-            Prescaler::DividedBy10 => Presc::DIV10,
-            Prescaler::DividedBy12 => Presc::DIV12,
-            Prescaler::DividedBy16 => Presc::DIV16,
-            Prescaler::DividedBy32 => Presc::DIV32,
-            Prescaler::DividedBy64 => Presc::DIV64,
-            Prescaler::DividedBy128 => Presc::DIV128,
-            Prescaler::DividedBy256 => Presc::DIV256,
-        }
+fn from_ker_ck(frequency: Hertz) -> Presc {
+    let raw_prescaler = rcc::raw_prescaler(frequency.0, MAX_ADC_CLK_FREQ.0);
+    match raw_prescaler {
+        0 => Presc::DIV1,
+        1 => Presc::DIV2,
+        2..=3 => Presc::DIV4,
+        4..=5 => Presc::DIV6,
+        6..=7 => Presc::DIV8,
+        8..=9 => Presc::DIV10,
+        10..=11 => Presc::DIV12,
+        _ => unimplemented!(),
     }
 }
 
@@ -185,6 +99,127 @@ pub trait Instance: SealedInstance + crate::PeripheralType + crate::rcc::RccPeri
     type Interrupt: crate::interrupt::typelevel::Interrupt;
 }
 
+foreach_adc!(
+    (ADC4, $common_inst:ident, $clock:ident) => {
+        use crate::peripherals::ADC4;
+
+        impl super::BasicAnyInstance for ADC4 {
+            type SampleTime = SampleTime;
+        }
+
+        impl super::SealedAnyInstance for ADC4 {
+            fn dr() -> *mut u16 {
+                ADC4::regs().dr().as_ptr() as *mut u16
+            }
+
+            fn enable() {
+                if !ADC4::regs().cr().read().aden()  || !ADC4::regs().isr().read().adrdy() {
+                    ADC4::regs().isr().write(|w| w.set_adrdy(true));
+                    ADC4::regs().cr().modify(|w| w.set_aden(true));
+                    while !ADC4::regs().isr().read().adrdy() {}
+                }
+            }
+
+            fn start() {
+                // Start conversion
+                ADC4::regs().cr().modify(|reg| {
+                    reg.set_adstart(true);
+                });
+            }
+
+            fn stop() {
+                let cr = ADC4::regs().cr().read();
+                if cr.adstart() {
+                    ADC4::regs().cr().modify(|w| w.set_adstp(true));
+                    while ADC4::regs().cr().read().adstart() {}
+                }
+
+                if cr.aden() || cr.adstart() {
+                    ADC4::regs().cr().modify(|w| w.set_addis(true));
+                    while ADC4::regs().cr().read().aden() {}
+                }
+
+                // Reset configuration.
+                ADC4::regs().cfgr1().modify(|reg| {
+                    reg.set_dmaen(false);
+                });
+            }
+
+            fn configure_dma(conversion_mode: ConversionMode) {
+                match conversion_mode {
+                    ConversionMode::Singular => {
+                        ADC4::regs().isr().modify(|reg| {
+                            reg.set_ovr(true);
+                            reg.set_eos(true);
+                            reg.set_eoc(true);
+                        });
+
+                        ADC4::regs().cfgr1().modify(|reg| {
+                            reg.set_dmaen(true);
+                            reg.set_dmacfg(Dmacfg::ONE_SHOT);
+                            #[cfg(stm32u5)]
+                            reg.set_chselrmod(false);
+                            #[cfg(stm32wba)]
+                            reg.set_chselrmod(Chselrmod::ENABLE_INPUT)
+                        });
+                    }
+                    #[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
+                    _ => unreachable!(),
+                }
+            }
+
+            fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
+                let mut prev_channel: i16 = -1;
+                #[cfg(stm32wba)]
+                ADC4::regs().chselr().write_value(Chselr(0_u32));
+                #[cfg(stm32u5)]
+                ADC4::regs().chselrmod0().write_value(Chselr(0_u32));
+                for (_i, ((channel, _), sample_time)) in sequence.enumerate() {
+                    ADC4::regs().smpr().modify(|w| {
+                        w.set_smp(_i, sample_time);
+                    });
+
+                    let channel_num = channel;
+                    if channel_num as i16 <= prev_channel {
+                        return;
+                    };
+                    prev_channel = channel_num as i16;
+
+                    #[cfg(stm32wba)]
+                    ADC4::regs().chselr().modify(|w| {
+                        w.set_chsel0(channel as usize, true);
+                    });
+                    #[cfg(stm32u5)]
+                    ADC4::regs().chselrmod0().modify(|w| {
+                        w.set_chsel(channel as usize, true);
+                    });
+                }
+            }
+
+            fn convert() -> u16 {
+                // Reset interrupts
+                ADC4::regs().isr().modify(|reg| {
+                    reg.set_eos(true);
+                    reg.set_eoc(true);
+                });
+
+                // Start conversion
+                ADC4::regs().cr().modify(|reg| {
+                    reg.set_adstart(true);
+                });
+
+                while !ADC4::regs().isr().read().eos() {
+                    // spin
+                }
+
+                ADC4::regs().dr().read().0 as u16
+            }
+        }
+
+        impl super::AnyInstance for ADC4 {}
+    };
+);
+
 pub struct Adc4<'d, T: Instance> {
     #[allow(unused)]
     adc: crate::Peri<'d, T>,
@@ -196,15 +231,15 @@ pub enum Adc4Error {
     DMAError,
 }
 
-impl<'d, T: Instance> Adc4<'d, T> {
+impl<'d, T: Instance + super::AnyInstance> super::Adc<'d, T> {
     /// Create a new ADC driver.
-    pub fn new(adc: Peri<'d, T>) -> Self {
+    pub fn new_adc4(adc: Peri<'d, T>) -> Self {
         rcc::enable_and_reset::<T>();
-        let prescaler = Prescaler::from_ker_ck(T::frequency());
+        let prescaler = from_ker_ck(T::frequency());
 
-        T::regs().ccr().modify(|w| w.set_presc(prescaler.presc()));
+        T::regs().ccr().modify(|w| w.set_presc(prescaler));
 
-        let frequency = Hertz(T::frequency().0 / prescaler.divisor());
+        let frequency = T::frequency() / prescaler;
         info!("ADC4 frequency set to {}", frequency);
 
         if frequency > MAX_ADC_CLK_FREQ {
@@ -214,20 +249,6 @@ impl<'d, T: Instance> Adc4<'d, T> {
             );
         }
 
-        let mut s = Self { adc };
-
-        s.power_up();
-
-        s.calibrate();
-        blocking_delay_us(1);
-
-        s.enable();
-        s.configure();
-
-        s
-    }
-
-    fn power_up(&mut self) {
         T::regs().isr().modify(|w| {
             w.set_ldordy(true);
         });
@@ -239,22 +260,15 @@ impl<'d, T: Instance> Adc4<'d, T> {
         T::regs().isr().modify(|w| {
             w.set_ldordy(true);
         });
-    }
 
-    fn calibrate(&mut self) {
         T::regs().cr().modify(|w| w.set_adcal(true));
         while T::regs().cr().read().adcal() {}
         T::regs().isr().modify(|w| w.set_eocal(true));
-    }
 
-    fn enable(&mut self) {
-        T::regs().isr().write(|w| w.set_adrdy(true));
-        T::regs().cr().modify(|w| w.set_aden(true));
-        while !T::regs().isr().read().adrdy() {}
-        T::regs().isr().write(|w| w.set_adrdy(true));
-    }
+        blocking_delay_us(1);
+
+        T::enable();
 
-    fn configure(&mut self) {
         // single conversion mode, software trigger
         T::regs().cfgr1().modify(|w| {
             #[cfg(stm32u5)]
@@ -280,61 +294,63 @@ impl<'d, T: Instance> Adc4<'d, T> {
                 w.set_smpsel(i, Smpsel::SMP1);
             }
         });
+
+        Self { adc }
     }
 
     /// Enable reading the voltage reference internal channel.
-    pub fn enable_vrefint(&self) -> VrefInt {
+    pub fn enable_vrefint_adc4(&self) -> super::VrefInt {
         T::regs().ccr().modify(|w| {
             w.set_vrefen(true);
         });
 
-        VrefInt {}
+        super::VrefInt {}
     }
 
     /// Enable reading the temperature internal channel.
-    pub fn enable_temperature(&self) -> Temperature {
+    pub fn enable_temperature_adc4(&self) -> super::Temperature {
         T::regs().ccr().modify(|w| {
             w.set_vsensesel(true);
         });
 
-        Temperature {}
+        super::Temperature {}
     }
 
     /// Enable reading the vbat internal channel.
     #[cfg(stm32u5)]
-    pub fn enable_vbat(&self) -> Vbat {
+    pub fn enable_vbat_adc4(&self) -> super::Vbat {
         T::regs().ccr().modify(|w| {
             w.set_vbaten(true);
         });
 
-        Vbat {}
+        super::Vbat {}
     }
 
     /// Enable reading the vbat internal channel.
-    pub fn enable_vcore(&self) -> Vcore {
-        Vcore {}
+    pub fn enable_vcore_adc4(&self) -> super::Vcore {
+        super::Vcore {}
     }
 
     /// Enable reading the vbat internal channel.
     #[cfg(stm32u5)]
-    pub fn enable_dac_channel(&self, dac: DacChannel) -> Dac {
+    pub fn enable_dac_channel_adc4(&self, dac: DacChannel) -> super::Dac {
         let mux;
         match dac {
             DacChannel::OUT1 => mux = false,
             DacChannel::OUT2 => mux = true,
         }
         T::regs().or().modify(|w| w.set_chn21sel(mux));
-        Dac {}
+        super::Dac {}
     }
 
     /// Set the ADC resolution.
-    pub fn set_resolution(&mut self, resolution: Resolution) {
+    pub fn set_resolution_adc4(&mut self, resolution: Resolution) {
         T::regs().cfgr1().modify(|w| w.set_res(resolution.into()));
     }
 
     /// Set hardware averaging.
     #[cfg(stm32u5)]
-    pub fn set_averaging(&mut self, averaging: Averaging) {
+    pub fn set_averaging_adc4(&mut self, averaging: Averaging) {
         let (enable, samples, right_shift) = match averaging {
             Averaging::Disabled => (false, OversamplingRatio::OVERSAMPLE2X, 0),
             Averaging::Samples2 => (true, OversamplingRatio::OVERSAMPLE2X, 1),
@@ -354,7 +370,7 @@ impl<'d, T: Instance> Adc4<'d, T> {
         })
     }
     #[cfg(stm32wba)]
-    pub fn set_averaging(&mut self, averaging: Averaging) {
+    pub fn set_averaging_adc4(&mut self, averaging: Averaging) {
         let (enable, samples, right_shift) = match averaging {
             Averaging::Disabled => (false, OversamplingRatio::OVERSAMPLE2X, Ovss::SHIFT0),
             Averaging::Samples2 => (true, OversamplingRatio::OVERSAMPLE2X, Ovss::SHIFT1),
@@ -373,168 +389,4 @@ impl<'d, T: Instance> Adc4<'d, T> {
             w.set_ovse(enable)
         })
     }
-
-    /// Read an ADC channel.
-    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>, sample_time: SampleTime) -> u16 {
-        T::regs().smpr().modify(|w| {
-            w.set_smp(0, sample_time);
-        });
-
-        channel.setup();
-
-        // Select channel
-        #[cfg(stm32wba)]
-        {
-            T::regs().chselr().write_value(Chselr(0_u32));
-            T::regs().chselr().modify(|w| {
-                w.set_chsel0(channel.channel() as usize, true);
-            });
-        }
-        #[cfg(stm32u5)]
-        {
-            T::regs().chselrmod0().write_value(Chselr(0_u32));
-            T::regs().chselrmod0().modify(|w| {
-                w.set_chsel(channel.channel() as usize, true);
-            });
-        }
-
-        // Reset interrupts
-        T::regs().isr().modify(|reg| {
-            reg.set_eos(true);
-            reg.set_eoc(true);
-        });
-
-        // Start conversion
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
-        });
-
-        while !T::regs().isr().read().eos() {
-            // spin
-        }
-
-        T::regs().dr().read().0 as u16
-    }
-
-    /// Read one or multiple ADC channels using DMA.
-    ///
-    /// `sequence` iterator and `readings` must have the same length.
-    /// The channels in `sequence` must be in ascending order.
-    ///
-    /// Example
-    /// ```rust,ignore
-    /// use embassy_stm32::adc::adc4;
-    /// use embassy_stm32::adc::AdcChannel;
-    ///
-    /// let mut adc4 = adc4::Adc4::new(p.ADC4);
-    /// let mut adc4_pin1 = p.PC1;
-    /// let mut adc4_pin2 = p.PC0;
-    /// let mut.into()d41 = adc4_pin1.into();
-    /// let mut.into()d42 = adc4_pin2.into();
-    /// let mut measurements = [0u16; 2];
-    /// // not that the channels must be in ascending order
-    /// adc4.read(
-    ///     &mut p.GPDMA1_CH1,
-    ///    [
-    ///        &mut.into()d42,
-    ///        &mut.into()d41,
-    ///    ]
-    ///    .into_iter(),
-    ///    &mut measurements,
-    /// ).await.unwrap();
-    /// ```
-    pub async fn read(
-        &mut self,
-        rx_dma: Peri<'_, impl RxDma4<T>>,
-        sequence: impl ExactSizeIterator<Item = &mut AnyAdcChannel<T>>,
-        readings: &mut [u16],
-    ) -> Result<(), Adc4Error> {
-        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
-        assert!(
-            sequence.len() == readings.len(),
-            "Sequence length must be equal to readings length"
-        );
-
-        // Ensure no conversions are ongoing
-        Self::cancel_conversions();
-
-        T::regs().isr().modify(|reg| {
-            reg.set_ovr(true);
-            reg.set_eos(true);
-            reg.set_eoc(true);
-        });
-
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_dmaen(true);
-            reg.set_dmacfg(Dmacfg::ONE_SHOT);
-            #[cfg(stm32u5)]
-            reg.set_chselrmod(false);
-            #[cfg(stm32wba)]
-            reg.set_chselrmod(Chselrmod::ENABLE_INPUT)
-        });
-
-        // Verify and activate sequence
-        let mut prev_channel: i16 = -1;
-        #[cfg(stm32wba)]
-        T::regs().chselr().write_value(Chselr(0_u32));
-        #[cfg(stm32u5)]
-        T::regs().chselrmod0().write_value(Chselr(0_u32));
-        for channel in sequence {
-            let channel_num = channel.channel;
-            if channel_num as i16 <= prev_channel {
-                return Err(Adc4Error::InvalidSequence);
-            };
-            prev_channel = channel_num as i16;
-
-            #[cfg(stm32wba)]
-            T::regs().chselr().modify(|w| {
-                w.set_chsel0(channel.channel as usize, true);
-            });
-            #[cfg(stm32u5)]
-            T::regs().chselrmod0().modify(|w| {
-                w.set_chsel(channel.channel as usize, true);
-            });
-        }
-
-        let request = rx_dma.request();
-        let transfer = unsafe {
-            Transfer::new_read(
-                rx_dma,
-                request,
-                T::regs().dr().as_ptr() as *mut u16,
-                readings,
-                Default::default(),
-            )
-        };
-
-        // Start conversion
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
-        });
-
-        transfer.await;
-
-        // Ensure conversions are finished.
-        Self::cancel_conversions();
-
-        // Reset configuration.
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_dmaen(false);
-        });
-
-        if T::regs().isr().read().ovr() {
-            Err(Adc4Error::DMAError)
-        } else {
-            Ok(())
-        }
-    }
-
-    fn cancel_conversions() {
-        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
-            T::regs().cr().modify(|reg| {
-                reg.set_adstp(true);
-            });
-            while T::regs().cr().read().adstart() {}
-        }
-    }
 }
diff --git a/embassy-stm32/src/adc/c0.rs b/embassy-stm32/src/adc/c0.rs
index bc97a7c4b..3e109e429 100644
--- a/embassy-stm32/src/adc/c0.rs
+++ b/embassy-stm32/src/adc/c0.rs
@@ -1,12 +1,10 @@
-use pac::adc::vals::Scandir;
 #[allow(unused)]
 use pac::adc::vals::{Adstp, Align, Ckmode, Dmacfg, Exten, Ovrmod, Ovsr};
 use pac::adccommon::vals::Presc;
+use stm32_metapac::adc::vals::{SampleTime, Scandir};
 
-use super::{
-    Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel, blocking_delay_us,
-};
-use crate::dma::Transfer;
+use super::{Adc, Instance, Resolution, blocking_delay_us};
+use crate::adc::{AnyInstance, ConversionMode};
 use crate::time::Hertz;
 use crate::{Peri, pac, rcc};
 
@@ -19,7 +17,6 @@ const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(25);
 
 const TIME_ADC_VOLTAGE_REGUALTOR_STARTUP_US: u32 = 20;
 
-const NUM_HW_CHANNELS: u8 = 22;
 const CHSELR_SQ_SIZE: usize = 8;
 const CHSELR_SQ_MAX_CHANNEL: u8 = 14;
 const CHSELR_SQ_SEQUENCE_END_MARKER: u8 = 0b1111;
@@ -32,123 +29,169 @@ impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
     const CHANNEL: u8 = 9;
 }
 
-#[derive(Copy, Clone, Debug)]
-pub enum Prescaler {
-    NotDivided,
-    DividedBy2,
-    DividedBy4,
-    DividedBy6,
-    DividedBy8,
-    DividedBy10,
-    DividedBy12,
-    DividedBy16,
-    DividedBy32,
-    DividedBy64,
-    DividedBy128,
-    DividedBy256,
+fn from_ker_ck(frequency: Hertz) -> Presc {
+    let raw_prescaler = rcc::raw_prescaler(frequency.0, MAX_ADC_CLK_FREQ.0);
+    match raw_prescaler {
+        0 => Presc::DIV1,
+        1 => Presc::DIV2,
+        2..=3 => Presc::DIV4,
+        4..=5 => Presc::DIV6,
+        6..=7 => Presc::DIV8,
+        8..=9 => Presc::DIV10,
+        10..=11 => Presc::DIV12,
+        _ => unimplemented!(),
+    }
 }
 
-impl Prescaler {
-    fn from_ker_ck(frequency: Hertz) -> Self {
-        let raw_prescaler = frequency.0 / MAX_ADC_CLK_FREQ.0;
-        match raw_prescaler {
-            0 => Self::NotDivided,
-            1 => Self::DividedBy2,
-            2..=3 => Self::DividedBy4,
-            4..=5 => Self::DividedBy6,
-            6..=7 => Self::DividedBy8,
-            8..=9 => Self::DividedBy10,
-            10..=11 => Self::DividedBy12,
-            _ => unimplemented!(),
-        }
+impl<T: Instance> super::SealedAnyInstance for T {
+    fn dr() -> *mut u16 {
+        T::regs().dr().as_ptr() as *mut u16
+    }
+
+    fn enable() {
+        T::regs().isr().modify(|w| w.set_adrdy(true));
+        T::regs().cr().modify(|w| w.set_aden(true));
+        // ADRDY is "ADC ready". Wait until it will be True.
+        while !T::regs().isr().read().adrdy() {}
     }
 
-    #[allow(unused)]
-    fn divisor(&self) -> u32 {
-        match self {
-            Prescaler::NotDivided => 1,
-            Prescaler::DividedBy2 => 2,
-            Prescaler::DividedBy4 => 4,
-            Prescaler::DividedBy6 => 6,
-            Prescaler::DividedBy8 => 8,
-            Prescaler::DividedBy10 => 10,
-            Prescaler::DividedBy12 => 12,
-            Prescaler::DividedBy16 => 16,
-            Prescaler::DividedBy32 => 32,
-            Prescaler::DividedBy64 => 64,
-            Prescaler::DividedBy128 => 128,
-            Prescaler::DividedBy256 => 256,
+    fn start() {
+        // Start conversion
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
+    }
+
+    fn stop() {
+        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
+            T::regs().cr().modify(|reg| {
+                reg.set_adstp(Adstp::STOP);
+            });
+            while T::regs().cr().read().adstart() {}
         }
+
+        // Reset configuration.
+        T::regs().cfgr1().modify(|reg| {
+            reg.set_cont(false);
+            reg.set_dmacfg(Dmacfg::from_bits(0));
+            reg.set_dmaen(false);
+        });
     }
 
-    fn presc(&self) -> Presc {
-        match self {
-            Prescaler::NotDivided => Presc::DIV1,
-            Prescaler::DividedBy2 => Presc::DIV2,
-            Prescaler::DividedBy4 => Presc::DIV4,
-            Prescaler::DividedBy6 => Presc::DIV6,
-            Prescaler::DividedBy8 => Presc::DIV8,
-            Prescaler::DividedBy10 => Presc::DIV10,
-            Prescaler::DividedBy12 => Presc::DIV12,
-            Prescaler::DividedBy16 => Presc::DIV16,
-            Prescaler::DividedBy32 => Presc::DIV32,
-            Prescaler::DividedBy64 => Presc::DIV64,
-            Prescaler::DividedBy128 => Presc::DIV128,
-            Prescaler::DividedBy256 => Presc::DIV256,
+    fn configure_dma(conversion_mode: super::ConversionMode) {
+        match conversion_mode {
+            ConversionMode::Singular => {
+                // Enable overrun control, so no new DMA requests will be generated until
+                // previous DR values is read.
+                T::regs().isr().modify(|reg| {
+                    reg.set_ovr(true);
+                });
+
+                // Set continuous mode with oneshot dma.
+                T::regs().cfgr1().modify(|reg| {
+                    reg.set_discen(false);
+                    reg.set_cont(true);
+                    reg.set_dmacfg(Dmacfg::DMA_ONE_SHOT);
+                    reg.set_dmaen(true);
+                    reg.set_ovrmod(Ovrmod::PRESERVE);
+                });
+            }
         }
     }
-}
 
-#[cfg(feature = "defmt")]
-impl<'a> defmt::Format for Prescaler {
-    fn format(&self, fmt: defmt::Formatter) {
-        match self {
-            Prescaler::NotDivided => defmt::write!(fmt, "Prescaler::NotDivided"),
-            Prescaler::DividedBy2 => defmt::write!(fmt, "Prescaler::DividedBy2"),
-            Prescaler::DividedBy4 => defmt::write!(fmt, "Prescaler::DividedBy4"),
-            Prescaler::DividedBy6 => defmt::write!(fmt, "Prescaler::DividedBy6"),
-            Prescaler::DividedBy8 => defmt::write!(fmt, "Prescaler::DividedBy8"),
-            Prescaler::DividedBy10 => defmt::write!(fmt, "Prescaler::DividedBy10"),
-            Prescaler::DividedBy12 => defmt::write!(fmt, "Prescaler::DividedBy12"),
-            Prescaler::DividedBy16 => defmt::write!(fmt, "Prescaler::DividedBy16"),
-            Prescaler::DividedBy32 => defmt::write!(fmt, "Prescaler::DividedBy32"),
-            Prescaler::DividedBy64 => defmt::write!(fmt, "Prescaler::DividedBy64"),
-            Prescaler::DividedBy128 => defmt::write!(fmt, "Prescaler::DividedBy128"),
-            Prescaler::DividedBy256 => defmt::write!(fmt, "Prescaler::DividedBy256"),
+    fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), Self::SampleTime)>) {
+        let mut needs_hw = sequence.len() == 1 || sequence.len() > CHSELR_SQ_SIZE;
+        let mut is_ordered_up = true;
+        let mut is_ordered_down = true;
+
+        let sequence_len = sequence.len();
+        let mut hw_channel_selection: u32 = 0;
+        let mut last_channel: u8 = 0;
+        let mut sample_time: Self::SampleTime = SampleTime::CYCLES2_5;
+
+        T::regs().chselr_sq().write(|w| {
+            for (i, ((channel, _), _sample_time)) in sequence.enumerate() {
+                assert!(
+                    sample_time == _sample_time || i == 0,
+                    "C0 only supports one sample time for the sequence."
+                );
+
+                sample_time = _sample_time;
+                needs_hw = needs_hw || channel > CHSELR_SQ_MAX_CHANNEL;
+                is_ordered_up = is_ordered_up && (channel > last_channel || i == 0);
+                is_ordered_down = is_ordered_down && (channel < last_channel || i == 0);
+                hw_channel_selection += 1 << channel;
+                last_channel = channel;
+
+                if !needs_hw {
+                    w.set_sq(i, channel);
+                }
+            }
+
+            for i in sequence_len..CHSELR_SQ_SIZE {
+                w.set_sq(i, CHSELR_SQ_SEQUENCE_END_MARKER);
+            }
+        });
+
+        if needs_hw {
+            assert!(
+                sequence_len <= CHSELR_SQ_SIZE || is_ordered_up || is_ordered_down,
+                "Sequencer is required because of unordered channels, but read set cannot be more than {} in size.",
+                CHSELR_SQ_SIZE
+            );
+            assert!(
+                sequence_len > CHSELR_SQ_SIZE || is_ordered_up || is_ordered_down,
+                "Sequencer is required because of unordered channels, but only support HW channels smaller than {}.",
+                CHSELR_SQ_MAX_CHANNEL
+            );
+
+            // Set required channels for multi-convert.
+            unsafe { (T::regs().chselr().as_ptr() as *mut u32).write_volatile(hw_channel_selection) }
         }
+
+        T::regs().smpr().modify(|w| {
+            w.smpsel(0);
+            w.set_smp1(sample_time);
+        });
+
+        T::regs().cfgr1().modify(|reg| {
+            reg.set_chselrmod(!needs_hw);
+            reg.set_align(Align::RIGHT);
+            reg.set_scandir(if is_ordered_up { Scandir::UP } else { Scandir::BACK });
+        });
+
+        // Trigger and wait for the channel selection procedure to complete.
+        T::regs().isr().modify(|w| w.set_ccrdy(false));
+        while !T::regs().isr().read().ccrdy() {}
     }
-}
 
-/// Number of samples used for averaging.
-/// TODO: Implement hardware averaging setting.
-#[allow(unused)]
-#[derive(Copy, Clone, Debug)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Averaging {
-    Disabled,
-    Samples2,
-    Samples4,
-    Samples8,
-    Samples16,
-    Samples32,
-    Samples64,
-    Samples128,
-    Samples256,
-    Samples512,
-    Samples1024,
+    fn convert() -> u16 {
+        // Set single conversion mode.
+        T::regs().cfgr1().modify(|w| w.set_cont(false));
+
+        // Start conversion
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
+
+        // Waiting for End Of Conversion (EOC).
+        while !T::regs().isr().read().eoc() {}
+
+        T::regs().dr().read().data() as u16
+    }
 }
 
-impl<'d, T: Instance> Adc<'d, T> {
+impl<'d, T: AnyInstance> Adc<'d, T> {
     /// Create a new ADC driver.
     pub fn new(adc: Peri<'d, T>, resolution: Resolution) -> Self {
         rcc::enable_and_reset::<T>();
 
         T::regs().cfgr2().modify(|w| w.set_ckmode(Ckmode::SYSCLK));
 
-        let prescaler = Prescaler::from_ker_ck(T::frequency());
-        T::common_regs().ccr().modify(|w| w.set_presc(prescaler.presc()));
+        let prescaler = from_ker_ck(T::frequency());
+        T::common_regs().ccr().modify(|w| w.set_presc(prescaler));
 
-        let frequency = Hertz(T::frequency().0 / prescaler.divisor());
+        let frequency = T::frequency() / prescaler;
         debug!("ADC frequency set to {}", frequency);
 
         if frequency > MAX_ADC_CLK_FREQ {
@@ -158,32 +201,16 @@ impl<'d, T: Instance> Adc<'d, T> {
             );
         }
 
-        let mut s = Self { adc };
-
-        s.power_up();
-
-        s.set_resolution(resolution);
-
-        s.calibrate();
-
-        s.enable();
-
-        s.configure_default();
-
-        s
-    }
-
-    fn power_up(&mut self) {
         T::regs().cr().modify(|reg| {
             reg.set_advregen(true);
         });
 
         // "The software must wait for the ADC voltage regulator startup time."
         // See datasheet for the value.
-        blocking_delay_us(TIME_ADC_VOLTAGE_REGUALTOR_STARTUP_US + 1);
-    }
+        blocking_delay_us(TIME_ADC_VOLTAGE_REGUALTOR_STARTUP_US as u64 + 1);
+
+        T::regs().cfgr1().modify(|reg| reg.set_res(resolution));
 
-    fn calibrate(&mut self) {
         // We have to make sure AUTOFF is OFF, but keep its value after calibration.
         let autoff_value = T::regs().cfgr1().read().autoff();
         T::regs().cfgr1().modify(|w| w.set_autoff(false));
@@ -197,22 +224,17 @@ impl<'d, T: Instance> Adc<'d, T> {
         debug!("ADC calibration value: {}.", T::regs().dr().read().data());
 
         T::regs().cfgr1().modify(|w| w.set_autoff(autoff_value));
-    }
 
-    fn enable(&mut self) {
-        T::regs().isr().modify(|w| w.set_adrdy(true));
-        T::regs().cr().modify(|w| w.set_aden(true));
-        // ADRDY is "ADC ready". Wait until it will be True.
-        while !T::regs().isr().read().adrdy() {}
-    }
+        T::enable();
 
-    fn configure_default(&mut self) {
         // single conversion mode, software trigger
         T::regs().cfgr1().modify(|w| {
             w.set_cont(false);
             w.set_exten(Exten::DISABLED);
             w.set_align(Align::RIGHT);
         });
+
+        Self { adc }
     }
 
     /// Enable reading the voltage reference internal channel.
@@ -233,219 +255,4 @@ impl<'d, T: Instance> Adc<'d, T> {
 
         super::Temperature {}
     }
-
-    /// Set the ADC sample time.
-    /// Shall only be called when ADC is not converting.
-    pub fn set_sample_time_all_channels(&mut self, sample_time: SampleTime) {
-        // Set all channels to use SMP1 field as source.
-        T::regs().smpr().modify(|w| {
-            w.smpsel(0);
-            w.set_smp1(sample_time);
-        });
-    }
-
-    /// Set the ADC resolution.
-    pub fn set_resolution(&mut self, resolution: Resolution) {
-        T::regs().cfgr1().modify(|reg| reg.set_res(resolution));
-    }
-
-    /// Perform a single conversion.
-    fn convert(&mut self) -> u16 {
-        // Set single conversion mode.
-        T::regs().cfgr1().modify(|w| w.set_cont(false));
-
-        // Start conversion
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
-        });
-
-        // Waiting for End Of Conversion (EOC).
-        while !T::regs().isr().read().eoc() {}
-
-        T::regs().dr().read().data() as u16
-    }
-
-    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>, sample_time: SampleTime) -> u16 {
-        self.set_sample_time_all_channels(sample_time);
-
-        Self::configure_channel(channel);
-        T::regs().cfgr1().write(|reg| {
-            reg.set_chselrmod(false);
-            reg.set_align(Align::RIGHT);
-        });
-        self.convert()
-    }
-
-    fn setup_channel_sequencer<'a>(channel_sequence: impl ExactSizeIterator<Item = &'a mut AnyAdcChannel<T>>) {
-        assert!(
-            channel_sequence.len() <= CHSELR_SQ_SIZE,
-            "Seqenced read set cannot be more than {} in size.",
-            CHSELR_SQ_SIZE
-        );
-        let mut last_sq_set: usize = 0;
-        T::regs().chselr_sq().write(|w| {
-            for (i, channel) in channel_sequence.enumerate() {
-                assert!(
-                    channel.channel() <= CHSELR_SQ_MAX_CHANNEL,
-                    "Sequencer only support HW channels smaller than {}.",
-                    CHSELR_SQ_MAX_CHANNEL
-                );
-                w.set_sq(i, channel.channel());
-                last_sq_set = i;
-            }
-
-            for i in (last_sq_set + 1)..CHSELR_SQ_SIZE {
-                w.set_sq(i, CHSELR_SQ_SEQUENCE_END_MARKER);
-            }
-        });
-
-        Self::apply_channel_conf()
-    }
-
-    async fn dma_convert(&mut self, rx_dma: Peri<'_, impl RxDma<T>>, readings: &mut [u16]) {
-        // Enable overrun control, so no new DMA requests will be generated until
-        // previous DR values is read.
-        T::regs().isr().modify(|reg| {
-            reg.set_ovr(true);
-        });
-
-        // Set continuous mode with oneshot dma.
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_discen(false);
-            reg.set_cont(true);
-            reg.set_dmacfg(Dmacfg::DMA_ONE_SHOT);
-            reg.set_dmaen(true);
-            reg.set_ovrmod(Ovrmod::PRESERVE);
-        });
-
-        let request = rx_dma.request();
-        let transfer = unsafe {
-            Transfer::new_read(
-                rx_dma,
-                request,
-                T::regs().dr().as_ptr() as *mut u16,
-                readings,
-                Default::default(),
-            )
-        };
-
-        // Start conversion.
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
-        });
-
-        // Wait for conversion sequence to finish.
-        transfer.await;
-
-        // Ensure conversions are finished.
-        Self::cancel_conversions();
-
-        // Reset configuration.
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_cont(false);
-            reg.set_dmacfg(Dmacfg::from_bits(0));
-            reg.set_dmaen(false);
-        });
-    }
-
-    /// Read one or multiple ADC channels using DMA in hardware order.
-    /// Readings will be ordered based on **hardware** ADC channel number and `scandir` setting.
-    /// Readings won't be in the same order as in the `set`!
-    ///
-    /// In STM32C0, channels bigger than 14 cannot be read using sequencer, so you have to use
-    /// either blocking reads or use the mechanism to read in HW order (CHSELRMOD=0).
-    /// TODO(chudsaviet): externalize generic code and merge with read().
-    pub async fn read_in_hw_order(
-        &mut self,
-        rx_dma: Peri<'_, impl RxDma<T>>,
-        hw_channel_selection: u32,
-        scandir: Scandir,
-        readings: &mut [u16],
-    ) {
-        assert!(
-            hw_channel_selection != 0,
-            "Some bits in `hw_channel_selection` shall be set."
-        );
-        assert!(
-            (hw_channel_selection >> NUM_HW_CHANNELS) == 0,
-            "STM32C0 only have {} ADC channels. `hw_channel_selection` cannot have bits higher than this number set.",
-            NUM_HW_CHANNELS
-        );
-        // To check for correct readings slice size, we shall solve Hamming weight problem,
-        // which is either slow or memory consuming.
-        // Since we have limited resources, we don't do it here.
-        // Not doing this have a great potential for a bug through.
-
-        // Ensure no conversions are ongoing.
-        Self::cancel_conversions();
-
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_chselrmod(false);
-            reg.set_scandir(scandir);
-            reg.set_align(Align::RIGHT);
-        });
-
-        // Set required channels for multi-convert.
-        unsafe { (T::regs().chselr().as_ptr() as *mut u32).write_volatile(hw_channel_selection) }
-
-        Self::apply_channel_conf();
-
-        self.dma_convert(rx_dma, readings).await
-    }
-
-    // Read ADC channels in specified order using DMA (CHSELRMOD = 1).
-    // In STM32C0, only lower 14 ADC channels can be read this way.
-    // For other channels, use `read_in_hw_order()` or blocking read.
-    pub async fn read(
-        &mut self,
-        rx_dma: Peri<'_, impl RxDma<T>>,
-        channel_sequence: impl ExactSizeIterator<Item = &mut AnyAdcChannel<T>>,
-        readings: &mut [u16],
-    ) {
-        assert!(
-            channel_sequence.len() != 0,
-            "Asynchronous read channel sequence cannot be empty."
-        );
-        assert!(
-            channel_sequence.len() == readings.len(),
-            "Channel sequence length must be equal to readings length."
-        );
-
-        // Ensure no conversions are ongoing.
-        Self::cancel_conversions();
-
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_chselrmod(true);
-            reg.set_align(Align::RIGHT);
-        });
-
-        Self::setup_channel_sequencer(channel_sequence);
-
-        self.dma_convert(rx_dma, readings).await
-    }
-
-    fn configure_channel(channel: &mut impl AdcChannel<T>) {
-        channel.setup();
-        // write() because we want all other bits to be set to 0.
-        T::regs()
-            .chselr()
-            .write(|w| w.set_chsel(channel.channel().into(), true));
-
-        Self::apply_channel_conf();
-    }
-
-    fn apply_channel_conf() {
-        // Trigger and wait for the channel selection procedure to complete.
-        T::regs().isr().modify(|w| w.set_ccrdy(false));
-        while !T::regs().isr().read().ccrdy() {}
-    }
-
-    fn cancel_conversions() {
-        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
-            T::regs().cr().modify(|reg| {
-                reg.set_adstp(Adstp::STOP);
-            });
-            while T::regs().cr().read().adstart() {}
-        }
-    }
 }
diff --git a/embassy-stm32/src/adc/f1.rs b/embassy-stm32/src/adc/f1.rs
index f6220de78..d6c6f480b 100644
--- a/embassy-stm32/src/adc/f1.rs
+++ b/embassy-stm32/src/adc/f1.rs
@@ -43,7 +43,7 @@ impl<'d, T: Instance> Adc<'d, T> {
 
         // 11.4: Before starting a calibration, the ADC must have been in power-on state (ADON bit = ‘1’)
         // for at least two ADC clock cycles.
-        blocking_delay_us((1_000_000 * 2) / Self::freq().0 + 1);
+        blocking_delay_us((1_000_000 * 2) / Self::freq().0 as u64 + 1);
 
         // Reset calibration
         T::regs().cr2().modify(|reg| reg.set_rstcal(true));
@@ -58,7 +58,7 @@ impl<'d, T: Instance> Adc<'d, T> {
         }
 
         // One cycle after calibration
-        blocking_delay_us((1_000_000 * 1) / Self::freq().0 + 1);
+        blocking_delay_us((1_000_000 * 1) / Self::freq().0 as u64 + 1);
 
         T::Interrupt::unpend();
         unsafe { T::Interrupt::enable() };
diff --git a/embassy-stm32/src/adc/f3.rs b/embassy-stm32/src/adc/f3.rs
index 4a77f3c5b..29bfdac97 100644
--- a/embassy-stm32/src/adc/f3.rs
+++ b/embassy-stm32/src/adc/f3.rs
@@ -62,7 +62,7 @@ impl<'d, T: Instance> Adc<'d, T> {
         while T::regs().cr().read().adcal() {}
 
         // Wait more than 4 clock cycles after adcal is cleared (RM0364 p. 223).
-        blocking_delay_us((1_000_000 * 4) / Self::freq().0 + 1);
+        blocking_delay_us((1_000_000 * 4) / Self::freq().0 as u64 + 1);
 
         // Enable the adc
         T::regs().cr().modify(|w| w.set_aden(true));
diff --git a/embassy-stm32/src/adc/g4.rs b/embassy-stm32/src/adc/g4.rs
index 6430b0243..1767a3bb3 100644
--- a/embassy-stm32/src/adc/g4.rs
+++ b/embassy-stm32/src/adc/g4.rs
@@ -1,24 +1,21 @@
-use core::mem;
-
+#[cfg(stm32g4)]
+use pac::adc::regs::Difsel as DifselReg;
+#[allow(unused)]
+#[cfg(stm32g4)]
+pub use pac::adc::vals::{Adcaldif, Adstp, Difsel, Dmacfg, Dmaen, Exten, Rovsm, Trovs};
 #[allow(unused)]
 #[cfg(stm32h7)]
 use pac::adc::vals::{Adcaldif, Difsel, Exten};
-#[allow(unused)]
-#[cfg(stm32g4)]
-pub use pac::adc::vals::{Adcaldif, Difsel, Exten, Rovsm, Trovs};
-pub use pac::adccommon::vals::Presc;
-pub use stm32_metapac::adc::vals::{Adstp, Dmacfg, Dmaen};
-pub use stm32_metapac::adccommon::vals::Dual;
-
-use super::{Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, blocking_delay_us};
-use crate::adc::SealedAdcChannel;
-use crate::dma::Transfer;
+pub use pac::adccommon::vals::{Dual, Presc};
+
+use super::{
+    Adc, AnyAdcChannel, ConversionMode, Instance, RegularConversionMode, Resolution, RxDma, SampleTime,
+    blocking_delay_us,
+};
+use crate::adc::{AnyInstance, SealedAdcChannel};
 use crate::time::Hertz;
 use crate::{Peri, pac, rcc};
 
-mod ringbuffered;
-pub use ringbuffered::RingBufferedAdc;
-
 mod injected;
 pub use injected::InjectedAdc;
 
@@ -35,72 +32,31 @@ const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(60);
 #[cfg(stm32h7)]
 const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(50);
 
-// NOTE (unused): The prescaler enum closely copies the hardware capabilities,
-// but high prescaling doesn't make a lot of sense in the current implementation and is ommited.
-#[allow(unused)]
-enum Prescaler {
-    NotDivided,
-    DividedBy2,
-    DividedBy4,
-    DividedBy6,
-    DividedBy8,
-    DividedBy10,
-    DividedBy12,
-    DividedBy16,
-    DividedBy32,
-    DividedBy64,
-    DividedBy128,
-    DividedBy256,
-}
-
-impl Prescaler {
-    fn from_ker_ck(frequency: Hertz) -> Self {
-        let raw_prescaler = frequency.0 / MAX_ADC_CLK_FREQ.0;
-        match raw_prescaler {
-            0 => Self::NotDivided,
-            1 => Self::DividedBy2,
-            2..=3 => Self::DividedBy4,
-            4..=5 => Self::DividedBy6,
-            6..=7 => Self::DividedBy8,
-            8..=9 => Self::DividedBy10,
-            10..=11 => Self::DividedBy12,
-            _ => unimplemented!(),
-        }
-    }
-
-    fn divisor(&self) -> u32 {
-        match self {
-            Prescaler::NotDivided => 1,
-            Prescaler::DividedBy2 => 2,
-            Prescaler::DividedBy4 => 4,
-            Prescaler::DividedBy6 => 6,
-            Prescaler::DividedBy8 => 8,
-            Prescaler::DividedBy10 => 10,
-            Prescaler::DividedBy12 => 12,
-            Prescaler::DividedBy16 => 16,
-            Prescaler::DividedBy32 => 32,
-            Prescaler::DividedBy64 => 64,
-            Prescaler::DividedBy128 => 128,
-            Prescaler::DividedBy256 => 256,
-        }
+fn from_ker_ck(frequency: Hertz) -> Presc {
+    let raw_prescaler = rcc::raw_prescaler(frequency.0, MAX_ADC_CLK_FREQ.0);
+    match raw_prescaler {
+        0 => Presc::DIV1,
+        1 => Presc::DIV2,
+        2..=3 => Presc::DIV4,
+        4..=5 => Presc::DIV6,
+        6..=7 => Presc::DIV8,
+        8..=9 => Presc::DIV10,
+        10..=11 => Presc::DIV12,
+        _ => unimplemented!(),
     }
+}
 
-    fn presc(&self) -> Presc {
-        match self {
-            Prescaler::NotDivided => Presc::DIV1,
-            Prescaler::DividedBy2 => Presc::DIV2,
-            Prescaler::DividedBy4 => Presc::DIV4,
-            Prescaler::DividedBy6 => Presc::DIV6,
-            Prescaler::DividedBy8 => Presc::DIV8,
-            Prescaler::DividedBy10 => Presc::DIV10,
-            Prescaler::DividedBy12 => Presc::DIV12,
-            Prescaler::DividedBy16 => Presc::DIV16,
-            Prescaler::DividedBy32 => Presc::DIV32,
-            Prescaler::DividedBy64 => Presc::DIV64,
-            Prescaler::DividedBy128 => Presc::DIV128,
-            Prescaler::DividedBy256 => Presc::DIV256,
-        }
-    }
+/// ADC configuration
+#[derive(Default)]
+pub struct AdcConfig {
+    pub dual_mode: Option<Dual>,
+    pub resolution: Option<Resolution>,
+    #[cfg(stm32g4)]
+    pub oversampling_shift: Option<u8>,
+    #[cfg(stm32g4)]
+    pub oversampling_ratio: Option<u8>,
+    #[cfg(stm32g4)]
+    pub oversampling_mode: Option<(Rovsm, Trovs, bool)>,
 }
 
 // Trigger source for ADC conversions¨
@@ -112,25 +68,189 @@ pub struct ConversionTrigger {
     pub edge: Exten,
 }
 
-// Conversion mode for regular ADC channels
-#[derive(Copy, Clone)]
-pub enum RegularConversionMode {
-    // Samples as fast as possible
-    Continuous,
-    // Sample at rate determined by external trigger
-    Triggered(ConversionTrigger),
+impl<T: Instance> super::SealedAnyInstance for T {
+    fn dr() -> *mut u16 {
+        T::regs().dr().as_ptr() as *mut u16
+    }
+
+    fn enable() {
+        // Make sure bits are off
+        while T::regs().cr().read().addis() {
+            // spin
+        }
+
+        if !T::regs().cr().read().aden() {
+            // Enable ADC
+            T::regs().isr().modify(|reg| {
+                reg.set_adrdy(true);
+            });
+            T::regs().cr().modify(|reg| {
+                reg.set_aden(true);
+            });
+
+            while !T::regs().isr().read().adrdy() {
+                // spin
+            }
+        }
+    }
+
+    fn start() {
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
+    }
+
+    fn stop() {
+        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
+            T::regs().cr().modify(|reg| {
+                reg.set_adstp(Adstp::STOP);
+            });
+            // The software must poll ADSTART until the bit is reset before assuming the
+            // ADC is completely stopped
+            while T::regs().cr().read().adstart() {}
+        }
+
+        // Disable dma control and continuous conversion, if enabled
+        T::regs().cfgr().modify(|reg| {
+            reg.set_cont(false);
+            reg.set_dmaen(Dmaen::DISABLE);
+        });
+    }
+
+    fn convert() -> u16 {
+        T::regs().isr().modify(|reg| {
+            reg.set_eos(true);
+            reg.set_eoc(true);
+        });
+
+        // Start conversion
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
+
+        while !T::regs().isr().read().eos() {
+            // spin
+        }
+
+        T::regs().dr().read().0 as u16
+    }
+
+    fn configure_dma(conversion_mode: ConversionMode) {
+        T::regs().isr().modify(|reg| {
+            reg.set_ovr(true);
+        });
+
+        T::regs().cfgr().modify(|reg| {
+            reg.set_discen(false); // Convert all channels for each trigger
+            reg.set_dmacfg(match conversion_mode {
+                ConversionMode::Singular => Dmacfg::ONE_SHOT,
+                ConversionMode::Repeated(_) => Dmacfg::CIRCULAR,
+            });
+            reg.set_dmaen(Dmaen::ENABLE);
+        });
+
+        if let ConversionMode::Repeated(mode) = conversion_mode {
+            match mode {
+                RegularConversionMode::Continuous => {
+                    T::regs().cfgr().modify(|reg| {
+                        reg.set_cont(true);
+                    });
+                }
+                RegularConversionMode::Triggered(trigger) => {
+                    T::regs().cfgr().modify(|r| {
+                        r.set_cont(false); // New trigger is neede for each sample to be read
+                    });
+
+                    T::regs().cfgr().modify(|r| {
+                        r.set_extsel(trigger.channel);
+                        r.set_exten(trigger.edge);
+                    });
+
+                    // Regular conversions uses DMA so no need to generate interrupt
+                    T::regs().ier().modify(|r| r.set_eosie(false));
+                }
+            }
+        }
+    }
+
+    fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
+        T::regs().cr().modify(|w| w.set_aden(false));
+
+        // Set sequence length
+        T::regs().sqr1().modify(|w| {
+            w.set_l(sequence.len() as u8 - 1);
+        });
+
+        #[cfg(stm32g4)]
+        let mut difsel = DifselReg::default();
+        let mut smpr = T::regs().smpr().read();
+        let mut smpr2 = T::regs().smpr2().read();
+        let mut sqr1 = T::regs().sqr1().read();
+        let mut sqr2 = T::regs().sqr2().read();
+        let mut sqr3 = T::regs().sqr3().read();
+        let mut sqr4 = T::regs().sqr4().read();
+
+        // Configure channels and ranks
+        for (_i, ((ch, is_differential), sample_time)) in sequence.enumerate() {
+            let sample_time = sample_time.into();
+            if ch <= 9 {
+                smpr.set_smp(ch as _, sample_time);
+            } else {
+                smpr2.set_smp((ch - 10) as _, sample_time);
+            }
+
+            match _i {
+                0..=3 => {
+                    sqr1.set_sq(_i, ch);
+                }
+                4..=8 => {
+                    sqr2.set_sq(_i - 4, ch);
+                }
+                9..=13 => {
+                    sqr3.set_sq(_i - 9, ch);
+                }
+                14..=15 => {
+                    sqr4.set_sq(_i - 14, ch);
+                }
+                _ => unreachable!(),
+            }
+
+            #[cfg(stm32g4)]
+            {
+                if ch < 18 {
+                    difsel.set_difsel(
+                        ch.into(),
+                        if is_differential {
+                            Difsel::DIFFERENTIAL
+                        } else {
+                            Difsel::SINGLE_ENDED
+                        },
+                    );
+                }
+            }
+        }
+
+        T::regs().smpr().write_value(smpr);
+        T::regs().smpr2().write_value(smpr2);
+        T::regs().sqr1().write_value(sqr1);
+        T::regs().sqr2().write_value(sqr2);
+        T::regs().sqr3().write_value(sqr3);
+        T::regs().sqr4().write_value(sqr4);
+        #[cfg(stm32g4)]
+        T::regs().difsel().write_value(difsel);
+    }
 }
 
-impl<'d, T: Instance> Adc<'d, T> {
+impl<'d, T: Instance + AnyInstance> Adc<'d, T> {
     /// Create a new ADC driver.
-    pub fn new(adc: Peri<'d, T>) -> Self {
+    pub fn new(adc: Peri<'d, T>, config: AdcConfig) -> Self {
         rcc::enable_and_reset::<T>();
 
-        let prescaler = Prescaler::from_ker_ck(T::frequency());
+        let prescaler = from_ker_ck(T::frequency());
 
-        T::common_regs().ccr().modify(|w| w.set_presc(prescaler.presc()));
+        T::common_regs().ccr().modify(|w| w.set_presc(prescaler));
 
-        let frequency = Hertz(T::frequency().0 / prescaler.divisor());
+        let frequency = T::frequency() / prescaler;
         trace!("ADC frequency set to {}", frequency);
 
         if frequency > MAX_ADC_CLK_FREQ {
@@ -173,7 +293,7 @@ impl<'d, T: Instance> Adc<'d, T> {
 
         blocking_delay_us(20);
 
-        Self::enable();
+        T::enable();
 
         // single conversion mode, software trigger
         T::regs().cfgr().modify(|w| {
@@ -181,28 +301,34 @@ impl<'d, T: Instance> Adc<'d, T> {
             w.set_exten(Exten::DISABLED);
         });
 
-        Self { adc }
-    }
+        if let Some(dual) = config.dual_mode {
+            T::common_regs().ccr().modify(|reg| {
+                reg.set_dual(dual);
+            })
+        }
 
-    fn enable() {
-        // Make sure bits are off
-        while T::regs().cr().read().addis() {
-            // spin
+        if let Some(resolution) = config.resolution {
+            T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
         }
 
-        if !T::regs().cr().read().aden() {
-            // Enable ADC
-            T::regs().isr().modify(|reg| {
-                reg.set_adrdy(true);
-            });
-            T::regs().cr().modify(|reg| {
-                reg.set_aden(true);
-            });
+        #[cfg(stm32g4)]
+        if let Some(shift) = config.oversampling_shift {
+            T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
+        }
 
-            while !T::regs().isr().read().adrdy() {
-                // spin
-            }
+        #[cfg(stm32g4)]
+        if let Some(ratio) = config.oversampling_ratio {
+            T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
         }
+
+        #[cfg(stm32g4)]
+        if let Some((mode, trig_mode, enable)) = config.oversampling_mode {
+            T::regs().cfgr2().modify(|reg| reg.set_trovs(trig_mode));
+            T::regs().cfgr2().modify(|reg| reg.set_rovsm(mode));
+            T::regs().cfgr2().modify(|reg| reg.set_rovse(enable));
+        }
+
+        Self { adc }
     }
 
     /// Enable reading the voltage reference internal channel.
@@ -241,26 +367,6 @@ impl<'d, T: Instance> Adc<'d, T> {
         super::Vbat {}
     }
 
-    /// Set oversampling shift.
-    #[cfg(stm32g4)]
-    pub fn set_oversampling_shift(&mut self, shift: u8) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
-    }
-
-    /// Set oversampling ratio.
-    #[cfg(stm32g4)]
-    pub fn set_oversampling_ratio(&mut self, ratio: u8) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
-    }
-
-    /// Enable oversampling in regular mode.
-    #[cfg(stm32g4)]
-    pub fn enable_regular_oversampling_mode(&mut self, mode: Rovsm, trig_mode: Trovs, enable: bool) {
-        T::regs().cfgr2().modify(|reg| reg.set_trovs(trig_mode));
-        T::regs().cfgr2().modify(|reg| reg.set_rovsm(mode));
-        T::regs().cfgr2().modify(|reg| reg.set_rovse(enable));
-    }
-
     // Reads that are not implemented as INJECTED in "blocking_read"
     // #[cfg(stm32g4)]
     // pub fn enalble_injected_oversampling_mode(&mut self, enable: bool) {
@@ -274,311 +380,6 @@ impl<'d, T: Instance> Adc<'d, T> {
     //     T::regs().cfgr2().modify(|reg| reg.set_jovse(enable));
     // }
 
-    /// Set the ADC resolution.
-    pub fn set_resolution(&mut self, resolution: Resolution) {
-        T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
-    }
-
-    /// Perform a single conversion.
-    fn convert(&mut self) -> u16 {
-        T::regs().isr().modify(|reg| {
-            reg.set_eos(true);
-            reg.set_eoc(true);
-        });
-
-        // Start conversion
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
-        });
-
-        while !T::regs().isr().read().eos() {
-            // spin
-        }
-
-        T::regs().dr().read().0 as u16
-    }
-
-    /// Read an ADC pin.
-    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>, sample_time: SampleTime) -> u16 {
-        channel.setup();
-
-        Self::configure_sequence([((channel.channel(), channel.is_differential()), sample_time)].into_iter());
-
-        #[cfg(stm32h7)]
-        {
-            T::regs().cfgr2().modify(|w| w.set_lshift(0));
-            T::regs()
-                .pcsel()
-                .write(|w| w.set_pcsel(channel.channel() as _, Pcsel::PRESELECTED));
-        }
-
-        self.convert()
-    }
-
-    /// Start regular adc conversion
-    pub(super) fn start() {
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
-        });
-    }
-
-    /// Stop regular conversions
-    pub(super) fn stop() {
-        Self::stop_regular_conversions();
-    }
-
-    /// Teardown method for stopping regular ADC conversions
-    pub(super) fn teardown_dma() {
-        Self::stop_regular_conversions();
-
-        // Disable dma control
-        T::regs().cfgr().modify(|reg| {
-            reg.set_dmaen(Dmaen::DISABLE);
-        });
-    }
-
-    /// Read one or multiple ADC regular channels using DMA.
-    ///
-    /// `sequence` iterator and `readings` must have the same length.
-    ///
-    /// Example
-    /// ```rust,ignore
-    /// use embassy_stm32::adc::{Adc, AdcChannel}
-    ///
-    /// let mut adc = Adc::new(p.ADC1);
-    /// let mut adc_pin0 = p.PA0.into();
-    /// let mut adc_pin1 = p.PA1.into();
-    /// let mut measurements = [0u16; 2];
-    ///
-    /// adc.read(
-    ///     p.DMA1_CH2.reborrow(),
-    ///     [
-    ///         (&mut *adc_pin0, SampleTime::CYCLES160_5),
-    ///         (&mut *adc_pin1, SampleTime::CYCLES160_5),
-    ///     ]
-    ///     .into_iter(),
-    ///     &mut measurements,
-    /// )
-    /// .await;
-    /// defmt::info!("measurements: {}", measurements);
-    /// ```
-    ///
-    /// Note: This is not very efficient as the ADC needs to be reconfigured for each read. Use
-    /// `into_ring_buffered`, `into_ring_buffered_and_injected`
-    pub async fn read(
-        &mut self,
-        rx_dma: Peri<'_, impl RxDma<T>>,
-        sequence: impl ExactSizeIterator<Item = (&mut AnyAdcChannel<T>, SampleTime)>,
-        readings: &mut [u16],
-    ) {
-        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
-        assert!(
-            sequence.len() == readings.len(),
-            "Sequence length must be equal to readings length"
-        );
-        assert!(
-            sequence.len() <= 16,
-            "Asynchronous read sequence cannot be more than 16 in length"
-        );
-
-        // Ensure no conversions are ongoing and ADC is enabled.
-        Self::stop_regular_conversions();
-        Self::enable();
-
-        Self::configure_sequence(
-            sequence.map(|(channel, sample_time)| ((channel.channel, channel.is_differential), sample_time)),
-        );
-
-        // Set continuous mode with oneshot dma.
-        // Clear overrun flag before starting transfer.
-        T::regs().isr().modify(|reg| {
-            reg.set_ovr(true);
-        });
-
-        T::regs().cfgr().modify(|reg| {
-            reg.set_discen(false);
-            reg.set_cont(true);
-            reg.set_dmacfg(Dmacfg::ONE_SHOT);
-            reg.set_dmaen(Dmaen::ENABLE);
-        });
-
-        let request = rx_dma.request();
-        let transfer = unsafe {
-            Transfer::new_read(
-                rx_dma,
-                request,
-                T::regs().dr().as_ptr() as *mut u16,
-                readings,
-                Default::default(),
-            )
-        };
-
-        // Start conversion
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
-        });
-
-        // Wait for conversion sequence to finish.
-        transfer.await;
-
-        // Ensure conversions are finished.
-        Self::stop_regular_conversions();
-
-        // Reset configuration.
-        T::regs().cfgr().modify(|reg| {
-            reg.set_cont(false);
-        });
-    }
-
-    pub(super) fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
-        // Set sequence length
-        T::regs().sqr1().modify(|w| {
-            w.set_l(sequence.len() as u8 - 1);
-        });
-
-        // Configure channels and ranks
-        for (_i, ((ch, is_differential), sample_time)) in sequence.enumerate() {
-            let sample_time = sample_time.into();
-            if ch <= 9 {
-                T::regs().smpr().modify(|reg| reg.set_smp(ch as _, sample_time));
-            } else {
-                T::regs().smpr2().modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
-            }
-
-            match _i {
-                0..=3 => {
-                    T::regs().sqr1().modify(|w| {
-                        w.set_sq(_i, ch);
-                    });
-                }
-                4..=8 => {
-                    T::regs().sqr2().modify(|w| {
-                        w.set_sq(_i - 4, ch);
-                    });
-                }
-                9..=13 => {
-                    T::regs().sqr3().modify(|w| {
-                        w.set_sq(_i - 9, ch);
-                    });
-                }
-                14..=15 => {
-                    T::regs().sqr4().modify(|w| {
-                        w.set_sq(_i - 14, ch);
-                    });
-                }
-                _ => unreachable!(),
-            }
-
-            #[cfg(stm32g4)]
-            {
-                T::regs().cr().modify(|w| w.set_aden(false)); // disable adc
-
-                T::regs().difsel().modify(|w| {
-                    w.set_difsel(
-                        ch.into(),
-                        if is_differential {
-                            Difsel::DIFFERENTIAL
-                        } else {
-                            Difsel::SINGLE_ENDED
-                        },
-                    );
-                });
-
-                T::regs().cr().modify(|w| w.set_aden(true)); // enable adc
-            }
-        }
-    }
-
-    /// Set external trigger for regular conversion sequence
-    fn set_regular_conversion_trigger(&mut self, trigger: ConversionTrigger) {
-        T::regs().cfgr().modify(|r| {
-            r.set_extsel(trigger.channel);
-            r.set_exten(trigger.edge);
-        });
-        // Regular conversions uses DMA so no need to generate interrupt
-        T::regs().ier().modify(|r| r.set_eosie(false));
-    }
-
-    // Dual ADC mode selection
-    pub fn configure_dual_mode(&mut self, val: Dual) {
-        T::common_regs().ccr().modify(|reg| {
-            reg.set_dual(val);
-        })
-    }
-
-    /// Configures the ADC to use a DMA ring buffer for continuous data acquisition.
-    ///
-    /// Use the [`read`] method to retrieve measurements from the DMA ring buffer. The read buffer
-    /// should be exactly half the size of `dma_buf`. When using triggered mode, it is recommended
-    /// to configure `dma_buf` as a double buffer so that one half can be read while the other half
-    /// is being filled by the DMA, preventing data loss. The trigger period of the ADC effectively
-    /// defines the period at which the buffer should be read.
-    ///
-    /// If continous conversion mode is selected, the provided `dma_buf` must be large enough to prevent
-    /// DMA buffer overruns. Its length should be a multiple of the number of ADC channels being measured.
-    /// For example, if 3 channels are measured and you want to store 40 samples per channel,
-    /// the buffer length should be `3 * 40 = 120`.
-    ///
-    /// # Parameters
-    /// - `dma`: The DMA peripheral used to transfer ADC data into the buffer.
-    /// - `dma_buf`: The buffer where DMA stores ADC samples.
-    /// - `regular_sequence`: Sequence of channels and sample times for regular ADC conversions.
-    /// - `regular_conversion_mode`: Mode for regular conversions (continuous or triggered).
-    ///
-    /// # Returns
-    /// A `RingBufferedAdc<'a, T>` instance configured for continuous DMA-based sampling.
-    pub fn into_ring_buffered<'a>(
-        mut self,
-        dma: Peri<'a, impl RxDma<T>>,
-        dma_buf: &'a mut [u16],
-        sequence: impl ExactSizeIterator<Item = (AnyAdcChannel<T>, SampleTime)>,
-        mode: RegularConversionMode,
-    ) -> RingBufferedAdc<'a, T> {
-        assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
-        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
-        assert!(
-            sequence.len() <= 16,
-            "Asynchronous read sequence cannot be more than 16 in length"
-        );
-        // reset conversions and enable the adc
-        Self::stop_regular_conversions();
-        Self::enable();
-
-        //adc side setup
-        Self::configure_sequence(
-            sequence.map(|(channel, sample_time)| ((channel.channel, channel.is_differential), sample_time)),
-        );
-
-        // Clear overrun flag before starting transfer.
-        T::regs().isr().modify(|reg| {
-            reg.set_ovr(true);
-        });
-
-        T::regs().cfgr().modify(|reg| {
-            reg.set_discen(false); // Convert all channels for each trigger
-            reg.set_dmacfg(Dmacfg::CIRCULAR);
-            reg.set_dmaen(Dmaen::ENABLE);
-        });
-
-        match mode {
-            RegularConversionMode::Continuous => {
-                T::regs().cfgr().modify(|reg| {
-                    reg.set_cont(true);
-                });
-            }
-            RegularConversionMode::Triggered(trigger) => {
-                T::regs().cfgr().modify(|r| {
-                    r.set_cont(false); // New trigger is neede for each sample to be read
-                });
-                self.set_regular_conversion_trigger(trigger);
-            }
-        }
-
-        mem::forget(self);
-
-        RingBufferedAdc::new(dma, dma_buf)
-    }
-
     /// Configures the ADC for injected conversions.
     ///
     /// Injected conversions are separate from the regular conversion sequence and are typically
@@ -607,7 +408,7 @@ impl<'d, T: Instance> Adc<'d, T> {
     /// - Accessing samples beyond `N` will result in a panic; use the returned type
     ///   `InjectedAdc<T, N>` to enforce bounds at compile time.
     pub fn setup_injected_conversions<'a, const N: usize>(
-        mut self,
+        self,
         sequence: [(AnyAdcChannel<T>, SampleTime); N],
         trigger: ConversionTrigger,
         interrupt: bool,
@@ -619,8 +420,7 @@ impl<'d, T: Instance> Adc<'d, T> {
             NR_INJECTED_RANKS
         );
 
-        Self::stop_regular_conversions();
-        Self::enable();
+        T::enable();
 
         T::regs().jsqr().modify(|w| w.set_jl(N as u8 - 1));
 
@@ -649,8 +449,16 @@ impl<'d, T: Instance> Adc<'d, T> {
 
         T::regs().cfgr().modify(|reg| reg.set_jdiscen(false));
 
-        self.set_injected_conversion_trigger(trigger);
-        self.enable_injected_eos_interrupt(interrupt);
+        // Set external trigger for injected conversion sequence
+        // Possible trigger values are seen in Table 167 in RM0440 Rev 9
+        T::regs().jsqr().modify(|r| {
+            r.set_jextsel(trigger.channel);
+            r.set_jexten(trigger.edge);
+        });
+
+        // Enable end of injected sequence interrupt
+        T::regs().ier().modify(|r| r.set_jeosie(interrupt));
+
         Self::start_injected_conversions();
 
         InjectedAdc::new(sequence) // InjectedAdc<'a, T, N> now borrows the channels
@@ -683,12 +491,12 @@ impl<'d, T: Instance> Adc<'d, T> {
         self,
         dma: Peri<'a, impl RxDma<T>>,
         dma_buf: &'a mut [u16],
-        regular_sequence: impl ExactSizeIterator<Item = (AnyAdcChannel<T>, SampleTime)>,
+        regular_sequence: impl ExactSizeIterator<Item = (AnyAdcChannel<T>, T::SampleTime)>,
         regular_conversion_mode: RegularConversionMode,
         injected_sequence: [(AnyAdcChannel<T>, SampleTime); N],
         injected_trigger: ConversionTrigger,
         injected_interrupt: bool,
-    ) -> (RingBufferedAdc<'a, T>, InjectedAdc<T, N>) {
+    ) -> (super::RingBufferedAdc<'a, T>, InjectedAdc<T, N>) {
         unsafe {
             (
                 Self {
@@ -721,32 +529,6 @@ impl<'d, T: Instance> Adc<'d, T> {
             reg.set_jadstart(true);
         });
     }
-
-    /// Set external trigger for injected conversion sequence
-    /// Possible trigger values are seen in Table 167 in RM0440 Rev 9
-    fn set_injected_conversion_trigger(&mut self, trigger: ConversionTrigger) {
-        T::regs().jsqr().modify(|r| {
-            r.set_jextsel(trigger.channel);
-            r.set_jexten(trigger.edge);
-        });
-    }
-
-    /// Enable end of injected sequence interrupt
-    fn enable_injected_eos_interrupt(&mut self, enable: bool) {
-        T::regs().ier().modify(|r| r.set_jeosie(enable));
-    }
-
-    // Stop regular conversions
-    fn stop_regular_conversions() {
-        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
-            T::regs().cr().modify(|reg| {
-                reg.set_adstp(Adstp::STOP);
-            });
-            // The software must poll ADSTART until the bit is reset before assuming the
-            // ADC is completely stopped
-            while T::regs().cr().read().adstart() {}
-        }
-    }
 }
 
 impl<T: Instance, const N: usize> InjectedAdc<T, N> {
diff --git a/embassy-stm32/src/adc/injected.rs b/embassy-stm32/src/adc/injected.rs
index f9f1bba2a..ccaa5d1b2 100644
--- a/embassy-stm32/src/adc/injected.rs
+++ b/embassy-stm32/src/adc/injected.rs
@@ -5,9 +5,9 @@ use core::sync::atomic::{Ordering, compiler_fence};
 use embassy_hal_internal::Peri;
 
 use super::{AnyAdcChannel, SampleTime};
-use crate::adc::Adc;
 #[allow(unused_imports)]
 use crate::adc::Instance;
+use crate::adc::{Adc, AnyInstance};
 
 /// Injected ADC sequence with owned channels.
 pub struct InjectedAdc<T: Instance, const N: usize> {
@@ -36,9 +36,9 @@ impl<T: Instance, const N: usize> InjectedAdc<T, N> {
     }
 }
 
-impl<T: Instance, const N: usize> Drop for InjectedAdc<T, N> {
+impl<T: Instance + AnyInstance, const N: usize> Drop for InjectedAdc<T, N> {
     fn drop(&mut self) {
-        Adc::<T>::teardown_dma();
+        T::stop();
         compiler_fence(Ordering::SeqCst);
     }
 }
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index e321c4fa1..6d53d9b91 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -17,6 +17,9 @@
 #[cfg_attr(adc_c0, path = "c0.rs")]
 mod _version;
 
+#[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
+mod ringbuffered;
+
 use core::marker::PhantomData;
 
 #[allow(unused)]
@@ -25,26 +28,25 @@ pub use _version::*;
 use embassy_hal_internal::{PeripheralType, impl_peripheral};
 #[cfg(any(adc_f1, adc_f3v1, adc_v1, adc_l0, adc_f3v2))]
 use embassy_sync::waitqueue::AtomicWaker;
+#[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
+pub use ringbuffered::RingBufferedAdc;
 
 #[cfg(any(adc_u5, adc_wba))]
 #[path = "adc4.rs"]
 pub mod adc4;
 
+#[allow(unused)]
+pub(self) use crate::block_for_us as blocking_delay_us;
 pub use crate::pac::adc::vals;
 #[cfg(not(any(adc_f1, adc_f3v3)))]
 pub use crate::pac::adc::vals::Res as Resolution;
 pub use crate::pac::adc::vals::SampleTime;
 use crate::peripherals;
 
-#[cfg(not(adc_wba))]
-dma_trait!(RxDma, Instance);
-#[cfg(adc_u5)]
-dma_trait!(RxDma4, adc4::Instance);
-#[cfg(adc_wba)]
-dma_trait!(RxDma4, adc4::Instance);
+dma_trait!(RxDma, AnyInstance);
 
 /// Analog to Digital driver.
-pub struct Adc<'d, T: Instance> {
+pub struct Adc<'d, T: AnyInstance> {
     #[allow(unused)]
     adc: crate::Peri<'d, T>,
 }
@@ -87,21 +89,262 @@ pub(crate) trait SealedAdcChannel<T> {
     }
 }
 
-/// Performs a busy-wait delay for a specified number of microseconds.
-#[allow(unused)]
-pub(crate) fn blocking_delay_us(us: u32) {
-    cfg_if::cfg_if! {
-        // this does strange things on stm32wlx in low power mode depending on exactly when it's called
-        // as in sometimes 15 us (1 tick) would take > 20 seconds.
-        if #[cfg(all(feature = "time", all(not(feature = "low-power"), not(stm32wlex))))] {
-            let duration = embassy_time::Duration::from_micros(us as u64);
-            embassy_time::block_for(duration);
-        } else {
-            let freq = unsafe { crate::rcc::get_freqs() }.sys.to_hertz().unwrap().0 as u64;
-            let us = us as u64;
-            let cycles = freq * us / 1_000_000;
-            cortex_m::asm::delay(cycles as u32);
-        }
+// Temporary patch for ADCs that have not implemented the standard iface yet
+#[cfg(any(adc_v1, adc_l0, adc_f1, adc_f3v1, adc_f3v2, adc_f3v3, adc_v1))]
+trait_set::trait_set! {
+    pub trait AnyInstance = Instance;
+}
+
+#[cfg(any(
+    adc_v2, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_g4, adc_c0
+))]
+pub trait BasicAnyInstance {
+    type SampleTime;
+}
+
+#[cfg(any(
+    adc_v2, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_g4, adc_c0
+))]
+pub(self) trait SealedAnyInstance: BasicAnyInstance {
+    fn enable();
+    fn start();
+    fn stop();
+    fn convert() -> u16;
+    fn configure_dma(conversion_mode: ConversionMode);
+    fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), Self::SampleTime)>);
+    #[allow(dead_code)]
+    fn dr() -> *mut u16;
+}
+
+// On chips without ADC4, AnyInstance is an Instance
+#[cfg(any(adc_v2, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_g4, adc_c0))]
+#[allow(private_bounds)]
+pub trait AnyInstance: SealedAnyInstance + Instance {}
+
+// On chips with ADC4, AnyInstance is an Instance or adc4::Instance
+#[cfg(any(adc_v4, adc_u5, adc_wba))]
+#[allow(private_bounds)]
+pub trait AnyInstance: SealedAnyInstance + crate::PeripheralType + crate::rcc::RccPeripheral {}
+
+// Implement AnyInstance automatically for SealedAnyInstance
+#[cfg(any(
+    adc_v2, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_g4, adc_c0
+))]
+impl<T: SealedAnyInstance + Instance> BasicAnyInstance for T {
+    type SampleTime = SampleTime;
+}
+
+#[cfg(any(
+    adc_v2, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_g4, adc_c0
+))]
+impl<T: SealedAnyInstance + Instance> AnyInstance for T {}
+
+#[cfg(any(adc_c0, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5))]
+/// Number of samples used for averaging.
+#[derive(Copy, Clone, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Averaging {
+    Disabled,
+    Samples2,
+    Samples4,
+    Samples8,
+    Samples16,
+    Samples32,
+    Samples64,
+    Samples128,
+    Samples256,
+    #[cfg(any(adc_c0, adc_v4, adc_u5))]
+    Samples512,
+    #[cfg(any(adc_c0, adc_v4, adc_u5))]
+    Samples1024,
+}
+
+#[cfg(any(
+    adc_v2, adc_g4, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_c0
+))]
+pub(crate) enum ConversionMode {
+    // Should match the cfg on "read" below
+    #[cfg(any(adc_g4, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_c0))]
+    Singular,
+    // Should match the cfg on "into_ring_buffered" below
+    #[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
+    Repeated(RegularConversionMode),
+}
+
+// Should match the cfg on "into_ring_buffered" below
+#[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
+// Conversion mode for regular ADC channels
+#[derive(Copy, Clone)]
+pub enum RegularConversionMode {
+    // Samples as fast as possible
+    Continuous,
+    #[cfg(adc_g4)]
+    // Sample at rate determined by external trigger
+    Triggered(ConversionTrigger),
+}
+
+impl<'d, T: AnyInstance> Adc<'d, T> {
+    #[cfg(any(
+        adc_v2, adc_g4, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_u5, adc_v4, adc_wba, adc_c0
+    ))]
+    /// Read an ADC pin.
+    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>, sample_time: T::SampleTime) -> u16 {
+        #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5, adc_wba))]
+        channel.setup();
+
+        // Ensure no conversions are ongoing
+        T::stop();
+        #[cfg(any(adc_v2, adc_v3, adc_g0, adc_h7rs, adc_u0, adc_u5, adc_wba, adc_c0))]
+        T::enable();
+        T::configure_sequence([((channel.channel(), channel.is_differential()), sample_time)].into_iter());
+
+        // On chips with differential channels, enable after configure_sequence to allow setting differential channels
+        //
+        // TODO: If hardware allows, enable after configure_sequence on all chips
+        #[cfg(any(adc_g4, adc_h5))]
+        T::enable();
+
+        T::convert()
+    }
+
+    #[cfg(any(adc_g4, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_c0))]
+    /// Read one or multiple ADC regular channels using DMA.
+    ///
+    /// `sequence` iterator and `readings` must have the same length.
+    ///
+    /// Example
+    /// ```rust,ignore
+    /// use embassy_stm32::adc::{Adc, AdcChannel}
+    ///
+    /// let mut adc = Adc::new(p.ADC1);
+    /// let mut adc_pin0 = p.PA0.into();
+    /// let mut adc_pin1 = p.PA1.into();
+    /// let mut measurements = [0u16; 2];
+    ///
+    /// adc.read(
+    ///     p.DMA1_CH2.reborrow(),
+    ///     [
+    ///         (&mut *adc_pin0, SampleTime::CYCLES160_5),
+    ///         (&mut *adc_pin1, SampleTime::CYCLES160_5),
+    ///     ]
+    ///     .into_iter(),
+    ///     &mut measurements,
+    /// )
+    /// .await;
+    /// defmt::info!("measurements: {}", measurements);
+    /// ```
+    ///
+    /// Note: This is not very efficient as the ADC needs to be reconfigured for each read. Use
+    /// `into_ring_buffered`, `into_ring_buffered_and_injected`
+    ///
+    /// Note: Depending on hardware limitations, this method may require channels to be passed
+    /// in order or require the sequence to have the same sample time for all channnels, depending
+    /// on the number and properties of the channels in the sequence. This method will panic if
+    /// the hardware cannot deliver the requested configuration.
+    pub async fn read(
+        &mut self,
+        rx_dma: embassy_hal_internal::Peri<'_, impl RxDma<T>>,
+        sequence: impl ExactSizeIterator<Item = (&mut AnyAdcChannel<T>, T::SampleTime)>,
+        readings: &mut [u16],
+    ) {
+        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
+        assert!(
+            sequence.len() == readings.len(),
+            "Sequence length must be equal to readings length"
+        );
+        assert!(
+            sequence.len() <= 16,
+            "Asynchronous read sequence cannot be more than 16 in length"
+        );
+
+        // Ensure no conversions are ongoing
+        T::stop();
+        #[cfg(any(adc_g0, adc_v3, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_c0))]
+        T::enable();
+
+        T::configure_sequence(
+            sequence.map(|(channel, sample_time)| ((channel.channel, channel.is_differential), sample_time)),
+        );
+
+        // On chips with differential channels, enable after configure_sequence to allow setting differential channels
+        //
+        // TODO: If hardware allows, enable after configure_sequence on all chips
+        #[cfg(any(adc_g4, adc_h5))]
+        T::enable();
+        T::configure_dma(ConversionMode::Singular);
+
+        let request = rx_dma.request();
+        let transfer =
+            unsafe { crate::dma::Transfer::new_read(rx_dma, request, T::dr(), readings, Default::default()) };
+
+        T::start();
+
+        // Wait for conversion sequence to finish.
+        transfer.await;
+
+        // Ensure conversions are finished.
+        T::stop();
+    }
+
+    #[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
+    /// Configures the ADC to use a DMA ring buffer for continuous data acquisition.
+    ///
+    /// Use the [`read`] method to retrieve measurements from the DMA ring buffer. The read buffer
+    /// should be exactly half the size of `dma_buf`. When using triggered mode, it is recommended
+    /// to configure `dma_buf` as a double buffer so that one half can be read while the other half
+    /// is being filled by the DMA, preventing data loss. The trigger period of the ADC effectively
+    /// defines the period at which the buffer should be read.
+    ///
+    /// If continous conversion mode is selected, the provided `dma_buf` must be large enough to prevent
+    /// DMA buffer overruns. Its length should be a multiple of the number of ADC channels being measured.
+    /// For example, if 3 channels are measured and you want to store 40 samples per channel,
+    /// the buffer length should be `3 * 40 = 120`.
+    ///
+    /// # Parameters
+    /// - `dma`: The DMA peripheral used to transfer ADC data into the buffer.
+    /// - `dma_buf`: The buffer where DMA stores ADC samples.
+    /// - `regular_sequence`: Sequence of channels and sample times for regular ADC conversions.
+    /// - `regular_conversion_mode`: Mode for regular conversions (continuous or triggered).
+    ///
+    /// # Returns
+    /// A `RingBufferedAdc<'a, T>` instance configured for continuous DMA-based sampling.
+    ///
+    /// Note: Depending on hardware limitations, this method may require channels to be passed
+    /// in order or require the sequence to have the same sample time for all channnels, depending
+    /// on the number and properties of the channels in the sequence. This method will panic if
+    /// the hardware cannot deliver the requested configuration.
+    pub fn into_ring_buffered<'a>(
+        self,
+        dma: embassy_hal_internal::Peri<'a, impl RxDma<T>>,
+        dma_buf: &'a mut [u16],
+        sequence: impl ExactSizeIterator<Item = (AnyAdcChannel<T>, T::SampleTime)>,
+        mode: RegularConversionMode,
+    ) -> RingBufferedAdc<'a, T> {
+        assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
+        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
+        assert!(
+            sequence.len() <= 16,
+            "Asynchronous read sequence cannot be more than 16 in length"
+        );
+        // Ensure no conversions are ongoing
+        T::stop();
+        #[cfg(any(adc_g0, adc_v3, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_c0))]
+        T::enable();
+
+        T::configure_sequence(
+            sequence.map(|(channel, sample_time)| ((channel.channel, channel.is_differential), sample_time)),
+        );
+
+        // On chips with differential channels, enable after configure_sequence to allow setting differential channels
+        //
+        // TODO: If hardware allows, enable after configure_sequence on all chips
+        #[cfg(any(adc_g4, adc_h5))]
+        T::enable();
+        T::configure_dma(ConversionMode::Repeated(mode));
+
+        core::mem::forget(self);
+
+        RingBufferedAdc::new(dma, dma_buf)
     }
 }
 
@@ -143,6 +386,14 @@ impl SpecialChannel for Temperature {}
 pub struct Vbat;
 impl SpecialChannel for Vbat {}
 
+/// Vcore channel.
+pub struct Vcore;
+impl SpecialChannel for Vcore {}
+
+/// Internal dac channel.
+pub struct Dac;
+impl SpecialChannel for Dac {}
+
 /// ADC instance.
 #[cfg(not(any(
     adc_f1, adc_v1, adc_l0, adc_v2, adc_v3, adc_v4, adc_g4, adc_f3v1, adc_f3v2, adc_g0, adc_u0, adc_h5, adc_h7rs,
@@ -187,9 +438,9 @@ pub struct AnyAdcChannel<T> {
     is_differential: bool,
     _phantom: PhantomData<T>,
 }
-impl_peripheral!(AnyAdcChannel<T: Instance>);
-impl<T: Instance> AdcChannel<T> for AnyAdcChannel<T> {}
-impl<T: Instance> SealedAdcChannel<T> for AnyAdcChannel<T> {
+impl_peripheral!(AnyAdcChannel<T: AnyInstance>);
+impl<T: AnyInstance> AdcChannel<T> for AnyAdcChannel<T> {}
+impl<T: AnyInstance> SealedAdcChannel<T> for AnyAdcChannel<T> {
     fn channel(&self) -> u8 {
         self.channel
     }
diff --git a/embassy-stm32/src/adc/ringbuffered.rs b/embassy-stm32/src/adc/ringbuffered.rs
index 024c6acdc..5437866d3 100644
--- a/embassy-stm32/src/adc/ringbuffered.rs
+++ b/embassy-stm32/src/adc/ringbuffered.rs
@@ -4,7 +4,7 @@ use core::sync::atomic::{Ordering, compiler_fence};
 #[allow(unused_imports)]
 use embassy_hal_internal::Peri;
 
-use crate::adc::Adc;
+use crate::adc::AnyInstance;
 #[allow(unused_imports)]
 use crate::adc::{Instance, RxDma};
 #[allow(unused_imports)]
@@ -19,7 +19,7 @@ pub struct RingBufferedAdc<'d, T: Instance> {
     ring_buf: ReadableRingBuffer<'d, u16>,
 }
 
-impl<'d, T: Instance> RingBufferedAdc<'d, T> {
+impl<'d, T: Instance + AnyInstance> RingBufferedAdc<'d, T> {
     pub(crate) fn new(dma: Peri<'d, impl RxDma<T>>, dma_buf: &'d mut [u16]) -> Self {
         //dma side setup
         let opts = TransferOptions {
@@ -45,12 +45,10 @@ impl<'d, T: Instance> RingBufferedAdc<'d, T> {
         compiler_fence(Ordering::SeqCst);
         self.ring_buf.start();
 
-        Adc::<T>::start();
+        T::start();
     }
 
     pub fn stop(&mut self) {
-        Adc::<T>::stop();
-
         self.ring_buf.request_pause();
 
         compiler_fence(Ordering::SeqCst);
@@ -161,7 +159,7 @@ impl<'d, T: Instance> RingBufferedAdc<'d, T> {
                     return Ok(len);
                 }
                 Err(_) => {
-                    self.stop();
+                    self.ring_buf.request_pause();
 
                     return Err(OverrunError);
                 }
@@ -170,9 +168,9 @@ impl<'d, T: Instance> RingBufferedAdc<'d, T> {
     }
 }
 
-impl<T: Instance> Drop for RingBufferedAdc<'_, T> {
+impl<T: Instance + AnyInstance> Drop for RingBufferedAdc<'_, T> {
     fn drop(&mut self) {
-        Adc::<T>::teardown_dma();
+        T::stop();
 
         compiler_fence(Ordering::SeqCst);
 
diff --git a/embassy-stm32/src/adc/v2.rs b/embassy-stm32/src/adc/v2.rs
index efa1cc68c..3c4431ae0 100644
--- a/embassy-stm32/src/adc/v2.rs
+++ b/embassy-stm32/src/adc/v2.rs
@@ -1,15 +1,12 @@
-use core::mem;
 use core::sync::atomic::{Ordering, compiler_fence};
 
-use super::{Temperature, Vbat, VrefInt, blocking_delay_us};
-use crate::adc::{Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel};
+use super::{ConversionMode, Temperature, Vbat, VrefInt, blocking_delay_us};
+use crate::adc::{Adc, Instance, Resolution, SampleTime};
 use crate::pac::adc::vals;
+pub use crate::pac::adccommon::vals::Adcpre;
 use crate::time::Hertz;
 use crate::{Peri, rcc};
 
-mod ringbuffered;
-pub use ringbuffered::RingBufferedAdc;
-
 fn clear_interrupt_flags(r: crate::pac::adc::Adc) {
     r.sr().modify(|regs| {
         regs.set_eoc(false);
@@ -54,156 +51,75 @@ impl Temperature {
     }
 }
 
-enum Prescaler {
-    Div2,
-    Div4,
-    Div6,
-    Div8,
-}
-
-impl Prescaler {
-    fn from_pclk2(freq: Hertz) -> Self {
-        // Datasheet for F2 specifies min frequency 0.6 MHz, and max 30 MHz (with VDDA 2.4-3.6V).
-        #[cfg(stm32f2)]
-        const MAX_FREQUENCY: Hertz = Hertz(30_000_000);
-        // Datasheet for both F4 and F7 specifies min frequency 0.6 MHz, typ freq. 30 MHz and max 36 MHz.
-        #[cfg(not(stm32f2))]
-        const MAX_FREQUENCY: Hertz = Hertz(36_000_000);
-        let raw_div = freq.0 / MAX_FREQUENCY.0;
-        match raw_div {
-            0..=1 => Self::Div2,
-            2..=3 => Self::Div4,
-            4..=5 => Self::Div6,
-            6..=7 => Self::Div8,
-            _ => panic!("Selected PCLK2 frequency is too high for ADC with largest possible prescaler."),
-        }
+fn from_pclk2(freq: Hertz) -> Adcpre {
+    // Datasheet for F2 specifies min frequency 0.6 MHz, and max 30 MHz (with VDDA 2.4-3.6V).
+    #[cfg(stm32f2)]
+    const MAX_FREQUENCY: Hertz = Hertz(30_000_000);
+    // Datasheet for both F4 and F7 specifies min frequency 0.6 MHz, typ freq. 30 MHz and max 36 MHz.
+    #[cfg(not(stm32f2))]
+    const MAX_FREQUENCY: Hertz = Hertz(36_000_000);
+    let raw_div = rcc::raw_prescaler(freq.0, MAX_FREQUENCY.0);
+    match raw_div {
+        0..=1 => Adcpre::DIV2,
+        2..=3 => Adcpre::DIV4,
+        4..=5 => Adcpre::DIV6,
+        6..=7 => Adcpre::DIV8,
+        _ => panic!("Selected PCLK2 frequency is too high for ADC with largest possible prescaler."),
     }
+}
 
-    fn adcpre(&self) -> crate::pac::adccommon::vals::Adcpre {
-        match self {
-            Prescaler::Div2 => crate::pac::adccommon::vals::Adcpre::DIV2,
-            Prescaler::Div4 => crate::pac::adccommon::vals::Adcpre::DIV4,
-            Prescaler::Div6 => crate::pac::adccommon::vals::Adcpre::DIV6,
-            Prescaler::Div8 => crate::pac::adccommon::vals::Adcpre::DIV8,
-        }
-    }
+/// ADC configuration
+#[derive(Default)]
+pub struct AdcConfig {
+    resolution: Option<Resolution>,
 }
 
-impl<'d, T> Adc<'d, T>
-where
-    T: Instance,
-{
-    pub fn new(adc: Peri<'d, T>) -> Self {
-        rcc::enable_and_reset::<T>();
+impl<T: Instance> super::SealedAnyInstance for T {
+    fn dr() -> *mut u16 {
+        T::regs().dr().as_ptr() as *mut u16
+    }
 
-        let presc = Prescaler::from_pclk2(T::frequency());
-        T::common_regs().ccr().modify(|w| w.set_adcpre(presc.adcpre()));
+    fn enable() {
         T::regs().cr2().modify(|reg| {
             reg.set_adon(true);
         });
 
         blocking_delay_us(3);
-
-        Self { adc }
-    }
-
-    /// Configures the ADC to use a DMA ring buffer for continuous data acquisition.
-    ///
-    /// The `dma_buf` should be large enough to prevent DMA buffer overrun.
-    /// The length of the `dma_buf` should be a multiple of the ADC channel count.
-    /// For example, if 3 channels are measured, its length can be 3 * 40 = 120 measurements.
-    ///
-    /// `read` method is used to read out measurements from the DMA ring buffer, and its buffer should be exactly half of the `dma_buf` length.
-    /// It is critical to call `read` frequently to prevent DMA buffer overrun.
-    ///
-    /// [`read`]: #method.read
-    pub fn into_ring_buffered<'a>(
-        self,
-        dma: Peri<'d, impl RxDma<T>>,
-        dma_buf: &'d mut [u16],
-        sequence: impl ExactSizeIterator<Item = (AnyAdcChannel<T>, SampleTime)>,
-    ) -> RingBufferedAdc<'d, T> {
-        assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
-
-        Self::configure_sequence(sequence.map(|(mut channel, sample_time)| {
-            channel.setup();
-
-            (channel.channel, sample_time)
-        }));
-        compiler_fence(Ordering::SeqCst);
-
-        Self::setup_dma();
-
-        // Don't disable the clock
-        mem::forget(self);
-
-        RingBufferedAdc::new(dma, dma_buf)
-    }
-
-    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>, sample_time: SampleTime) -> u16 {
-        channel.setup();
-
-        // Configure ADC
-        let channel = channel.channel();
-
-        Self::configure_sequence([(channel, sample_time)].into_iter());
-        Self::blocking_convert()
-    }
-
-    /// Enables internal voltage reference and returns [VrefInt], which can be used in
-    /// [Adc::read_internal()] to perform conversion.
-    pub fn enable_vrefint(&self) -> VrefInt {
-        T::common_regs().ccr().modify(|reg| {
-            reg.set_tsvrefe(true);
-        });
-
-        VrefInt {}
-    }
-
-    /// Enables internal temperature sensor and returns [Temperature], which can be used in
-    /// [Adc::read_internal()] to perform conversion.
-    ///
-    /// On STM32F42 and STM32F43 this can not be used together with [Vbat]. If both are enabled,
-    /// temperature sensor will return vbat value.
-    pub fn enable_temperature(&self) -> Temperature {
-        T::common_regs().ccr().modify(|reg| {
-            reg.set_tsvrefe(true);
-        });
-
-        Temperature {}
-    }
-
-    /// Enables vbat input and returns [Vbat], which can be used in
-    /// [Adc::read_internal()] to perform conversion.
-    pub fn enable_vbat(&self) -> Vbat {
-        T::common_regs().ccr().modify(|reg| {
-            reg.set_vbate(true);
-        });
-
-        Vbat {}
     }
 
-    pub(super) fn start() {
+    fn start() {
         // Begin ADC conversions
         T::regs().cr2().modify(|reg| {
-            reg.set_adon(true);
             reg.set_swstart(true);
         });
     }
 
-    pub(super) fn stop() {
+    fn stop() {
+        let r = T::regs();
+
         // Stop ADC
-        T::regs().cr2().modify(|reg| {
+        r.cr2().modify(|reg| {
             // Stop ADC
             reg.set_swstart(false);
+            // Stop ADC
+            reg.set_adon(false);
+            // Stop DMA
+            reg.set_dma(false);
         });
-    }
 
-    pub fn set_resolution(&mut self, resolution: Resolution) {
-        T::regs().cr1().modify(|reg| reg.set_res(resolution.into()));
+        r.cr1().modify(|w| {
+            // Disable interrupt for end of conversion
+            w.set_eocie(false);
+            // Disable interrupt for overrun
+            w.set_ovrie(false);
+        });
+
+        clear_interrupt_flags(r);
+
+        compiler_fence(Ordering::SeqCst);
     }
 
-    pub(super) fn blocking_convert() -> u16 {
+    fn convert() -> u16 {
         // clear end of conversion flag
         T::regs().sr().modify(|reg| {
             reg.set_eoc(false);
@@ -224,7 +140,44 @@ where
         T::regs().dr().read().0 as u16
     }
 
-    pub(super) fn configure_sequence(sequence: impl ExactSizeIterator<Item = (u8, SampleTime)>) {
+    fn configure_dma(conversion_mode: ConversionMode) {
+        match conversion_mode {
+            ConversionMode::Repeated(_) => {
+                let r = T::regs();
+
+                // Clear all interrupts
+                r.sr().modify(|regs| {
+                    regs.set_eoc(false);
+                    regs.set_ovr(false);
+                    regs.set_strt(false);
+                });
+
+                r.cr1().modify(|w| {
+                    // Enable interrupt for end of conversion
+                    w.set_eocie(true);
+                    // Enable interrupt for overrun
+                    w.set_ovrie(true);
+                    // Scanning converisons of multiple channels
+                    w.set_scan(true);
+                    // Continuous conversion mode
+                    w.set_discen(false);
+                });
+
+                r.cr2().modify(|w| {
+                    // Enable DMA mode
+                    w.set_dma(true);
+                    // Enable continuous conversions
+                    w.set_cont(true);
+                    // DMA requests are issues as long as DMA=1 and data are converted.
+                    w.set_dds(vals::Dds::CONTINUOUS);
+                    // EOC flag is set at the end of each conversion.
+                    w.set_eocs(vals::Eocs::EACH_CONVERSION);
+                });
+            }
+        }
+    }
+
+    fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
         T::regs().cr2().modify(|reg| {
             reg.set_adon(true);
         });
@@ -234,7 +187,7 @@ where
             r.set_l((sequence.len() - 1).try_into().unwrap());
         });
 
-        for (i, (ch, sample_time)) in sequence.enumerate() {
+        for (i, ((ch, _), sample_time)) in sequence.enumerate() {
             // Set the channel in the right sequence field.
             T::regs().sqr3().modify(|w| w.set_sq(i, ch));
 
@@ -246,63 +199,61 @@ where
             }
         }
     }
+}
 
-    pub(super) fn setup_dma() {
-        let r = T::regs();
+impl<'d, T> Adc<'d, T>
+where
+    T: Instance + super::AnyInstance,
+{
+    pub fn new(adc: Peri<'d, T>) -> Self {
+        Self::new_with_config(adc, Default::default())
+    }
 
-        // Clear all interrupts
-        r.sr().modify(|regs| {
-            regs.set_eoc(false);
-            regs.set_ovr(false);
-            regs.set_strt(false);
-        });
+    pub fn new_with_config(adc: Peri<'d, T>, config: AdcConfig) -> Self {
+        rcc::enable_and_reset::<T>();
 
-        r.cr1().modify(|w| {
-            // Enable interrupt for end of conversion
-            w.set_eocie(true);
-            // Enable interrupt for overrun
-            w.set_ovrie(true);
-            // Scanning converisons of multiple channels
-            w.set_scan(true);
-            // Continuous conversion mode
-            w.set_discen(false);
-        });
+        let presc = from_pclk2(T::frequency());
+        T::common_regs().ccr().modify(|w| w.set_adcpre(presc));
+        T::enable();
 
-        r.cr2().modify(|w| {
-            // Enable DMA mode
-            w.set_dma(true);
-            // Enable continuous conversions
-            w.set_cont(true);
-            // DMA requests are issues as long as DMA=1 and data are converted.
-            w.set_dds(vals::Dds::CONTINUOUS);
-            // EOC flag is set at the end of each conversion.
-            w.set_eocs(vals::Eocs::EACH_CONVERSION);
-        });
-    }
+        if let Some(resolution) = config.resolution {
+            T::regs().cr1().modify(|reg| reg.set_res(resolution.into()));
+        }
 
-    pub(super) fn teardown_dma() {
-        let r = T::regs();
+        Self { adc }
+    }
 
-        // Stop ADC
-        r.cr2().modify(|reg| {
-            // Stop ADC
-            reg.set_swstart(false);
-            // Stop ADC
-            reg.set_adon(false);
-            // Stop DMA
-            reg.set_dma(false);
+    /// Enables internal voltage reference and returns [VrefInt], which can be used in
+    /// [Adc::read_internal()] to perform conversion.
+    pub fn enable_vrefint(&self) -> VrefInt {
+        T::common_regs().ccr().modify(|reg| {
+            reg.set_tsvrefe(true);
         });
 
-        r.cr1().modify(|w| {
-            // Disable interrupt for end of conversion
-            w.set_eocie(false);
-            // Disable interrupt for overrun
-            w.set_ovrie(false);
+        VrefInt {}
+    }
+
+    /// Enables internal temperature sensor and returns [Temperature], which can be used in
+    /// [Adc::read_internal()] to perform conversion.
+    ///
+    /// On STM32F42 and STM32F43 this can not be used together with [Vbat]. If both are enabled,
+    /// temperature sensor will return vbat value.
+    pub fn enable_temperature(&self) -> Temperature {
+        T::common_regs().ccr().modify(|reg| {
+            reg.set_tsvrefe(true);
         });
 
-        clear_interrupt_flags(r);
+        Temperature {}
+    }
 
-        compiler_fence(Ordering::SeqCst);
+    /// Enables vbat input and returns [Vbat], which can be used in
+    /// [Adc::read_internal()] to perform conversion.
+    pub fn enable_vbat(&self) -> Vbat {
+        T::common_regs().ccr().modify(|reg| {
+            reg.set_vbate(true);
+        });
+
+        Vbat {}
     }
 }
 
diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs
index cbc217545..b270588c4 100644
--- a/embassy-stm32/src/adc/v3.rs
+++ b/embassy-stm32/src/adc/v3.rs
@@ -1,9 +1,9 @@
 use cfg_if::cfg_if;
 #[cfg(adc_g0)]
 use heapless::Vec;
-use pac::adc::vals::Dmacfg;
 #[cfg(adc_g0)]
-use pac::adc::vals::{Ckmode, Smpsel};
+use pac::adc::vals::Ckmode;
+use pac::adc::vals::Dmacfg;
 #[cfg(adc_v3)]
 use pac::adc::vals::{OversamplingRatio, OversamplingShift, Rovsm, Trovs};
 #[cfg(adc_g0)]
@@ -11,18 +11,8 @@ pub use pac::adc::vals::{Ovsr, Ovss, Presc};
 
 #[allow(unused_imports)]
 use super::SealedAdcChannel;
-use super::{
-    Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, Temperature, Vbat, VrefInt,
-    blocking_delay_us,
-};
-
-#[cfg(any(adc_v3, adc_g0, adc_u0))]
-mod ringbuffered;
-
-#[cfg(any(adc_v3, adc_g0, adc_u0))]
-use ringbuffered::RingBufferedAdc;
-
-use crate::dma::Transfer;
+use super::{Adc, Averaging, Instance, Resolution, SampleTime, Temperature, Vbat, VrefInt, blocking_delay_us};
+use crate::adc::ConversionMode;
 use crate::{Peri, pac, rcc};
 
 /// Default VREF voltage used for sample conversion to millivolts.
@@ -75,7 +65,7 @@ impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
 }
 #[cfg(any(adc_h5, adc_h7rs))]
 impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
-    const CHANNEL: u8 = 2;
+    const CHANNEL: u8 = 16;
 }
 #[cfg(adc_u0)]
 impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
@@ -89,10 +79,10 @@ impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
 cfg_if! {
     if #[cfg(any(adc_h5, adc_h7rs))] {
         pub struct VddCore;
-        impl<T: Instance> AdcChannel<T> for VddCore {}
+        impl<T: Instance> super::AdcChannel<T> for VddCore {}
         impl<T: Instance> super::SealedAdcChannel<T> for VddCore {
             fn channel(&self) -> u8 {
-                6
+                17
             }
         }
     }
@@ -101,7 +91,7 @@ cfg_if! {
 cfg_if! {
     if #[cfg(adc_u0)] {
         pub struct DacOut;
-        impl<T: Instance> AdcChannel<T> for DacOut {}
+        impl<T: Instance> super::AdcChannel<T> for DacOut {}
         impl<T: Instance> super::SealedAdcChannel<T> for DacOut {
             fn channel(&self) -> u8 {
                 19
@@ -110,21 +100,6 @@ cfg_if! {
     }
 }
 
-/// Number of samples used for averaging.
-#[derive(Copy, Clone, Debug)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Averaging {
-    Disabled,
-    Samples2,
-    Samples4,
-    Samples8,
-    Samples16,
-    Samples32,
-    Samples64,
-    Samples128,
-    Samples256,
-}
-
 cfg_if! { if #[cfg(adc_g0)] {
 
 /// Synchronous PCLK prescaler
@@ -145,310 +120,148 @@ pub enum Clock {
 
 }}
 
-impl<'d, T: Instance> Adc<'d, T> {
-    /// Enable the voltage regulator
-    fn init_regulator() {
-        rcc::enable_and_reset::<T>();
-        T::regs().cr().modify(|reg| {
-            #[cfg(not(any(adc_g0, adc_u0)))]
-            reg.set_deeppwd(false);
-            reg.set_advregen(true);
-        });
-
-        // If this is false then each ADC_CHSELR bit enables an input channel.
-        // This is the reset value, so has no effect.
-        #[cfg(any(adc_g0, adc_u0))]
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_chselrmod(false);
-        });
+#[cfg(adc_u0)]
+type Ovss = u8;
+#[cfg(adc_u0)]
+type Ovsr = u8;
+#[cfg(adc_v3)]
+type Ovss = OversamplingShift;
+#[cfg(adc_v3)]
+type Ovsr = OversamplingRatio;
+
+/// Adc configuration
+#[derive(Default)]
+pub struct AdcConfig {
+    #[cfg(any(adc_u0, adc_g0, adc_v3))]
+    pub oversampling_shift: Option<Ovss>,
+    #[cfg(any(adc_u0, adc_g0, adc_v3))]
+    pub oversampling_ratio: Option<Ovsr>,
+    #[cfg(any(adc_u0, adc_g0))]
+    pub oversampling_enable: Option<bool>,
+    #[cfg(adc_v3)]
+    pub oversampling_mode: Option<(Rovsm, Trovs, bool)>,
+    #[cfg(adc_g0)]
+    pub clock: Option<Clock>,
+    pub resolution: Option<Resolution>,
+    pub averaging: Option<Averaging>,
+}
 
-        blocking_delay_us(20);
+impl<T: Instance> super::SealedAnyInstance for T {
+    fn dr() -> *mut u16 {
+        T::regs().dr().as_ptr() as *mut u16
     }
 
-    /// Calibrate to remove conversion offset
-    fn init_calibrate() {
-        T::regs().cr().modify(|reg| {
-            reg.set_adcal(true);
-        });
-
-        while T::regs().cr().read().adcal() {
+    // Enable ADC only when it is not already running.
+    fn enable() {
+        // Make sure bits are off
+        while T::regs().cr().read().addis() {
             // spin
         }
 
-        blocking_delay_us(1);
+        if !T::regs().cr().read().aden() {
+            // Enable ADC
+            T::regs().isr().modify(|reg| {
+                reg.set_adrdy(true);
+            });
+            T::regs().cr().modify(|reg| {
+                reg.set_aden(true);
+            });
+
+            while !T::regs().isr().read().adrdy() {
+                // spin
+            }
+        }
     }
 
-    #[cfg(any(adc_v3, adc_g0, adc_u0))]
-    pub(super) fn start() {
-        // Start adc conversion
+    fn start() {
         T::regs().cr().modify(|reg| {
             reg.set_adstart(true);
         });
     }
 
-    #[cfg(any(adc_v3, adc_g0, adc_u0))]
-    pub(super) fn stop() {
-        // Stop adc conversion
+    fn stop() {
+        // Ensure conversions are finished.
         if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
             T::regs().cr().modify(|reg| {
                 reg.set_adstp(true);
             });
             while T::regs().cr().read().adstart() {}
         }
-    }
 
-    #[cfg(any(adc_v3, adc_g0, adc_u0))]
-    pub(super) fn teardown_dma() {
-        //disable dma control
+        // Reset configuration.
         #[cfg(not(any(adc_g0, adc_u0)))]
         T::regs().cfgr().modify(|reg| {
+            reg.set_cont(false);
             reg.set_dmaen(false);
         });
         #[cfg(any(adc_g0, adc_u0))]
         T::regs().cfgr1().modify(|reg| {
+            reg.set_cont(false);
             reg.set_dmaen(false);
         });
     }
 
-    /// Initialize the ADC leaving any analog clock at reset value.
-    /// For G0 and WL, this is the async clock without prescaler.
-    pub fn new(adc: Peri<'d, T>) -> Self {
-        Self::init_regulator();
-        Self::init_calibrate();
-        Self { adc }
-    }
-
-    #[cfg(adc_g0)]
-    /// Initialize ADC with explicit clock for the analog ADC
-    pub fn new_with_clock(adc: Peri<'d, T>, clock: Clock) -> Self {
-        Self::init_regulator();
-
-        #[cfg(any(stm32wl5x))]
-        {
-            // Reset value 0 is actually _No clock selected_ in the STM32WL5x reference manual
-            let async_clock_available = pac::RCC.ccipr().read().adcsel() != pac::rcc::vals::Adcsel::_RESERVED_0;
-            match clock {
-                Clock::Async { div: _ } => {
-                    assert!(async_clock_available);
-                }
-                Clock::Sync { div: _ } => {
-                    if async_clock_available {
-                        warn!("Not using configured ADC clock");
-                    }
-                }
-            }
-        }
-        match clock {
-            Clock::Async { div } => T::regs().ccr().modify(|reg| reg.set_presc(div)),
-            Clock::Sync { div } => T::regs().cfgr2().modify(|reg| {
-                reg.set_ckmode(match div {
-                    CkModePclk::DIV1 => Ckmode::PCLK,
-                    CkModePclk::DIV2 => Ckmode::PCLK_DIV2,
-                    CkModePclk::DIV4 => Ckmode::PCLK_DIV4,
-                })
-            }),
-        }
-
-        Self::init_calibrate();
-
-        Self { adc }
-    }
+    /// Perform a single conversion.
+    fn convert() -> u16 {
+        // Some models are affected by an erratum:
+        // If we perform conversions slower than 1 kHz, the first read ADC value can be
+        // corrupted, so we discard it and measure again.
+        //
+        // STM32L471xx: Section 2.7.3
+        // STM32G4: Section 2.7.3
+        #[cfg(any(rcc_l4, rcc_g4))]
+        let len = 2;
 
-    // Enable ADC only when it is not already running.
-    fn enable(&mut self) {
-        // Make sure bits are off
-        while T::regs().cr().read().addis() {
-            // spin
-        }
+        #[cfg(not(any(rcc_l4, rcc_g4)))]
+        let len = 1;
 
-        if !T::regs().cr().read().aden() {
-            // Enable ADC
+        for _ in 0..len {
             T::regs().isr().modify(|reg| {
-                reg.set_adrdy(true);
+                reg.set_eos(true);
+                reg.set_eoc(true);
             });
+
+            // Start conversion
             T::regs().cr().modify(|reg| {
-                reg.set_aden(true);
+                reg.set_adstart(true);
             });
 
-            while !T::regs().isr().read().adrdy() {
+            while !T::regs().isr().read().eos() {
                 // spin
             }
         }
-    }
-
-    pub fn enable_vrefint(&self) -> VrefInt {
-        #[cfg(not(any(adc_g0, adc_u0)))]
-        T::common_regs().ccr().modify(|reg| {
-            reg.set_vrefen(true);
-        });
-        #[cfg(any(adc_g0, adc_u0))]
-        T::regs().ccr().modify(|reg| {
-            reg.set_vrefen(true);
-        });
-
-        // "Table 24. Embedded internal voltage reference" states that it takes a maximum of 12 us
-        // to stabilize the internal voltage reference.
-        blocking_delay_us(15);
-
-        VrefInt {}
-    }
-
-    pub fn enable_temperature(&self) -> Temperature {
-        cfg_if! {
-            if #[cfg(any(adc_g0, adc_u0))] {
-                T::regs().ccr().modify(|reg| {
-                    reg.set_tsen(true);
-                });
-            } else if #[cfg(any(adc_h5, adc_h7rs))] {
-                T::common_regs().ccr().modify(|reg| {
-                    reg.set_tsen(true);
-                });
-            } else {
-                T::common_regs().ccr().modify(|reg| {
-                    reg.set_ch17sel(true);
-                });
-            }
-        }
-
-        Temperature {}
-    }
 
-    pub fn enable_vbat(&self) -> Vbat {
-        cfg_if! {
-            if #[cfg(any(adc_g0, adc_u0))] {
-                T::regs().ccr().modify(|reg| {
-                    reg.set_vbaten(true);
-                });
-            } else if #[cfg(any(adc_h5, adc_h7rs))] {
-                T::common_regs().ccr().modify(|reg| {
-                    reg.set_vbaten(true);
-                });
-            } else {
-                T::common_regs().ccr().modify(|reg| {
-                    reg.set_ch18sel(true);
-                });
-            }
-        }
-
-        Vbat {}
-    }
-
-    /// Set the ADC resolution.
-    pub fn set_resolution(&mut self, resolution: Resolution) {
-        #[cfg(not(any(adc_g0, adc_u0)))]
-        T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
-        #[cfg(any(adc_g0, adc_u0))]
-        T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into()));
-    }
-
-    pub fn set_averaging(&mut self, averaging: Averaging) {
-        let (enable, samples, right_shift) = match averaging {
-            Averaging::Disabled => (false, 0, 0),
-            Averaging::Samples2 => (true, 0, 1),
-            Averaging::Samples4 => (true, 1, 2),
-            Averaging::Samples8 => (true, 2, 3),
-            Averaging::Samples16 => (true, 3, 4),
-            Averaging::Samples32 => (true, 4, 5),
-            Averaging::Samples64 => (true, 5, 6),
-            Averaging::Samples128 => (true, 6, 7),
-            Averaging::Samples256 => (true, 7, 8),
-        };
-        T::regs().cfgr2().modify(|reg| {
-            #[cfg(not(any(adc_g0, adc_u0)))]
-            reg.set_rovse(enable);
-            #[cfg(any(adc_g0, adc_u0))]
-            reg.set_ovse(enable);
-            #[cfg(any(adc_h5, adc_h7rs))]
-            reg.set_ovsr(samples.into());
-            #[cfg(not(any(adc_h5, adc_h7rs)))]
-            reg.set_ovsr(samples.into());
-            reg.set_ovss(right_shift.into());
-        })
-    }
-    /*
-    /// Convert a raw sample from the `Temperature` to deg C
-    pub fn to_degrees_centigrade(sample: u16) -> f32 {
-        (130.0 - 30.0) / (VtempCal130::get().read() as f32 - VtempCal30::get().read() as f32)
-            * (sample as f32 - VtempCal30::get().read() as f32)
-            + 30.0
+        T::regs().dr().read().0 as u16
     }
-     */
 
-    /// Perform a single conversion.
-    fn convert(&mut self) -> u16 {
+    fn configure_dma(conversion_mode: ConversionMode) {
+        // Set continuous mode with oneshot dma.
+        // Clear overrun flag before starting transfer.
         T::regs().isr().modify(|reg| {
-            reg.set_eos(true);
-            reg.set_eoc(true);
-        });
-
-        // Start conversion
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
+            reg.set_ovr(true);
         });
 
-        while !T::regs().isr().read().eos() {
-            // spin
-        }
+        #[cfg(not(any(adc_g0, adc_u0)))]
+        let regs = T::regs().cfgr();
 
-        T::regs().dr().read().0 as u16
-    }
+        #[cfg(any(adc_g0, adc_u0))]
+        let regs = T::regs().cfgr1();
 
-    /// Read an ADC channel.
-    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>, sample_time: SampleTime) -> u16 {
-        self.read_channel(channel, sample_time)
+        regs.modify(|reg| {
+            reg.set_discen(false);
+            reg.set_cont(true);
+            reg.set_dmacfg(match conversion_mode {
+                ConversionMode::Singular => Dmacfg::ONE_SHOT,
+                #[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
+                ConversionMode::Repeated(_) => Dmacfg::CIRCULAR,
+            });
+            reg.set_dmaen(true);
+        });
     }
 
-    /// Read one or multiple ADC channels using DMA.
-    ///
-    /// `readings` must have a length that is a multiple of the length of the
-    /// `sequence` iterator.
-    ///
-    /// Note: The order of values in `readings` is defined by the pin ADC
-    /// channel number and not the pin order in `sequence`.
-    ///
-    /// Example
-    /// ```rust,ignore
-    /// use embassy_stm32::adc::{Adc, AdcChannel}
-    ///
-    /// let mut adc = Adc::new(p.ADC1);
-    /// let mut adc_pin0 = p.PA0.degrade_adc();
-    /// let mut adc_pin1 = p.PA1.degrade_adc();
-    /// let mut measurements = [0u16; 2];
-    ///
-    /// adc.read(
-    ///     p.DMA1_CH2.reborrow(),
-    ///     [
-    ///         (&mut *adc_pin0, SampleTime::CYCLES160_5),
-    ///         (&mut *adc_pin1, SampleTime::CYCLES160_5),
-    ///     ]
-    ///     .into_iter(),
-    ///     &mut measurements,
-    /// )
-    /// .await;
-    /// defmt::info!("measurements: {}", measurements);
-    /// ```
-    pub async fn read(
-        &mut self,
-        rx_dma: Peri<'_, impl RxDma<T>>,
-        sequence: impl ExactSizeIterator<Item = (&mut AnyAdcChannel<T>, SampleTime)>,
-        readings: &mut [u16],
-    ) {
-        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
-        assert!(
-            readings.len() % sequence.len() == 0,
-            "Readings length must be a multiple of sequence length"
-        );
-        assert!(
-            sequence.len() <= 16,
-            "Asynchronous read sequence cannot be more than 16 in length"
-        );
-
-        #[cfg(all(feature = "low-power", stm32wlex))]
-        let _device_busy = crate::low_power::DeviceBusy::new_stop1();
-
-        // Ensure no conversions are ongoing and ADC is enabled.
-        Self::cancel_conversions();
-        self.enable();
+    fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
+        #[cfg(adc_h5)]
+        T::regs().cr().modify(|w| w.set_aden(false));
 
         // Set sequence length
         #[cfg(not(any(adc_g0, adc_u0)))]
@@ -462,10 +275,10 @@ impl<'d, T: Instance> Adc<'d, T> {
 
             T::regs().chselr().write(|chselr| {
                 T::regs().smpr().write(|smpr| {
-                    for (channel, sample_time) in sequence {
-                        chselr.set_chsel(channel.channel.into(), true);
+                    for ((channel, _), sample_time) in sequence {
+                        chselr.set_chsel(channel.into(), true);
                         if let Some(i) = sample_times.iter().position(|&t| t == sample_time) {
-                            smpr.set_smpsel(channel.channel.into(), (i as u8).into());
+                            smpr.set_smpsel(channel.into(), (i as u8).into());
                         } else {
                             smpr.set_sample_time(sample_times.len(), sample_time);
                             if let Err(_) = sample_times.push(sample_time) {
@@ -484,42 +297,86 @@ impl<'d, T: Instance> Adc<'d, T> {
             #[cfg(adc_u0)]
             let mut channel_mask = 0;
 
+            #[cfg(adc_h5)]
+            let mut difsel = 0u32;
+
             // Configure channels and ranks
-            for (_i, (channel, sample_time)) in sequence.enumerate() {
-                Self::configure_channel(channel, sample_time);
+            for (_i, ((channel, _is_differential), sample_time)) in sequence.enumerate() {
+                // RM0492, RM0481, etc.
+                // "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
+                #[cfg(any(adc_h5, adc_h7rs))]
+                if channel == 0 {
+                    T::regs().or().modify(|reg| reg.set_op0(true));
+                }
+
+                // Configure channel
+                cfg_if! {
+                    if #[cfg(adc_u0)] {
+                        // On G0 and U6 all channels use the same sampling time.
+                        T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into()));
+                    } else if #[cfg(any(adc_h5, adc_h7rs))] {
+                        match channel {
+                            0..=9 => T::regs().smpr1().modify(|w| w.set_smp(channel as usize % 10, sample_time.into())),
+                            _ => T::regs().smpr2().modify(|w| w.set_smp(channel as usize % 10, sample_time.into())),
+                        }
+                    } else {
+                        let sample_time = sample_time.into();
+                        T::regs()
+                            .smpr(channel as usize / 10)
+                            .modify(|reg| reg.set_smp(channel as usize % 10, sample_time));
+                    }
+                }
+
+                #[cfg(stm32h7)]
+                {
+                    use crate::pac::adc::vals::Pcsel;
+
+                    T::regs().cfgr2().modify(|w| w.set_lshift(0));
+                    T::regs()
+                        .pcsel()
+                        .write(|w| w.set_pcsel(channel.channel() as _, Pcsel::PRESELECTED));
+                }
 
                 // Each channel is sampled according to sequence
                 #[cfg(not(any(adc_g0, adc_u0)))]
                 match _i {
                     0..=3 => {
                         T::regs().sqr1().modify(|w| {
-                            w.set_sq(_i, channel.channel());
+                            w.set_sq(_i, channel);
                         });
                     }
                     4..=8 => {
                         T::regs().sqr2().modify(|w| {
-                            w.set_sq(_i - 4, channel.channel());
+                            w.set_sq(_i - 4, channel);
                         });
                     }
                     9..=13 => {
                         T::regs().sqr3().modify(|w| {
-                            w.set_sq(_i - 9, channel.channel());
+                            w.set_sq(_i - 9, channel);
                         });
                     }
                     14..=15 => {
                         T::regs().sqr4().modify(|w| {
-                            w.set_sq(_i - 14, channel.channel());
+                            w.set_sq(_i - 14, channel);
                         });
                     }
                     _ => unreachable!(),
                 }
 
+                #[cfg(adc_h5)]
+                {
+                    difsel |= (_is_differential as u32) << channel;
+                }
+
                 #[cfg(adc_u0)]
                 {
-                    channel_mask |= 1 << channel.channel();
+                    channel_mask |= 1 << channel;
                 }
             }
 
+            #[cfg(adc_h5)]
+            T::regs().difsel().write(|w| w.set_difsel(difsel));
+
             // On G0 and U0 enabled channels are sampled from 0 to last channel.
             // It is possible to add up to 8 sequences if CHSELRMOD = 1.
             // However for supporting more than 8 channels alternative CHSELRMOD = 0 approach is used.
@@ -528,312 +385,234 @@ impl<'d, T: Instance> Adc<'d, T> {
                 reg.set_chsel(channel_mask);
             });
         }
-        // Set continuous mode with oneshot dma.
-        // Clear overrun flag before starting transfer.
-        T::regs().isr().modify(|reg| {
-            reg.set_ovr(true);
-        });
+    }
+}
 
-        #[cfg(not(any(adc_g0, adc_u0)))]
-        T::regs().cfgr().modify(|reg| {
-            reg.set_discen(false);
-            reg.set_cont(true);
-            reg.set_dmacfg(Dmacfg::ONE_SHOT);
-            reg.set_dmaen(true);
+impl<'d, T: Instance> Adc<'d, T> {
+    /// Enable the voltage regulator
+    fn init_regulator() {
+        rcc::enable_and_reset::<T>();
+        T::regs().cr().modify(|reg| {
+            #[cfg(not(any(adc_g0, adc_u0)))]
+            reg.set_deeppwd(false);
+            reg.set_advregen(true);
         });
+
+        // If this is false then each ADC_CHSELR bit enables an input channel.
+        // This is the reset value, so has no effect.
         #[cfg(any(adc_g0, adc_u0))]
         T::regs().cfgr1().modify(|reg| {
-            reg.set_discen(false);
-            reg.set_cont(true);
-            reg.set_dmacfg(Dmacfg::ONE_SHOT);
-            reg.set_dmaen(true);
+            reg.set_chselrmod(false);
         });
 
-        let request = rx_dma.request();
-        let transfer = unsafe {
-            Transfer::new_read(
-                rx_dma,
-                request,
-                T::regs().dr().as_ptr() as *mut u16,
-                readings,
-                Default::default(),
-            )
-        };
+        blocking_delay_us(20);
+    }
 
-        // Start conversion
+    /// Calibrate to remove conversion offset
+    fn init_calibrate() {
         T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
+            reg.set_adcal(true);
         });
 
-        // Wait for conversion sequence to finish.
-        transfer.await;
-
-        // Ensure conversions are finished.
-        Self::cancel_conversions();
+        while T::regs().cr().read().adcal() {
+            // spin
+        }
 
-        // Reset configuration.
-        #[cfg(not(any(adc_g0, adc_u0)))]
-        T::regs().cfgr().modify(|reg| {
-            reg.set_cont(false);
-        });
-        #[cfg(any(adc_g0, adc_u0))]
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_cont(false);
-        });
+        blocking_delay_us(1);
     }
 
-    /// Configures the ADC to use a DMA ring buffer for continuous data acquisition.
-    ///
-    /// The `dma_buf` should be large enough to prevent DMA buffer overrun.
-    /// The length of the `dma_buf` should be a multiple of the ADC channel count.
-    /// For example, if 3 channels are measured, its length can be 3 * 40 = 120 measurements.
-    ///
-    /// `read` method is used to read out measurements from the DMA ring buffer, and its buffer should be exactly half of the `dma_buf` length.
-    /// It is critical to call `read` frequently to prevent DMA buffer overrun.
-    ///
-    /// [`read`]: #method.read
-    #[cfg(any(adc_v3, adc_g0, adc_u0))]
-    pub fn into_ring_buffered<'a>(
-        &mut self,
-        dma: Peri<'a, impl RxDma<T>>,
-        dma_buf: &'a mut [u16],
-        sequence: impl ExactSizeIterator<Item = (AnyAdcChannel<T>, SampleTime)>,
-    ) -> RingBufferedAdc<'a, T> {
-        assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
-        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
-        assert!(
-            sequence.len() <= 16,
-            "Asynchronous read sequence cannot be more than 16 in length"
-        );
-        // reset conversions and enable the adc
-        Self::cancel_conversions();
-        self.enable();
-
-        //adc side setup
+    /// Initialize the ADC leaving any analog clock at reset value.
+    /// For G0 and WL, this is the async clock without prescaler.
+    pub fn new(adc: Peri<'d, T>) -> Self {
+        Self::init_regulator();
+        Self::init_calibrate();
+        Self { adc }
+    }
 
-        // Set sequence length
-        #[cfg(not(any(adc_g0, adc_u0)))]
-        T::regs().sqr1().modify(|w| {
-            w.set_l(sequence.len() as u8 - 1);
-        });
+    pub fn new_with_config(adc: Peri<'d, T>, config: AdcConfig) -> Self {
+        #[cfg(not(adc_g0))]
+        let s = Self::new(adc);
 
         #[cfg(adc_g0)]
-        {
-            let mut sample_times = Vec::<SampleTime, SAMPLE_TIMES_CAPACITY>::new();
+        let s = match config.clock {
+            Some(clock) => Self::new_with_clock(adc, clock),
+            None => Self::new(adc),
+        };
 
-            T::regs().chselr().write(|chselr| {
-                T::regs().smpr().write(|smpr| {
-                    for (channel, sample_time) in sequence {
-                        chselr.set_chsel(channel.channel.into(), true);
-                        if let Some(i) = sample_times.iter().position(|&t| t == sample_time) {
-                            smpr.set_smpsel(channel.channel.into(), (i as u8).into());
-                        } else {
-                            smpr.set_sample_time(sample_times.len(), sample_time);
-                            if let Err(_) = sample_times.push(sample_time) {
-                                panic!(
-                                    "Implementation is limited to {} unique sample times among all channels.",
-                                    SAMPLE_TIMES_CAPACITY
-                                );
-                            }
-                        }
-                    }
-                })
-            });
+        #[cfg(any(adc_g0, adc_u0, adc_v3))]
+        if let Some(shift) = config.oversampling_shift {
+            T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
         }
-        #[cfg(not(adc_g0))]
-        {
-            #[cfg(adc_u0)]
-            let mut channel_mask = 0;
 
-            // Configure channels and ranks
-            for (_i, (mut channel, sample_time)) in sequence.enumerate() {
-                Self::configure_channel(&mut channel, sample_time);
+        #[cfg(any(adc_g0, adc_u0, adc_v3))]
+        if let Some(ratio) = config.oversampling_ratio {
+            T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
+        }
 
-                // Each channel is sampled according to sequence
-                #[cfg(not(any(adc_g0, adc_u0)))]
-                match _i {
-                    0..=3 => {
-                        T::regs().sqr1().modify(|w| {
-                            w.set_sq(_i, channel.channel());
-                        });
-                    }
-                    4..=8 => {
-                        T::regs().sqr2().modify(|w| {
-                            w.set_sq(_i - 4, channel.channel());
-                        });
-                    }
-                    9..=13 => {
-                        T::regs().sqr3().modify(|w| {
-                            w.set_sq(_i - 9, channel.channel());
-                        });
-                    }
-                    14..=15 => {
-                        T::regs().sqr4().modify(|w| {
-                            w.set_sq(_i - 14, channel.channel());
-                        });
-                    }
-                    _ => unreachable!(),
-                }
+        #[cfg(any(adc_g0, adc_u0))]
+        if let Some(enable) = config.oversampling_enable {
+            T::regs().cfgr2().modify(|reg| reg.set_ovse(enable));
+        }
 
-                #[cfg(adc_u0)]
-                {
-                    channel_mask |= 1 << channel.channel();
-                }
-            }
+        #[cfg(adc_v3)]
+        if let Some((mode, trig_mode, enable)) = config.oversampling_mode {
+            T::regs().cfgr2().modify(|reg| reg.set_trovs(trig_mode));
+            T::regs().cfgr2().modify(|reg| reg.set_rovsm(mode));
+            T::regs().cfgr2().modify(|reg| reg.set_rovse(enable));
+        }
 
-            // On G0 and U0 enabled channels are sampled from 0 to last channel.
-            // It is possible to add up to 8 sequences if CHSELRMOD = 1.
-            // However for supporting more than 8 channels alternative CHSELRMOD = 0 approach is used.
-            #[cfg(adc_u0)]
-            T::regs().chselr().modify(|reg| {
-                reg.set_chsel(channel_mask);
-            });
+        if let Some(resolution) = config.resolution {
+            #[cfg(not(any(adc_g0, adc_u0)))]
+            T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
+            #[cfg(any(adc_g0, adc_u0))]
+            T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into()));
         }
-        // Set continuous mode with Circular dma.
-        // Clear overrun flag before starting transfer.
-        T::regs().isr().modify(|reg| {
-            reg.set_ovr(true);
-        });
 
-        #[cfg(not(any(adc_g0, adc_u0)))]
-        T::regs().cfgr().modify(|reg| {
-            reg.set_discen(false);
-            reg.set_cont(true);
-            reg.set_dmacfg(Dmacfg::CIRCULAR);
-            reg.set_dmaen(true);
-        });
-        #[cfg(any(adc_g0, adc_u0))]
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_discen(false);
-            reg.set_cont(true);
-            reg.set_dmacfg(Dmacfg::CIRCULAR);
-            reg.set_dmaen(true);
-        });
+        if let Some(averaging) = config.averaging {
+            let (enable, samples, right_shift) = match averaging {
+                Averaging::Disabled => (false, 0, 0),
+                Averaging::Samples2 => (true, 0, 1),
+                Averaging::Samples4 => (true, 1, 2),
+                Averaging::Samples8 => (true, 2, 3),
+                Averaging::Samples16 => (true, 3, 4),
+                Averaging::Samples32 => (true, 4, 5),
+                Averaging::Samples64 => (true, 5, 6),
+                Averaging::Samples128 => (true, 6, 7),
+                Averaging::Samples256 => (true, 7, 8),
+            };
+            T::regs().cfgr2().modify(|reg| {
+                #[cfg(not(any(adc_g0, adc_u0)))]
+                reg.set_rovse(enable);
+                #[cfg(any(adc_g0, adc_u0))]
+                reg.set_ovse(enable);
+                #[cfg(any(adc_h5, adc_h7rs))]
+                reg.set_ovsr(samples.into());
+                #[cfg(not(any(adc_h5, adc_h7rs)))]
+                reg.set_ovsr(samples.into());
+                reg.set_ovss(right_shift.into());
+            })
+        }
 
-        RingBufferedAdc::new(dma, dma_buf)
+        s
     }
 
-    #[cfg(not(adc_g0))]
-    fn configure_channel(channel: &mut impl AdcChannel<T>, sample_time: SampleTime) {
-        // RM0492, RM0481, etc.
-        // "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
-        #[cfg(any(adc_h5, adc_h7rs))]
-        if channel.channel() == 0 {
-            T::regs().or().modify(|reg| reg.set_op0(true));
+    #[cfg(adc_g0)]
+    /// Initialize ADC with explicit clock for the analog ADC
+    pub fn new_with_clock(adc: Peri<'d, T>, clock: Clock) -> Self {
+        Self::init_regulator();
+
+        #[cfg(any(stm32wl5x))]
+        {
+            // Reset value 0 is actually _No clock selected_ in the STM32WL5x reference manual
+            let async_clock_available = pac::RCC.ccipr().read().adcsel() != pac::rcc::vals::Adcsel::_RESERVED_0;
+            match clock {
+                Clock::Async { div: _ } => {
+                    assert!(async_clock_available);
+                }
+                Clock::Sync { div: _ } => {
+                    if async_clock_available {
+                        warn!("Not using configured ADC clock");
+                    }
+                }
+            }
+        }
+        match clock {
+            Clock::Async { div } => T::regs().ccr().modify(|reg| reg.set_presc(div)),
+            Clock::Sync { div } => T::regs().cfgr2().modify(|reg| {
+                reg.set_ckmode(match div {
+                    CkModePclk::DIV1 => Ckmode::PCLK,
+                    CkModePclk::DIV2 => Ckmode::PCLK_DIV2,
+                    CkModePclk::DIV4 => Ckmode::PCLK_DIV4,
+                })
+            }),
         }
 
-        // Configure channel
-        Self::set_channel_sample_time(channel.channel(), sample_time);
+        Self::init_calibrate();
+
+        Self { adc }
     }
 
-    fn read_channel(&mut self, channel: &mut impl AdcChannel<T>, sample_time: SampleTime) -> u16 {
-        self.enable();
-        #[cfg(not(adc_g0))]
-        Self::configure_channel(channel, sample_time);
-        #[cfg(adc_g0)]
-        T::regs().smpr().write(|reg| {
-            reg.set_sample_time(0, sample_time);
-            reg.set_smpsel(channel.channel().into(), Smpsel::SMP1);
-        });
-        // Select channel
+    pub fn enable_vrefint(&self) -> VrefInt {
         #[cfg(not(any(adc_g0, adc_u0)))]
-        T::regs().sqr1().write(|reg| reg.set_sq(0, channel.channel()));
+        T::common_regs().ccr().modify(|reg| {
+            reg.set_vrefen(true);
+        });
         #[cfg(any(adc_g0, adc_u0))]
-        T::regs().chselr().write(|reg| {
-            #[cfg(adc_g0)]
-            reg.set_chsel(channel.channel().into(), true);
-            #[cfg(adc_u0)]
-            reg.set_chsel(1 << channel.channel());
+        T::regs().ccr().modify(|reg| {
+            reg.set_vrefen(true);
         });
 
-        // Some models are affected by an erratum:
-        // If we perform conversions slower than 1 kHz, the first read ADC value can be
-        // corrupted, so we discard it and measure again.
-        //
-        // STM32L471xx: Section 2.7.3
-        // STM32G4: Section 2.7.3
-        #[cfg(any(rcc_l4, rcc_g4))]
-        let _ = self.convert();
-        let val = self.convert();
-
-        T::regs().cr().modify(|reg| reg.set_addis(true));
-
-        // RM0492, RM0481, etc.
-        // "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
-        #[cfg(any(adc_h5, adc_h7rs))]
-        if channel.channel() == 0 {
-            T::regs().or().modify(|reg| reg.set_op0(false));
-        }
-
-        val
-    }
-
-    #[cfg(adc_g0)]
-    pub fn set_oversampling_shift(&mut self, shift: Ovss) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
-    }
-    #[cfg(adc_u0)]
-    pub fn set_oversampling_shift(&mut self, shift: u8) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
-    }
+        // "Table 24. Embedded internal voltage reference" states that it takes a maximum of 12 us
+        // to stabilize the internal voltage reference.
+        blocking_delay_us(15);
 
-    #[cfg(adc_g0)]
-    pub fn set_oversampling_ratio(&mut self, ratio: Ovsr) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
-    }
-    #[cfg(adc_u0)]
-    pub fn set_oversampling_ratio(&mut self, ratio: u8) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
+        VrefInt {}
     }
 
-    #[cfg(any(adc_g0, adc_u0))]
-    pub fn oversampling_enable(&mut self, enable: bool) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovse(enable));
-    }
+    pub fn enable_temperature(&self) -> Temperature {
+        cfg_if! {
+            if #[cfg(any(adc_g0, adc_u0))] {
+                T::regs().ccr().modify(|reg| {
+                    reg.set_tsen(true);
+                });
+            } else if #[cfg(any(adc_h5, adc_h7rs))] {
+                T::common_regs().ccr().modify(|reg| {
+                    reg.set_tsen(true);
+                });
+            } else {
+                T::common_regs().ccr().modify(|reg| {
+                    reg.set_ch17sel(true);
+                });
+            }
+        }
 
-    #[cfg(adc_v3)]
-    pub fn enable_regular_oversampling_mode(&mut self, mode: Rovsm, trig_mode: Trovs, enable: bool) {
-        T::regs().cfgr2().modify(|reg| reg.set_trovs(trig_mode));
-        T::regs().cfgr2().modify(|reg| reg.set_rovsm(mode));
-        T::regs().cfgr2().modify(|reg| reg.set_rovse(enable));
+        Temperature {}
     }
 
-    #[cfg(adc_v3)]
-    pub fn set_oversampling_ratio(&mut self, ratio: OversamplingRatio) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
-    }
+    pub fn enable_vbat(&self) -> Vbat {
+        cfg_if! {
+            if #[cfg(any(adc_g0, adc_u0))] {
+                T::regs().ccr().modify(|reg| {
+                    reg.set_vbaten(true);
+                });
+            } else if #[cfg(any(adc_h5, adc_h7rs))] {
+                T::common_regs().ccr().modify(|reg| {
+                    reg.set_vbaten(true);
+                });
+            } else {
+                T::common_regs().ccr().modify(|reg| {
+                    reg.set_ch18sel(true);
+                });
+            }
+        }
 
-    #[cfg(adc_v3)]
-    pub fn set_oversampling_shift(&mut self, shift: OversamplingShift) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
+        Vbat {}
     }
 
-    #[cfg(not(adc_g0))]
-    fn set_channel_sample_time(_ch: u8, sample_time: SampleTime) {
+    pub fn disable_vbat(&self) {
         cfg_if! {
-            if #[cfg(adc_u0)] {
-                // On G0 and U6 all channels use the same sampling time.
-                T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into()));
+            if #[cfg(any(adc_g0, adc_u0))] {
+                T::regs().ccr().modify(|reg| {
+                    reg.set_vbaten(false);
+                });
             } else if #[cfg(any(adc_h5, adc_h7rs))] {
-                match _ch {
-                    0..=9 => T::regs().smpr1().modify(|w| w.set_smp(_ch as usize % 10, sample_time.into())),
-                    _ => T::regs().smpr2().modify(|w| w.set_smp(_ch as usize % 10, sample_time.into())),
-                }
+                T::common_regs().ccr().modify(|reg| {
+                    reg.set_vbaten(false);
+                });
             } else {
-                let sample_time = sample_time.into();
-                T::regs()
-                    .smpr(_ch as usize / 10)
-                    .modify(|reg| reg.set_smp(_ch as usize % 10, sample_time));
+                T::common_regs().ccr().modify(|reg| {
+                    reg.set_ch18sel(false);
+                });
             }
         }
     }
 
-    fn cancel_conversions() {
-        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
-            T::regs().cr().modify(|reg| {
-                reg.set_adstp(true);
-            });
-            while T::regs().cr().read().adstart() {}
-        }
+    /*
+    /// Convert a raw sample from the `Temperature` to deg C
+    pub fn to_degrees_centigrade(sample: u16) -> f32 {
+        (130.0 - 30.0) / (VtempCal130::get().read() as f32 - VtempCal30::get().read() as f32)
+            * (sample as f32 - VtempCal30::get().read() as f32)
+            + 30.0
     }
+     */
 }
diff --git a/embassy-stm32/src/adc/v4.rs b/embassy-stm32/src/adc/v4.rs
index 1d5d3fb92..a3d9e6176 100644
--- a/embassy-stm32/src/adc/v4.rs
+++ b/embassy-stm32/src/adc/v4.rs
@@ -4,11 +4,8 @@ use pac::adc::vals::{Adcaldif, Boost};
 use pac::adc::vals::{Adstp, Difsel, Dmngt, Exten, Pcsel};
 use pac::adccommon::vals::Presc;
 
-use super::{
-    Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel, Temperature, Vbat,
-    VrefInt, blocking_delay_us,
-};
-use crate::dma::Transfer;
+use super::{Adc, Averaging, Instance, Resolution, SampleTime, Temperature, Vbat, VrefInt, blocking_delay_us};
+use crate::adc::ConversionMode;
 use crate::time::Hertz;
 use crate::{Peri, pac, rcc};
 
@@ -62,101 +59,191 @@ impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
     const CHANNEL: u8 = 18;
 }
 
-// NOTE (unused): The prescaler enum closely copies the hardware capabilities,
-// but high prescaling doesn't make a lot of sense in the current implementation and is ommited.
-#[allow(unused)]
-enum Prescaler {
-    NotDivided,
-    DividedBy2,
-    DividedBy4,
-    DividedBy6,
-    DividedBy8,
-    DividedBy10,
-    DividedBy12,
-    DividedBy16,
-    DividedBy32,
-    DividedBy64,
-    DividedBy128,
-    DividedBy256,
+fn from_ker_ck(frequency: Hertz) -> Presc {
+    let raw_prescaler = rcc::raw_prescaler(frequency.0, MAX_ADC_CLK_FREQ.0);
+    match raw_prescaler {
+        0 => Presc::DIV1,
+        1 => Presc::DIV2,
+        2..=3 => Presc::DIV4,
+        4..=5 => Presc::DIV6,
+        6..=7 => Presc::DIV8,
+        8..=9 => Presc::DIV10,
+        10..=11 => Presc::DIV12,
+        _ => unimplemented!(),
+    }
+}
+
+/// Adc configuration
+#[derive(Default)]
+pub struct AdcConfig {
+    pub resolution: Option<Resolution>,
+    pub averaging: Option<Averaging>,
 }
 
-impl Prescaler {
-    fn from_ker_ck(frequency: Hertz) -> Self {
-        let raw_prescaler = frequency.0 / MAX_ADC_CLK_FREQ.0;
-        match raw_prescaler {
-            0 => Self::NotDivided,
-            1 => Self::DividedBy2,
-            2..=3 => Self::DividedBy4,
-            4..=5 => Self::DividedBy6,
-            6..=7 => Self::DividedBy8,
-            8..=9 => Self::DividedBy10,
-            10..=11 => Self::DividedBy12,
-            _ => unimplemented!(),
+impl<T: Instance> super::SealedAnyInstance for T {
+    fn dr() -> *mut u16 {
+        T::regs().dr().as_ptr() as *mut u16
+    }
+
+    fn enable() {
+        T::regs().isr().write(|w| w.set_adrdy(true));
+        T::regs().cr().modify(|w| w.set_aden(true));
+        while !T::regs().isr().read().adrdy() {}
+        T::regs().isr().write(|w| w.set_adrdy(true));
+    }
+
+    fn start() {
+        // Start conversion
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
+    }
+
+    fn stop() {
+        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
+            T::regs().cr().modify(|reg| {
+                reg.set_adstp(Adstp::STOP);
+            });
+            while T::regs().cr().read().adstart() {}
         }
+
+        // Reset configuration.
+        T::regs().cfgr().modify(|reg| {
+            reg.set_cont(false);
+            reg.set_dmngt(Dmngt::from_bits(0));
+        });
     }
 
-    fn divisor(&self) -> u32 {
-        match self {
-            Prescaler::NotDivided => 1,
-            Prescaler::DividedBy2 => 2,
-            Prescaler::DividedBy4 => 4,
-            Prescaler::DividedBy6 => 6,
-            Prescaler::DividedBy8 => 8,
-            Prescaler::DividedBy10 => 10,
-            Prescaler::DividedBy12 => 12,
-            Prescaler::DividedBy16 => 16,
-            Prescaler::DividedBy32 => 32,
-            Prescaler::DividedBy64 => 64,
-            Prescaler::DividedBy128 => 128,
-            Prescaler::DividedBy256 => 256,
+    fn convert() -> u16 {
+        T::regs().isr().modify(|reg| {
+            reg.set_eos(true);
+            reg.set_eoc(true);
+        });
+
+        // Start conversion
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
+
+        while !T::regs().isr().read().eos() {
+            // spin
         }
+
+        T::regs().dr().read().0 as u16
     }
 
-    fn presc(&self) -> Presc {
-        match self {
-            Prescaler::NotDivided => Presc::DIV1,
-            Prescaler::DividedBy2 => Presc::DIV2,
-            Prescaler::DividedBy4 => Presc::DIV4,
-            Prescaler::DividedBy6 => Presc::DIV6,
-            Prescaler::DividedBy8 => Presc::DIV8,
-            Prescaler::DividedBy10 => Presc::DIV10,
-            Prescaler::DividedBy12 => Presc::DIV12,
-            Prescaler::DividedBy16 => Presc::DIV16,
-            Prescaler::DividedBy32 => Presc::DIV32,
-            Prescaler::DividedBy64 => Presc::DIV64,
-            Prescaler::DividedBy128 => Presc::DIV128,
-            Prescaler::DividedBy256 => Presc::DIV256,
+    fn configure_dma(conversion_mode: ConversionMode) {
+        match conversion_mode {
+            ConversionMode::Singular => {
+                T::regs().isr().modify(|reg| {
+                    reg.set_ovr(true);
+                });
+                T::regs().cfgr().modify(|reg| {
+                    reg.set_cont(true);
+                    reg.set_dmngt(Dmngt::DMA_ONE_SHOT);
+                });
+            }
+            #[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
+            _ => unreachable!(),
         }
     }
-}
 
-/// Number of samples used for averaging.
-#[derive(Copy, Clone, Debug)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Averaging {
-    Disabled,
-    Samples2,
-    Samples4,
-    Samples8,
-    Samples16,
-    Samples32,
-    Samples64,
-    Samples128,
-    Samples256,
-    Samples512,
-    Samples1024,
+    fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
+        // Set sequence length
+        T::regs().sqr1().modify(|w| {
+            w.set_l(sequence.len() as u8 - 1);
+        });
+
+        // Configure channels and ranks
+        for (i, ((channel, _), sample_time)) in sequence.enumerate() {
+            let sample_time = sample_time.into();
+            if channel <= 9 {
+                T::regs().smpr(0).modify(|reg| reg.set_smp(channel as _, sample_time));
+            } else {
+                T::regs()
+                    .smpr(1)
+                    .modify(|reg| reg.set_smp((channel - 10) as _, sample_time));
+            }
+
+            #[cfg(any(stm32h7, stm32u5))]
+            {
+                T::regs().cfgr2().modify(|w| w.set_lshift(0));
+                T::regs()
+                    .pcsel()
+                    .modify(|w| w.set_pcsel(channel as _, Pcsel::PRESELECTED));
+            }
+
+            match i {
+                0..=3 => {
+                    T::regs().sqr1().modify(|w| {
+                        w.set_sq(i, channel);
+                    });
+                }
+                4..=8 => {
+                    T::regs().sqr2().modify(|w| {
+                        w.set_sq(i - 4, channel);
+                    });
+                }
+                9..=13 => {
+                    T::regs().sqr3().modify(|w| {
+                        w.set_sq(i - 9, channel);
+                    });
+                }
+                14..=15 => {
+                    T::regs().sqr4().modify(|w| {
+                        w.set_sq(i - 14, channel);
+                    });
+                }
+                _ => unreachable!(),
+            }
+        }
+    }
 }
 
-impl<'d, T: Instance> Adc<'d, T> {
+impl<'d, T: Instance + super::AnyInstance> Adc<'d, T> {
+    pub fn new_with_config(adc: Peri<'d, T>, config: AdcConfig) -> Self {
+        let s = Self::new(adc);
+
+        // Set the ADC resolution.
+        if let Some(resolution) = config.resolution {
+            T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
+        }
+
+        // Set hardware averaging.
+        if let Some(averaging) = config.averaging {
+            let (enable, samples, right_shift) = match averaging {
+                Averaging::Disabled => (false, 0, 0),
+                Averaging::Samples2 => (true, 1, 1),
+                Averaging::Samples4 => (true, 3, 2),
+                Averaging::Samples8 => (true, 7, 3),
+                Averaging::Samples16 => (true, 15, 4),
+                Averaging::Samples32 => (true, 31, 5),
+                Averaging::Samples64 => (true, 63, 6),
+                Averaging::Samples128 => (true, 127, 7),
+                Averaging::Samples256 => (true, 255, 8),
+                Averaging::Samples512 => (true, 511, 9),
+                Averaging::Samples1024 => (true, 1023, 10),
+            };
+
+            T::regs().cfgr2().modify(|reg| {
+                reg.set_rovse(enable);
+                reg.set_ovsr(samples);
+                reg.set_ovss(right_shift);
+            })
+        }
+
+        s
+    }
+
     /// Create a new ADC driver.
     pub fn new(adc: Peri<'d, T>) -> Self {
         rcc::enable_and_reset::<T>();
 
-        let prescaler = Prescaler::from_ker_ck(T::frequency());
+        let prescaler = from_ker_ck(T::frequency());
 
-        T::common_regs().ccr().modify(|w| w.set_presc(prescaler.presc()));
+        T::common_regs().ccr().modify(|w| w.set_presc(prescaler));
 
-        let frequency = Hertz(T::frequency().0 / prescaler.divisor());
+        let frequency = T::frequency() / prescaler;
         info!("ADC frequency set to {}", frequency);
 
         if frequency > MAX_ADC_CLK_FREQ {
@@ -179,37 +266,20 @@ impl<'d, T: Instance> Adc<'d, T> {
             };
             T::regs().cr().modify(|w| w.set_boost(boost));
         }
-        let mut s = Self { adc };
-        s.power_up();
-        s.configure_differential_inputs();
 
-        s.calibrate();
-        blocking_delay_us(1);
-
-        s.enable();
-        s.configure();
-
-        s
-    }
-
-    fn power_up(&mut self) {
         T::regs().cr().modify(|reg| {
             reg.set_deeppwd(false);
             reg.set_advregen(true);
         });
 
         blocking_delay_us(10);
-    }
 
-    fn configure_differential_inputs(&mut self) {
         T::regs().difsel().modify(|w| {
             for n in 0..20 {
                 w.set_difsel(n, Difsel::SINGLE_ENDED);
             }
         });
-    }
 
-    fn calibrate(&mut self) {
         T::regs().cr().modify(|w| {
             #[cfg(not(adc_u5))]
             w.set_adcaldif(Adcaldif::SINGLE_ENDED);
@@ -219,21 +289,18 @@ impl<'d, T: Instance> Adc<'d, T> {
         T::regs().cr().modify(|w| w.set_adcal(true));
 
         while T::regs().cr().read().adcal() {}
-    }
 
-    fn enable(&mut self) {
-        T::regs().isr().write(|w| w.set_adrdy(true));
-        T::regs().cr().modify(|w| w.set_aden(true));
-        while !T::regs().isr().read().adrdy() {}
-        T::regs().isr().write(|w| w.set_adrdy(true));
-    }
+        blocking_delay_us(1);
+
+        T::enable();
 
-    fn configure(&mut self) {
         // single conversion mode, software trigger
         T::regs().cfgr().modify(|w| {
             w.set_cont(false);
             w.set_exten(Exten::DISABLED);
         });
+
+        Self { adc }
     }
 
     /// Enable reading the voltage reference internal channel.
@@ -262,218 +329,4 @@ impl<'d, T: Instance> Adc<'d, T> {
 
         Vbat {}
     }
-
-    /// Set the ADC resolution.
-    pub fn set_resolution(&mut self, resolution: Resolution) {
-        T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
-    }
-
-    /// Set hardware averaging.
-    pub fn set_averaging(&mut self, averaging: Averaging) {
-        let (enable, samples, right_shift) = match averaging {
-            Averaging::Disabled => (false, 0, 0),
-            Averaging::Samples2 => (true, 1, 1),
-            Averaging::Samples4 => (true, 3, 2),
-            Averaging::Samples8 => (true, 7, 3),
-            Averaging::Samples16 => (true, 15, 4),
-            Averaging::Samples32 => (true, 31, 5),
-            Averaging::Samples64 => (true, 63, 6),
-            Averaging::Samples128 => (true, 127, 7),
-            Averaging::Samples256 => (true, 255, 8),
-            Averaging::Samples512 => (true, 511, 9),
-            Averaging::Samples1024 => (true, 1023, 10),
-        };
-
-        T::regs().cfgr2().modify(|reg| {
-            reg.set_rovse(enable);
-            reg.set_ovsr(samples);
-            reg.set_ovss(right_shift);
-        })
-    }
-
-    /// Perform a single conversion.
-    fn convert(&mut self) -> u16 {
-        T::regs().isr().modify(|reg| {
-            reg.set_eos(true);
-            reg.set_eoc(true);
-        });
-
-        // Start conversion
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
-        });
-
-        while !T::regs().isr().read().eos() {
-            // spin
-        }
-
-        T::regs().dr().read().0 as u16
-    }
-
-    /// Read an ADC channel.
-    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>, sample_time: SampleTime) -> u16 {
-        self.read_channel(channel, sample_time)
-    }
-
-    /// Read one or multiple ADC channels using DMA.
-    ///
-    /// `sequence` iterator and `readings` must have the same length.
-    ///
-    /// Example
-    /// ```rust,ignore
-    /// use embassy_stm32::adc::{Adc, AdcChannel}
-    ///
-    /// let mut adc = Adc::new(p.ADC1);
-    /// let mut adc_pin0 = p.PA0.into();
-    /// let mut adc_pin2 = p.PA2.into();
-    /// let mut measurements = [0u16; 2];
-    ///
-    /// adc.read(
-    ///     p.DMA2_CH0.reborrow(),
-    ///     [
-    ///         (&mut *adc_pin0, SampleTime::CYCLES112),
-    ///         (&mut *adc_pin2, SampleTime::CYCLES112),
-    ///     ]
-    ///     .into_iter(),
-    ///     &mut measurements,
-    /// )
-    /// .await;
-    /// defmt::info!("measurements: {}", measurements);
-    /// ```
-    pub async fn read(
-        &mut self,
-        rx_dma: Peri<'_, impl RxDma<T>>,
-        sequence: impl ExactSizeIterator<Item = (&mut AnyAdcChannel<T>, SampleTime)>,
-        readings: &mut [u16],
-    ) {
-        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
-        assert!(
-            sequence.len() == readings.len(),
-            "Sequence length must be equal to readings length"
-        );
-        assert!(
-            sequence.len() <= 16,
-            "Asynchronous read sequence cannot be more than 16 in length"
-        );
-
-        // Ensure no conversions are ongoing
-        Self::cancel_conversions();
-
-        // Set sequence length
-        T::regs().sqr1().modify(|w| {
-            w.set_l(sequence.len() as u8 - 1);
-        });
-
-        // Configure channels and ranks
-        for (i, (channel, sample_time)) in sequence.enumerate() {
-            Self::configure_channel(channel, sample_time);
-            match i {
-                0..=3 => {
-                    T::regs().sqr1().modify(|w| {
-                        w.set_sq(i, channel.channel());
-                    });
-                }
-                4..=8 => {
-                    T::regs().sqr2().modify(|w| {
-                        w.set_sq(i - 4, channel.channel());
-                    });
-                }
-                9..=13 => {
-                    T::regs().sqr3().modify(|w| {
-                        w.set_sq(i - 9, channel.channel());
-                    });
-                }
-                14..=15 => {
-                    T::regs().sqr4().modify(|w| {
-                        w.set_sq(i - 14, channel.channel());
-                    });
-                }
-                _ => unreachable!(),
-            }
-        }
-
-        // Set continuous mode with oneshot dma.
-        // Clear overrun flag before starting transfer.
-
-        T::regs().isr().modify(|reg| {
-            reg.set_ovr(true);
-        });
-        T::regs().cfgr().modify(|reg| {
-            reg.set_cont(true);
-            reg.set_dmngt(Dmngt::DMA_ONE_SHOT);
-        });
-
-        let request = rx_dma.request();
-        let transfer = unsafe {
-            Transfer::new_read(
-                rx_dma,
-                request,
-                T::regs().dr().as_ptr() as *mut u16,
-                readings,
-                Default::default(),
-            )
-        };
-
-        // Start conversion
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
-        });
-
-        // Wait for conversion sequence to finish.
-        transfer.await;
-
-        // Ensure conversions are finished.
-        Self::cancel_conversions();
-
-        // Reset configuration.
-        T::regs().cfgr().modify(|reg| {
-            reg.set_cont(false);
-            reg.set_dmngt(Dmngt::from_bits(0));
-        });
-    }
-
-    fn configure_channel(channel: &mut impl AdcChannel<T>, sample_time: SampleTime) {
-        channel.setup();
-
-        let channel = channel.channel();
-
-        Self::set_channel_sample_time(channel, sample_time);
-
-        #[cfg(any(stm32h7, stm32u5))]
-        {
-            T::regs().cfgr2().modify(|w| w.set_lshift(0));
-            T::regs()
-                .pcsel()
-                .modify(|w| w.set_pcsel(channel as _, Pcsel::PRESELECTED));
-        }
-    }
-
-    fn read_channel(&mut self, channel: &mut impl AdcChannel<T>, sample_time: SampleTime) -> u16 {
-        Self::configure_channel(channel, sample_time);
-
-        T::regs().sqr1().modify(|reg| {
-            reg.set_sq(0, channel.channel());
-            reg.set_l(0);
-        });
-
-        self.convert()
-    }
-
-    fn set_channel_sample_time(ch: u8, sample_time: SampleTime) {
-        let sample_time = sample_time.into();
-        if ch <= 9 {
-            T::regs().smpr(0).modify(|reg| reg.set_smp(ch as _, sample_time));
-        } else {
-            T::regs().smpr(1).modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
-        }
-    }
-
-    fn cancel_conversions() {
-        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
-            T::regs().cr().modify(|reg| {
-                reg.set_adstp(Adstp::STOP);
-            });
-            while T::regs().cr().read().adstart() {}
-        }
-    }
 }
diff --git a/embassy-stm32/src/dma/dma_bdma.rs b/embassy-stm32/src/dma/dma_bdma.rs
index 90dbf4f09..b46ae2813 100644
--- a/embassy-stm32/src/dma/dma_bdma.rs
+++ b/embassy-stm32/src/dma/dma_bdma.rs
@@ -8,7 +8,7 @@ use embassy_sync::waitqueue::AtomicWaker;
 
 use super::ringbuffer::{DmaCtrl, Error, ReadableDmaRingBuffer, WritableDmaRingBuffer};
 use super::word::{Word, WordSize};
-use super::{AnyChannel, Channel, Dir, Request, STATE};
+use super::{AnyChannel, BusyChannel, Channel, Dir, Request, STATE};
 use crate::interrupt::typelevel::Interrupt;
 use crate::{interrupt, pac};
 
@@ -602,7 +602,7 @@ impl AnyChannel {
 /// DMA transfer.
 #[must_use = "futures do nothing unless you `.await` or poll them"]
 pub struct Transfer<'a> {
-    channel: Peri<'a, AnyChannel>,
+    channel: BusyChannel<'a>,
 }
 
 impl<'a> Transfer<'a> {
@@ -713,7 +713,9 @@ impl<'a> Transfer<'a> {
             _request, dir, peri_addr, mem_addr, mem_len, incr_mem, mem_size, peri_size, options,
         );
         channel.start();
-        Self { channel }
+        Self {
+            channel: BusyChannel::new(channel),
+        }
     }
 
     /// Request the transfer to pause, keeping the existing configuration for this channel.
@@ -816,7 +818,7 @@ impl<'a> DmaCtrl for DmaCtrlImpl<'a> {
 
 /// Ringbuffer for receiving data using DMA circular mode.
 pub struct ReadableRingBuffer<'a, W: Word> {
-    channel: Peri<'a, AnyChannel>,
+    channel: BusyChannel<'a>,
     ringbuf: ReadableDmaRingBuffer<'a, W>,
 }
 
@@ -853,7 +855,7 @@ impl<'a, W: Word> ReadableRingBuffer<'a, W> {
         );
 
         Self {
-            channel,
+            channel: BusyChannel::new(channel),
             ringbuf: ReadableDmaRingBuffer::new(buffer),
         }
     }
@@ -972,7 +974,7 @@ impl<'a, W: Word> Drop for ReadableRingBuffer<'a, W> {
 
 /// Ringbuffer for writing data using DMA circular mode.
 pub struct WritableRingBuffer<'a, W: Word> {
-    channel: Peri<'a, AnyChannel>,
+    channel: BusyChannel<'a>,
     ringbuf: WritableDmaRingBuffer<'a, W>,
 }
 
@@ -1009,7 +1011,7 @@ impl<'a, W: Word> WritableRingBuffer<'a, W> {
         );
 
         Self {
-            channel,
+            channel: BusyChannel::new(channel),
             ringbuf: WritableDmaRingBuffer::new(buffer),
         }
     }
diff --git a/embassy-stm32/src/dma/gpdma/mod.rs b/embassy-stm32/src/dma/gpdma/mod.rs
index 106558d20..383c74a78 100644
--- a/embassy-stm32/src/dma/gpdma/mod.rs
+++ b/embassy-stm32/src/dma/gpdma/mod.rs
@@ -11,6 +11,7 @@ use linked_list::Table;
 
 use super::word::{Word, WordSize};
 use super::{AnyChannel, Channel, Dir, Request, STATE};
+use crate::dma::BusyChannel;
 use crate::interrupt::typelevel::Interrupt;
 use crate::pac;
 use crate::pac::gpdma::vals;
@@ -408,7 +409,7 @@ impl AnyChannel {
 /// Linked-list DMA transfer.
 #[must_use = "futures do nothing unless you `.await` or poll them"]
 pub struct LinkedListTransfer<'a, const ITEM_COUNT: usize> {
-    channel: Peri<'a, AnyChannel>,
+    channel: BusyChannel<'a>,
 }
 
 impl<'a, const ITEM_COUNT: usize> LinkedListTransfer<'a, ITEM_COUNT> {
@@ -429,7 +430,9 @@ impl<'a, const ITEM_COUNT: usize> LinkedListTransfer<'a, ITEM_COUNT> {
         channel.configure_linked_list(&table, options);
         channel.start();
 
-        Self { channel }
+        Self {
+            channel: BusyChannel::new(channel),
+        }
     }
 
     /// Request the transfer to pause, keeping the existing configuration for this channel.
@@ -505,7 +508,7 @@ impl<'a, const ITEM_COUNT: usize> Future for LinkedListTransfer<'a, ITEM_COUNT>
 /// DMA transfer.
 #[must_use = "futures do nothing unless you `.await` or poll them"]
 pub struct Transfer<'a> {
-    channel: Peri<'a, AnyChannel>,
+    channel: BusyChannel<'a>,
 }
 
 impl<'a> Transfer<'a> {
@@ -625,7 +628,9 @@ impl<'a> Transfer<'a> {
         );
         channel.start();
 
-        Self { channel }
+        Self {
+            channel: BusyChannel::new(channel),
+        }
     }
 
     /// Request the transfer to pause, keeping the existing configuration for this channel.
diff --git a/embassy-stm32/src/dma/gpdma/ringbuffered.rs b/embassy-stm32/src/dma/gpdma/ringbuffered.rs
index 94c597e0d..54e4d5f71 100644
--- a/embassy-stm32/src/dma/gpdma/ringbuffered.rs
+++ b/embassy-stm32/src/dma/gpdma/ringbuffered.rs
@@ -12,7 +12,7 @@ use super::{AnyChannel, STATE, TransferOptions};
 use crate::dma::gpdma::linked_list::{RunMode, Table};
 use crate::dma::ringbuffer::{DmaCtrl, Error, ReadableDmaRingBuffer, WritableDmaRingBuffer};
 use crate::dma::word::Word;
-use crate::dma::{Channel, Dir, Request};
+use crate::dma::{BusyChannel, Channel, Dir, Request};
 
 struct DmaCtrlImpl<'a>(Peri<'a, AnyChannel>);
 
@@ -49,7 +49,7 @@ impl<'a> DmaCtrl for DmaCtrlImpl<'a> {
 
 /// Ringbuffer for receiving data using GPDMA linked-list mode.
 pub struct ReadableRingBuffer<'a, W: Word> {
-    channel: Peri<'a, AnyChannel>,
+    channel: BusyChannel<'a>,
     ringbuf: ReadableDmaRingBuffer<'a, W>,
     table: Table<2>,
     options: TransferOptions,
@@ -70,7 +70,7 @@ impl<'a, W: Word> ReadableRingBuffer<'a, W> {
         let table = Table::<2>::new_ping_pong::<W>(request, peri_addr, buffer, Dir::PeripheralToMemory);
 
         Self {
-            channel,
+            channel: BusyChannel::new(channel),
             ringbuf: ReadableDmaRingBuffer::new(buffer),
             table,
             options,
@@ -189,7 +189,7 @@ impl<'a, W: Word> Drop for ReadableRingBuffer<'a, W> {
 
 /// Ringbuffer for writing data using GPDMA linked-list mode.
 pub struct WritableRingBuffer<'a, W: Word> {
-    channel: Peri<'a, AnyChannel>,
+    channel: BusyChannel<'a>,
     ringbuf: WritableDmaRingBuffer<'a, W>,
     table: Table<2>,
     options: TransferOptions,
@@ -210,7 +210,7 @@ impl<'a, W: Word> WritableRingBuffer<'a, W> {
         let table = Table::<2>::new_ping_pong::<W>(request, peri_addr, buffer, Dir::MemoryToPeripheral);
 
         Self {
-            channel,
+            channel: BusyChannel::new(channel),
             ringbuf: WritableDmaRingBuffer::new(buffer),
             table,
             options,
diff --git a/embassy-stm32/src/dma/mod.rs b/embassy-stm32/src/dma/mod.rs
index de7a2c175..4becc2d87 100644
--- a/embassy-stm32/src/dma/mod.rs
+++ b/embassy-stm32/src/dma/mod.rs
@@ -3,11 +3,14 @@
 
 #[cfg(any(bdma, dma))]
 mod dma_bdma;
+use core::ops;
+
 #[cfg(any(bdma, dma))]
 pub use dma_bdma::*;
 
 #[cfg(gpdma)]
 pub(crate) mod gpdma;
+use embassy_hal_internal::Peri;
 #[cfg(gpdma)]
 pub use gpdma::ringbuffered::*;
 #[cfg(gpdma)]
@@ -48,6 +51,8 @@ pub type Request = ();
 pub(crate) trait SealedChannel {
     #[cfg(not(stm32n6))]
     fn id(&self) -> u8;
+    #[cfg(feature = "low-power")]
+    fn stop_mode(&self) -> crate::rcc::StopMode;
 }
 
 #[cfg(not(stm32n6))]
@@ -62,15 +67,25 @@ pub trait Channel: SealedChannel + PeripheralType + Into<AnyChannel> + 'static {
 
 #[cfg(not(stm32n6))]
 macro_rules! dma_channel_impl {
-    ($channel_peri:ident, $index:expr) => {
+    ($channel_peri:ident, $index:expr, $stop_mode:ident) => {
         impl crate::dma::SealedChannel for crate::peripherals::$channel_peri {
             fn id(&self) -> u8 {
                 $index
             }
+
+            #[cfg(feature = "low-power")]
+            fn stop_mode(&self) -> crate::rcc::StopMode {
+                crate::rcc::StopMode::$stop_mode
+            }
         }
         impl crate::dma::ChannelInterrupt for crate::peripherals::$channel_peri {
             unsafe fn on_irq() {
-                crate::dma::AnyChannel { id: $index }.on_irq();
+                crate::dma::AnyChannel {
+                    id: $index,
+                    #[cfg(feature = "low-power")]
+                    stop_mode: crate::rcc::StopMode::$stop_mode,
+                }
+                .on_irq();
             }
         }
 
@@ -80,15 +95,57 @@ macro_rules! dma_channel_impl {
             fn from(val: crate::peripherals::$channel_peri) -> Self {
                 Self {
                     id: crate::dma::SealedChannel::id(&val),
+                    #[cfg(feature = "low-power")]
+                    stop_mode: crate::dma::SealedChannel::stop_mode(&val),
                 }
             }
         }
     };
 }
 
+pub(crate) struct BusyChannel<'a> {
+    channel: Peri<'a, AnyChannel>,
+}
+
+impl<'a> BusyChannel<'a> {
+    pub fn new(channel: Peri<'a, AnyChannel>) -> Self {
+        #[cfg(feature = "low-power")]
+        critical_section::with(|cs| {
+            crate::rcc::increment_stop_refcount(cs, channel.stop_mode);
+        });
+
+        Self { channel }
+    }
+}
+
+impl<'a> Drop for BusyChannel<'a> {
+    fn drop(&mut self) {
+        #[cfg(feature = "low-power")]
+        critical_section::with(|cs| {
+            crate::rcc::decrement_stop_refcount(cs, self.stop_mode);
+        });
+    }
+}
+
+impl<'a> ops::Deref for BusyChannel<'a> {
+    type Target = Peri<'a, AnyChannel>;
+
+    fn deref(&self) -> &Self::Target {
+        &self.channel
+    }
+}
+
+impl<'a> ops::DerefMut for BusyChannel<'a> {
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.channel
+    }
+}
+
 /// Type-erased DMA channel.
 pub struct AnyChannel {
     pub(crate) id: u8,
+    #[cfg(feature = "low-power")]
+    pub(crate) stop_mode: crate::rcc::StopMode,
 }
 impl_peripheral!(AnyChannel);
 
@@ -103,6 +160,11 @@ impl SealedChannel for AnyChannel {
     fn id(&self) -> u8 {
         self.id
     }
+
+    #[cfg(feature = "low-power")]
+    fn stop_mode(&self) -> crate::rcc::StopMode {
+        self.stop_mode
+    }
 }
 impl Channel for AnyChannel {}
 
diff --git a/embassy-stm32/src/dsihost.rs b/embassy-stm32/src/dsihost.rs
index 59a2cbcdb..b8945820c 100644
--- a/embassy-stm32/src/dsihost.rs
+++ b/embassy-stm32/src/dsihost.rs
@@ -5,18 +5,11 @@ use core::marker::PhantomData;
 use embassy_hal_internal::PeripheralType;
 
 //use crate::gpio::{AnyPin, SealedPin};
+use crate::block_for_us;
 use crate::gpio::{AfType, AnyPin, OutputType, Speed};
 use crate::rcc::{self, RccPeripheral};
 use crate::{Peri, peripherals};
 
-/// Performs a busy-wait delay for a specified number of microseconds.
-pub fn blocking_delay_ms(ms: u32) {
-    #[cfg(feature = "time")]
-    embassy_time::block_for(embassy_time::Duration::from_millis(ms as u64));
-    #[cfg(not(feature = "time"))]
-    cortex_m::asm::delay(unsafe { crate::rcc::get_freqs() }.sys.to_hertz().unwrap().0 / 1_000 * ms);
-}
-
 /// PacketTypes extracted from CubeMX
 #[repr(u8)]
 #[allow(dead_code)]
@@ -334,7 +327,7 @@ impl<'d, T: Instance> DsiHost<'d, T> {
             if T::regs().gpsr().read().cmdfe() {
                 return Ok(());
             }
-            blocking_delay_ms(1);
+            block_for_us(1_000);
         }
         Err(Error::FifoTimeout)
     }
@@ -345,7 +338,7 @@ impl<'d, T: Instance> DsiHost<'d, T> {
             if !T::regs().gpsr().read().cmdff() {
                 return Ok(());
             }
-            blocking_delay_ms(1);
+            block_for_us(1_000);
         }
         Err(Error::FifoTimeout)
     }
@@ -356,7 +349,7 @@ impl<'d, T: Instance> DsiHost<'d, T> {
             if !self.read_busy() {
                 return Ok(());
             }
-            blocking_delay_ms(1);
+            block_for_us(1_000);
         }
         Err(Error::ReadTimeout)
     }
@@ -367,7 +360,7 @@ impl<'d, T: Instance> DsiHost<'d, T> {
             if !T::regs().gpsr().read().prdfe() {
                 return Ok(());
             }
-            blocking_delay_ms(1);
+            block_for_us(1_000);
         }
         Err(Error::FifoTimeout)
     }
diff --git a/embassy-stm32/src/eth/generic_phy.rs b/embassy-stm32/src/eth/generic_phy.rs
index 774beef80..0a5f41de0 100644
--- a/embassy-stm32/src/eth/generic_phy.rs
+++ b/embassy-stm32/src/eth/generic_phy.rs
@@ -8,6 +8,7 @@ use embassy_time::{Duration, Timer};
 use futures_util::FutureExt;
 
 use super::{Phy, StationManagement};
+use crate::block_for_us as blocking_delay_us;
 
 #[allow(dead_code)]
 mod phy_consts {
@@ -43,21 +44,23 @@ mod phy_consts {
 use self::phy_consts::*;
 
 /// Generic SMI Ethernet PHY implementation
-pub struct GenericPhy {
+pub struct GenericPhy<SM: StationManagement> {
     phy_addr: u8,
+    sm: SM,
     #[cfg(feature = "time")]
     poll_interval: Duration,
 }
 
-impl GenericPhy {
+impl<SM: StationManagement> GenericPhy<SM> {
     /// Construct the PHY. It assumes the address `phy_addr` in the SMI communication
     ///
     /// # Panics
     /// `phy_addr` must be in range `0..32`
-    pub fn new(phy_addr: u8) -> Self {
+    pub fn new(sm: SM, phy_addr: u8) -> Self {
         assert!(phy_addr < 32);
         Self {
             phy_addr,
+            sm,
             #[cfg(feature = "time")]
             poll_interval: Duration::from_millis(500),
         }
@@ -67,8 +70,9 @@ impl GenericPhy {
     ///
     /// # Panics
     /// Initialization panics if PHY didn't respond on any address
-    pub fn new_auto() -> Self {
+    pub fn new_auto(sm: SM) -> Self {
         Self {
+            sm,
             phy_addr: 0xFF,
             #[cfg(feature = "time")]
             poll_interval: Duration::from_millis(500),
@@ -76,27 +80,14 @@ impl GenericPhy {
     }
 }
 
-// TODO: Factor out to shared functionality
-fn blocking_delay_us(us: u32) {
-    #[cfg(feature = "time")]
-    embassy_time::block_for(Duration::from_micros(us as u64));
-    #[cfg(not(feature = "time"))]
-    {
-        let freq = unsafe { crate::rcc::get_freqs() }.sys.to_hertz().unwrap().0 as u64;
-        let us = us as u64;
-        let cycles = freq * us / 1_000_000;
-        cortex_m::asm::delay(cycles as u32);
-    }
-}
-
-impl Phy for GenericPhy {
-    fn phy_reset<S: StationManagement>(&mut self, sm: &mut S) {
+impl<SM: StationManagement> Phy for GenericPhy<SM> {
+    fn phy_reset(&mut self) {
         // Detect SMI address
         if self.phy_addr == 0xFF {
             for addr in 0..32 {
-                sm.smi_write(addr, PHY_REG_BCR, PHY_REG_BCR_RESET);
+                self.sm.smi_write(addr, PHY_REG_BCR, PHY_REG_BCR_RESET);
                 for _ in 0..10 {
-                    if sm.smi_read(addr, PHY_REG_BCR) & PHY_REG_BCR_RESET != PHY_REG_BCR_RESET {
+                    if self.sm.smi_read(addr, PHY_REG_BCR) & PHY_REG_BCR_RESET != PHY_REG_BCR_RESET {
                         trace!("Found ETH PHY on address {}", addr);
                         self.phy_addr = addr;
                         return;
@@ -108,30 +99,30 @@ impl Phy for GenericPhy {
             panic!("PHY did not respond");
         }
 
-        sm.smi_write(self.phy_addr, PHY_REG_BCR, PHY_REG_BCR_RESET);
-        while sm.smi_read(self.phy_addr, PHY_REG_BCR) & PHY_REG_BCR_RESET == PHY_REG_BCR_RESET {}
+        self.sm.smi_write(self.phy_addr, PHY_REG_BCR, PHY_REG_BCR_RESET);
+        while self.sm.smi_read(self.phy_addr, PHY_REG_BCR) & PHY_REG_BCR_RESET == PHY_REG_BCR_RESET {}
     }
 
-    fn phy_init<S: StationManagement>(&mut self, sm: &mut S) {
+    fn phy_init(&mut self) {
         // Clear WU CSR
-        self.smi_write_ext(sm, PHY_REG_WUCSR, 0);
+        self.smi_write_ext(PHY_REG_WUCSR, 0);
 
         // Enable auto-negotiation
-        sm.smi_write(
+        self.sm.smi_write(
             self.phy_addr,
             PHY_REG_BCR,
             PHY_REG_BCR_AN | PHY_REG_BCR_ANRST | PHY_REG_BCR_100M,
         );
     }
 
-    fn poll_link<S: StationManagement>(&mut self, sm: &mut S, cx: &mut Context) -> bool {
+    fn poll_link(&mut self, cx: &mut Context) -> bool {
         #[cfg(not(feature = "time"))]
         cx.waker().wake_by_ref();
 
         #[cfg(feature = "time")]
         let _ = Timer::after(self.poll_interval).poll_unpin(cx);
 
-        let bsr = sm.smi_read(self.phy_addr, PHY_REG_BSR);
+        let bsr = self.sm.smi_read(self.phy_addr, PHY_REG_BSR);
 
         // No link without autonegotiate
         if bsr & PHY_REG_BSR_ANDONE == 0 {
@@ -148,7 +139,7 @@ impl Phy for GenericPhy {
 }
 
 /// Public functions for the PHY
-impl GenericPhy {
+impl<SM: StationManagement> GenericPhy<SM> {
     /// Set the SMI polling interval.
     #[cfg(feature = "time")]
     pub fn set_poll_interval(&mut self, poll_interval: Duration) {
@@ -156,10 +147,15 @@ impl GenericPhy {
     }
 
     // Writes a value to an extended PHY register in MMD address space
-    fn smi_write_ext<S: StationManagement>(&mut self, sm: &mut S, reg_addr: u16, reg_data: u16) {
-        sm.smi_write(self.phy_addr, PHY_REG_CTL, 0x0003); // set address
-        sm.smi_write(self.phy_addr, PHY_REG_ADDAR, reg_addr);
-        sm.smi_write(self.phy_addr, PHY_REG_CTL, 0x4003); // set data
-        sm.smi_write(self.phy_addr, PHY_REG_ADDAR, reg_data);
+    fn smi_write_ext(&mut self, reg_addr: u16, reg_data: u16) {
+        self.sm.smi_write(self.phy_addr, PHY_REG_CTL, 0x0003); // set address
+        self.sm.smi_write(self.phy_addr, PHY_REG_ADDAR, reg_addr);
+        self.sm.smi_write(self.phy_addr, PHY_REG_CTL, 0x4003); // set data
+        self.sm.smi_write(self.phy_addr, PHY_REG_ADDAR, reg_data);
+    }
+
+    /// Access the underlying station management.
+    pub fn station_management(&mut self) -> &mut SM {
+        &mut self.sm
     }
 }
diff --git a/embassy-stm32/src/eth/mod.rs b/embassy-stm32/src/eth/mod.rs
index 10b3a0517..c8bce0e8a 100644
--- a/embassy-stm32/src/eth/mod.rs
+++ b/embassy-stm32/src/eth/mod.rs
@@ -5,6 +5,7 @@
 #[cfg_attr(eth_v2, path = "v2/mod.rs")]
 mod _version;
 mod generic_phy;
+mod sma;
 
 use core::mem::MaybeUninit;
 use core::task::Context;
@@ -15,6 +16,7 @@ use embassy_sync::waitqueue::AtomicWaker;
 
 pub use self::_version::{InterruptHandler, *};
 pub use self::generic_phy::*;
+pub use self::sma::{Sma, StationManagement};
 use crate::rcc::RccPeripheral;
 
 #[allow(unused)]
@@ -109,7 +111,7 @@ impl<'d, T: Instance, P: Phy> embassy_net_driver::Driver for Ethernet<'d, T, P>
     }
 
     fn link_state(&mut self, cx: &mut Context) -> LinkState {
-        if self.phy.poll_link(&mut self.station_management, cx) {
+        if self.phy.poll_link(cx) {
             LinkState::Up
         } else {
             LinkState::Down
@@ -157,32 +159,17 @@ impl<'a, 'd> embassy_net_driver::TxToken for TxToken<'a, 'd> {
     }
 }
 
-/// Station Management Interface (SMI) on an ethernet PHY
-pub trait StationManagement {
-    /// Read a register over SMI.
-    fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16;
-    /// Write a register over SMI.
-    fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16);
-}
-
 /// Trait for an Ethernet PHY
 pub trait Phy {
     /// Reset PHY and wait for it to come out of reset.
-    fn phy_reset<S: StationManagement>(&mut self, sm: &mut S);
+    fn phy_reset(&mut self);
     /// PHY initialisation.
-    fn phy_init<S: StationManagement>(&mut self, sm: &mut S);
+    fn phy_init(&mut self);
     /// Poll link to see if it is up and FD with 100Mbps
-    fn poll_link<S: StationManagement>(&mut self, sm: &mut S, cx: &mut Context) -> bool;
+    fn poll_link(&mut self, cx: &mut Context) -> bool;
 }
 
 impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
-    /// Directly expose the SMI interface used by the Ethernet driver.
-    ///
-    /// This can be used to for example configure special PHY registers for compliance testing.
-    pub fn station_management(&mut self) -> &mut impl StationManagement {
-        &mut self.station_management
-    }
-
     /// Access the user-supplied `Phy`.
     pub fn phy(&self) -> &P {
         &self.phy
@@ -212,8 +199,8 @@ impl Instance for crate::peripherals::ETH {}
 pin_trait!(RXClkPin, Instance, @A);
 pin_trait!(TXClkPin, Instance, @A);
 pin_trait!(RefClkPin, Instance, @A);
-pin_trait!(MDIOPin, Instance, @A);
-pin_trait!(MDCPin, Instance, @A);
+pin_trait!(MDIOPin, sma::Instance, @A);
+pin_trait!(MDCPin, sma::Instance, @A);
 pin_trait!(RXDVPin, Instance, @A);
 pin_trait!(CRSPin, Instance, @A);
 pin_trait!(RXD0Pin, Instance, @A);
diff --git a/embassy-stm32/src/eth/sma/mod.rs b/embassy-stm32/src/eth/sma/mod.rs
new file mode 100644
index 000000000..6c851911d
--- /dev/null
+++ b/embassy-stm32/src/eth/sma/mod.rs
@@ -0,0 +1,42 @@
+//! Station Management Agent (also known as MDIO or SMI).
+
+#![macro_use]
+
+#[cfg_attr(eth_v2, path = "v2.rs")]
+#[cfg_attr(any(eth_v1a, eth_v1b, eth_v1c), path = "v1.rs")]
+mod _version;
+
+use embassy_hal_internal::PeripheralType;
+use stm32_metapac::common::{RW, Reg};
+
+pub use self::_version::*;
+
+/// Station Management Interface (SMI).
+pub trait StationManagement {
+    /// Read a register over SMI.
+    fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16;
+    /// Write a register over SMI.
+    fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16);
+}
+
+trait SealedInstance {
+    fn regs() -> (Reg<AddressRegister, RW>, Reg<DataRegister, RW>);
+}
+
+/// MDIO instance.
+#[allow(private_bounds)]
+pub trait Instance: SealedInstance + PeripheralType + Send + 'static {}
+
+impl SealedInstance for crate::peripherals::ETH_SMA {
+    fn regs() -> (Reg<AddressRegister, RW>, Reg<DataRegister, RW>) {
+        let mac = crate::pac::ETH.ethernet_mac();
+
+        #[cfg(any(eth_v1a, eth_v1b, eth_v1c))]
+        return (mac.macmiiar(), mac.macmiidr());
+
+        #[cfg(eth_v2)]
+        return (mac.macmdioar(), mac.macmdiodr());
+    }
+}
+
+impl Instance for crate::peripherals::ETH_SMA {}
diff --git a/embassy-stm32/src/eth/sma/v1.rs b/embassy-stm32/src/eth/sma/v1.rs
new file mode 100644
index 000000000..db64a6c78
--- /dev/null
+++ b/embassy-stm32/src/eth/sma/v1.rs
@@ -0,0 +1,102 @@
+use embassy_hal_internal::Peri;
+pub(crate) use regs::{Macmiiar as AddressRegister, Macmiidr as DataRegister};
+use stm32_metapac::eth::regs;
+use stm32_metapac::eth::vals::{Cr, MbProgress, Mw};
+
+use super::{Instance, StationManagement};
+use crate::eth::{MDCPin, MDIOPin};
+use crate::gpio::{AfType, AnyPin, OutputType, SealedPin, Speed};
+
+/// Station Management Agent.
+///
+/// This peripheral is used for SMI reads and writes to the connected
+/// ethernet PHY/device(s).
+pub struct Sma<'d, T: Instance> {
+    _peri: Peri<'d, T>,
+    clock_range: Cr,
+    pins: [Peri<'d, AnyPin>; 2],
+}
+
+impl<'d, T: Instance> Sma<'d, T> {
+    /// Create a new instance of this peripheral.
+    pub fn new<#[cfg(afio)] A>(
+        peri: Peri<'d, T>,
+        mdio: Peri<'d, if_afio!(impl MDIOPin<T, A>)>,
+        mdc: Peri<'d, if_afio!(impl MDCPin<T, A>)>,
+    ) -> Self {
+        set_as_af!(mdio, AfType::output(OutputType::PushPull, Speed::VeryHigh));
+        set_as_af!(mdc, AfType::output(OutputType::PushPull, Speed::VeryHigh));
+
+        // Enable necessary clocks.
+        critical_section::with(|_| {
+            #[cfg(eth_v1a)]
+            let reg = crate::pac::RCC.ahbenr();
+
+            #[cfg(any(eth_v1b, eth_v1c))]
+            let reg = crate::pac::RCC.ahb1enr();
+
+            reg.modify(|w| {
+                w.set_ethen(true);
+            })
+        });
+
+        let hclk = unsafe { crate::rcc::get_freqs().hclk1.to_hertz() };
+        let hclk = unwrap!(hclk, "SMA requires HCLK to be enabled, but it was not.");
+        let hclk_mhz = hclk.0 / 1_000_000;
+
+        // Set the MDC clock frequency in the range 1MHz - 2.5MHz
+        let clock_range = match hclk_mhz {
+            0..=24 => panic!("Invalid HCLK frequency - should be at least 25 MHz."),
+            25..=34 => Cr::CR_20_35,     // Divide by 16
+            35..=59 => Cr::CR_35_60,     // Divide by 26
+            60..=99 => Cr::CR_60_100,    // Divide by 42
+            100..=149 => Cr::CR_100_150, // Divide by 62
+            150..=216 => Cr::CR_150_168, // Divide by 102
+            _ => {
+                panic!("HCLK results in MDC clock > 2.5MHz even for the highest CSR clock divider")
+            }
+        };
+
+        Self {
+            _peri: peri,
+            clock_range,
+            pins: [mdio.into(), mdc.into()],
+        }
+    }
+}
+
+impl<T: Instance> StationManagement for Sma<'_, T> {
+    fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16 {
+        let (macmiiar, macmiidr) = T::regs();
+
+        macmiiar.modify(|w| {
+            w.set_pa(phy_addr);
+            w.set_mr(reg);
+            w.set_mw(Mw::READ); // read operation
+            w.set_cr(self.clock_range);
+            w.set_mb(MbProgress::BUSY); // indicate that operation is in progress
+        });
+        while macmiiar.read().mb() == MbProgress::BUSY {}
+        macmiidr.read().md()
+    }
+
+    fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16) {
+        let (macmiiar, macmiidr) = T::regs();
+
+        macmiidr.write(|w| w.set_md(val));
+        macmiiar.modify(|w| {
+            w.set_pa(phy_addr);
+            w.set_mr(reg);
+            w.set_mw(Mw::WRITE); // write
+            w.set_cr(self.clock_range);
+            w.set_mb(MbProgress::BUSY);
+        });
+        while macmiiar.read().mb() == MbProgress::BUSY {}
+    }
+}
+
+impl<T: Instance> Drop for Sma<'_, T> {
+    fn drop(&mut self) {
+        self.pins.iter_mut().for_each(|p| p.set_as_disconnected());
+    }
+}
diff --git a/embassy-stm32/src/eth/sma/v2.rs b/embassy-stm32/src/eth/sma/v2.rs
new file mode 100644
index 000000000..6bc5230b5
--- /dev/null
+++ b/embassy-stm32/src/eth/sma/v2.rs
@@ -0,0 +1,94 @@
+use embassy_hal_internal::Peri;
+pub(crate) use regs::{Macmdioar as AddressRegister, Macmdiodr as DataRegister};
+use stm32_metapac::eth::regs;
+
+use super::{Instance, StationManagement};
+use crate::eth::{MDCPin, MDIOPin};
+use crate::gpio::{AfType, AnyPin, OutputType, SealedPin, Speed};
+
+/// Station Management Agent.
+///
+/// This peripheral is used for SMI reads and writes to the connected
+/// ethernet PHY/device(s).
+pub struct Sma<'d, T: Instance> {
+    _peri: Peri<'d, T>,
+    pins: [Peri<'d, AnyPin>; 2],
+    clock_range: u8,
+}
+
+impl<'d, T: Instance> Sma<'d, T> {
+    /// Create a new instance of this peripheral.
+    pub fn new(peri: Peri<'d, T>, mdio: Peri<'d, impl MDIOPin<T>>, mdc: Peri<'d, impl MDCPin<T>>) -> Self {
+        set_as_af!(mdio, AfType::output(OutputType::PushPull, Speed::VeryHigh));
+        set_as_af!(mdc, AfType::output(OutputType::PushPull, Speed::VeryHigh));
+
+        // Enable necessary clocks.
+        critical_section::with(|_| {
+            crate::pac::RCC.ahb1enr().modify(|w| {
+                w.set_ethen(true);
+            })
+        });
+
+        let hclk = unsafe { crate::rcc::get_freqs().hclk1.to_hertz() };
+        let hclk = unwrap!(hclk, "SMA requires HCLK to be enabled, but it was not.");
+        let hclk_mhz = hclk.0 / 1_000_000;
+
+        // Set the MDC clock frequency in the range 1MHz - 2.5MHz
+        let clock_range = match hclk_mhz {
+            0..=34 => 2,    // Divide by 16
+            35..=59 => 3,   // Divide by 26
+            60..=99 => 0,   // Divide by 42
+            100..=149 => 1, // Divide by 62
+            150..=249 => 4, // Divide by 102
+            250..=310 => 5, // Divide by 124
+            _ => {
+                panic!("HCLK results in MDC clock > 2.5MHz even for the highest CSR clock divider")
+            }
+        };
+
+        Self {
+            _peri: peri,
+            clock_range,
+            pins: [mdio.into(), mdc.into()],
+        }
+    }
+}
+
+impl<T: Instance> StationManagement for Sma<'_, T> {
+    fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16 {
+        let (macmdioar, macmdiodr) = T::regs();
+
+        macmdioar.modify(|w| {
+            w.set_pa(phy_addr);
+            w.set_rda(reg);
+            w.set_goc(0b11); // read
+            w.set_cr(self.clock_range);
+            w.set_mb(true);
+        });
+
+        while macmdioar.read().mb() {}
+
+        macmdiodr.read().md()
+    }
+
+    fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16) {
+        let (macmdioar, macmdiodr) = T::regs();
+
+        macmdiodr.write(|w| w.set_md(val));
+        macmdioar.modify(|w| {
+            w.set_pa(phy_addr);
+            w.set_rda(reg);
+            w.set_goc(0b01); // write
+            w.set_cr(self.clock_range);
+            w.set_mb(true);
+        });
+
+        while macmdioar.read().mb() {}
+    }
+}
+
+impl<T: Instance> Drop for Sma<'_, T> {
+    fn drop(&mut self) {
+        self.pins.iter_mut().for_each(|p| p.set_as_disconnected());
+    }
+}
diff --git a/embassy-stm32/src/eth/v1/mod.rs b/embassy-stm32/src/eth/v1/mod.rs
index a77eb8719..8de26ce9d 100644
--- a/embassy-stm32/src/eth/v1/mod.rs
+++ b/embassy-stm32/src/eth/v1/mod.rs
@@ -3,11 +3,10 @@
 mod rx_desc;
 mod tx_desc;
 
-use core::marker::PhantomData;
 use core::sync::atomic::{Ordering, fence};
 
 use embassy_hal_internal::Peri;
-use stm32_metapac::eth::vals::{Apcs, Cr, Dm, DmaomrSr, Fes, Ftf, Ifg, MbProgress, Mw, Pbl, Rsf, St, Tsf};
+use stm32_metapac::eth::vals::{Apcs, Dm, DmaomrSr, Fes, Ftf, Ifg, Pbl, Rsf, St, Tsf};
 
 pub(crate) use self::rx_desc::{RDes, RDesRing};
 pub(crate) use self::tx_desc::{TDes, TDesRing};
@@ -22,7 +21,6 @@ use crate::pac::AFIO;
 #[cfg(any(eth_v1b, eth_v1c))]
 use crate::pac::SYSCFG;
 use crate::pac::{ETH, RCC};
-use crate::rcc::SealedRccPeripheral;
 
 /// Interrupt handler.
 pub struct InterruptHandler {}
@@ -53,14 +51,13 @@ pub struct Ethernet<'d, T: Instance, P: Phy> {
 
     pins: Pins<'d>,
     pub(crate) phy: P,
-    pub(crate) station_management: EthernetStationManagement<T>,
     pub(crate) mac_addr: [u8; 6],
 }
 
 /// Pins of ethernet driver.
 enum Pins<'d> {
-    Rmii([Peri<'d, AnyPin>; 9]),
-    Mii([Peri<'d, AnyPin>; 14]),
+    Rmii([Peri<'d, AnyPin>; 7]),
+    Mii([Peri<'d, AnyPin>; 12]),
 }
 
 #[cfg(eth_v1a)]
@@ -97,68 +94,105 @@ macro_rules! config_pins {
     };
 }
 
-impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
+impl<'d, T: Instance, SMA: sma::Instance> Ethernet<'d, T, GenericPhy<Sma<'d, SMA>>> {
+    /// Create a new RMII ethernet driver using 7 pins.
+    ///
+    /// This function uses a [`GenericPhy::new_auto`] as PHY, created using the
+    /// provided [`SMA`](sma::Instance), and MDIO and MDC pins.
+    ///
+    /// See [`Ethernet::new_with_phy`] for creating an RMII ethernet
+    /// river with a non-standard PHY.
+    ///
     /// safety: the returned instance is not leak-safe
     pub fn new<const TX: usize, const RX: usize, #[cfg(afio)] A>(
         queue: &'d mut PacketQueue<TX, RX>,
         peri: Peri<'d, T>,
         irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
         ref_clk: Peri<'d, if_afio!(impl RefClkPin<T, A>)>,
-        mdio: Peri<'d, if_afio!(impl MDIOPin<T, A>)>,
-        mdc: Peri<'d, if_afio!(impl MDCPin<T, A>)>,
         crs: Peri<'d, if_afio!(impl CRSPin<T, A>)>,
         rx_d0: Peri<'d, if_afio!(impl RXD0Pin<T, A>)>,
         rx_d1: Peri<'d, if_afio!(impl RXD1Pin<T, A>)>,
         tx_d0: Peri<'d, if_afio!(impl TXD0Pin<T, A>)>,
         tx_d1: Peri<'d, if_afio!(impl TXD1Pin<T, A>)>,
         tx_en: Peri<'d, if_afio!(impl TXEnPin<T, A>)>,
-        phy: P,
         mac_addr: [u8; 6],
+        sma: Peri<'d, SMA>,
+        mdio: Peri<'d, if_afio!(impl MDIOPin<SMA, A>)>,
+        mdc: Peri<'d, if_afio!(impl MDCPin<SMA, A>)>,
     ) -> Self {
-        // Enable the necessary Clocks
-        #[cfg(eth_v1a)]
-        critical_section::with(|_| {
-            RCC.apb2enr().modify(|w| w.set_afioen(true));
-
-            // Select RMII (Reduced Media Independent Interface)
-            // Must be done prior to enabling peripheral clock
-            AFIO.mapr().modify(|w| {
-                w.set_mii_rmii_sel(true);
-                w.set_swj_cfg(crate::pac::afio::vals::SwjCfg::NO_OP);
-            });
+        let sma = Sma::new(sma, mdio, mdc);
+        let phy = GenericPhy::new_auto(sma);
 
-            RCC.ahbenr().modify(|w| {
-                w.set_ethen(true);
-                w.set_ethtxen(true);
-                w.set_ethrxen(true);
-            });
-        });
+        Self::new_with_phy(
+            queue, peri, irq, ref_clk, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en, mac_addr, phy,
+        )
+    }
 
-        #[cfg(any(eth_v1b, eth_v1c))]
-        critical_section::with(|_| {
-            RCC.ahb1enr().modify(|w| {
-                w.set_ethen(true);
-                w.set_ethtxen(true);
-                w.set_ethrxen(true);
-            });
+    /// Create a new MII ethernet driver using 14 pins.
+    ///
+    /// This function uses a [`GenericPhy::new_auto`] as PHY, created using the
+    /// provided [`SMA`](sma::Instance), and MDIO and MDC pins.
+    ///
+    /// See [`Ethernet::new_mii_with_phy`] for creating an RMII ethernet
+    /// river with a non-standard PHY.
+    pub fn new_mii<const TX: usize, const RX: usize, #[cfg(afio)] A>(
+        queue: &'d mut PacketQueue<TX, RX>,
+        peri: Peri<'d, T>,
+        irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
+        rx_clk: Peri<'d, if_afio!(impl RXClkPin<T, A>)>,
+        tx_clk: Peri<'d, if_afio!(impl TXClkPin<T, A>)>,
+        rxdv: Peri<'d, if_afio!(impl RXDVPin<T, A>)>,
+        rx_d0: Peri<'d, if_afio!(impl RXD0Pin<T, A>)>,
+        rx_d1: Peri<'d, if_afio!(impl RXD1Pin<T, A>)>,
+        rx_d2: Peri<'d, if_afio!(impl RXD2Pin<T, A>)>,
+        rx_d3: Peri<'d, if_afio!(impl RXD3Pin<T, A>)>,
+        tx_d0: Peri<'d, if_afio!(impl TXD0Pin<T, A>)>,
+        tx_d1: Peri<'d, if_afio!(impl TXD1Pin<T, A>)>,
+        tx_d2: Peri<'d, if_afio!(impl TXD2Pin<T, A>)>,
+        tx_d3: Peri<'d, if_afio!(impl TXD3Pin<T, A>)>,
+        tx_en: Peri<'d, if_afio!(impl TXEnPin<T, A>)>,
+        mac_addr: [u8; 6],
+        sma: Peri<'d, SMA>,
+        mdio: Peri<'d, if_afio!(impl MDIOPin<SMA, A>)>,
+        mdc: Peri<'d, if_afio!(impl MDCPin<SMA, A>)>,
+    ) -> Self {
+        let sma = Sma::new(sma, mdio, mdc);
+        let phy = GenericPhy::new_auto(sma);
 
-            // RMII (Reduced Media Independent Interface)
-            SYSCFG.pmc().modify(|w| w.set_mii_rmii_sel(true));
-        });
+        Self::new_mii_with_phy(
+            queue, peri, irq, rx_clk, tx_clk, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en,
+            mac_addr, phy,
+        )
+    }
+}
 
+impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
+    /// safety: the returned instance is not leak-safe
+    pub fn new_with_phy<const TX: usize, const RX: usize, #[cfg(afio)] A>(
+        queue: &'d mut PacketQueue<TX, RX>,
+        peri: Peri<'d, T>,
+        irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
+        ref_clk: Peri<'d, if_afio!(impl RefClkPin<T, A>)>,
+        crs: Peri<'d, if_afio!(impl CRSPin<T, A>)>,
+        rx_d0: Peri<'d, if_afio!(impl RXD0Pin<T, A>)>,
+        rx_d1: Peri<'d, if_afio!(impl RXD1Pin<T, A>)>,
+        tx_d0: Peri<'d, if_afio!(impl TXD0Pin<T, A>)>,
+        tx_d1: Peri<'d, if_afio!(impl TXD1Pin<T, A>)>,
+        tx_en: Peri<'d, if_afio!(impl TXEnPin<T, A>)>,
+        mac_addr: [u8; 6],
+        phy: P,
+    ) -> Self {
         #[cfg(eth_v1a)]
         {
             config_in_pins!(ref_clk, rx_d0, rx_d1);
-            config_af_pins!(mdio, mdc, tx_d0, tx_d1, tx_en);
+            config_af_pins!(tx_d0, tx_d1, tx_en);
         }
 
         #[cfg(any(eth_v1b, eth_v1c))]
-        config_pins!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
+        config_pins!(ref_clk, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
 
         let pins = Pins::Rmii([
             ref_clk.into(),
-            mdio.into(),
-            mdc.into(),
             crs.into(),
             rx_d0.into(),
             rx_d1.into(),
@@ -167,7 +201,7 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
             tx_en.into(),
         ]);
 
-        Self::new_inner(queue, peri, irq, pins, phy, mac_addr)
+        Self::new_inner(queue, peri, irq, pins, phy, mac_addr, true)
     }
 
     fn new_inner<const TX: usize, const RX: usize>(
@@ -177,7 +211,39 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
         pins: Pins<'d>,
         phy: P,
         mac_addr: [u8; 6],
+        rmii_mii_sel: bool,
     ) -> Self {
+        // Enable the necessary Clocks
+        #[cfg(eth_v1a)]
+        critical_section::with(|_| {
+            RCC.apb2enr().modify(|w| w.set_afioen(true));
+
+            // Select (R)MII (Reduced Media Independent Interface)
+            // Must be done prior to enabling peripheral clock
+            AFIO.mapr().modify(|w| {
+                w.set_mii_rmii_sel(rmii_mii_sel);
+                w.set_swj_cfg(crate::pac::afio::vals::SwjCfg::NO_OP);
+            });
+
+            RCC.ahbenr().modify(|w| {
+                w.set_ethen(true);
+                w.set_ethtxen(true);
+                w.set_ethrxen(true);
+            });
+        });
+
+        #[cfg(any(eth_v1b, eth_v1c))]
+        critical_section::with(|_| {
+            RCC.ahb1enr().modify(|w| {
+                w.set_ethen(true);
+                w.set_ethtxen(true);
+                w.set_ethrxen(true);
+            });
+
+            // (R)MII ((Reduced) Media Independent Interface)
+            SYSCFG.pmc().modify(|w| w.set_mii_rmii_sel(rmii_mii_sel));
+        });
+
         let dma = T::regs().ethernet_dma();
         let mac = T::regs().ethernet_mac();
 
@@ -226,30 +292,10 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
 
         // TODO MTU size setting not found for v1 ethernet, check if correct
 
-        let hclk = <T as SealedRccPeripheral>::frequency();
-        let hclk_mhz = hclk.0 / 1_000_000;
-
-        // Set the MDC clock frequency in the range 1MHz - 2.5MHz
-        let clock_range = match hclk_mhz {
-            0..=24 => panic!("Invalid HCLK frequency - should be at least 25 MHz."),
-            25..=34 => Cr::CR_20_35,     // Divide by 16
-            35..=59 => Cr::CR_35_60,     // Divide by 26
-            60..=99 => Cr::CR_60_100,    // Divide by 42
-            100..=149 => Cr::CR_100_150, // Divide by 62
-            150..=216 => Cr::CR_150_168, // Divide by 102
-            _ => {
-                panic!("HCLK results in MDC clock > 2.5MHz even for the highest CSR clock divider")
-            }
-        };
-
         let mut this = Self {
             _peri: peri,
             pins,
             phy: phy,
-            station_management: EthernetStationManagement {
-                peri: PhantomData,
-                clock_range: clock_range,
-            },
             mac_addr,
             tx: TDesRing::new(&mut queue.tx_desc, &mut queue.tx_buf),
             rx: RDesRing::new(&mut queue.rx_desc, &mut queue.rx_buf),
@@ -279,8 +325,8 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
             w.set_tie(true);
         });
 
-        this.phy.phy_reset(&mut this.station_management);
-        this.phy.phy_init(&mut this.station_management);
+        this.phy.phy_reset();
+        this.phy.phy_init();
 
         interrupt::ETH.unpend();
         unsafe { interrupt::ETH.enable() };
@@ -288,15 +334,13 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
         this
     }
 
-    /// Create a new MII ethernet driver using 14 pins.
-    pub fn new_mii<const TX: usize, const RX: usize, #[cfg(afio)] A>(
+    /// Create a new MII ethernet driver using 12 pins.
+    pub fn new_mii_with_phy<const TX: usize, const RX: usize, #[cfg(afio)] A>(
         queue: &'d mut PacketQueue<TX, RX>,
         peri: Peri<'d, T>,
         irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
         rx_clk: Peri<'d, if_afio!(impl RXClkPin<T, A>)>,
         tx_clk: Peri<'d, if_afio!(impl TXClkPin<T, A>)>,
-        mdio: Peri<'d, if_afio!(impl MDIOPin<T, A>)>,
-        mdc: Peri<'d, if_afio!(impl MDCPin<T, A>)>,
         rxdv: Peri<'d, if_afio!(impl RXDVPin<T, A>)>,
         rx_d0: Peri<'d, if_afio!(impl RXD0Pin<T, A>)>,
         rx_d1: Peri<'d, if_afio!(impl RXD1Pin<T, A>)>,
@@ -307,58 +351,23 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
         tx_d2: Peri<'d, if_afio!(impl TXD2Pin<T, A>)>,
         tx_d3: Peri<'d, if_afio!(impl TXD3Pin<T, A>)>,
         tx_en: Peri<'d, if_afio!(impl TXEnPin<T, A>)>,
-        phy: P,
         mac_addr: [u8; 6],
+        phy: P,
     ) -> Self {
-        // TODO: Handle optional signals like CRS, MII_COL, RX_ER?
-
-        // Enable the necessary Clocks
-        #[cfg(eth_v1a)]
-        critical_section::with(|_| {
-            RCC.apb2enr().modify(|w| w.set_afioen(true));
-
-            // Select MII (Media Independent Interface)
-            // Must be done prior to enabling peripheral clock
-            AFIO.mapr().modify(|w| {
-                w.set_mii_rmii_sel(false);
-                w.set_swj_cfg(crate::pac::afio::vals::SwjCfg::NO_OP);
-            });
-
-            RCC.ahbenr().modify(|w| {
-                w.set_ethen(true);
-                w.set_ethtxen(true);
-                w.set_ethrxen(true);
-            });
-        });
-
-        #[cfg(any(eth_v1b, eth_v1c))]
-        critical_section::with(|_| {
-            RCC.ahb1enr().modify(|w| {
-                w.set_ethen(true);
-                w.set_ethtxen(true);
-                w.set_ethrxen(true);
-            });
-
-            // MII (Media Independent Interface)
-            SYSCFG.pmc().modify(|w| w.set_mii_rmii_sel(false));
-        });
-
         #[cfg(eth_v1a)]
         {
             config_in_pins!(rx_clk, tx_clk, rx_d0, rx_d1, rx_d2, rx_d3, rxdv);
-            config_af_pins!(mdio, mdc, tx_d0, tx_d1, tx_d2, tx_d3, tx_en);
+            config_af_pins!(tx_d0, tx_d1, tx_d2, tx_d3, tx_en);
         }
 
         #[cfg(any(eth_v1b, eth_v1c))]
         config_pins!(
-            rx_clk, tx_clk, mdio, mdc, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en
+            rx_clk, tx_clk, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en
         );
 
         let pins = Pins::Mii([
             rx_clk.into(),
             tx_clk.into(),
-            mdio.into(),
-            mdc.into(),
             rxdv.into(),
             rx_d0.into(),
             rx_d1.into(),
@@ -371,43 +380,7 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
             tx_en.into(),
         ]);
 
-        Self::new_inner(queue, peri, irq, pins, phy, mac_addr)
-    }
-}
-
-/// Ethernet station management interface.
-pub(crate) struct EthernetStationManagement<T: Instance> {
-    peri: PhantomData<T>,
-    clock_range: Cr,
-}
-
-impl<T: Instance> StationManagement for EthernetStationManagement<T> {
-    fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16 {
-        let mac = T::regs().ethernet_mac();
-
-        mac.macmiiar().modify(|w| {
-            w.set_pa(phy_addr);
-            w.set_mr(reg);
-            w.set_mw(Mw::READ); // read operation
-            w.set_cr(self.clock_range);
-            w.set_mb(MbProgress::BUSY); // indicate that operation is in progress
-        });
-        while mac.macmiiar().read().mb() == MbProgress::BUSY {}
-        mac.macmiidr().read().md()
-    }
-
-    fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16) {
-        let mac = T::regs().ethernet_mac();
-
-        mac.macmiidr().write(|w| w.set_md(val));
-        mac.macmiiar().modify(|w| {
-            w.set_pa(phy_addr);
-            w.set_mr(reg);
-            w.set_mw(Mw::WRITE); // write
-            w.set_cr(self.clock_range);
-            w.set_mb(MbProgress::BUSY);
-        });
-        while mac.macmiiar().read().mb() == MbProgress::BUSY {}
+        Self::new_inner(queue, peri, irq, pins, phy, mac_addr, false)
     }
 }
 
diff --git a/embassy-stm32/src/eth/v2/mod.rs b/embassy-stm32/src/eth/v2/mod.rs
index 39a6e8b0f..7f92e351c 100644
--- a/embassy-stm32/src/eth/v2/mod.rs
+++ b/embassy-stm32/src/eth/v2/mod.rs
@@ -1,6 +1,5 @@
 mod descriptors;
 
-use core::marker::PhantomData;
 use core::sync::atomic::{Ordering, fence};
 
 use embassy_hal_internal::Peri;
@@ -12,7 +11,6 @@ use crate::gpio::{AfType, AnyPin, OutputType, SealedPin as _, Speed};
 use crate::interrupt;
 use crate::interrupt::InterruptExt;
 use crate::pac::ETH;
-use crate::rcc::SealedRccPeripheral;
 
 /// Interrupt handler.
 pub struct InterruptHandler {}
@@ -42,14 +40,13 @@ pub struct Ethernet<'d, T: Instance, P: Phy> {
     pub(crate) rx: RDesRing<'d>,
     pins: Pins<'d>,
     pub(crate) phy: P,
-    pub(crate) station_management: EthernetStationManagement<T>,
     pub(crate) mac_addr: [u8; 6],
 }
 
 /// Pins of ethernet driver.
 enum Pins<'d> {
-    Rmii([Peri<'d, AnyPin>; 9]),
-    Mii([Peri<'d, AnyPin>; 14]),
+    Rmii([Peri<'d, AnyPin>; 7]),
+    Mii([Peri<'d, AnyPin>; 12]),
 }
 
 macro_rules! config_pins {
@@ -63,41 +60,96 @@ macro_rules! config_pins {
     };
 }
 
-impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
-    /// Create a new RMII ethernet driver using 9 pins.
+impl<'d, T: Instance, SMA: sma::Instance> Ethernet<'d, T, GenericPhy<Sma<'d, SMA>>> {
+    /// Create a new RMII ethernet driver using 7 pins.
+    ///
+    /// This function uses a [`GenericPhy::new_auto`] as PHY, created using the
+    /// provided [`SMA`](sma::Instance), and MDIO and MDC pins.
+    ///
+    /// See [`Ethernet::new_with_phy`] for creating an RMII ethernet
+    /// river with a non-standard PHY.
     pub fn new<const TX: usize, const RX: usize>(
         queue: &'d mut PacketQueue<TX, RX>,
         peri: Peri<'d, T>,
         irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
         ref_clk: Peri<'d, impl RefClkPin<T>>,
-        mdio: Peri<'d, impl MDIOPin<T>>,
-        mdc: Peri<'d, impl MDCPin<T>>,
         crs: Peri<'d, impl CRSPin<T>>,
         rx_d0: Peri<'d, impl RXD0Pin<T>>,
         rx_d1: Peri<'d, impl RXD1Pin<T>>,
         tx_d0: Peri<'d, impl TXD0Pin<T>>,
         tx_d1: Peri<'d, impl TXD1Pin<T>>,
         tx_en: Peri<'d, impl TXEnPin<T>>,
-        phy: P,
         mac_addr: [u8; 6],
+        sma: Peri<'d, SMA>,
+        mdio: Peri<'d, impl MDIOPin<SMA>>,
+        mdc: Peri<'d, impl MDCPin<SMA>>,
     ) -> Self {
-        // Enable the necessary clocks
-        critical_section::with(|_| {
-            crate::pac::RCC.ahb1enr().modify(|w| {
-                w.set_ethen(true);
-                w.set_ethtxen(true);
-                w.set_ethrxen(true);
-            });
+        let sma = Sma::new(sma, mdio, mdc);
+        let phy = GenericPhy::new_auto(sma);
 
-            crate::pac::SYSCFG.pmcr().modify(|w| w.set_eth_sel_phy(EthSelPhy::RMII));
-        });
+        Self::new_with_phy(
+            queue, peri, irq, ref_clk, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en, mac_addr, phy,
+        )
+    }
+
+    /// Create a new MII ethernet driver using 14 pins.
+    ///
+    /// This function uses a [`GenericPhy::new_auto`] as PHY, created using the
+    /// provided [`SMA`](sma::Instance), and MDIO and MDC pins.
+    ///
+    /// See [`Ethernet::new_mii_with_phy`] for creating an RMII ethernet
+    /// river with a non-standard PHY.
+    pub fn new_mii<const TX: usize, const RX: usize>(
+        queue: &'d mut PacketQueue<TX, RX>,
+        peri: Peri<'d, T>,
+        irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
+        rx_clk: Peri<'d, impl RXClkPin<T>>,
+        tx_clk: Peri<'d, impl TXClkPin<T>>,
+        rxdv: Peri<'d, impl RXDVPin<T>>,
+        rx_d0: Peri<'d, impl RXD0Pin<T>>,
+        rx_d1: Peri<'d, impl RXD1Pin<T>>,
+        rx_d2: Peri<'d, impl RXD2Pin<T>>,
+        rx_d3: Peri<'d, impl RXD3Pin<T>>,
+        tx_d0: Peri<'d, impl TXD0Pin<T>>,
+        tx_d1: Peri<'d, impl TXD1Pin<T>>,
+        tx_d2: Peri<'d, impl TXD2Pin<T>>,
+        tx_d3: Peri<'d, impl TXD3Pin<T>>,
+        tx_en: Peri<'d, impl TXEnPin<T>>,
+        mac_addr: [u8; 6],
+        sma: Peri<'d, SMA>,
+        mdio: Peri<'d, impl MDIOPin<SMA>>,
+        mdc: Peri<'d, impl MDCPin<SMA>>,
+    ) -> Self {
+        let sma = Sma::new(sma, mdio, mdc);
+        let phy = GenericPhy::new_auto(sma);
+
+        Self::new_mii_with_phy(
+            queue, peri, irq, rx_clk, tx_clk, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en,
+            mac_addr, phy,
+        )
+    }
+}
 
-        config_pins!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
+impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
+    /// Create a new RMII ethernet driver using 7 pins.
+    pub fn new_with_phy<const TX: usize, const RX: usize>(
+        queue: &'d mut PacketQueue<TX, RX>,
+        peri: Peri<'d, T>,
+        irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
+        ref_clk: Peri<'d, impl RefClkPin<T>>,
+        crs: Peri<'d, impl CRSPin<T>>,
+        rx_d0: Peri<'d, impl RXD0Pin<T>>,
+        rx_d1: Peri<'d, impl RXD1Pin<T>>,
+        tx_d0: Peri<'d, impl TXD0Pin<T>>,
+        tx_d1: Peri<'d, impl TXD1Pin<T>>,
+        tx_en: Peri<'d, impl TXEnPin<T>>,
+        mac_addr: [u8; 6],
+        phy: P,
+    ) -> Self {
+        config_pins!(ref_clk, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
 
         let pins = Pins::Rmii([
             ref_clk.into(),
-            mdio.into(),
-            mdc.into(),
             crs.into(),
             rx_d0.into(),
             rx_d1.into(),
@@ -106,18 +158,16 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
             tx_en.into(),
         ]);
 
-        Self::new_inner(queue, peri, irq, pins, phy, mac_addr)
+        Self::new_inner(queue, peri, irq, pins, phy, mac_addr, EthSelPhy::RMII)
     }
 
-    /// Create a new MII ethernet driver using 14 pins.
-    pub fn new_mii<const TX: usize, const RX: usize>(
+    /// Create a new MII ethernet driver using 12 pins.
+    pub fn new_mii_with_phy<const TX: usize, const RX: usize>(
         queue: &'d mut PacketQueue<TX, RX>,
         peri: Peri<'d, T>,
         irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
         rx_clk: Peri<'d, impl RXClkPin<T>>,
         tx_clk: Peri<'d, impl TXClkPin<T>>,
-        mdio: Peri<'d, impl MDIOPin<T>>,
-        mdc: Peri<'d, impl MDCPin<T>>,
         rxdv: Peri<'d, impl RXDVPin<T>>,
         rx_d0: Peri<'d, impl RXD0Pin<T>>,
         rx_d1: Peri<'d, impl RXD1Pin<T>>,
@@ -128,31 +178,16 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
         tx_d2: Peri<'d, impl TXD2Pin<T>>,
         tx_d3: Peri<'d, impl TXD3Pin<T>>,
         tx_en: Peri<'d, impl TXEnPin<T>>,
-        phy: P,
         mac_addr: [u8; 6],
+        phy: P,
     ) -> Self {
-        // Enable the necessary clocks
-        critical_section::with(|_| {
-            crate::pac::RCC.ahb1enr().modify(|w| {
-                w.set_ethen(true);
-                w.set_ethtxen(true);
-                w.set_ethrxen(true);
-            });
-
-            crate::pac::SYSCFG
-                .pmcr()
-                .modify(|w| w.set_eth_sel_phy(EthSelPhy::MII_GMII));
-        });
-
         config_pins!(
-            rx_clk, tx_clk, mdio, mdc, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en
+            rx_clk, tx_clk, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en
         );
 
         let pins = Pins::Mii([
             rx_clk.into(),
             tx_clk.into(),
-            mdio.into(),
-            mdc.into(),
             rxdv.into(),
             rx_d0.into(),
             rx_d1.into(),
@@ -165,7 +200,7 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
             tx_en.into(),
         ]);
 
-        Self::new_inner(queue, peri, irq, pins, phy, mac_addr)
+        Self::new_inner(queue, peri, irq, pins, phy, mac_addr, EthSelPhy::MII_GMII)
     }
 
     fn new_inner<const TX: usize, const RX: usize>(
@@ -175,7 +210,19 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
         pins: Pins<'d>,
         phy: P,
         mac_addr: [u8; 6],
+        eth_sel_phy: EthSelPhy,
     ) -> Self {
+        // Enable the necessary clocks
+        critical_section::with(|_| {
+            crate::pac::RCC.ahb1enr().modify(|w| {
+                w.set_ethen(true);
+                w.set_ethtxen(true);
+                w.set_ethrxen(true);
+            });
+
+            crate::pac::SYSCFG.pmcr().modify(|w| w.set_eth_sel_phy(eth_sel_phy));
+        });
+
         let dma = T::regs().ethernet_dma();
         let mac = T::regs().ethernet_mac();
         let mtl = T::regs().ethernet_mtl();
@@ -237,32 +284,12 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
             w.set_rbsz(RX_BUFFER_SIZE as u16);
         });
 
-        let hclk = <T as SealedRccPeripheral>::frequency();
-        let hclk_mhz = hclk.0 / 1_000_000;
-
-        // Set the MDC clock frequency in the range 1MHz - 2.5MHz
-        let clock_range = match hclk_mhz {
-            0..=34 => 2,    // Divide by 16
-            35..=59 => 3,   // Divide by 26
-            60..=99 => 0,   // Divide by 42
-            100..=149 => 1, // Divide by 62
-            150..=249 => 4, // Divide by 102
-            250..=310 => 5, // Divide by 124
-            _ => {
-                panic!("HCLK results in MDC clock > 2.5MHz even for the highest CSR clock divider")
-            }
-        };
-
         let mut this = Self {
             _peri: peri,
             tx: TDesRing::new(&mut queue.tx_desc, &mut queue.tx_buf),
             rx: RDesRing::new(&mut queue.rx_desc, &mut queue.rx_buf),
             pins,
             phy,
-            station_management: EthernetStationManagement {
-                peri: PhantomData,
-                clock_range: clock_range,
-            },
             mac_addr,
         };
 
@@ -288,8 +315,8 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
             w.set_tie(true);
         });
 
-        this.phy.phy_reset(&mut this.station_management);
-        this.phy.phy_init(&mut this.station_management);
+        this.phy.phy_reset();
+        this.phy.phy_init();
 
         interrupt::ETH.unpend();
         unsafe { interrupt::ETH.enable() };
@@ -298,42 +325,6 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
     }
 }
 
-/// Ethernet SMI driver.
-pub struct EthernetStationManagement<T: Instance> {
-    peri: PhantomData<T>,
-    clock_range: u8,
-}
-
-impl<T: Instance> StationManagement for EthernetStationManagement<T> {
-    fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16 {
-        let mac = T::regs().ethernet_mac();
-
-        mac.macmdioar().modify(|w| {
-            w.set_pa(phy_addr);
-            w.set_rda(reg);
-            w.set_goc(0b11); // read
-            w.set_cr(self.clock_range);
-            w.set_mb(true);
-        });
-        while mac.macmdioar().read().mb() {}
-        mac.macmdiodr().read().md()
-    }
-
-    fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16) {
-        let mac = T::regs().ethernet_mac();
-
-        mac.macmdiodr().write(|w| w.set_md(val));
-        mac.macmdioar().modify(|w| {
-            w.set_pa(phy_addr);
-            w.set_rda(reg);
-            w.set_goc(0b01); // write
-            w.set_cr(self.clock_range);
-            w.set_mb(true);
-        });
-        while mac.macmdioar().read().mb() {}
-    }
-}
-
 impl<'d, T: Instance, P: Phy> Drop for Ethernet<'d, T, P> {
     fn drop(&mut self) {
         let dma = T::regs().ethernet_dma();
diff --git a/embassy-stm32/src/exti.rs b/embassy-stm32/src/exti.rs
index cb46d362c..7b7896d46 100644
--- a/embassy-stm32/src/exti.rs
+++ b/embassy-stm32/src/exti.rs
@@ -5,13 +5,16 @@ use core::marker::PhantomData;
 use core::pin::Pin;
 use core::task::{Context, Poll};
 
-use embassy_hal_internal::{PeripheralType, impl_peripheral};
+use embassy_hal_internal::PeripheralType;
 use embassy_sync::waitqueue::AtomicWaker;
+use futures_util::FutureExt;
 
-use crate::gpio::{AnyPin, Input, Level, Pin as GpioPin, PinNumber, Pull};
+use crate::gpio::{AnyPin, ExtiPin, Input, Level, Pin as GpioPin, PinNumber, Pull};
+use crate::interrupt::Interrupt as InterruptEnum;
+use crate::interrupt::typelevel::{Binding, Handler, Interrupt as InterruptType};
 use crate::pac::EXTI;
 use crate::pac::exti::regs::Lines;
-use crate::{Peri, interrupt, pac, peripherals};
+use crate::{Peri, pac};
 
 const EXTI_COUNT: usize = 16;
 static EXTI_WAKERS: [AtomicWaker; EXTI_COUNT] = [const { AtomicWaker::new() }; EXTI_COUNT];
@@ -105,10 +108,17 @@ impl<'d> Unpin for ExtiInput<'d> {}
 
 impl<'d> ExtiInput<'d> {
     /// Create an EXTI input.
-    pub fn new<T: GpioPin>(pin: Peri<'d, T>, ch: Peri<'d, T::ExtiChannel>, pull: Pull) -> Self {
-        // Needed if using AnyPin+AnyChannel.
-        assert_eq!(pin.pin(), ch.number());
-
+    ///
+    /// The Binding must bind the Channel's IRQ to [InterruptHandler].
+    pub fn new<T: ExtiPin + GpioPin>(
+        pin: Peri<'d, T>,
+        _ch: Peri<'d, T::ExtiChannel>,
+        pull: Pull,
+        _irq: impl Binding<
+            <<T as ExtiPin>::ExtiChannel as Channel>::IRQ,
+            InterruptHandler<<<T as ExtiPin>::ExtiChannel as Channel>::IRQ>,
+        >,
+    ) -> Self {
         Self {
             pin: Input::new(pin, pull),
         }
@@ -133,7 +143,7 @@ impl<'d> ExtiInput<'d> {
     ///
     /// This returns immediately if the pin is already high.
     pub async fn wait_for_high(&mut self) {
-        let fut = ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), true, false);
+        let fut = ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), true, false, true);
         if self.is_high() {
             return;
         }
@@ -144,7 +154,7 @@ impl<'d> ExtiInput<'d> {
     ///
     /// This returns immediately if the pin is already low.
     pub async fn wait_for_low(&mut self) {
-        let fut = ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), false, true);
+        let fut = ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), false, true, true);
         if self.is_low() {
             return;
         }
@@ -155,19 +165,40 @@ impl<'d> ExtiInput<'d> {
     ///
     /// If the pin is already high, it will wait for it to go low then back high.
     pub async fn wait_for_rising_edge(&mut self) {
-        ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), true, false).await
+        ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), true, false, true).await
+    }
+
+    /// Asynchronously wait until the pin sees a rising edge.
+    ///
+    /// If the pin is already high, it will wait for it to go low then back high.
+    pub fn poll_for_rising_edge<'a>(&mut self, cx: &mut Context<'a>) {
+        let _ =
+            ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), true, false, false).poll_unpin(cx);
     }
 
     /// Asynchronously wait until the pin sees a falling edge.
     ///
     /// If the pin is already low, it will wait for it to go high then back low.
     pub async fn wait_for_falling_edge(&mut self) {
-        ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), false, true).await
+        ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), false, true, true).await
+    }
+
+    /// Asynchronously wait until the pin sees a falling edge.
+    ///
+    /// If the pin is already low, it will wait for it to go high then back low.
+    pub fn poll_for_falling_edge<'a>(&mut self, cx: &mut Context<'a>) {
+        let _ =
+            ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), false, true, false).poll_unpin(cx);
     }
 
     /// Asynchronously wait until the pin sees any edge (either rising or falling).
     pub async fn wait_for_any_edge(&mut self) {
-        ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), true, true).await
+        ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), true, true, true).await
+    }
+
+    /// Asynchronously wait until the pin sees any edge (either rising or falling).
+    pub fn poll_for_any_edge<'a>(&mut self, cx: &mut Context<'a>) {
+        let _ = ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), true, true, false).poll_unpin(cx);
     }
 }
 
@@ -227,11 +258,12 @@ impl<'d> embedded_hal_async::digital::Wait for ExtiInput<'d> {
 #[must_use = "futures do nothing unless you `.await` or poll them"]
 struct ExtiInputFuture<'a> {
     pin: PinNumber,
+    drop: bool,
     phantom: PhantomData<&'a mut AnyPin>,
 }
 
 impl<'a> ExtiInputFuture<'a> {
-    fn new(pin: PinNumber, port: PinNumber, rising: bool, falling: bool) -> Self {
+    fn new(pin: PinNumber, port: PinNumber, rising: bool, falling: bool, drop: bool) -> Self {
         critical_section::with(|_| {
             let pin = pin as usize;
             exticr_regs().exticr(pin / 4).modify(|w| w.set_exti(pin % 4, port));
@@ -252,6 +284,7 @@ impl<'a> ExtiInputFuture<'a> {
 
         Self {
             pin,
+            drop,
             phantom: PhantomData,
         }
     }
@@ -259,10 +292,12 @@ impl<'a> ExtiInputFuture<'a> {
 
 impl<'a> Drop for ExtiInputFuture<'a> {
     fn drop(&mut self) {
-        critical_section::with(|_| {
-            let pin = self.pin as _;
-            cpu_regs().imr(0).modify(|w| w.set_line(pin, false));
-        });
+        if self.drop {
+            critical_section::with(|_| {
+                let pin = self.pin as _;
+                cpu_regs().imr(0).modify(|w| w.set_line(pin, false));
+            });
+        }
     }
 }
 
@@ -302,7 +337,7 @@ macro_rules! foreach_exti_irq {
             (EXTI15) => { $action!(EXTI15); };
 
             // plus the weird ones
-            (EXTI0_1)   => { $action!( EXTI0_1 ); };
+            (EXTI0_1)   => { $action!(EXTI0_1); };
             (EXTI15_10) => { $action!(EXTI15_10); };
             (EXTI15_4)  => { $action!(EXTI15_4); };
             (EXTI1_0)   => { $action!(EXTI1_0); };
@@ -315,57 +350,67 @@ macro_rules! foreach_exti_irq {
     };
 }
 
-macro_rules! impl_irq {
-    ($e:ident) => {
-        #[allow(non_snake_case)]
-        #[cfg(feature = "rt")]
-        #[interrupt]
-        unsafe fn $e() {
-            on_irq()
-        }
-    };
+///EXTI interrupt handler. All EXTI interrupt vectors should be bound to this handler.
+///
+/// It is generic over the [Interrupt](InterruptType) rather
+/// than the [Channel] because it should not be bound multiple
+/// times to the same vector on chips which multiplex multiple EXTI interrupts into one vector.
+//
+// It technically doesn't need to be generic at all, except to satisfy the generic argument
+// of [Handler]. All EXTI interrupts eventually land in the same on_irq() function.
+pub struct InterruptHandler<T: crate::interrupt::typelevel::Interrupt> {
+    _phantom: PhantomData<T>,
 }
 
-foreach_exti_irq!(impl_irq);
+impl<T: InterruptType> Handler<T> for InterruptHandler<T> {
+    unsafe fn on_interrupt() {
+        on_irq()
+    }
+}
 
 trait SealedChannel {}
 
 /// EXTI channel trait.
 #[allow(private_bounds)]
 pub trait Channel: PeripheralType + SealedChannel + Sized {
-    /// Get the EXTI channel number.
+    /// EXTI channel number.
     fn number(&self) -> PinNumber;
+    /// [Enum-level Interrupt](InterruptEnum), which may be the same for multiple channels.
+    fn irq(&self) -> InterruptEnum;
+    /// [Type-level Interrupt](InterruptType), which may be the same for multiple channels.
+    type IRQ: InterruptType;
 }
 
-/// Type-erased EXTI channel.
+//Doc isn't hidden in order to surface the explanation to users, even though it's completely inoperable, not just deprecated.
+//Entire type along with doc can probably be removed after deprecation has appeared in a release once.
+/// Deprecated type-erased EXTI channel.
 ///
-/// This represents ownership over any EXTI channel, known at runtime.
+/// Support for AnyChannel was removed in order to support manually bindable EXTI interrupts via bind_interrupts; [ExtiInput::new()]
+/// must know the required IRQ at compile time, and therefore cannot support type-erased channels.
+#[deprecated = "type-erased EXTI channels are no longer supported, in order to support manually bindable EXTI interrupts (more info: https://github.com/embassy-rs/embassy/pull/4922)"]
 pub struct AnyChannel {
+    #[allow(unused)]
     number: PinNumber,
 }
 
-impl_peripheral!(AnyChannel);
-impl SealedChannel for AnyChannel {}
-impl Channel for AnyChannel {
-    fn number(&self) -> PinNumber {
-        self.number
-    }
-}
-
 macro_rules! impl_exti {
     ($type:ident, $number:expr) => {
-        impl SealedChannel for peripherals::$type {}
-        impl Channel for peripherals::$type {
+        impl SealedChannel for crate::peripherals::$type {}
+        impl Channel for crate::peripherals::$type {
             fn number(&self) -> PinNumber {
                 $number
             }
+            fn irq(&self) -> InterruptEnum {
+                crate::_generated::peripheral_interrupts::EXTI::$type::IRQ
+            }
+            type IRQ = crate::_generated::peripheral_interrupts::EXTI::$type;
         }
 
-        impl From<peripherals::$type> for AnyChannel {
-            fn from(val: peripherals::$type) -> Self {
-                Self {
-                    number: val.number() as PinNumber,
-                }
+        //Still here to surface deprecation messages to the user - remove when removing AnyChannel
+        #[allow(deprecated)]
+        impl From<crate::peripherals::$type> for AnyChannel {
+            fn from(_val: crate::peripherals::$type) -> Self {
+                Self { number: $number }
             }
         }
     };
diff --git a/embassy-stm32/src/flash/c.rs b/embassy-stm32/src/flash/c.rs
new file mode 100644
index 000000000..0ad1002b0
--- /dev/null
+++ b/embassy-stm32/src/flash/c.rs
@@ -0,0 +1,131 @@
+use core::ptr::write_volatile;
+use core::sync::atomic::{Ordering, fence};
+
+use cortex_m::interrupt;
+
+use super::{FlashSector, WRITE_SIZE};
+use crate::flash::Error;
+use crate::pac;
+
+pub(crate) unsafe fn lock() {
+    pac::FLASH.cr().modify(|w| w.set_lock(true));
+}
+pub(crate) unsafe fn unlock() {
+    // Wait, while the memory interface is busy.
+    wait_busy();
+
+    // Unlock flash
+    if pac::FLASH.cr().read().lock() {
+        pac::FLASH.keyr().write_value(0x4567_0123);
+        pac::FLASH.keyr().write_value(0xCDEF_89AB);
+    }
+}
+
+pub(crate) unsafe fn enable_blocking_write() {
+    assert_eq!(0, WRITE_SIZE % 4);
+    pac::FLASH.cr().write(|w| w.set_pg(true));
+}
+
+pub(crate) unsafe fn disable_blocking_write() {
+    pac::FLASH.cr().write(|w| w.set_pg(false));
+}
+
+pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
+    let mut address = start_address;
+    for val in buf.chunks(4) {
+        write_volatile(address as *mut u32, u32::from_le_bytes(unwrap!(val.try_into())));
+        address += val.len() as u32;
+
+        // prevents parallelism errors
+        fence(Ordering::SeqCst);
+    }
+
+    wait_ready_blocking()
+}
+
+pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
+    let idx = (sector.start - super::FLASH_BASE as u32) / super::BANK1_REGION.erase_size as u32;
+
+    #[cfg(feature = "defmt")]
+    defmt::trace!(
+        "STM32C0 Erase: addr=0x{:08x}, idx={}, erase_size={}",
+        sector.start,
+        idx,
+        super::BANK1_REGION.erase_size
+    );
+
+    wait_busy();
+    clear_all_err();
+
+    // Explicitly unlock before erase
+    unlock();
+
+    interrupt::free(|_| {
+        #[cfg(feature = "defmt")]
+        {
+            let cr_before = pac::FLASH.cr().read();
+            defmt::trace!("FLASH_CR before: 0x{:08x}", cr_before.0);
+        }
+
+        pac::FLASH.cr().modify(|w| {
+            w.set_per(true);
+            w.set_pnb(idx as u8);
+            w.set_strt(true);
+        });
+
+        #[cfg(feature = "defmt")]
+        {
+            let cr_after = pac::FLASH.cr().read();
+            defmt::trace!(
+                "FLASH_CR after: 0x{:08x}, PER={}, PNB={}, STRT={}",
+                cr_after.0,
+                cr_after.per(),
+                cr_after.pnb(),
+                cr_after.strt()
+            );
+        }
+    });
+
+    let ret: Result<(), Error> = wait_ready_blocking();
+
+    // Clear erase bit
+    pac::FLASH.cr().modify(|w| w.set_per(false));
+
+    // Explicitly lock after erase
+    lock();
+
+    // Extra wait to ensure operation completes
+    wait_busy();
+
+    ret
+}
+
+pub(crate) unsafe fn wait_ready_blocking() -> Result<(), Error> {
+    while pac::FLASH.sr().read().bsy() {}
+
+    let sr = pac::FLASH.sr().read();
+
+    if sr.progerr() {
+        return Err(Error::Prog);
+    }
+
+    if sr.wrperr() {
+        return Err(Error::Protected);
+    }
+
+    if sr.pgaerr() {
+        return Err(Error::Unaligned);
+    }
+
+    Ok(())
+}
+
+pub(crate) unsafe fn clear_all_err() {
+    // read and write back the same value.
+    // This clears all "write 1 to clear" bits.
+    pac::FLASH.sr().modify(|_| {});
+}
+
+fn wait_busy() {
+    while pac::FLASH.sr().read().bsy() {}
+}
diff --git a/embassy-stm32/src/flash/common.rs b/embassy-stm32/src/flash/common.rs
index b595938a6..60d00e766 100644
--- a/embassy-stm32/src/flash/common.rs
+++ b/embassy-stm32/src/flash/common.rs
@@ -102,7 +102,13 @@ pub(super) unsafe fn blocking_write(
     }
 
     let mut address = base + offset;
-    trace!("Writing {} bytes at 0x{:x}", bytes.len(), address);
+    trace!(
+        "Writing {} bytes at 0x{:x} (base=0x{:x}, offset=0x{:x})",
+        bytes.len(),
+        address,
+        base,
+        offset
+    );
 
     for chunk in bytes.chunks(WRITE_SIZE) {
         write_chunk(address, chunk)?;
diff --git a/embassy-stm32/src/flash/g.rs b/embassy-stm32/src/flash/g.rs
index d026541a4..d7ba2f571 100644
--- a/embassy-stm32/src/flash/g.rs
+++ b/embassy-stm32/src/flash/g.rs
@@ -44,7 +44,6 @@ pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE])
 }
 
 pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
-    let idx = (sector.start - super::FLASH_BASE as u32) / super::BANK1_REGION.erase_size as u32;
     wait_busy();
     clear_all_err();
 
@@ -54,9 +53,9 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
             #[cfg(any(flash_g0x0, flash_g0x1, flash_g4c3))]
             w.set_bker(sector.bank == crate::flash::FlashBank::Bank2);
             #[cfg(flash_g0x0)]
-            w.set_pnb(idx as u16);
+            w.set_pnb(sector.index_in_bank as u16);
             #[cfg(not(flash_g0x0))]
-            w.set_pnb(idx as u8);
+            w.set_pnb(sector.index_in_bank as u8);
             w.set_strt(true);
         });
     });
diff --git a/embassy-stm32/src/flash/h7.rs b/embassy-stm32/src/flash/h7.rs
index 8a43cce3f..b342f4a83 100644
--- a/embassy-stm32/src/flash/h7.rs
+++ b/embassy-stm32/src/flash/h7.rs
@@ -1,10 +1,31 @@
 use core::ptr::write_volatile;
 use core::sync::atomic::{Ordering, fence};
 
+use embassy_sync::waitqueue::AtomicWaker;
+use pac::flash::regs::Sr;
+
 use super::{BANK1_REGION, FLASH_REGIONS, FlashSector, WRITE_SIZE};
 use crate::flash::Error;
 use crate::pac;
 
+static WAKER: AtomicWaker = AtomicWaker::new();
+
+pub(crate) unsafe fn on_interrupt() {
+    // Clear IRQ flags
+    pac::FLASH.bank(0).ccr().write(|w| {
+        w.set_clr_eop(true);
+        w.set_clr_operr(true);
+    });
+    if is_dual_bank() {
+        pac::FLASH.bank(1).ccr().write(|w| {
+            w.set_clr_eop(true);
+            w.set_clr_operr(true);
+        });
+    }
+
+    WAKER.wake();
+}
+
 const fn is_dual_bank() -> bool {
     FLASH_REGIONS.len() >= 2
 }
@@ -29,12 +50,68 @@ pub(crate) unsafe fn unlock() {
     }
 }
 
+pub(crate) unsafe fn enable_write() {
+    enable_blocking_write();
+}
+
+pub(crate) unsafe fn disable_write() {
+    disable_blocking_write();
+}
+
 pub(crate) unsafe fn enable_blocking_write() {
     assert_eq!(0, WRITE_SIZE % 4);
 }
 
 pub(crate) unsafe fn disable_blocking_write() {}
 
+pub(crate) async unsafe fn write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
+    // We cannot have the write setup sequence in begin_write as it depends on the address
+    let bank = if start_address < BANK1_REGION.end() {
+        pac::FLASH.bank(0)
+    } else {
+        pac::FLASH.bank(1)
+    };
+    bank.cr().write(|w| {
+        w.set_pg(true);
+        #[cfg(flash_h7)]
+        w.set_psize(2); // 32 bits at once
+        w.set_eopie(true);
+        w.set_operrie(true);
+    });
+    cortex_m::asm::isb();
+    cortex_m::asm::dsb();
+    fence(Ordering::SeqCst);
+
+    let mut res = None;
+    let mut address = start_address;
+    for val in buf.chunks(4) {
+        write_volatile(address as *mut u32, u32::from_le_bytes(unwrap!(val.try_into())));
+        address += val.len() as u32;
+
+        res = Some(wait_ready(bank).await);
+        bank.sr().modify(|w| {
+            if w.eop() {
+                w.set_eop(true);
+            }
+        });
+        if unwrap!(res).is_err() {
+            break;
+        }
+    }
+
+    cortex_m::asm::isb();
+    cortex_m::asm::dsb();
+    fence(Ordering::SeqCst);
+
+    bank.cr().write(|w| {
+        w.set_pg(false);
+        w.set_eopie(false);
+        w.set_operrie(false);
+    });
+
+    unwrap!(res)
+}
+
 pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
     // We cannot have the write setup sequence in begin_write as it depends on the address
     let bank = if start_address < BANK1_REGION.end() {
@@ -77,6 +154,36 @@ pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE])
     unwrap!(res)
 }
 
+pub(crate) async unsafe fn erase_sector(sector: &FlashSector) -> Result<(), Error> {
+    let bank = pac::FLASH.bank(sector.bank as usize);
+    bank.cr().modify(|w| {
+        w.set_ser(true);
+        #[cfg(flash_h7)]
+        w.set_snb(sector.index_in_bank);
+        #[cfg(flash_h7ab)]
+        w.set_ssn(sector.index_in_bank);
+        w.set_eopie(true);
+        w.set_operrie(true);
+    });
+
+    bank.cr().modify(|w| {
+        w.set_start(true);
+    });
+
+    cortex_m::asm::isb();
+    cortex_m::asm::dsb();
+    fence(Ordering::SeqCst);
+
+    let ret: Result<(), Error> = wait_ready(bank).await;
+    bank.cr().modify(|w| {
+        w.set_ser(false);
+        w.set_eopie(false);
+        w.set_operrie(false);
+    });
+    bank_clear_all_err(bank);
+    ret
+}
+
 pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
     let bank = pac::FLASH.bank(sector.bank as usize);
     bank.cr().modify(|w| {
@@ -112,46 +219,59 @@ unsafe fn bank_clear_all_err(bank: pac::flash::Bank) {
     bank.sr().modify(|_| {});
 }
 
+async fn wait_ready(bank: pac::flash::Bank) -> Result<(), Error> {
+    use core::future::poll_fn;
+    use core::task::Poll;
+
+    poll_fn(|cx| {
+        WAKER.register(cx.waker());
+
+        let sr = bank.sr().read();
+        if !sr.bsy() && !sr.qw() {
+            Poll::Ready(get_result(sr))
+        } else {
+            return Poll::Pending;
+        }
+    })
+    .await
+}
+
 unsafe fn blocking_wait_ready(bank: pac::flash::Bank) -> Result<(), Error> {
     loop {
         let sr = bank.sr().read();
 
         if !sr.bsy() && !sr.qw() {
-            if sr.wrperr() {
-                return Err(Error::Protected);
-            }
-            if sr.pgserr() {
-                error!("pgserr");
-                return Err(Error::Seq);
-            }
-            if sr.incerr() {
-                // writing to a different address when programming 256 bit word was not finished
-                error!("incerr");
-                return Err(Error::Seq);
-            }
-            if sr.crcrderr() {
-                error!("crcrderr");
-                return Err(Error::Seq);
-            }
-            if sr.operr() {
-                return Err(Error::Prog);
-            }
-            if sr.sneccerr1() {
-                // single ECC error
-                return Err(Error::Prog);
-            }
-            if sr.dbeccerr() {
-                // double ECC error
-                return Err(Error::Prog);
-            }
-            if sr.rdperr() {
-                return Err(Error::Protected);
-            }
-            if sr.rdserr() {
-                return Err(Error::Protected);
-            }
-
-            return Ok(());
+            return get_result(sr);
         }
     }
 }
+
+fn get_result(sr: Sr) -> Result<(), Error> {
+    if sr.wrperr() {
+        Err(Error::Protected)
+    } else if sr.pgserr() {
+        error!("pgserr");
+        Err(Error::Seq)
+    } else if sr.incerr() {
+        // writing to a different address when programming 256 bit word was not finished
+        error!("incerr");
+        Err(Error::Seq)
+    } else if sr.crcrderr() {
+        error!("crcrderr");
+        Err(Error::Seq)
+    } else if sr.operr() {
+        Err(Error::Prog)
+    } else if sr.sneccerr1() {
+        // single ECC error
+        Err(Error::Prog)
+    } else if sr.dbeccerr() {
+        // double ECC error
+        Err(Error::Prog)
+    } else if sr.rdperr() {
+        Err(Error::Protected)
+    } else if sr.rdserr() {
+        Err(Error::Protected)
+    } else {
+        Ok(())
+    }
+}
diff --git a/embassy-stm32/src/flash/mod.rs b/embassy-stm32/src/flash/mod.rs
index 3e74d857a..6211a37b7 100644
--- a/embassy-stm32/src/flash/mod.rs
+++ b/embassy-stm32/src/flash/mod.rs
@@ -1,14 +1,14 @@
 //! Flash memory (FLASH)
 use embedded_storage::nor_flash::{NorFlashError, NorFlashErrorKind};
 
-#[cfg(flash_f4)]
+#[cfg(any(flash_f4, flash_h7, flash_h7ab))]
 mod asynch;
 #[cfg(flash)]
 mod common;
 #[cfg(eeprom)]
 mod eeprom;
 
-#[cfg(flash_f4)]
+#[cfg(any(flash_f4, flash_h7, flash_h7ab))]
 pub use asynch::InterruptHandler;
 #[cfg(flash)]
 pub use common::*;
@@ -99,6 +99,7 @@ compile_error!("The 'eeprom' cfg is enabled for a non-L0/L1 chip family. This is
 #[cfg_attr(flash_f4, path = "f4.rs")]
 #[cfg_attr(flash_f7, path = "f7.rs")]
 #[cfg_attr(any(flash_g0x0, flash_g0x1, flash_g4c2, flash_g4c3, flash_g4c4), path = "g.rs")]
+#[cfg_attr(flash_c0, path = "c.rs")]
 #[cfg_attr(flash_h7, path = "h7.rs")]
 #[cfg_attr(flash_h7ab, path = "h7.rs")]
 #[cfg_attr(any(flash_u5, flash_wba), path = "u5.rs")]
@@ -108,7 +109,7 @@ compile_error!("The 'eeprom' cfg is enabled for a non-L0/L1 chip family. This is
 #[cfg_attr(
     not(any(
         flash_l0, flash_l1, flash_l4, flash_l5, flash_wl, flash_wb, flash_f0, flash_f1, flash_f2, flash_f3, flash_f4,
-        flash_f7, flash_g0x0, flash_g0x1, flash_g4c2, flash_g4c3, flash_g4c4, flash_h7, flash_h7ab, flash_u5,
+        flash_f7, flash_g0x0, flash_g0x1, flash_g4c2, flash_g4c3, flash_g4c4, flash_c0, flash_h7, flash_h7ab, flash_u5,
         flash_wba, flash_h50, flash_u0, flash_h5,
     )),
     path = "other.rs"
diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs
index 17c5a9962..e7d4e9ad3 100644
--- a/embassy-stm32/src/gpio.rs
+++ b/embassy-stm32/src/gpio.rs
@@ -812,15 +812,19 @@ pub type PinNumber = u8;
 #[cfg(stm32n6)]
 pub type PinNumber = u16;
 
-/// GPIO pin trait.
+/// Pin that can be used to configure an [ExtiInput](crate::exti::ExtiInput). This trait is lost when converting to [AnyPin].
+#[cfg(feature = "exti")]
 #[allow(private_bounds)]
-pub trait Pin: PeripheralType + Into<AnyPin> + SealedPin + Sized + 'static {
+pub trait ExtiPin: PeripheralType + SealedPin {
     /// EXTI channel assigned to this pin.
     ///
     /// For example, PC4 uses EXTI4.
-    #[cfg(feature = "exti")]
     type ExtiChannel: crate::exti::Channel;
+}
 
+/// GPIO pin trait.
+#[allow(private_bounds)]
+pub trait Pin: PeripheralType + Into<AnyPin> + SealedPin + Sized + 'static {
     /// Number of the pin within the port (0..31)
     #[inline]
     fn pin(&self) -> PinNumber {
@@ -834,7 +838,7 @@ pub trait Pin: PeripheralType + Into<AnyPin> + SealedPin + Sized + 'static {
     }
 }
 
-/// Type-erased GPIO pin
+/// Type-erased GPIO pin.
 pub struct AnyPin {
     pin_port: PinNumber,
 }
@@ -862,10 +866,7 @@ impl AnyPin {
 }
 
 impl_peripheral!(AnyPin);
-impl Pin for AnyPin {
-    #[cfg(feature = "exti")]
-    type ExtiChannel = crate::exti::AnyChannel;
-}
+impl Pin for AnyPin {}
 impl SealedPin for AnyPin {
     #[inline]
     fn pin_port(&self) -> PinNumber {
@@ -878,7 +879,9 @@ impl SealedPin for AnyPin {
 foreach_pin!(
     ($pin_name:ident, $port_name:ident, $port_num:expr, $pin_num:expr, $exti_ch:ident) => {
         impl Pin for peripherals::$pin_name {
-            #[cfg(feature = "exti")]
+        }
+        #[cfg(feature = "exti")]
+        impl ExtiPin for peripherals::$pin_name {
             type ExtiChannel = peripherals::$exti_ch;
         }
         impl SealedPin for peripherals::$pin_name {
diff --git a/embassy-stm32/src/hsem/mod.rs b/embassy-stm32/src/hsem/mod.rs
index 4d3a5d68d..e62de0454 100644
--- a/embassy-stm32/src/hsem/mod.rs
+++ b/embassy-stm32/src/hsem/mod.rs
@@ -1,14 +1,22 @@
 //! Hardware Semaphore (HSEM)
 
+use core::future::poll_fn;
+use core::marker::PhantomData;
+use core::sync::atomic::{Ordering, compiler_fence};
+use core::task::Poll;
+
+#[cfg(all(stm32wb, feature = "low-power"))]
+use critical_section::CriticalSection;
 use embassy_hal_internal::PeripheralType;
+use embassy_sync::waitqueue::AtomicWaker;
 
 // TODO: This code works for all HSEM implemenations except for the STM32WBA52/4/5xx MCUs.
 // Those MCUs have a different HSEM implementation (Secure semaphore lock support,
 // Privileged / unprivileged semaphore lock support, Semaphore lock protection via semaphore attribute),
 // which is not yet supported by this code.
 use crate::Peri;
-use crate::pac;
 use crate::rcc::{self, RccPeripheral};
+use crate::{interrupt, pac};
 
 /// HSEM error.
 #[derive(Debug)]
@@ -41,63 +49,152 @@ pub enum CoreId {
     Core1 = 0x8,
 }
 
-/// Get the current core id
-/// This code assume that it is only executed on a Cortex-M M0+, M4 or M7 core.
-#[inline(always)]
-pub fn get_current_coreid() -> CoreId {
-    let cpuid = unsafe { cortex_m::peripheral::CPUID::PTR.read_volatile().base.read() };
-    match (cpuid & 0x000000F0) >> 4 {
-        #[cfg(any(stm32wb, stm32wl))]
-        0x0 => CoreId::Core1,
+impl CoreId {
+    /// Get the current core id
+    /// This code assume that it is only executed on a Cortex-M M0+, M4 or M7 core.
+    pub fn current() -> Self {
+        let cpuid = unsafe { cortex_m::peripheral::CPUID::PTR.read_volatile().base.read() };
+        match (cpuid & 0x000000F0) >> 4 {
+            #[cfg(any(stm32wb, stm32wl))]
+            0x0 => CoreId::Core1,
 
-        #[cfg(not(any(stm32h745, stm32h747, stm32h755, stm32h757)))]
-        0x4 => CoreId::Core0,
+            #[cfg(not(any(stm32h745, stm32h747, stm32h755, stm32h757)))]
+            0x4 => CoreId::Core0,
 
-        #[cfg(any(stm32h745, stm32h747, stm32h755, stm32h757))]
-        0x4 => CoreId::Core1,
+            #[cfg(any(stm32h745, stm32h747, stm32h755, stm32h757))]
+            0x4 => CoreId::Core1,
 
-        #[cfg(any(stm32h745, stm32h747, stm32h755, stm32h757))]
-        0x7 => CoreId::Core0,
-        _ => panic!("Unknown Cortex-M core"),
+            #[cfg(any(stm32h745, stm32h747, stm32h755, stm32h757))]
+            0x7 => CoreId::Core0,
+            _ => panic!("Unknown Cortex-M core"),
+        }
+    }
+
+    /// Translates the core ID to an index into the interrupt registers.
+    pub fn to_index(&self) -> usize {
+        match &self {
+            CoreId::Core0 => 0,
+            #[cfg(any(stm32h745, stm32h747, stm32h755, stm32h757, stm32wb, stm32wl))]
+            CoreId::Core1 => 1,
+        }
     }
 }
 
-/// Translates the core ID to an index into the interrupt registers.
-#[inline(always)]
-fn core_id_to_index(core: CoreId) -> usize {
-    match core {
-        CoreId::Core0 => 0,
-        #[cfg(any(stm32h745, stm32h747, stm32h755, stm32h757, stm32wb, stm32wl))]
-        CoreId::Core1 => 1,
+#[cfg(not(all(stm32wb, feature = "low-power")))]
+const PUB_CHANNELS: usize = 6;
+
+#[cfg(all(stm32wb, feature = "low-power"))]
+const PUB_CHANNELS: usize = 4;
+
+/// TX interrupt handler.
+pub struct HardwareSemaphoreInterruptHandler<T: Instance> {
+    _phantom: PhantomData<T>,
+}
+
+impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for HardwareSemaphoreInterruptHandler<T> {
+    unsafe fn on_interrupt() {
+        let core_id = CoreId::current();
+
+        for number in 0..5 {
+            if T::regs().isr(core_id.to_index()).read().isf(number as usize) {
+                T::regs()
+                    .icr(core_id.to_index())
+                    .write(|w| w.set_isc(number as usize, true));
+
+                T::regs()
+                    .ier(core_id.to_index())
+                    .modify(|w| w.set_ise(number as usize, false));
+
+                T::state().waker_for(number).wake();
+            }
+        }
     }
 }
 
-/// HSEM driver
-pub struct HardwareSemaphore<'d, T: Instance> {
-    _peri: Peri<'d, T>,
+/// Hardware semaphore mutex
+pub struct HardwareSemaphoreMutex<'a, T: Instance> {
+    index: u8,
+    process_id: u8,
+    _lifetime: PhantomData<&'a mut T>,
 }
 
-impl<'d, T: Instance> HardwareSemaphore<'d, T> {
-    /// Creates a new HardwareSemaphore instance.
-    pub fn new(peripheral: Peri<'d, T>) -> Self {
-        rcc::enable_and_reset::<T>();
+impl<'a, T: Instance> Drop for HardwareSemaphoreMutex<'a, T> {
+    fn drop(&mut self) {
+        HardwareSemaphoreChannel::<'a, T> {
+            index: self.index,
+            _lifetime: PhantomData,
+        }
+        .unlock(self.process_id);
+    }
+}
+
+/// Hardware semaphore channel
+pub struct HardwareSemaphoreChannel<'a, T: Instance> {
+    index: u8,
+    _lifetime: PhantomData<&'a mut T>,
+}
+
+impl<'a, T: Instance> HardwareSemaphoreChannel<'a, T> {
+    pub(crate) const fn new(number: u8) -> Self {
+        core::assert!(number > 0 && number <= 6);
+
+        Self {
+            index: number - 1,
+            _lifetime: PhantomData,
+        }
+    }
+
+    /// Locks the semaphore.
+    /// The 2-step lock procedure consists in a write to lock the semaphore, followed by a read to
+    /// check if the lock has been successful, carried out from the HSEM_Rx register.
+    pub async fn lock(&mut self, process_id: u8) -> HardwareSemaphoreMutex<'a, T> {
+        let core_id = CoreId::current();
+
+        poll_fn(|cx| {
+            T::state().waker_for(self.index).register(cx.waker());
+
+            compiler_fence(Ordering::SeqCst);
+
+            T::regs()
+                .ier(core_id.to_index())
+                .modify(|w| w.set_ise(self.index as usize, true));
+
+            match self.try_lock(process_id) {
+                Some(mutex) => Poll::Ready(mutex),
+                None => Poll::Pending,
+            }
+        })
+        .await
+    }
 
-        HardwareSemaphore { _peri: peripheral }
+    /// Try to lock the semaphor
+    /// The 2-step lock procedure consists in a write to lock the semaphore, followed by a read to
+    /// check if the lock has been successful, carried out from the HSEM_Rx register.
+    pub fn try_lock(&mut self, process_id: u8) -> Option<HardwareSemaphoreMutex<'a, T>> {
+        if self.two_step_lock(process_id).is_ok() {
+            Some(HardwareSemaphoreMutex {
+                index: self.index,
+                process_id: process_id,
+                _lifetime: PhantomData,
+            })
+        } else {
+            None
+        }
     }
 
     /// Locks the semaphore.
     /// The 2-step lock procedure consists in a write to lock the semaphore, followed by a read to
     /// check if the lock has been successful, carried out from the HSEM_Rx register.
-    pub fn two_step_lock(&mut self, sem_id: u8, process_id: u8) -> Result<(), HsemError> {
-        T::regs().r(sem_id as usize).write(|w| {
+    pub fn two_step_lock(&mut self, process_id: u8) -> Result<(), HsemError> {
+        T::regs().r(self.index as usize).write(|w| {
             w.set_procid(process_id);
-            w.set_coreid(get_current_coreid() as u8);
+            w.set_coreid(CoreId::current() as u8);
             w.set_lock(true);
         });
-        let reg = T::regs().r(sem_id as usize).read();
+        let reg = T::regs().r(self.index as usize).read();
         match (
             reg.lock(),
-            reg.coreid() == get_current_coreid() as u8,
+            reg.coreid() == CoreId::current() as u8,
             reg.procid() == process_id,
         ) {
             (true, true, true) => Ok(()),
@@ -108,9 +205,9 @@ impl<'d, T: Instance> HardwareSemaphore<'d, T> {
     /// Locks the semaphore.
     /// The 1-step procedure consists in a read to lock and check the semaphore in a single step,
     /// carried out from the HSEM_RLRx register.
-    pub fn one_step_lock(&mut self, sem_id: u8) -> Result<(), HsemError> {
-        let reg = T::regs().rlr(sem_id as usize).read();
-        match (reg.lock(), reg.coreid() == get_current_coreid() as u8, reg.procid()) {
+    pub fn one_step_lock(&mut self) -> Result<(), HsemError> {
+        let reg = T::regs().rlr(self.index as usize).read();
+        match (reg.lock(), reg.coreid() == CoreId::current() as u8, reg.procid()) {
             (false, true, 0) => Ok(()),
             _ => Err(HsemError::LockFailed),
         }
@@ -119,14 +216,60 @@ impl<'d, T: Instance> HardwareSemaphore<'d, T> {
     /// Unlocks the semaphore.
     /// Unlocking a semaphore is a protected process, to prevent accidental clearing by a AHB bus
     /// core ID or by a process not having the semaphore lock right.
-    pub fn unlock(&mut self, sem_id: u8, process_id: u8) {
-        T::regs().r(sem_id as usize).write(|w| {
+    pub fn unlock(&mut self, process_id: u8) {
+        T::regs().r(self.index as usize).write(|w| {
             w.set_procid(process_id);
-            w.set_coreid(get_current_coreid() as u8);
+            w.set_coreid(CoreId::current() as u8);
             w.set_lock(false);
         });
     }
 
+    /// Return the channel number
+    pub const fn channel(&self) -> u8 {
+        self.index + 1
+    }
+}
+
+/// HSEM driver
+pub struct HardwareSemaphore<T: Instance> {
+    _type: PhantomData<T>,
+}
+
+impl<T: Instance> HardwareSemaphore<T> {
+    /// Creates a new HardwareSemaphore instance.
+    pub fn new<'d>(
+        _peripheral: Peri<'d, T>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, HardwareSemaphoreInterruptHandler<T>> + 'd,
+    ) -> Self {
+        rcc::enable_and_reset::<T>();
+
+        HardwareSemaphore { _type: PhantomData }
+    }
+
+    /// Get a single channel, and keep the global struct
+    pub const fn channel_for<'a>(&'a mut self, number: u8) -> HardwareSemaphoreChannel<'a, T> {
+        #[cfg(all(stm32wb, feature = "low-power"))]
+        core::assert!(number != 3 && number != 4);
+
+        HardwareSemaphoreChannel::new(number)
+    }
+
+    /// Split the global struct into channels
+    ///
+    /// If using low-power mode, channels 3 and 4 will not be returned
+    pub const fn split<'a>(self) -> [HardwareSemaphoreChannel<'a, T>; PUB_CHANNELS] {
+        [
+            HardwareSemaphoreChannel::new(1),
+            HardwareSemaphoreChannel::new(2),
+            #[cfg(not(all(stm32wb, feature = "low-power")))]
+            HardwareSemaphoreChannel::new(3),
+            #[cfg(not(all(stm32wb, feature = "low-power")))]
+            HardwareSemaphoreChannel::new(4),
+            HardwareSemaphoreChannel::new(5),
+            HardwareSemaphoreChannel::new(6),
+        ]
+    }
+
     /// Unlocks all semaphores.
     /// All semaphores locked by a COREID can be unlocked at once by using the HSEM_CR
     /// register. Write COREID and correct KEY value in HSEM_CR. All locked semaphores with a
@@ -138,11 +281,6 @@ impl<'d, T: Instance> HardwareSemaphore<'d, T> {
         });
     }
 
-    /// Checks if the semaphore is locked.
-    pub fn is_semaphore_locked(&self, sem_id: u8) -> bool {
-        T::regs().r(sem_id as usize).read().lock()
-    }
-
     /// Sets the clear (unlock) key
     pub fn set_clear_key(&mut self, key: u16) {
         T::regs().keyr().modify(|w| w.set_key(key));
@@ -152,38 +290,61 @@ impl<'d, T: Instance> HardwareSemaphore<'d, T> {
     pub fn get_clear_key(&mut self) -> u16 {
         T::regs().keyr().read().key()
     }
+}
 
-    /// Sets the interrupt enable bit for the semaphore.
-    pub fn enable_interrupt(&mut self, core_id: CoreId, sem_x: usize, enable: bool) {
-        T::regs()
-            .ier(core_id_to_index(core_id))
-            .modify(|w| w.set_ise(sem_x, enable));
+#[cfg(all(stm32wb, feature = "low-power"))]
+pub(crate) fn init_hsem(cs: CriticalSection) {
+    rcc::enable_and_reset_with_cs::<crate::peripherals::HSEM>(cs);
+
+    unsafe {
+        crate::rcc::REFCOUNT_STOP1 = 0;
+        crate::rcc::REFCOUNT_STOP2 = 0;
     }
+}
 
-    /// Gets the interrupt flag for the semaphore.
-    pub fn is_interrupt_active(&mut self, core_id: CoreId, sem_x: usize) -> bool {
-        T::regs().isr(core_id_to_index(core_id)).read().isf(sem_x)
+struct State {
+    wakers: [AtomicWaker; 6],
+}
+
+impl State {
+    const fn new() -> Self {
+        Self {
+            wakers: [const { AtomicWaker::new() }; 6],
+        }
     }
 
-    /// Clears the interrupt flag for the semaphore.
-    pub fn clear_interrupt(&mut self, core_id: CoreId, sem_x: usize) {
-        T::regs()
-            .icr(core_id_to_index(core_id))
-            .write(|w| w.set_isc(sem_x, false));
+    const fn waker_for(&self, index: u8) -> &AtomicWaker {
+        &self.wakers[index as usize]
     }
 }
 
 trait SealedInstance {
     fn regs() -> pac::hsem::Hsem;
+    fn state() -> &'static State;
 }
 
 /// HSEM instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + Send + 'static {}
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + Send + 'static {
+    /// Interrupt for this peripheral.
+    type Interrupt: interrupt::typelevel::Interrupt;
+}
 
 impl SealedInstance for crate::peripherals::HSEM {
     fn regs() -> crate::pac::hsem::Hsem {
         crate::pac::HSEM
     }
+
+    fn state() -> &'static State {
+        static STATE: State = State::new();
+        &STATE
+    }
 }
-impl Instance for crate::peripherals::HSEM {}
+
+foreach_interrupt!(
+    ($inst:ident, hsem, $block:ident, $signal_name:ident, $irq:ident) => {
+        impl Instance for crate::peripherals::$inst {
+            type Interrupt = crate::interrupt::typelevel::$irq;
+        }
+    };
+);
diff --git a/embassy-stm32/src/hspi/mod.rs b/embassy-stm32/src/hspi/mod.rs
index 69baa708e..1d3560678 100644
--- a/embassy-stm32/src/hspi/mod.rs
+++ b/embassy-stm32/src/hspi/mod.rs
@@ -391,7 +391,7 @@ impl<'d, T: Instance, M: PeriMode> Hspi<'d, T, M> {
         while T::REGS.sr().read().busy() {}
 
         T::REGS.cr().modify(|w| {
-            w.set_fmode(0.into());
+            w.set_fmode(FunctionalMode::IndirectWrite.into());
         });
 
         // Configure alternate bytes
@@ -498,7 +498,8 @@ impl<'d, T: Instance, M: PeriMode> Hspi<'d, T, M> {
             w.set_dmaen(false);
         });
 
-        self.configure_command(&transaction, Some(buf.len()))?;
+        let transfer_size_bytes = buf.len() * W::size().bytes();
+        self.configure_command(&transaction, Some(transfer_size_bytes))?;
 
         let current_address = T::REGS.ar().read().address();
         let current_instruction = T::REGS.ir().read().instruction();
@@ -537,7 +538,8 @@ impl<'d, T: Instance, M: PeriMode> Hspi<'d, T, M> {
             w.set_dmaen(false);
         });
 
-        self.configure_command(&transaction, Some(buf.len()))?;
+        let transfer_size_bytes = buf.len() * W::size().bytes();
+        self.configure_command(&transaction, Some(transfer_size_bytes))?;
 
         T::REGS
             .cr()
@@ -767,7 +769,8 @@ impl<'d, T: Instance> Hspi<'d, T, Async> {
         // Wait for peripheral to be free
         while T::REGS.sr().read().busy() {}
 
-        self.configure_command(&transaction, Some(buf.len()))?;
+        let transfer_size_bytes = buf.len() * W::size().bytes();
+        self.configure_command(&transaction, Some(transfer_size_bytes))?;
 
         let current_address = T::REGS.ar().read().address();
         let current_instruction = T::REGS.ir().read().instruction();
@@ -782,16 +785,18 @@ impl<'d, T: Instance> Hspi<'d, T, Async> {
             T::REGS.ar().write(|v| v.set_address(current_address));
         }
 
-        let transfer = unsafe {
-            self.dma
-                .as_mut()
-                .unwrap()
-                .read(T::REGS.dr().as_ptr() as *mut W, buf, Default::default())
-        };
+        for chunk in buf.chunks_mut(0xFFFF / W::size().bytes()) {
+            let transfer = unsafe {
+                self.dma
+                    .as_mut()
+                    .unwrap()
+                    .read(T::REGS.dr().as_ptr() as *mut W, chunk, Default::default())
+            };
 
-        T::REGS.cr().modify(|w| w.set_dmaen(true));
+            T::REGS.cr().modify(|w| w.set_dmaen(true));
 
-        transfer.blocking_wait();
+            transfer.blocking_wait();
+        }
 
         finish_dma(T::REGS);
 
@@ -807,21 +812,24 @@ impl<'d, T: Instance> Hspi<'d, T, Async> {
         // Wait for peripheral to be free
         while T::REGS.sr().read().busy() {}
 
-        self.configure_command(&transaction, Some(buf.len()))?;
+        let transfer_size_bytes = buf.len() * W::size().bytes();
+        self.configure_command(&transaction, Some(transfer_size_bytes))?;
         T::REGS
             .cr()
             .modify(|v| v.set_fmode(FunctionalMode::IndirectWrite.into()));
 
-        let transfer = unsafe {
-            self.dma
-                .as_mut()
-                .unwrap()
-                .write(buf, T::REGS.dr().as_ptr() as *mut W, Default::default())
-        };
+        for chunk in buf.chunks(0xFFFF / W::size().bytes()) {
+            let transfer = unsafe {
+                self.dma
+                    .as_mut()
+                    .unwrap()
+                    .write(chunk, T::REGS.dr().as_ptr() as *mut W, Default::default())
+            };
 
-        T::REGS.cr().modify(|w| w.set_dmaen(true));
+            T::REGS.cr().modify(|w| w.set_dmaen(true));
 
-        transfer.blocking_wait();
+            transfer.blocking_wait();
+        }
 
         finish_dma(T::REGS);
 
@@ -837,7 +845,8 @@ impl<'d, T: Instance> Hspi<'d, T, Async> {
         // Wait for peripheral to be free
         while T::REGS.sr().read().busy() {}
 
-        self.configure_command(&transaction, Some(buf.len()))?;
+        let transfer_size_bytes = buf.len() * W::size().bytes();
+        self.configure_command(&transaction, Some(transfer_size_bytes))?;
 
         let current_address = T::REGS.ar().read().address();
         let current_instruction = T::REGS.ir().read().instruction();
@@ -852,16 +861,18 @@ impl<'d, T: Instance> Hspi<'d, T, Async> {
             T::REGS.ar().write(|v| v.set_address(current_address));
         }
 
-        let transfer = unsafe {
-            self.dma
-                .as_mut()
-                .unwrap()
-                .read(T::REGS.dr().as_ptr() as *mut W, buf, Default::default())
-        };
+        for chunk in buf.chunks_mut(0xFFFF / W::size().bytes()) {
+            let transfer = unsafe {
+                self.dma
+                    .as_mut()
+                    .unwrap()
+                    .read(T::REGS.dr().as_ptr() as *mut W, chunk, Default::default())
+            };
 
-        T::REGS.cr().modify(|w| w.set_dmaen(true));
+            T::REGS.cr().modify(|w| w.set_dmaen(true));
 
-        transfer.await;
+            transfer.await;
+        }
 
         finish_dma(T::REGS);
 
@@ -877,21 +888,25 @@ impl<'d, T: Instance> Hspi<'d, T, Async> {
         // Wait for peripheral to be free
         while T::REGS.sr().read().busy() {}
 
-        self.configure_command(&transaction, Some(buf.len()))?;
+        let transfer_size_bytes = buf.len() * W::size().bytes();
+        self.configure_command(&transaction, Some(transfer_size_bytes))?;
         T::REGS
             .cr()
             .modify(|v| v.set_fmode(FunctionalMode::IndirectWrite.into()));
 
-        let transfer = unsafe {
-            self.dma
-                .as_mut()
-                .unwrap()
-                .write(buf, T::REGS.dr().as_ptr() as *mut W, Default::default())
-        };
+        // TODO: implement this using a LinkedList DMA to offload the whole transfer off the CPU.
+        for chunk in buf.chunks(0xFFFF / W::size().bytes()) {
+            let transfer = unsafe {
+                self.dma
+                    .as_mut()
+                    .unwrap()
+                    .write(chunk, T::REGS.dr().as_ptr() as *mut W, Default::default())
+            };
 
-        T::REGS.cr().modify(|w| w.set_dmaen(true));
+            T::REGS.cr().modify(|w| w.set_dmaen(true));
 
-        transfer.await;
+            transfer.await;
+        }
 
         finish_dma(T::REGS);
 
diff --git a/embassy-stm32/src/i2c/v2.rs b/embassy-stm32/src/i2c/v2.rs
index 4527e55b9..b2ba94e21 100644
--- a/embassy-stm32/src/i2c/v2.rs
+++ b/embassy-stm32/src/i2c/v2.rs
@@ -98,6 +98,27 @@ pub(crate) unsafe fn on_interrupt<T: Instance>() {
 }
 
 impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
+    #[inline]
+    fn to_reload(reload: bool) -> i2c::vals::Reload {
+        if reload {
+            i2c::vals::Reload::NOT_COMPLETED
+        } else {
+            i2c::vals::Reload::COMPLETED
+        }
+    }
+
+    /// Calculate total bytes in a group of operations
+    #[inline]
+    fn total_operation_bytes(operations: &[Operation<'_>]) -> usize {
+        operations
+            .iter()
+            .map(|op| match op {
+                Operation::Write(buf) => buf.len(),
+                Operation::Read(buf) => buf.len(),
+            })
+            .sum()
+    }
+
     pub(crate) fn init(&mut self, config: Config) {
         self.info.regs.cr1().modify(|reg| {
             reg.set_pe(false);
@@ -147,12 +168,6 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
         // `buffer`. The START bit can be set even if the bus
         // is BUSY or I2C is in slave mode.
 
-        let reload = if reload {
-            i2c::vals::Reload::NOT_COMPLETED
-        } else {
-            i2c::vals::Reload::COMPLETED
-        };
-
         info.regs.cr2().modify(|w| {
             w.set_sadd(address.addr() << 1);
             w.set_add10(address.add_mode());
@@ -160,7 +175,7 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
             w.set_nbytes(length as u8);
             w.set_start(true);
             w.set_autoend(stop.autoend());
-            w.set_reload(reload);
+            w.set_reload(Self::to_reload(reload));
         });
 
         Ok(())
@@ -172,28 +187,25 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
         length: usize,
         stop: Stop,
         reload: bool,
+        restart: bool,
         timeout: Timeout,
     ) -> Result<(), Error> {
         assert!(length < 256);
 
-        // Wait for any previous address sequence to end
-        // automatically. This could be up to 50% of a bus
-        // cycle (ie. up to 0.5/freq)
-        while info.regs.cr2().read().start() {
-            timeout.check()?;
-        }
+        if !restart {
+            // Wait for any previous address sequence to end
+            // automatically. This could be up to 50% of a bus
+            // cycle (ie. up to 0.5/freq)
+            while info.regs.cr2().read().start() {
+                timeout.check()?;
+            }
 
-        // Wait for the bus to be free
-        while info.regs.isr().read().busy() {
-            timeout.check()?;
+            // Wait for the bus to be free
+            while info.regs.isr().read().busy() {
+                timeout.check()?;
+            }
         }
 
-        let reload = if reload {
-            i2c::vals::Reload::NOT_COMPLETED
-        } else {
-            i2c::vals::Reload::COMPLETED
-        };
-
         // Set START and prepare to send `bytes`. The
         // START bit can be set even if the bus is BUSY or
         // I2C is in slave mode.
@@ -204,28 +216,36 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
             w.set_nbytes(length as u8);
             w.set_start(true);
             w.set_autoend(stop.autoend());
-            w.set_reload(reload);
+            w.set_reload(Self::to_reload(reload));
         });
 
         Ok(())
     }
 
-    fn reload(info: &'static Info, length: usize, will_reload: bool, timeout: Timeout) -> Result<(), Error> {
+    fn reload(
+        info: &'static Info,
+        length: usize,
+        will_reload: bool,
+        stop: Stop,
+        timeout: Timeout,
+    ) -> Result<(), Error> {
         assert!(length < 256 && length > 0);
 
-        while !info.regs.isr().read().tcr() {
+        // Wait for either TCR (Transfer Complete Reload) or TC (Transfer Complete)
+        // TCR occurs when RELOAD=1, TC occurs when RELOAD=0
+        // Both indicate the peripheral is ready for the next transfer
+        loop {
+            let isr = info.regs.isr().read();
+            if isr.tcr() || isr.tc() {
+                break;
+            }
             timeout.check()?;
         }
 
-        let will_reload = if will_reload {
-            i2c::vals::Reload::NOT_COMPLETED
-        } else {
-            i2c::vals::Reload::COMPLETED
-        };
-
         info.regs.cr2().modify(|w| {
             w.set_nbytes(length as u8);
-            w.set_reload(will_reload);
+            w.set_reload(Self::to_reload(will_reload));
+            w.set_autoend(stop.autoend());
         });
 
         Ok(())
@@ -369,7 +389,9 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
         loop {
             let isr = self.info.regs.isr().read();
             self.error_occurred(&isr, timeout)?;
-            if isr.tc() {
+            // Wait for either TC or TCR - both indicate transfer completion
+            // TCR occurs when RELOAD=1, TC occurs when RELOAD=0
+            if isr.tc() || isr.tcr() {
                 return Ok(());
             }
             timeout.check()?;
@@ -396,14 +418,20 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
             address,
             read.len().min(255),
             Stop::Automatic,
-            last_chunk_idx != 0,
+            last_chunk_idx != 0, // reload
             restart,
             timeout,
         )?;
 
         for (number, chunk) in read.chunks_mut(255).enumerate() {
             if number != 0 {
-                Self::reload(self.info, chunk.len(), number != last_chunk_idx, timeout)?;
+                Self::reload(
+                    self.info,
+                    chunk.len(),
+                    number != last_chunk_idx,
+                    Stop::Automatic,
+                    timeout,
+                )?;
             }
 
             for byte in chunk {
@@ -441,6 +469,7 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
             write.len().min(255),
             Stop::Software,
             last_chunk_idx != 0,
+            false, // restart
             timeout,
         ) {
             if send_stop {
@@ -451,7 +480,13 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
 
         for (number, chunk) in write.chunks(255).enumerate() {
             if number != 0 {
-                Self::reload(self.info, chunk.len(), number != last_chunk_idx, timeout)?;
+                Self::reload(
+                    self.info,
+                    chunk.len(),
+                    number != last_chunk_idx,
+                    Stop::Software,
+                    timeout,
+                )?;
             }
 
             for byte in chunk {
@@ -507,9 +542,215 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
     ///
     /// [transaction contract]: embedded_hal_1::i2c::I2c::transaction
     pub fn blocking_transaction(&mut self, addr: u8, operations: &mut [Operation<'_>]) -> Result<(), Error> {
-        let _ = addr;
-        let _ = operations;
-        todo!()
+        if operations.is_empty() {
+            return Err(Error::ZeroLengthTransfer);
+        }
+
+        let address = addr.into();
+        let timeout = self.timeout();
+
+        // Group consecutive operations of the same type
+        let mut op_idx = 0;
+        let mut is_first_group = true;
+
+        while op_idx < operations.len() {
+            // Determine the type of current group and find all consecutive operations of same type
+            let is_read = matches!(operations[op_idx], Operation::Read(_));
+            let group_start = op_idx;
+
+            // Find end of this group (consecutive operations of same type)
+            while op_idx < operations.len() && matches!(operations[op_idx], Operation::Read(_)) == is_read {
+                op_idx += 1;
+            }
+            let group_end = op_idx;
+            let is_last_group = op_idx >= operations.len();
+
+            // Execute this group of operations
+            if is_read {
+                self.execute_read_group(
+                    address,
+                    &mut operations[group_start..group_end],
+                    is_first_group,
+                    is_last_group,
+                    timeout,
+                )?;
+            } else {
+                self.execute_write_group(
+                    address,
+                    &operations[group_start..group_end],
+                    is_first_group,
+                    is_last_group,
+                    timeout,
+                )?;
+            }
+
+            is_first_group = false;
+        }
+
+        Ok(())
+    }
+
+    fn execute_write_group(
+        &mut self,
+        address: Address,
+        operations: &[Operation<'_>],
+        is_first_group: bool,
+        is_last_group: bool,
+        timeout: Timeout,
+    ) -> Result<(), Error> {
+        // Calculate total bytes across all operations in this group
+        let total_bytes = Self::total_operation_bytes(operations);
+
+        if total_bytes == 0 {
+            // Handle empty write group - just send address
+            if is_first_group {
+                Self::master_write(self.info, address, 0, Stop::Software, false, !is_first_group, timeout)?;
+            }
+            if is_last_group {
+                self.master_stop();
+            }
+            return Ok(());
+        }
+
+        let mut total_remaining = total_bytes;
+        let mut first_chunk = true;
+
+        for operation in operations {
+            if let Operation::Write(buffer) = operation {
+                for chunk in buffer.chunks(255) {
+                    let chunk_len = chunk.len();
+                    total_remaining -= chunk_len;
+                    let is_last_chunk = total_remaining == 0;
+                    let will_reload = !is_last_chunk;
+
+                    if first_chunk {
+                        // First chunk: initiate transfer
+                        // If not first group, use RESTART instead of START
+                        Self::master_write(
+                            self.info,
+                            address,
+                            chunk_len,
+                            Stop::Software,
+                            will_reload,
+                            !is_first_group,
+                            timeout,
+                        )?;
+                        first_chunk = false;
+                    } else {
+                        // Subsequent chunks: use reload
+                        // Always use Software stop for writes
+                        Self::reload(self.info, chunk_len, will_reload, Stop::Software, timeout)?;
+                    }
+
+                    // Send data bytes
+                    for byte in chunk {
+                        self.wait_txis(timeout)?;
+                        self.info.regs.txdr().write(|w| w.set_txdata(*byte));
+                    }
+                }
+            }
+        }
+
+        // Wait for transfer to complete
+        if is_last_group {
+            self.wait_tc(timeout)?;
+            self.master_stop();
+            self.wait_stop(timeout)?;
+        } else {
+            // Wait for TC before next group (enables RESTART)
+            self.wait_tc(timeout)?;
+        }
+
+        Ok(())
+    }
+
+    fn execute_read_group(
+        &mut self,
+        address: Address,
+        operations: &mut [Operation<'_>],
+        is_first_group: bool,
+        is_last_group: bool,
+        timeout: Timeout,
+    ) -> Result<(), Error> {
+        // Calculate total bytes across all operations in this group
+        let total_bytes = Self::total_operation_bytes(operations);
+
+        if total_bytes == 0 {
+            // Handle empty read group
+            if is_first_group {
+                Self::master_read(
+                    self.info,
+                    address,
+                    0,
+                    if is_last_group { Stop::Automatic } else { Stop::Software },
+                    false, // reload
+                    !is_first_group,
+                    timeout,
+                )?;
+            }
+            if is_last_group {
+                self.wait_stop(timeout)?;
+            }
+            return Ok(());
+        }
+
+        let mut total_remaining = total_bytes;
+        let mut first_chunk = true;
+
+        for operation in operations {
+            if let Operation::Read(buffer) = operation {
+                for chunk in buffer.chunks_mut(255) {
+                    let chunk_len = chunk.len();
+                    total_remaining -= chunk_len;
+                    let is_last_chunk = total_remaining == 0;
+                    let will_reload = !is_last_chunk;
+
+                    if first_chunk {
+                        // First chunk: initiate transfer
+                        let stop = if is_last_group && is_last_chunk {
+                            Stop::Automatic
+                        } else {
+                            Stop::Software
+                        };
+
+                        Self::master_read(
+                            self.info,
+                            address,
+                            chunk_len,
+                            stop,
+                            will_reload,
+                            !is_first_group, // restart if not first group
+                            timeout,
+                        )?;
+                        first_chunk = false;
+                    } else {
+                        // Subsequent chunks: use reload
+                        let stop = if is_last_group && is_last_chunk {
+                            Stop::Automatic
+                        } else {
+                            Stop::Software
+                        };
+                        Self::reload(self.info, chunk_len, will_reload, stop, timeout)?;
+                    }
+
+                    // Receive data bytes
+                    for byte in chunk {
+                        self.wait_rxne(timeout)?;
+                        *byte = self.info.regs.rxdr().read().rxdata();
+                    }
+                }
+            }
+        }
+
+        // Wait for transfer to complete
+        if is_last_group {
+            self.wait_stop(timeout)?;
+        }
+        // For non-last read groups, don't wait for TC - the peripheral may hold SCL low
+        // in Software AUTOEND mode until the next START is issued. Just proceed directly
+        // to the next group which will issue RESTART and release the clock.
+
+        Ok(())
     }
 
     /// Blocking write multiple buffers.
@@ -531,6 +772,7 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
             first_length.min(255),
             Stop::Software,
             (first_length > 255) || (last_slice_index != 0),
+            false, // restart
             timeout,
         ) {
             self.master_stop();
@@ -552,6 +794,7 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
                     self.info,
                     slice_len.min(255),
                     (idx != last_slice_index) || (slice_len > 255),
+                    Stop::Software,
                     timeout,
                 ) {
                     if err != Error::Nack {
@@ -567,6 +810,7 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
                         self.info,
                         chunk.len(),
                         (number != last_chunk_idx) || (idx != last_slice_index),
+                        Stop::Software,
                         timeout,
                     ) {
                         if err != Error::Nack {
@@ -610,6 +854,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
         first_slice: bool,
         last_slice: bool,
         send_stop: bool,
+        restart: bool,
         timeout: Timeout,
     ) -> Result<(), Error> {
         let total_len = write.len();
@@ -676,10 +921,17 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
                         total_len.min(255),
                         Stop::Software,
                         (total_len > 255) || !last_slice,
+                        restart,
                         timeout,
                     )?;
                 } else {
-                    Self::reload(self.info, total_len.min(255), (total_len > 255) || !last_slice, timeout)?;
+                    Self::reload(
+                        self.info,
+                        total_len.min(255),
+                        (total_len > 255) || !last_slice,
+                        Stop::Software,
+                        timeout,
+                    )?;
                     self.info.regs.cr1().modify(|w| w.set_tcie(true));
                 }
             } else if !(isr.tcr() || isr.tc()) {
@@ -688,9 +940,13 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
             } else if remaining_len == 0 {
                 return Poll::Ready(Ok(()));
             } else {
-                let last_piece = (remaining_len <= 255) && last_slice;
-
-                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !last_piece, timeout) {
+                if let Err(e) = Self::reload(
+                    self.info,
+                    remaining_len.min(255),
+                    (remaining_len > 255) || !last_slice,
+                    Stop::Software,
+                    timeout,
+                ) {
                     return Poll::Ready(Err(e));
                 }
                 self.info.regs.cr1().modify(|w| w.set_tcie(true));
@@ -702,10 +958,9 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
         .await?;
 
         dma_transfer.await;
-        if last_slice {
-            // This should be done already
-            self.wait_tc(timeout)?;
-        }
+
+        // Always wait for TC after DMA completes - needed for consecutive buffers
+        self.wait_tc(timeout)?;
 
         if last_slice & send_stop {
             self.master_stop();
@@ -780,7 +1035,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
                     address,
                     total_len.min(255),
                     Stop::Automatic,
-                    total_len > 255,
+                    total_len > 255, // reload
                     restart,
                     timeout,
                 )?;
@@ -788,12 +1043,10 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
                     return Poll::Ready(Ok(()));
                 }
             } else if isr.tcr() {
-                // poll_fn was woken without an interrupt present
-                return Poll::Pending;
-            } else {
+                // Transfer Complete Reload - need to set up next chunk
                 let last_piece = remaining_len <= 255;
 
-                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !last_piece, timeout) {
+                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !last_piece, Stop::Automatic, timeout) {
                     return Poll::Ready(Err(e));
                 }
                 // Return here if we are on last chunk,
@@ -802,6 +1055,9 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
                     return Poll::Ready(Ok(()));
                 }
                 self.info.regs.cr1().modify(|w| w.set_tcie(true));
+            } else {
+                // poll_fn was woken without TCR interrupt
+                return Poll::Pending;
             }
 
             remaining_len = remaining_len.saturating_sub(255);
@@ -819,14 +1075,12 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
 
     /// Write.
     pub async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Error> {
-        #[cfg(all(feature = "low-power", stm32wlex))]
-        let _device_busy = crate::low_power::DeviceBusy::new_stop1();
         let timeout = self.timeout();
         if write.is_empty() {
             self.write_internal(address.into(), write, true, timeout)
         } else {
             timeout
-                .with(self.write_dma_internal(address.into(), write, true, true, true, timeout))
+                .with(self.write_dma_internal(address.into(), write, true, true, true, false, timeout))
                 .await
         }
     }
@@ -835,23 +1089,29 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
     ///
     /// The buffers are concatenated in a single write transaction.
     pub async fn write_vectored(&mut self, address: Address, write: &[&[u8]]) -> Result<(), Error> {
-        #[cfg(all(feature = "low-power", stm32wlex))]
-        let _device_busy = crate::low_power::DeviceBusy::new_stop1();
         let timeout = self.timeout();
 
         if write.is_empty() {
             return Err(Error::ZeroLengthTransfer);
         }
-        let mut iter = write.iter();
 
+        let mut iter = write.iter();
         let mut first = true;
         let mut current = iter.next();
+
         while let Some(c) = current {
             let next = iter.next();
             let is_last = next.is_none();
 
-            let fut = self.write_dma_internal(address, c, first, is_last, is_last, timeout);
+            let fut = self.write_dma_internal(
+                address, c, first,   // first_slice
+                is_last, // last_slice
+                is_last, // send_stop (only on last buffer)
+                false,   // restart (false for all - they're one continuous write)
+                timeout,
+            );
             timeout.with(fut).await?;
+
             first = false;
             current = next;
         }
@@ -860,8 +1120,6 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
 
     /// Read.
     pub async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error> {
-        #[cfg(all(feature = "low-power", stm32wlex))]
-        let _device_busy = crate::low_power::DeviceBusy::new_stop1();
         let timeout = self.timeout();
 
         if buffer.is_empty() {
@@ -874,14 +1132,12 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
 
     /// Write, restart, read.
     pub async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
-        #[cfg(all(feature = "low-power", stm32wlex))]
-        let _device_busy = crate::low_power::DeviceBusy::new_stop1();
         let timeout = self.timeout();
 
         if write.is_empty() {
             self.write_internal(address.into(), write, false, timeout)?;
         } else {
-            let fut = self.write_dma_internal(address.into(), write, true, true, false, timeout);
+            let fut = self.write_dma_internal(address.into(), write, true, true, false, false, timeout);
             timeout.with(fut).await?;
         }
 
@@ -901,11 +1157,298 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
     ///
     /// [transaction contract]: embedded_hal_1::i2c::I2c::transaction
     pub async fn transaction(&mut self, addr: u8, operations: &mut [Operation<'_>]) -> Result<(), Error> {
-        #[cfg(all(feature = "low-power", stm32wlex))]
-        let _device_busy = crate::low_power::DeviceBusy::new_stop1();
-        let _ = addr;
-        let _ = operations;
-        todo!()
+        if operations.is_empty() {
+            return Err(Error::ZeroLengthTransfer);
+        }
+
+        let address = addr.into();
+        let timeout = self.timeout();
+
+        // Group consecutive operations of the same type
+        let mut op_idx = 0;
+        let mut is_first_group = true;
+
+        while op_idx < operations.len() {
+            // Determine the type of current group and find all consecutive operations of same type
+            let is_read = matches!(operations[op_idx], Operation::Read(_));
+            let group_start = op_idx;
+
+            // Find end of this group (consecutive operations of same type)
+            while op_idx < operations.len() && matches!(operations[op_idx], Operation::Read(_)) == is_read {
+                op_idx += 1;
+            }
+            let group_end = op_idx;
+            let is_last_group = op_idx >= operations.len();
+
+            // Execute this group of operations
+            if is_read {
+                self.execute_read_group_async(
+                    address,
+                    &mut operations[group_start..group_end],
+                    is_first_group,
+                    is_last_group,
+                    timeout,
+                )
+                .await?;
+            } else {
+                self.execute_write_group_async(
+                    address,
+                    &operations[group_start..group_end],
+                    is_first_group,
+                    is_last_group,
+                    timeout,
+                )
+                .await?;
+            }
+
+            is_first_group = false;
+        }
+
+        Ok(())
+    }
+
+    async fn execute_write_group_async(
+        &mut self,
+        address: Address,
+        operations: &[Operation<'_>],
+        is_first_group: bool,
+        is_last_group: bool,
+        timeout: Timeout,
+    ) -> Result<(), Error> {
+        // Calculate total bytes across all operations in this group
+        let total_bytes = Self::total_operation_bytes(operations);
+
+        if total_bytes == 0 {
+            // Handle empty write group using blocking call
+            if is_first_group {
+                Self::master_write(self.info, address, 0, Stop::Software, false, !is_first_group, timeout)?;
+            }
+            if is_last_group {
+                self.master_stop();
+            }
+            return Ok(());
+        }
+
+        // Collect all write buffers
+        let mut write_buffers: heapless::Vec<&[u8], 16> = heapless::Vec::new();
+        for operation in operations {
+            if let Operation::Write(buffer) = operation {
+                if !buffer.is_empty() {
+                    let _ = write_buffers.push(buffer);
+                }
+            }
+        }
+
+        if write_buffers.is_empty() {
+            return Ok(());
+        }
+
+        // Send each buffer using DMA
+        let num_buffers = write_buffers.len();
+        for (idx, buffer) in write_buffers.iter().enumerate() {
+            let is_first_buffer = idx == 0;
+            let is_last_buffer = idx == num_buffers - 1;
+
+            let fut = self.write_dma_internal(
+                address,
+                buffer,
+                is_first_buffer,                    // first_slice
+                is_last_buffer,                     // last_slice
+                is_last_buffer && is_last_group,    // send_stop
+                is_first_buffer && !is_first_group, // restart (only for first buffer if not first group)
+                timeout,
+            );
+            timeout.with(fut).await?;
+        }
+
+        Ok(())
+    }
+
+    async fn execute_read_group_async(
+        &mut self,
+        address: Address,
+        operations: &mut [Operation<'_>],
+        is_first_group: bool,
+        is_last_group: bool,
+        timeout: Timeout,
+    ) -> Result<(), Error> {
+        // Calculate total bytes across all operations in this group
+        let total_bytes = Self::total_operation_bytes(operations);
+
+        if total_bytes == 0 {
+            // Handle empty read group using blocking call
+            if is_first_group {
+                Self::master_read(
+                    self.info,
+                    address,
+                    0,
+                    if is_last_group { Stop::Automatic } else { Stop::Software },
+                    false, // reload
+                    !is_first_group,
+                    timeout,
+                )?;
+            }
+            if is_last_group {
+                self.wait_stop(timeout)?;
+            }
+            return Ok(());
+        }
+
+        // Use DMA for read operations - need to handle multiple buffers
+        let restart = !is_first_group;
+        let mut total_remaining = total_bytes;
+        let mut is_first_in_group = true;
+
+        for operation in operations {
+            if let Operation::Read(buffer) = operation {
+                if buffer.is_empty() {
+                    // Skip empty buffers
+                    continue;
+                }
+
+                let buf_len = buffer.len();
+                total_remaining -= buf_len;
+                let is_last_in_group = total_remaining == 0;
+
+                // Perform DMA read
+                if is_first_in_group {
+                    // First buffer: use read_dma_internal which handles restart properly
+                    // Only use Automatic stop if this is the last buffer in the last group
+                    let stop_mode = if is_last_group && is_last_in_group {
+                        Stop::Automatic
+                    } else {
+                        Stop::Software
+                    };
+
+                    // We need a custom DMA read that respects our stop mode
+                    self.read_dma_group_internal(address, buffer, restart, stop_mode, timeout)
+                        .await?;
+                    is_first_in_group = false;
+                } else {
+                    // Subsequent buffers: need to reload and continue
+                    let stop_mode = if is_last_group && is_last_in_group {
+                        Stop::Automatic
+                    } else {
+                        Stop::Software
+                    };
+
+                    self.read_dma_group_internal(
+                        address, buffer, false, // no restart for subsequent buffers in same group
+                        stop_mode, timeout,
+                    )
+                    .await?;
+                }
+            }
+        }
+
+        // Wait for transfer to complete
+        if is_last_group {
+            self.wait_stop(timeout)?;
+        }
+
+        Ok(())
+    }
+
+    /// Internal DMA read helper for transaction groups
+    async fn read_dma_group_internal(
+        &mut self,
+        address: Address,
+        buffer: &mut [u8],
+        restart: bool,
+        stop_mode: Stop,
+        timeout: Timeout,
+    ) -> Result<(), Error> {
+        let total_len = buffer.len();
+
+        let dma_transfer = unsafe {
+            let regs = self.info.regs;
+            regs.cr1().modify(|w| {
+                w.set_rxdmaen(true);
+                w.set_tcie(true);
+                w.set_nackie(true);
+                w.set_errie(true);
+            });
+            let src = regs.rxdr().as_ptr() as *mut u8;
+
+            self.rx_dma.as_mut().unwrap().read(src, buffer, Default::default())
+        };
+
+        let mut remaining_len = total_len;
+
+        let on_drop = OnDrop::new(|| {
+            let regs = self.info.regs;
+            regs.cr1().modify(|w| {
+                w.set_rxdmaen(false);
+                w.set_tcie(false);
+                w.set_nackie(false);
+                w.set_errie(false);
+            });
+            regs.icr().write(|w| {
+                w.set_nackcf(true);
+                w.set_berrcf(true);
+                w.set_arlocf(true);
+                w.set_ovrcf(true);
+            });
+        });
+
+        poll_fn(|cx| {
+            self.state.waker.register(cx.waker());
+
+            let isr = self.info.regs.isr().read();
+
+            if isr.nackf() {
+                return Poll::Ready(Err(Error::Nack));
+            }
+            if isr.arlo() {
+                return Poll::Ready(Err(Error::Arbitration));
+            }
+            if isr.berr() {
+                return Poll::Ready(Err(Error::Bus));
+            }
+            if isr.ovr() {
+                return Poll::Ready(Err(Error::Overrun));
+            }
+
+            if remaining_len == total_len {
+                Self::master_read(
+                    self.info,
+                    address,
+                    total_len.min(255),
+                    stop_mode,
+                    total_len > 255, // reload
+                    restart,
+                    timeout,
+                )?;
+                if total_len <= 255 {
+                    return Poll::Ready(Ok(()));
+                }
+            } else if isr.tcr() {
+                // Transfer Complete Reload - need to set up next chunk
+                let last_piece = remaining_len <= 255;
+
+                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !last_piece, stop_mode, timeout) {
+                    return Poll::Ready(Err(e));
+                }
+                // Return here if we are on last chunk,
+                // end of transfer will be awaited with the DMA below
+                if last_piece {
+                    return Poll::Ready(Ok(()));
+                }
+                self.info.regs.cr1().modify(|w| w.set_tcie(true));
+            } else {
+                // poll_fn was woken without TCR interrupt
+                return Poll::Pending;
+            }
+
+            remaining_len = remaining_len.saturating_sub(255);
+            Poll::Pending
+        })
+        .await?;
+
+        dma_transfer.await;
+        drop(on_drop);
+
+        Ok(())
     }
 }
 
@@ -1043,7 +1586,13 @@ impl<'d, M: Mode> I2c<'d, M, MultiMaster> {
             if number == 0 {
                 Self::slave_start(self.info, chunk.len(), number != last_chunk_idx);
             } else {
-                Self::reload(self.info, chunk.len(), number != last_chunk_idx, timeout)?;
+                Self::reload(
+                    self.info,
+                    chunk.len(),
+                    number != last_chunk_idx,
+                    Stop::Software,
+                    timeout,
+                )?;
             }
 
             let mut index = 0;
@@ -1092,7 +1641,13 @@ impl<'d, M: Mode> I2c<'d, M, MultiMaster> {
             if number == 0 {
                 Self::slave_start(self.info, chunk.len(), number != last_chunk_idx);
             } else {
-                Self::reload(self.info, chunk.len(), number != last_chunk_idx, timeout)?;
+                Self::reload(
+                    self.info,
+                    chunk.len(),
+                    number != last_chunk_idx,
+                    Stop::Software,
+                    timeout,
+                )?;
             }
 
             let mut index = 0;
@@ -1228,7 +1783,13 @@ impl<'d> I2c<'d, Async, MultiMaster> {
                 Poll::Pending
             } else if isr.tcr() {
                 let is_last_slice = remaining_len <= 255;
-                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !is_last_slice, timeout) {
+                if let Err(e) = Self::reload(
+                    self.info,
+                    remaining_len.min(255),
+                    !is_last_slice,
+                    Stop::Software,
+                    timeout,
+                ) {
                     return Poll::Ready(Err(e));
                 }
                 remaining_len = remaining_len.saturating_sub(255);
@@ -1292,7 +1853,13 @@ impl<'d> I2c<'d, Async, MultiMaster> {
                 Poll::Pending
             } else if isr.tcr() {
                 let is_last_slice = remaining_len <= 255;
-                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !is_last_slice, timeout) {
+                if let Err(e) = Self::reload(
+                    self.info,
+                    remaining_len.min(255),
+                    !is_last_slice,
+                    Stop::Software,
+                    timeout,
+                ) {
                     return Poll::Ready(Err(e));
                 }
                 remaining_len = remaining_len.saturating_sub(255);
diff --git a/embassy-stm32/src/ipcc.rs b/embassy-stm32/src/ipcc.rs
index e1d8b1c2a..10c4a820b 100644
--- a/embassy-stm32/src/ipcc.rs
+++ b/embassy-stm32/src/ipcc.rs
@@ -1,9 +1,11 @@
 //! Inter-Process Communication Controller (IPCC)
 
 use core::future::poll_fn;
+use core::marker::PhantomData;
 use core::sync::atomic::{Ordering, compiler_fence};
 use core::task::Poll;
 
+use embassy_hal_internal::Peri;
 use embassy_sync::waitqueue::AtomicWaker;
 
 use crate::interrupt::typelevel::Interrupt;
@@ -17,25 +19,16 @@ impl interrupt::typelevel::Handler<interrupt::typelevel::IPCC_C1_RX> for Receive
     unsafe fn on_interrupt() {
         let regs = IPCC::regs();
 
-        let channels = [
-            IpccChannel::Channel1,
-            IpccChannel::Channel2,
-            IpccChannel::Channel3,
-            IpccChannel::Channel4,
-            IpccChannel::Channel5,
-            IpccChannel::Channel6,
-        ];
-
         // Status register gives channel occupied status. For rx, use cpu1.
         let sr = regs.cpu(1).sr().read();
         regs.cpu(0).mr().modify(|w| {
-            for channel in channels {
-                if sr.chf(channel as usize) {
+            for index in 0..5 {
+                if sr.chf(index as usize) {
                     // If bit is set to 1 then interrupt is disabled; we want to disable the interrupt
-                    w.set_chom(channel as usize, true);
+                    w.set_chom(index as usize, true);
 
                     // There shouldn't be a race because the channel is masked only if the interrupt has fired
-                    IPCC::state().rx_waker_for(channel).wake();
+                    IPCC::state().rx_waker_for(index).wake();
                 }
             }
         })
@@ -49,25 +42,16 @@ impl interrupt::typelevel::Handler<interrupt::typelevel::IPCC_C1_TX> for Transmi
     unsafe fn on_interrupt() {
         let regs = IPCC::regs();
 
-        let channels = [
-            IpccChannel::Channel1,
-            IpccChannel::Channel2,
-            IpccChannel::Channel3,
-            IpccChannel::Channel4,
-            IpccChannel::Channel5,
-            IpccChannel::Channel6,
-        ];
-
         // Status register gives channel occupied status. For tx, use cpu0.
         let sr = regs.cpu(0).sr().read();
         regs.cpu(0).mr().modify(|w| {
-            for channel in channels {
-                if !sr.chf(channel as usize) {
+            for index in 0..5 {
+                if !sr.chf(index as usize) {
                     // If bit is set to 1 then interrupt is disabled; we want to disable the interrupt
-                    w.set_chfm(channel as usize, true);
+                    w.set_chfm(index as usize, true);
 
                     // There shouldn't be a race because the channel is masked only if the interrupt has fired
-                    IPCC::state().tx_waker_for(channel).wake();
+                    IPCC::state().tx_waker_for(index).wake();
                 }
             }
         });
@@ -82,76 +66,55 @@ pub struct Config {
     // reserved for future use
 }
 
-/// Channel.
-#[allow(missing_docs)]
-#[derive(Debug, Clone, Copy)]
-#[repr(C)]
-pub enum IpccChannel {
-    Channel1 = 0,
-    Channel2 = 1,
-    Channel3 = 2,
-    Channel4 = 3,
-    Channel5 = 4,
-    Channel6 = 5,
+/// IPCC TX Channel
+pub struct IpccTxChannel<'a> {
+    index: u8,
+    _lifetime: PhantomData<&'a mut usize>,
 }
 
-/// IPCC driver.
-pub struct Ipcc;
-
-impl Ipcc {
-    /// Enable IPCC.
-    pub fn enable(_config: Config) {
-        rcc::enable_and_reset::<IPCC>();
-        IPCC::set_cpu2(true);
-
-        let regs = IPCC::regs();
-
-        regs.cpu(0).cr().modify(|w| {
-            w.set_rxoie(true);
-            w.set_txfie(true);
-        });
-
-        // enable interrupts
-        crate::interrupt::typelevel::IPCC_C1_RX::unpend();
-        crate::interrupt::typelevel::IPCC_C1_TX::unpend();
+impl<'a> IpccTxChannel<'a> {
+    pub(crate) const fn new(index: u8) -> Self {
+        core::assert!(index < 6);
 
-        unsafe { crate::interrupt::typelevel::IPCC_C1_RX::enable() };
-        unsafe { crate::interrupt::typelevel::IPCC_C1_TX::enable() };
+        Self {
+            index: index,
+            _lifetime: PhantomData,
+        }
     }
 
     /// Send data to an IPCC channel. The closure is called to write the data when appropriate.
-    pub async fn send(channel: IpccChannel, f: impl FnOnce()) {
+    pub async fn send(&mut self, f: impl FnOnce()) {
         let regs = IPCC::regs();
 
-        Self::flush(channel).await;
+        self.flush().await;
 
         f();
 
         compiler_fence(Ordering::SeqCst);
 
-        trace!("ipcc: ch {}: send data", channel as u8);
-        regs.cpu(0).scr().write(|w| w.set_chs(channel as usize, true));
+        trace!("ipcc: ch {}: send data", self.index as u8);
+        regs.cpu(0).scr().write(|w| w.set_chs(self.index as usize, true));
     }
 
     /// Wait for the tx channel to become clear
-    pub async fn flush(channel: IpccChannel) {
+    pub async fn flush(&mut self) {
         let regs = IPCC::regs();
 
         // This is a race, but is nice for debugging
-        if regs.cpu(0).sr().read().chf(channel as usize) {
-            trace!("ipcc: ch {}: wait for tx free", channel as u8);
+        if regs.cpu(0).sr().read().chf(self.index as usize) {
+            trace!("ipcc: ch {}: wait for tx free", self.index as u8);
         }
 
         poll_fn(|cx| {
-            IPCC::state().tx_waker_for(channel).register(cx.waker());
+            IPCC::state().tx_waker_for(self.index).register(cx.waker());
             // If bit is set to 1 then interrupt is disabled; we want to enable the interrupt
-            regs.cpu(0).mr().modify(|w| w.set_chfm(channel as usize, false));
+            regs.cpu(0).mr().modify(|w| w.set_chfm(self.index as usize, false));
 
             compiler_fence(Ordering::SeqCst);
 
-            if !regs.cpu(0).sr().read().chf(channel as usize) {
+            if !regs.cpu(0).sr().read().chf(self.index as usize) {
                 // If bit is set to 1 then interrupt is disabled; we want to disable the interrupt
-                regs.cpu(0).mr().modify(|w| w.set_chfm(channel as usize, true));
+                regs.cpu(0).mr().modify(|w| w.set_chfm(self.index as usize, true));
 
                 Poll::Ready(())
             } else {
@@ -160,27 +123,44 @@ impl Ipcc {
         })
         .await;
     }
+}
+
+/// IPCC RX Channel
+pub struct IpccRxChannel<'a> {
+    index: u8,
+    _lifetime: PhantomData<&'a mut usize>,
+}
+
+impl<'a> IpccRxChannel<'a> {
+    pub(crate) const fn new(index: u8) -> Self {
+        core::assert!(index < 6);
+
+        Self {
+            index: index,
+            _lifetime: PhantomData,
+        }
+    }
 
     /// Receive data from an IPCC channel. The closure is called to read the data when appropriate.
-    pub async fn receive<R>(channel: IpccChannel, mut f: impl FnMut() -> Option<R>) -> R {
+    pub async fn receive<R>(&mut self, mut f: impl FnMut() -> Option<R>) -> R {
         let regs = IPCC::regs();
 
         loop {
             // This is a race, but is nice for debugging
-            if !regs.cpu(1).sr().read().chf(channel as usize) {
-                trace!("ipcc: ch {}: wait for rx occupied", channel as u8);
+            if !regs.cpu(1).sr().read().chf(self.index as usize) {
+                trace!("ipcc: ch {}: wait for rx occupied", self.index as u8);
             }
 
             poll_fn(|cx| {
-                IPCC::state().rx_waker_for(channel).register(cx.waker());
+                IPCC::state().rx_waker_for(self.index).register(cx.waker());
                 // If bit is set to 1 then interrupt is disabled; we want to enable the interrupt
-                regs.cpu(0).mr().modify(|w| w.set_chom(channel as usize, false));
+                regs.cpu(0).mr().modify(|w| w.set_chom(self.index as usize, false));
 
                 compiler_fence(Ordering::SeqCst);
 
-                if regs.cpu(1).sr().read().chf(channel as usize) {
+                if regs.cpu(1).sr().read().chf(self.index as usize) {
                     // If bit is set to 1 then interrupt is disabled; we want to disable the interrupt
-                    regs.cpu(0).mr().modify(|w| w.set_chfm(channel as usize, true));
+                    regs.cpu(0).mr().modify(|w| w.set_chfm(self.index as usize, true));
 
                     Poll::Ready(())
                 } else {
@@ -189,21 +169,111 @@ impl Ipcc {
             })
             .await;
 
-            trace!("ipcc: ch {}: read data", channel as u8);
+            trace!("ipcc: ch {}: read data", self.index as u8);
 
             match f() {
                 Some(ret) => return ret,
                 None => {}
             }
 
-            trace!("ipcc: ch {}: clear rx", channel as u8);
+            trace!("ipcc: ch {}: clear rx", self.index as u8);
             compiler_fence(Ordering::SeqCst);
             // If the channel is clear and the read function returns none, fetch more data
-            regs.cpu(0).scr().write(|w| w.set_chc(channel as usize, true));
+            regs.cpu(0).scr().write(|w| w.set_chc(self.index as usize, true));
         }
     }
 }
 
+/// IPCC Channel
+pub struct IpccChannel<'a> {
+    index: u8,
+    _lifetime: PhantomData<&'a mut usize>,
+}
+
+impl<'a> IpccChannel<'a> {
+    pub(crate) const fn new(number: u8) -> Self {
+        core::assert!(number > 0 && number <= 6);
+
+        Self {
+            index: number - 1,
+            _lifetime: PhantomData,
+        }
+    }
+
+    /// Split into a tx and rx channel
+    pub const fn split(self) -> (IpccTxChannel<'a>, IpccRxChannel<'a>) {
+        (IpccTxChannel::new(self.index), IpccRxChannel::new(self.index))
+    }
+}
+
+/// IPCC driver.
+pub struct Ipcc {
+    _private: (),
+}
+
+impl Ipcc {
+    /// Creates a new HardwareSemaphore instance.
+    pub fn new<'d>(
+        _peripheral: Peri<'d, crate::peripherals::IPCC>,
+        _irq: impl interrupt::typelevel::Binding<interrupt::typelevel::IPCC_C1_RX, ReceiveInterruptHandler>
+        + interrupt::typelevel::Binding<interrupt::typelevel::IPCC_C1_TX, TransmitInterruptHandler>
+        + 'd,
+        _config: Config,
+    ) -> Self {
+        rcc::enable_and_reset::<IPCC>();
+        IPCC::set_cpu2(true);
+
+        let regs = IPCC::regs();
+
+        regs.cpu(0).cr().modify(|w| {
+            w.set_rxoie(true);
+            w.set_txfie(true);
+        });
+
+        // enable interrupts
+        crate::interrupt::typelevel::IPCC_C1_RX::unpend();
+        crate::interrupt::typelevel::IPCC_C1_TX::unpend();
+
+        unsafe { crate::interrupt::typelevel::IPCC_C1_RX::enable() };
+        unsafe { crate::interrupt::typelevel::IPCC_C1_TX::enable() };
+
+        Self { _private: () }
+    }
+
+    /// Split into a tx and rx channel
+    pub const fn split<'a>(self) -> [(IpccTxChannel<'a>, IpccRxChannel<'a>); 6] {
+        [
+            IpccChannel::new(1).split(),
+            IpccChannel::new(2).split(),
+            IpccChannel::new(3).split(),
+            IpccChannel::new(4).split(),
+            IpccChannel::new(5).split(),
+            IpccChannel::new(6).split(),
+        ]
+    }
+
+    /// Receive from a channel number
+    pub async unsafe fn receive<R>(number: u8, f: impl FnMut() -> Option<R>) -> R {
+        core::assert!(number > 0 && number <= 6);
+
+        IpccRxChannel::new(number - 1).receive(f).await
+    }
+
+    /// Send to a channel number
+    pub async unsafe fn send(number: u8, f: impl FnOnce()) {
+        core::assert!(number > 0 && number <= 6);
+
+        IpccTxChannel::new(number - 1).send(f).await
+    }
+
+    /// Send to a channel number
+    pub async unsafe fn flush(number: u8) {
+        core::assert!(number > 0 && number <= 6);
+
+        IpccTxChannel::new(number - 1).flush().await
+    }
+}
+
 impl SealedInstance for crate::peripherals::IPCC {
     fn regs() -> crate::pac::ipcc::Ipcc {
         crate::pac::IPCC
@@ -232,26 +302,12 @@ impl State {
         }
     }
 
-    const fn rx_waker_for(&self, channel: IpccChannel) -> &AtomicWaker {
-        match channel {
-            IpccChannel::Channel1 => &self.rx_wakers[0],
-            IpccChannel::Channel2 => &self.rx_wakers[1],
-            IpccChannel::Channel3 => &self.rx_wakers[2],
-            IpccChannel::Channel4 => &self.rx_wakers[3],
-            IpccChannel::Channel5 => &self.rx_wakers[4],
-            IpccChannel::Channel6 => &self.rx_wakers[5],
-        }
+    const fn rx_waker_for(&self, index: u8) -> &AtomicWaker {
+        &self.rx_wakers[index as usize]
     }
 
-    const fn tx_waker_for(&self, channel: IpccChannel) -> &AtomicWaker {
-        match channel {
-            IpccChannel::Channel1 => &self.tx_wakers[0],
-            IpccChannel::Channel2 => &self.tx_wakers[1],
-            IpccChannel::Channel3 => &self.tx_wakers[2],
-            IpccChannel::Channel4 => &self.tx_wakers[3],
-            IpccChannel::Channel5 => &self.tx_wakers[4],
-            IpccChannel::Channel6 => &self.tx_wakers[5],
-        }
+    const fn tx_waker_for(&self, index: u8) -> &AtomicWaker {
+        &self.tx_wakers[index as usize]
     }
 }
 
diff --git a/embassy-stm32/src/lcd.rs b/embassy-stm32/src/lcd.rs
new file mode 100644
index 000000000..ea29f1398
--- /dev/null
+++ b/embassy-stm32/src/lcd.rs
@@ -0,0 +1,510 @@
+//! LCD
+use core::marker::PhantomData;
+
+use embassy_hal_internal::{Peri, PeripheralType};
+
+use crate::gpio::{AfType, AnyPin, SealedPin};
+use crate::peripherals;
+use crate::rcc::{self, RccPeripheral};
+use crate::time::Hertz;
+
+#[cfg(any(stm32u0, stm32l073, stm32l083))]
+const NUM_SEGMENTS: u8 = 52;
+#[cfg(any(stm32wb, stm32l4x6, stm32l15x, stm32l162, stm32l4x3, stm32l4x6))]
+const NUM_SEGMENTS: u8 = 44;
+#[cfg(any(stm32l053, stm32l063, stm32l100))]
+const NUM_SEGMENTS: u8 = 32;
+
+/// LCD configuration struct
+#[non_exhaustive]
+#[derive(Debug, Clone, Copy)]
+pub struct Config {
+    #[cfg(lcd_v2)]
+    /// Enable the voltage output buffer for higher driving capability.
+    ///
+    /// The LCD driving capability is improved as buffers prevent the LCD capacitive loads from loading the resistor
+    /// bridge unacceptably and interfering with its voltage generation.
+    pub use_voltage_output_buffer: bool,
+    /// Enable SEG pin remapping. SEG[31:28] multiplexed with SEG[43:40]
+    pub use_segment_muxing: bool,
+    /// Bias selector
+    pub bias: Bias,
+    /// Duty selector
+    pub duty: Duty,
+    /// Internal or external voltage source
+    pub voltage_source: VoltageSource,
+    /// The frequency used to update the LCD with.
+    /// Should be between ~30 and ~100. Lower is better for power consumption, but has lower visual fidelity.
+    pub target_fps: Hertz,
+    /// LCD driver selector
+    pub drive: Drive,
+}
+
+impl Default for Config {
+    fn default() -> Self {
+        Self {
+            #[cfg(lcd_v2)]
+            use_voltage_output_buffer: false,
+            use_segment_muxing: false,
+            bias: Default::default(),
+            duty: Default::default(),
+            voltage_source: Default::default(),
+            target_fps: Hertz(60),
+            drive: Drive::Medium,
+        }
+    }
+}
+
+/// The number of voltage levels used when driving an LCD.
+/// Your LCD datasheet should tell you what to use.
+#[repr(u8)]
+#[derive(Debug, Default, Clone, Copy)]
+pub enum Bias {
+    /// 1/4 bias
+    #[default]
+    Quarter = 0b00,
+    /// 1/2 bias
+    Half = 0b01,
+    /// 1/3 bias
+    Third = 0b10,
+}
+
+/// The duty used by the LCD driver.
+///
+/// This is essentially how many COM pins you're using.
+#[repr(u8)]
+#[derive(Debug, Default, Clone, Copy)]
+pub enum Duty {
+    #[default]
+    /// Use a single COM pin
+    Static = 0b000,
+    /// Use two COM pins
+    Half = 0b001,
+    /// Use three COM pins
+    Third = 0b010,
+    /// Use four COM pins
+    Quarter = 0b011,
+    /// Use eight COM pins.
+    ///
+    /// In this mode, `COM[7:4]` outputs are available on `SEG[51:48]`.
+    /// This allows reducing the number of available segments.
+    Eigth = 0b100,
+}
+
+impl Duty {
+    fn num_com_pins(&self) -> u8 {
+        match self {
+            Duty::Static => 1,
+            Duty::Half => 2,
+            Duty::Third => 3,
+            Duty::Quarter => 4,
+            Duty::Eigth => 8,
+        }
+    }
+}
+
+/// Whether to use the internal or external voltage source to drive the LCD
+#[repr(u8)]
+#[derive(Debug, Default, Clone, Copy)]
+pub enum VoltageSource {
+    #[default]
+    /// Voltage stepup converter
+    Internal,
+    /// VLCD pin
+    External,
+}
+
+/// Defines the pulse duration in terms of ck_ps pulses.
+///
+/// A short pulse leads to lower power consumption, but displays with high internal resistance
+/// may need a longer pulse to achieve satisfactory contrast.
+/// Note that the pulse is never longer than one half prescaled LCD clock period.
+///
+/// Displays with high internal resistance may need a longer drive time to achieve satisfactory contrast.
+/// `PermanentHighDrive` is useful in this case if some additional power consumption can be tolerated.
+///
+/// Basically, for power usage, you want this as low as possible while still being able to use the LCD
+/// with a good enough contrast.
+#[repr(u8)]
+#[derive(Debug, Clone, Copy)]
+pub enum Drive {
+    /// Zero clock pulse on duration
+    Lowest = 0x00,
+    /// One clock pulse on duration
+    VeryLow = 0x01,
+    /// Two clock pulse on duration
+    Low = 0x02,
+    /// Three clock pulse on duration
+    Medium = 0x03,
+    /// Four clock pulse on duration
+    MediumHigh = 0x04,
+    /// Five clock pulse on duration
+    High = 0x05,
+    /// Six clock pulse on duration
+    VeryHigh = 0x06,
+    /// Seven clock pulse on duration
+    Highest = 0x07,
+    /// Enables the highdrive bit of the hardware
+    PermanentHighDrive = 0x09,
+}
+
+/// LCD driver.
+pub struct Lcd<'d, T: Instance> {
+    _peri: PhantomData<&'d mut T>,
+    duty: Duty,
+    ck_div: u32,
+}
+
+impl<'d, T: Instance> Lcd<'d, T> {
+    /// Initialize the lcd driver.
+    ///
+    /// The `pins` parameter must contain *all* segment and com pins that are connected to the LCD.
+    /// This is not further checked by this driver. Pins not routed to the LCD can be used for other purposes.
+    pub fn new<const N: usize>(
+        _peripheral: Peri<'d, T>,
+        config: Config,
+        vlcd_pin: Peri<'_, impl VlcdPin<T>>,
+        pins: [LcdPin<'d, T>; N],
+    ) -> Self {
+        rcc::enable_and_reset::<T>();
+
+        vlcd_pin.set_as_af(
+            vlcd_pin.af_num(),
+            AfType::output(crate::gpio::OutputType::PushPull, crate::gpio::Speed::VeryHigh),
+        );
+
+        assert_eq!(
+            pins.iter().filter(|pin| !pin.is_seg).count(),
+            config.duty.num_com_pins() as usize,
+            "The number of provided COM pins is not the same as the duty configures"
+        );
+
+        // Set the pins
+        for pin in pins {
+            pin.pin.set_as_af(
+                pin.af_num,
+                AfType::output(crate::gpio::OutputType::PushPull, crate::gpio::Speed::VeryHigh),
+            );
+        }
+
+        // Initialize the display ram to 0
+        for i in 0..8 {
+            T::regs().ram_com(i).low().write_value(0);
+            T::regs().ram_com(i).high().write_value(0);
+        }
+
+        // Calculate the clock dividers
+        let Some(lcd_clk) = (unsafe { rcc::get_freqs().rtc.to_hertz() }) else {
+            panic!("The LCD driver needs the RTC/LCD clock to be running");
+        };
+        let duty_divider = match config.duty {
+            Duty::Static => 1,
+            Duty::Half => 2,
+            Duty::Third => 3,
+            Duty::Quarter => 4,
+            Duty::Eigth => 8,
+        };
+        let target_clock = config.target_fps.0 * duty_divider;
+        let target_division = lcd_clk.0 / target_clock;
+
+        let mut ps = 0;
+        let mut div = 0;
+        let mut best_fps_match = u32::MAX;
+
+        for trial_div in 0..0xF {
+            let trial_ps = (target_division / (trial_div + 16))
+                .next_power_of_two()
+                .trailing_zeros();
+            let fps = lcd_clk.0 / ((1 << trial_ps) * (trial_div + 16)) / duty_divider;
+
+            if fps < config.target_fps.0 {
+                continue;
+            }
+
+            if fps < best_fps_match {
+                ps = trial_ps;
+                div = trial_div;
+                best_fps_match = fps;
+            }
+        }
+
+        let ck_div = lcd_clk.0 / ((1 << ps) * (div + 16));
+
+        trace!(
+            "lcd_clk: {}, fps: {}, ps: {}, div: {}, ck_div: {}",
+            lcd_clk, best_fps_match, ps, div, ck_div
+        );
+
+        if best_fps_match == u32::MAX || ps > 0xF {
+            panic!("Lcd clock error");
+        }
+
+        // Set the frame control
+        T::regs().fcr().modify(|w| {
+            w.set_ps(ps as u8);
+            w.set_div(div as u8);
+            w.set_cc(0b100); // Init in the middle-ish
+            w.set_dead(0b000);
+            w.set_pon(config.drive as u8 & 0x07);
+            w.set_hd((config.drive as u8 & !0x07) != 0);
+        });
+
+        // Wait for the frame control to synchronize
+        while !T::regs().sr().read().fcrsf() {}
+
+        // Set the control register values
+        T::regs().cr().modify(|w| {
+            #[cfg(lcd_v2)]
+            w.set_bufen(config.use_voltage_output_buffer);
+            w.set_mux_seg(config.use_segment_muxing);
+            w.set_bias(config.bias as u8);
+            w.set_duty(config.duty as u8);
+            w.set_vsel(matches!(config.voltage_source, VoltageSource::External));
+        });
+
+        // Enable the lcd
+        T::regs().cr().modify(|w| w.set_lcden(true));
+
+        // Wait for the lcd to be enabled
+        while !T::regs().sr().read().ens() {}
+
+        // Wait for the stepup converter to be ready
+        while !T::regs().sr().read().rdy() {}
+
+        Self {
+            _peri: PhantomData,
+            duty: config.duty,
+            ck_div,
+        }
+    }
+
+    /// Change the contrast by changing the voltage being used.
+    ///
+    /// This is from low at 0 to high at 7.
+    pub fn set_contrast_control(&mut self, value: u8) {
+        assert!((0..=7).contains(&value));
+        T::regs().fcr().modify(|w| w.set_cc(value));
+    }
+
+    /// Change the contrast by introducing a deadtime to the signals
+    /// where the voltages are held at 0V.
+    ///
+    /// This is from no dead time at 0 to high dead time at 7.
+    pub fn set_dead_time(&mut self, value: u8) {
+        assert!((0..=7).contains(&value));
+        T::regs()
+            .fcr()
+            .modify(|w: &mut stm32_metapac::lcd::regs::Fcr| w.set_dead(value));
+    }
+
+    /// Write data into the display RAM. This overwrites the data already in it for the specified com index.
+    ///
+    /// The `com_index` value determines which part of the RAM is written to.
+    /// The `segments` value is a bitmap where each bit represents whether a pixel is turned on or off.
+    ///
+    /// This function waits last update request to be finished, but does not submit the buffer to the LCD with a new request.
+    /// Submission has to be done manually using [Self::submit_frame].
+    pub fn write_com_segments(&mut self, com_index: u8, segments: u64) {
+        while T::regs().sr().read().udr() {}
+
+        assert!(
+            com_index < self.duty.num_com_pins(),
+            "Com index cannot be higher than number of configured com pins (through the Duty setting in the config)"
+        );
+
+        assert!(
+            segments.leading_zeros() >= 64 - self.num_segments() as u32,
+            "Invalid segment pixel set",
+        );
+
+        T::regs()
+            .ram_com(com_index as usize)
+            .low()
+            .write_value((segments & 0xFFFF_FFFF) as u32);
+        T::regs()
+            .ram_com(com_index as usize)
+            .high()
+            .write_value(((segments >> 32) & 0xFFFF_FFFF) as u32);
+    }
+
+    /// Read the data from the display RAM.
+    ///
+    /// The `com_index` value determines which part of the RAM is read from.
+    ///
+    /// This function waits for the last update request to be finished.
+    pub fn read_com_segments(&self, com_index: u8) -> u64 {
+        while T::regs().sr().read().udr() {}
+
+        assert!(
+            com_index < self.duty.num_com_pins(),
+            "Com index cannot be higher than number of configured com pins (through the Duty setting in the config)"
+        );
+
+        let low = T::regs().ram_com(com_index as usize).low().read();
+        let high = T::regs().ram_com(com_index as usize).high().read();
+
+        ((high as u64) << 32) | low as u64
+    }
+
+    /// Submit the current RAM data to the LCD.
+    ///
+    /// This function waits until the RAM is writable, but does not wait for the frame to be drawn.
+    pub fn submit_frame(&mut self) {
+        while T::regs().sr().read().udr() {}
+        // Clear the update done flag
+        T::regs().sr().write(|w| w.set_udd(true));
+        // Set the update request flag
+        T::regs().sr().write(|w| w.set_udr(true));
+    }
+
+    /// Get the number of segments that are supported on this LCD
+    pub fn num_segments(&self) -> u8 {
+        match self.duty {
+            Duty::Eigth => NUM_SEGMENTS - 4, // With 8 coms, 4 of the segment pins turn into com pins
+            _ => NUM_SEGMENTS,
+        }
+    }
+
+    /// Get the pixel mask for the current LCD setup.
+    /// This is a mask of all bits that are allowed to be set in the [Self::write_com_segments] function.
+    pub fn segment_pixel_mask(&self) -> u64 {
+        (1 << self.num_segments()) - 1
+    }
+
+    /// Get the number of COM pins that were configured through the Drive config
+    pub fn num_com_pins(&self) -> u8 {
+        self.duty.num_com_pins()
+    }
+
+    /// Set the blink behavior on some pixels.
+    ///
+    /// The blink frequency is an approximation. It's divided from the clock selected by the FPS.
+    /// Play with the FPS value if you want the blink frequency to be more accurate.
+    ///
+    /// If a blink frequency cannot be attained, this function will panic.
+    pub fn set_blink(&mut self, selector: BlinkSelector, freq: BlinkFreq) {
+        // Freq * 100 to be able to do integer math
+        let scaled_blink_freq = match freq {
+            BlinkFreq::Hz0_25 => 25,
+            BlinkFreq::Hz0_5 => 50,
+            BlinkFreq::Hz1 => 100,
+            BlinkFreq::Hz2 => 200,
+            BlinkFreq::Hz4 => 400,
+        };
+
+        let desired_divider = self.ck_div * 100 / scaled_blink_freq;
+        let target_divider = desired_divider.next_power_of_two();
+        let power_divisions = target_divider.trailing_zeros();
+
+        trace!(
+            "Setting LCD blink frequency -> desired_divider: {}, target_divider: {}",
+            desired_divider, target_divider
+        );
+
+        assert!(
+            (8..=1024).contains(&target_divider),
+            "LCD blink frequency cannot be attained"
+        );
+
+        T::regs().fcr().modify(|reg| {
+            reg.set_blinkf((power_divisions - 3) as u8);
+            reg.set_blink(selector as u8);
+        })
+    }
+}
+
+impl<'d, T: Instance> Drop for Lcd<'d, T> {
+    fn drop(&mut self) {
+        // Disable the lcd
+        T::regs().cr().modify(|w| w.set_lcden(false));
+        rcc::disable::<T>();
+    }
+}
+
+/// Blink frequency
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum BlinkFreq {
+    /// 0.25 hz
+    Hz0_25,
+    /// 0.5 hz
+    Hz0_5,
+    /// 1 hz
+    Hz1,
+    /// 2 hz
+    Hz2,
+    /// 4 hz
+    Hz4,
+}
+
+/// Blink pixel selector
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[repr(u8)]
+pub enum BlinkSelector {
+    /// No pixels blink
+    None = 0b00,
+    /// The SEG0, COM0 pixel blinks if the pixel is set
+    Seg0Com0 = 0b01,
+    /// The SEG0 pixel of all COMs blinks if the pixel is set
+    Seg0ComAll = 0b10,
+    /// All pixels blink if the pixel is set
+    All = 0b11,
+}
+
+/// A type-erased pin that can be configured as an LCD pin.
+/// This is used for passing pins to the new function in the array.
+pub struct LcdPin<'d, T: Instance> {
+    pin: Peri<'d, AnyPin>,
+    af_num: u8,
+    is_seg: bool,
+    _phantom: PhantomData<T>,
+}
+
+impl<'d, T: Instance> LcdPin<'d, T> {
+    /// Construct an LCD pin from any pin that supports it
+    pub fn new_seg(pin: Peri<'d, impl SegPin<T>>) -> Self {
+        let af = pin.af_num();
+
+        Self {
+            pin: pin.into(),
+            af_num: af,
+            is_seg: true,
+            _phantom: PhantomData,
+        }
+    }
+
+    /// Construct an LCD pin from any pin that supports it
+    pub fn new_com(pin: Peri<'d, impl ComPin<T>>) -> Self {
+        let af = pin.af_num();
+
+        Self {
+            pin: pin.into(),
+            af_num: af,
+            is_seg: false,
+            _phantom: PhantomData,
+        }
+    }
+}
+
+trait SealedInstance: crate::rcc::SealedRccPeripheral + PeripheralType {
+    fn regs() -> crate::pac::lcd::Lcd;
+}
+
+/// DSI instance trait.
+#[allow(private_bounds)]
+pub trait Instance: SealedInstance + RccPeripheral + 'static {}
+
+pin_trait!(SegPin, Instance);
+pin_trait!(ComPin, Instance);
+pin_trait!(VlcdPin, Instance);
+
+foreach_peripheral!(
+    (lcd, $inst:ident) => {
+        impl crate::lcd::SealedInstance for peripherals::$inst {
+            fn regs() -> crate::pac::lcd::Lcd {
+                crate::pac::$inst
+            }
+        }
+
+        impl crate::lcd::Instance for peripherals::$inst {}
+    };
+);
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs
index 680edf433..2f783bf64 100644
--- a/embassy-stm32/src/lib.rs
+++ b/embassy-stm32/src/lib.rs
@@ -95,6 +95,8 @@ pub mod i2c;
 pub mod i2s;
 #[cfg(stm32wb)]
 pub mod ipcc;
+#[cfg(lcd)]
+pub mod lcd;
 #[cfg(feature = "low-power")]
 pub mod low_power;
 #[cfg(lptim)]
@@ -151,7 +153,7 @@ pub use crate::_generated::interrupt;
 /// Macro to bind interrupts to handlers.
 ///
 /// This defines the right interrupt handlers, and creates a unit struct (like `struct Irqs;`)
-/// and implements the right [`Binding`]s for it. You can pass this struct to drivers to
+/// and implements the right [`Binding`](crate::interrupt::typelevel::Binding)s for it. You can pass this struct to drivers to
 /// prove at compile-time that the right interrupts have been bound.
 ///
 /// Example of how to bind one interrupt:
@@ -178,6 +180,10 @@ pub use crate::_generated::interrupt;
 ///     }
 /// );
 /// ```
+///
+/// Some chips collate multiple interrupt signals into a single interrupt vector. In the above example, I2C2_3 is a
+/// single vector which is activated by events and errors on both peripherals I2C2 and I2C3. Check your chip's list
+/// of interrupt vectors if you get an unexpected compile error trying to bind the standard name.
 // developer note: this macro can't be in `embassy-hal-internal` due to the use of `$crate`.
 #[macro_export]
 macro_rules! bind_interrupts {
@@ -649,12 +655,26 @@ fn init_hw(config: Config) -> Peripherals {
             rcc::init_rcc(cs, config.rcc);
 
             #[cfg(feature = "low-power")]
-            crate::rtc::init_rtc(cs, config.rtc);
+            rtc::init_rtc(cs, config.rtc, config.min_stop_pause);
 
-            #[cfg(feature = "low-power")]
-            crate::time_driver::get_driver().set_min_stop_pause(cs, config.min_stop_pause);
+            #[cfg(all(stm32wb, feature = "low-power"))]
+            hsem::init_hsem(cs);
         }
 
         p
     })
 }
+
+/// Performs a busy-wait delay for a specified number of microseconds.
+#[allow(unused)]
+pub(crate) fn block_for_us(us: u64) {
+    cfg_if::cfg_if! {
+        // this does strange things on stm32wlx in low power mode depending on exactly when it's called
+        // as in sometimes 15 us (1 tick) would take > 20 seconds.
+        if #[cfg(all(feature = "time", all(not(feature = "low-power"), not(stm32wlex))))] {
+            embassy_time::block_for(embassy_time::Duration::from_micros(us));
+        } else {
+            cortex_m::asm::delay(unsafe { rcc::get_freqs().sys.to_hertz().unwrap().0 as u64 * us  / 1_000_000 } as u32);
+        }
+    }
+}
diff --git a/embassy-stm32/src/low_power.rs b/embassy-stm32/src/low_power.rs
index 696dfe83f..bd8290da0 100644
--- a/embassy-stm32/src/low_power.rs
+++ b/embassy-stm32/src/low_power.rs
@@ -14,7 +14,7 @@
 //!
 //! Since entering and leaving low-power modes typically incurs a significant latency, the
 //! low-power executor will only attempt to enter when the next timer event is at least
-//! [`time_driver::MIN_STOP_PAUSE`] in the future.
+//! [`time_driver::min_stop_pause`] in the future.
 //!
 //! Currently there is no macro analogous to `embassy_executor::main` for this executor;
 //! consequently one must define their entrypoint manually. Moreover, you must relinquish control
@@ -22,21 +22,16 @@
 //!
 //! ```rust,no_run
 //! use embassy_executor::Spawner;
-//! use embassy_stm32::low_power::Executor;
+//! use embassy_stm32::low_power;
 //! use embassy_stm32::rtc::{Rtc, RtcConfig};
-//! use static_cell::StaticCell;
+//! use embassy_time::Duration;
 //!
-//! #[cortex_m_rt::entry]
-//! fn main() -> ! {
-//!     Executor::take().run(|spawner| {
-//!         spawner.spawn(unwrap!(async_main(spawner)));
-//!     });
-//! }
-//!
-//! #[embassy_executor::task]
+//! #[embassy_executor::main(executor = "low_power::Executor")]
 //! async fn async_main(spawner: Spawner) {
 //!     // initialize the platform...
 //!     let mut config = embassy_stm32::Config::default();
+//!     // the default value, but can be adjusted
+//!     config.min_stop_pause = Duration::from_millis(250);
 //!     // when enabled the power-consumption is much higher during stop, but debugging and RTT is working
 //!     config.enable_debug_during_sleep = false;
 //!     let p = embassy_stm32::init(config);
@@ -45,11 +40,9 @@
 //! }
 //! ```
 
-// TODO: Usage of `static mut` here is unsound. Fix then remove this `allow`.`
-#![allow(static_mut_refs)]
-
 use core::arch::asm;
 use core::marker::PhantomData;
+use core::mem;
 use core::sync::atomic::{Ordering, compiler_fence};
 
 use cortex_m::peripheral::SCB;
@@ -57,11 +50,13 @@ use critical_section::CriticalSection;
 use embassy_executor::*;
 
 use crate::interrupt;
+pub use crate::rcc::StopMode;
+use crate::rcc::{RCC_CONFIG, REFCOUNT_STOP1, REFCOUNT_STOP2, decrement_stop_refcount, increment_stop_refcount};
 use crate::time_driver::get_driver;
 
 const THREAD_PENDER: usize = usize::MAX;
 
-static mut EXECUTOR: Option<Executor> = None;
+static mut EXECUTOR_TAKEN: bool = false;
 
 /// Prevent the device from going into the stop mode if held
 pub struct DeviceBusy(StopMode);
@@ -79,15 +74,8 @@ impl DeviceBusy {
 
     /// Create a new DeviceBusy.
     pub fn new(stop_mode: StopMode) -> Self {
-        critical_section::with(|_| unsafe {
-            match stop_mode {
-                StopMode::Stop1 => {
-                    crate::rcc::REFCOUNT_STOP1 += 1;
-                }
-                StopMode::Stop2 => {
-                    crate::rcc::REFCOUNT_STOP2 += 1;
-                }
-            }
+        critical_section::with(|cs| {
+            increment_stop_refcount(cs, stop_mode);
         });
 
         Self(stop_mode)
@@ -96,15 +84,8 @@ impl DeviceBusy {
 
 impl Drop for DeviceBusy {
     fn drop(&mut self) {
-        critical_section::with(|_| unsafe {
-            match self.0 {
-                StopMode::Stop1 => {
-                    crate::rcc::REFCOUNT_STOP1 -= 1;
-                }
-                StopMode::Stop2 => {
-                    crate::rcc::REFCOUNT_STOP2 -= 1;
-                }
-            }
+        critical_section::with(|cs| {
+            decrement_stop_refcount(cs, self.0);
         });
     }
 }
@@ -137,34 +118,24 @@ foreach_interrupt! {
 /// prevents entering the given stop mode.
 pub fn stop_ready(stop_mode: StopMode) -> bool {
     critical_section::with(|cs| match Executor::stop_mode(cs) {
-        Some(StopMode::Stop2) => true,
+        Some(StopMode::Standby | StopMode::Stop2) => true,
         Some(StopMode::Stop1) => stop_mode == StopMode::Stop1,
         None => false,
     })
 }
 
-/// Available Stop modes.
-#[non_exhaustive]
-#[derive(PartialEq)]
-pub enum StopMode {
-    /// STOP 1
-    Stop1,
-    /// STOP 2
-    Stop2,
-}
+#[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba, stm32wb, stm32wlex, stm32u0))]
+use crate::pac::pwr::vals::Lpms;
 
-#[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba, stm32wlex, stm32u0))]
-use stm32_metapac::pwr::vals::Lpms;
-
-#[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba, stm32wlex, stm32u0))]
+#[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba, stm32wb, stm32wlex, stm32u0))]
 impl Into<Lpms> for StopMode {
     fn into(self) -> Lpms {
         match self {
             StopMode::Stop1 => Lpms::STOP1,
-            #[cfg(not(stm32wba))]
-            StopMode::Stop2 => Lpms::STOP2,
-            #[cfg(stm32wba)]
-            StopMode::Stop2 => Lpms::STOP1, // TODO: WBA has no STOP2?
+            #[cfg(not(any(stm32wb, stm32wba)))]
+            StopMode::Standby | StopMode::Stop2 => Lpms::STOP2,
+            #[cfg(any(stm32wb, stm32wba))]
+            StopMode::Standby | StopMode::Stop2 => Lpms::STOP1, // TODO: WBA has no STOP2?
         }
     }
 }
@@ -182,42 +153,47 @@ impl Into<Lpms> for StopMode {
 pub struct Executor {
     inner: raw::Executor,
     not_send: PhantomData<*mut ()>,
-    scb: SCB,
 }
 
 impl Executor {
     /// Create a new Executor.
-    pub fn take() -> &'static mut Self {
-        critical_section::with(|_| unsafe {
-            assert!(EXECUTOR.is_none());
-
-            EXECUTOR = Some(Self {
-                inner: raw::Executor::new(THREAD_PENDER as *mut ()),
-                not_send: PhantomData,
-                scb: cortex_m::Peripherals::steal().SCB,
-            });
-
-            let executor = EXECUTOR.as_mut().unwrap();
+    pub fn new() -> Self {
+        unsafe {
+            if EXECUTOR_TAKEN {
+                panic!("Low power executor can only be taken once.");
+            } else {
+                EXECUTOR_TAKEN = true;
+            }
+        }
 
-            executor
-        })
+        Self {
+            inner: raw::Executor::new(THREAD_PENDER as *mut ()),
+            not_send: PhantomData,
+        }
     }
 
     pub(crate) unsafe fn on_wakeup_irq() {
         critical_section::with(|cs| {
             #[cfg(stm32wlex)]
             {
-                let extscr = crate::pac::PWR.extscr().read();
+                use crate::pac::rcc::vals::Sw;
+                use crate::pac::{PWR, RCC};
+                use crate::rcc::init as init_rcc;
+
+                let extscr = PWR.extscr().read();
                 if extscr.c1stop2f() || extscr.c1stopf() {
                     // when we wake from any stop mode we need to re-initialize the rcc
-                    crate::rcc::apply_resume_config();
+                    while RCC.cfgr().read().sws() != Sw::MSI {}
+
+                    init_rcc(RCC_CONFIG.unwrap());
+
                     if extscr.c1stop2f() {
                         // when we wake from STOP2, we need to re-initialize the time driver
-                        crate::time_driver::init_timer(cs);
+                        get_driver().init_timer(cs);
                         // reset the refcounts for STOP2 and STOP1 (initializing the time driver will increment one of them for the timer)
                         // and given that we just woke from STOP2, we can reset them
-                        crate::rcc::REFCOUNT_STOP2 = 0;
-                        crate::rcc::REFCOUNT_STOP1 = 0;
+                        REFCOUNT_STOP2 = 0;
+                        REFCOUNT_STOP1 = 0;
                     }
                 }
             }
@@ -226,19 +202,90 @@ impl Executor {
         });
     }
 
+    const fn get_scb() -> SCB {
+        unsafe { mem::transmute(()) }
+    }
+
     fn stop_mode(_cs: CriticalSection) -> Option<StopMode> {
-        if unsafe { crate::rcc::REFCOUNT_STOP2 == 0 && crate::rcc::REFCOUNT_STOP1 == 0 } {
+        // We cannot enter standby because we will lose program state.
+        if unsafe { REFCOUNT_STOP2 == 0 && REFCOUNT_STOP1 == 0 } {
+            trace!("low power: stop 2");
             Some(StopMode::Stop2)
-        } else if unsafe { crate::rcc::REFCOUNT_STOP1 == 0 } {
+        } else if unsafe { REFCOUNT_STOP1 == 0 } {
+            trace!("low power: stop 1");
             Some(StopMode::Stop1)
         } else {
+            trace!("low power: not ready to stop (refcount_stop1: {})", unsafe {
+                REFCOUNT_STOP1
+            });
             None
         }
     }
 
+    #[cfg(all(stm32wb, feature = "low-power"))]
+    fn configure_stop_stm32wb(&self, _cs: CriticalSection) -> Result<(), ()> {
+        use core::task::Poll;
+
+        use embassy_futures::poll_once;
+
+        use crate::hsem::HardwareSemaphoreChannel;
+        use crate::pac::rcc::vals::{Smps, Sw};
+        use crate::pac::{PWR, RCC};
+
+        trace!("low power: trying to get sem3");
+
+        let sem3_mutex = match poll_once(HardwareSemaphoreChannel::<crate::peripherals::HSEM>::new(3).lock(0)) {
+            Poll::Pending => None,
+            Poll::Ready(mutex) => Some(mutex),
+        }
+        .ok_or(())?;
+
+        trace!("low power: got sem3");
+
+        let sem4_mutex = HardwareSemaphoreChannel::<crate::peripherals::HSEM>::new(4).try_lock(0);
+        if let Some(sem4_mutex) = sem4_mutex {
+            trace!("low power: got sem4");
+
+            if PWR.extscr().read().c2ds() {
+                drop(sem4_mutex);
+            } else {
+                return Ok(());
+            }
+        }
+
+        // Sem4 not granted
+        // Set HSION
+        RCC.cr().modify(|w| {
+            w.set_hsion(true);
+        });
+
+        // Wait for HSIRDY
+        while !RCC.cr().read().hsirdy() {}
+
+        // Set SW to HSI
+        RCC.cfgr().modify(|w| {
+            w.set_sw(Sw::HSI);
+        });
+
+        // Wait for SWS to report HSI
+        while !RCC.cfgr().read().sws().eq(&Sw::HSI) {}
+
+        // Set SMPSSEL to HSI
+        RCC.smpscr().modify(|w| {
+            w.set_smpssel(Smps::HSI);
+        });
+
+        drop(sem3_mutex);
+
+        Ok(())
+    }
+
     #[allow(unused_variables)]
-    fn configure_stop(&mut self, stop_mode: StopMode) {
-        #[cfg(any(stm32l4, stm32l5, stm32u5, stm32u0, stm32wba, stm32wlex))]
+    fn configure_stop(&self, _cs: CriticalSection, stop_mode: StopMode) -> Result<(), ()> {
+        #[cfg(all(stm32wb, feature = "low-power"))]
+        self.configure_stop_stm32wb(_cs)?;
+
+        #[cfg(any(stm32l4, stm32l5, stm32u5, stm32u0, stm32wb, stm32wba, stm32wlex))]
         crate::pac::PWR.cr1().modify(|m| m.set_lpms(stop_mode.into()));
         #[cfg(stm32h5)]
         crate::pac::PWR.pmcr().modify(|v| {
@@ -246,10 +293,12 @@ impl Executor {
             v.set_lpms(vals::Lpms::STOP);
             v.set_svos(vals::Svos::SCALE3);
         });
+
+        Ok(())
     }
 
-    fn configure_pwr(&mut self) {
-        self.scb.clear_sleepdeep();
+    fn configure_pwr(&self) {
+        Self::get_scb().clear_sleepdeep();
         // Clear any previous stop flags
         #[cfg(stm32wlex)]
         crate::pac::PWR.extscr().modify(|w| {
@@ -258,27 +307,18 @@ impl Executor {
 
         compiler_fence(Ordering::SeqCst);
 
-        let stop_mode = critical_section::with(|cs| Self::stop_mode(cs));
-
-        if stop_mode.is_none() {
-            trace!("low power: not ready to stop");
-            return;
-        }
-
-        if get_driver().pause_time().is_err() {
-            trace!("low power: failed to pause time");
-            return;
-        }
-
-        let stop_mode = stop_mode.unwrap();
-        match stop_mode {
-            StopMode::Stop1 => trace!("low power: stop 1"),
-            StopMode::Stop2 => trace!("low power: stop 2"),
-        }
-        self.configure_stop(stop_mode);
+        critical_section::with(|cs| {
+            let _ = unsafe { RCC_CONFIG }?;
+            let stop_mode = Self::stop_mode(cs)?;
+            get_driver().pause_time(cs).ok()?;
+            self.configure_stop(cs, stop_mode).ok()?;
 
-        #[cfg(not(feature = "low-power-debug-with-sleep"))]
-        self.scb.set_sleepdeep();
+            Some(())
+        })
+        .map(|_| {
+            #[cfg(not(feature = "low-power-debug-with-sleep"))]
+            Self::get_scb().set_sleepdeep();
+        });
     }
 
     /// Run the executor.
@@ -300,12 +340,11 @@ impl Executor {
     ///
     /// This function never returns.
     pub fn run(&'static mut self, init: impl FnOnce(Spawner)) -> ! {
-        let executor = unsafe { EXECUTOR.as_mut().unwrap() };
-        init(executor.inner.spawner());
+        init(self.inner.spawner());
 
         loop {
             unsafe {
-                executor.inner.poll();
+                self.inner.poll();
                 self.configure_pwr();
                 asm!("wfe");
                 #[cfg(stm32wlex)]
diff --git a/embassy-stm32/src/opamp.rs b/embassy-stm32/src/opamp.rs
index ac8d5de21..4a55f5bd3 100644
--- a/embassy-stm32/src/opamp.rs
+++ b/embassy-stm32/src/opamp.rs
@@ -4,19 +4,12 @@
 use embassy_hal_internal::PeripheralType;
 
 use crate::Peri;
+#[cfg(opamp_v5)]
+use crate::block_for_us;
 use crate::pac::opamp::vals::*;
 #[cfg(not(any(stm32g4, stm32f3)))]
 use crate::rcc::RccInfo;
 
-/// Performs a busy-wait delay for a specified number of microseconds.
-#[cfg(opamp_v5)]
-fn blocking_delay_ms(ms: u32) {
-    #[cfg(feature = "time")]
-    embassy_time::block_for(embassy_time::Duration::from_millis(ms as u64));
-    #[cfg(not(feature = "time"))]
-    cortex_m::asm::delay(unsafe { crate::rcc::get_freqs() }.sys.to_hertz().unwrap().0 / 1_000 * ms);
-}
-
 /// Gain
 #[allow(missing_docs)]
 #[derive(Clone, Copy)]
@@ -439,7 +432,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
 
             // The closer the trimming value is to the optimum trimming value, the longer it takes to stabilize
             // (with a maximum stabilization time remaining below 2 ms in any case) -- RM0440 25.3.7
-            blocking_delay_ms(2);
+            block_for_us(2_000);
 
             if !T::regs().csr().read().calout() {
                 if mid == 0 {
diff --git a/embassy-stm32/src/ospi/mod.rs b/embassy-stm32/src/ospi/mod.rs
index 592a8594a..2d5dbd95a 100644
--- a/embassy-stm32/src/ospi/mod.rs
+++ b/embassy-stm32/src/ospi/mod.rs
@@ -451,7 +451,7 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
         }
 
         T::REGS.cr().modify(|w| {
-            w.set_fmode(0.into());
+            w.set_fmode(vals::FunctionalMode::INDIRECT_WRITE);
         });
 
         // Configure alternate bytes
@@ -577,7 +577,8 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
             w.set_dmaen(false);
         });
 
-        self.configure_command(&transaction, Some(buf.len()))?;
+        let transfer_size_bytes = buf.len() * W::size().bytes();
+        self.configure_command(&transaction, Some(transfer_size_bytes))?;
 
         let current_address = T::REGS.ar().read().address();
         let current_instruction = T::REGS.ir().read().instruction();
@@ -616,7 +617,8 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
             w.set_dmaen(false);
         });
 
-        self.configure_command(&transaction, Some(buf.len()))?;
+        let transfer_size_bytes = buf.len() * W::size().bytes();
+        self.configure_command(&transaction, Some(transfer_size_bytes))?;
 
         T::REGS
             .cr()
@@ -1153,7 +1155,8 @@ impl<'d, T: Instance> Ospi<'d, T, Async> {
         // Wait for peripheral to be free
         while T::REGS.sr().read().busy() {}
 
-        self.configure_command(&transaction, Some(buf.len()))?;
+        let transfer_size_bytes = buf.len() * W::size().bytes();
+        self.configure_command(&transaction, Some(transfer_size_bytes))?;
 
         let current_address = T::REGS.ar().read().address();
         let current_instruction = T::REGS.ir().read().instruction();
@@ -1168,16 +1171,18 @@ impl<'d, T: Instance> Ospi<'d, T, Async> {
             T::REGS.ar().write(|v| v.set_address(current_address));
         }
 
-        let transfer = unsafe {
-            self.dma
-                .as_mut()
-                .unwrap()
-                .read(T::REGS.dr().as_ptr() as *mut W, buf, Default::default())
-        };
+        for chunk in buf.chunks_mut(0xFFFF / W::size().bytes()) {
+            let transfer = unsafe {
+                self.dma
+                    .as_mut()
+                    .unwrap()
+                    .read(T::REGS.dr().as_ptr() as *mut W, chunk, Default::default())
+            };
 
-        T::REGS.cr().modify(|w| w.set_dmaen(true));
+            T::REGS.cr().modify(|w| w.set_dmaen(true));
 
-        transfer.blocking_wait();
+            transfer.blocking_wait();
+        }
 
         finish_dma(T::REGS);
 
@@ -1193,13 +1198,14 @@ impl<'d, T: Instance> Ospi<'d, T, Async> {
         // Wait for peripheral to be free
         while T::REGS.sr().read().busy() {}
 
-        self.configure_command(&transaction, Some(buf.len()))?;
+        let transfer_size_bytes = buf.len() * W::size().bytes();
+        self.configure_command(&transaction, Some(transfer_size_bytes))?;
         T::REGS
             .cr()
             .modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECT_WRITE));
 
         // TODO: implement this using a LinkedList DMA to offload the whole transfer off the CPU.
-        for chunk in buf.chunks(0xFFFF) {
+        for chunk in buf.chunks(0xFFFF / W::size().bytes()) {
             let transfer = unsafe {
                 self.dma
                     .as_mut()
@@ -1226,7 +1232,8 @@ impl<'d, T: Instance> Ospi<'d, T, Async> {
         // Wait for peripheral to be free
         while T::REGS.sr().read().busy() {}
 
-        self.configure_command(&transaction, Some(buf.len()))?;
+        let transfer_size_bytes = buf.len() * W::size().bytes();
+        self.configure_command(&transaction, Some(transfer_size_bytes))?;
 
         let current_address = T::REGS.ar().read().address();
         let current_instruction = T::REGS.ir().read().instruction();
@@ -1241,16 +1248,18 @@ impl<'d, T: Instance> Ospi<'d, T, Async> {
             T::REGS.ar().write(|v| v.set_address(current_address));
         }
 
-        let transfer = unsafe {
-            self.dma
-                .as_mut()
-                .unwrap()
-                .read(T::REGS.dr().as_ptr() as *mut W, buf, Default::default())
-        };
+        for chunk in buf.chunks_mut(0xFFFF / W::size().bytes()) {
+            let transfer = unsafe {
+                self.dma
+                    .as_mut()
+                    .unwrap()
+                    .read(T::REGS.dr().as_ptr() as *mut W, chunk, Default::default())
+            };
 
-        T::REGS.cr().modify(|w| w.set_dmaen(true));
+            T::REGS.cr().modify(|w| w.set_dmaen(true));
 
-        transfer.await;
+            transfer.await;
+        }
 
         finish_dma(T::REGS);
 
@@ -1266,13 +1275,14 @@ impl<'d, T: Instance> Ospi<'d, T, Async> {
         // Wait for peripheral to be free
         while T::REGS.sr().read().busy() {}
 
-        self.configure_command(&transaction, Some(buf.len()))?;
+        let transfer_size_bytes = buf.len() * W::size().bytes();
+        self.configure_command(&transaction, Some(transfer_size_bytes))?;
         T::REGS
             .cr()
             .modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECT_WRITE));
 
         // TODO: implement this using a LinkedList DMA to offload the whole transfer off the CPU.
-        for chunk in buf.chunks(0xFFFF) {
+        for chunk in buf.chunks(0xFFFF / W::size().bytes()) {
             let transfer = unsafe {
                 self.dma
                     .as_mut()
diff --git a/embassy-stm32/src/rcc/l.rs b/embassy-stm32/src/rcc/l.rs
index 584957c6d..2e1cbd702 100644
--- a/embassy-stm32/src/rcc/l.rs
+++ b/embassy-stm32/src/rcc/l.rs
@@ -1,6 +1,3 @@
-#[cfg(all(feature = "low-power", stm32wlex))]
-use core::mem::MaybeUninit;
-
 #[cfg(any(stm32l0, stm32l1))]
 pub use crate::pac::pwr::vals::Vos as VoltageScale;
 use crate::pac::rcc::regs::Cfgr;
@@ -14,42 +11,6 @@ use crate::time::Hertz;
 /// HSI speed
 pub const HSI_FREQ: Hertz = Hertz(16_000_000);
 
-/// Saved RCC Config
-///
-/// Used when exiting STOP2 to re-enable clocks to their last configured state
-/// for chips that need it.
-#[cfg(all(feature = "low-power", stm32wlex))]
-static mut RESUME_RCC_CONFIG: MaybeUninit<Config> = MaybeUninit::uninit();
-
-/// Set the rcc config to be restored when exiting STOP2
-///
-/// Safety: Sets a mutable global.
-#[cfg(all(feature = "low-power", stm32wlex))]
-pub(crate) unsafe fn set_resume_config(config: Config) {
-    trace!("rcc set_resume_config()");
-    RESUME_RCC_CONFIG = MaybeUninit::new(config);
-}
-
-/// Get the rcc config to be restored when exiting STOP2
-///
-/// Safety: Reads a mutable global.
-#[cfg(all(feature = "low-power", stm32wlex))]
-pub(crate) unsafe fn get_resume_config() -> Config {
-    *(*core::ptr::addr_of_mut!(RESUME_RCC_CONFIG)).assume_init_ref()
-}
-
-#[cfg(all(feature = "low-power", stm32wlex))]
-/// Safety: should only be called from low power executable just after resuming from STOP2
-pub(crate) unsafe fn apply_resume_config() {
-    trace!("rcc apply_resume_config()");
-
-    while RCC.cfgr().read().sws() != Sysclk::MSI {}
-
-    let config = get_resume_config();
-
-    init(config);
-}
-
 #[derive(Clone, Copy, Eq, PartialEq)]
 pub enum HseMode {
     /// crystal/ceramic oscillator (HSEBYP=0)
@@ -193,10 +154,6 @@ fn msi_enable(range: MSIRange) {
 }
 
 pub(crate) unsafe fn init(config: Config) {
-    // save the rcc config because if we enter stop 2 we need to re-apply it on wakeup
-    #[cfg(all(feature = "low-power", stm32wlex))]
-    set_resume_config(config);
-
     // Switch to MSI to prevent problems with PLL configuration.
     if !RCC.cr().read().msion() {
         // Turn on MSI and configure it to 4MHz.
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index 592890777..85434fa83 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -49,6 +49,9 @@ pub(crate) static mut REFCOUNT_STOP1: u32 = 0;
 /// May be read without a critical section
 pub(crate) static mut REFCOUNT_STOP2: u32 = 0;
 
+#[cfg(feature = "low-power")]
+pub(crate) static mut RCC_CONFIG: Option<Config> = None;
+
 #[cfg(backup_sram)]
 pub(crate) static mut BKSRAM_RETAINED: bool = false;
 
@@ -108,6 +111,32 @@ pub fn clocks<'a>(_rcc: &'a crate::Peri<'a, crate::peripherals::RCC>) -> &'a Clo
     unsafe { get_freqs() }
 }
 
+#[cfg(feature = "low-power")]
+pub(crate) fn increment_stop_refcount(_cs: CriticalSection, stop_mode: StopMode) {
+    match stop_mode {
+        StopMode::Standby => {}
+        StopMode::Stop2 => unsafe {
+            REFCOUNT_STOP2 += 1;
+        },
+        StopMode::Stop1 => unsafe {
+            REFCOUNT_STOP1 += 1;
+        },
+    }
+}
+
+#[cfg(feature = "low-power")]
+pub(crate) fn decrement_stop_refcount(_cs: CriticalSection, stop_mode: StopMode) {
+    match stop_mode {
+        StopMode::Standby => {}
+        StopMode::Stop2 => unsafe {
+            REFCOUNT_STOP2 -= 1;
+        },
+        StopMode::Stop1 => unsafe {
+            REFCOUNT_STOP1 -= 1;
+        },
+    }
+}
+
 pub(crate) trait SealedRccPeripheral {
     fn frequency() -> Hertz;
     #[allow(dead_code)]
@@ -138,12 +167,19 @@ pub(crate) struct RccInfo {
     stop_mode: StopMode,
 }
 
+/// Specifies a limit for the stop mode of the peripheral or the stop mode to be entered.
+/// E.g. if `StopMode::Stop1` is selected, the peripheral prevents the chip from entering Stop1 mode.
 #[cfg(feature = "low-power")]
 #[allow(dead_code)]
-pub(crate) enum StopMode {
-    Standby,
-    Stop2,
+#[derive(Debug, Clone, Copy, PartialEq, Default)]
+pub enum StopMode {
+    #[default]
+    /// Peripheral prevents chip from entering Stop1 or executor will enter Stop1
     Stop1,
+    /// Peripheral prevents chip from entering Stop2 or executor will enter Stop2
+    Stop2,
+    /// Peripheral does not prevent chip from entering Stop
+    Standby,
 }
 
 impl RccInfo {
@@ -199,15 +235,7 @@ impl RccInfo {
         }
 
         #[cfg(feature = "low-power")]
-        match self.stop_mode {
-            StopMode::Standby => {}
-            StopMode::Stop2 => unsafe {
-                REFCOUNT_STOP2 += 1;
-            },
-            StopMode::Stop1 => unsafe {
-                REFCOUNT_STOP1 += 1;
-            },
-        }
+        increment_stop_refcount(_cs, self.stop_mode);
 
         // set the xxxRST bit
         let reset_ptr = self.reset_ptr();
@@ -265,15 +293,7 @@ impl RccInfo {
         }
 
         #[cfg(feature = "low-power")]
-        match self.stop_mode {
-            StopMode::Standby => {}
-            StopMode::Stop2 => unsafe {
-                REFCOUNT_STOP2 -= 1;
-            },
-            StopMode::Stop1 => unsafe {
-                REFCOUNT_STOP1 -= 1;
-            },
-        }
+        decrement_stop_refcount(_cs, self.stop_mode);
 
         // clear the xxxEN bit
         let enable_ptr = self.enable_ptr();
@@ -408,8 +428,39 @@ pub(crate) fn init_rcc(_cs: CriticalSection, config: Config) {
 
         #[cfg(feature = "low-power")]
         {
+            RCC_CONFIG = Some(config);
             REFCOUNT_STOP2 = 0;
             REFCOUNT_STOP1 = 0;
         }
     }
 }
+
+/// Calculate intermediate prescaler number used to calculate peripheral prescalers
+///
+/// This function is intended to calculate a number indicating a minimum division
+/// necessary to result in a frequency lower than the provided `freq_max`.
+///
+/// The returned value indicates the `val + 1` divider is necessary to result in
+/// the output frequency that is below the maximum provided.
+///
+/// For example:
+/// 0 = divider of 1 => no division necessary as the input frequency is below max
+/// 1 = divider of 2 => division by 2 necessary
+/// ...
+///
+/// The provided max frequency is inclusive. So if `freq_in == freq_max` the result
+/// will be 0, indicating that no division is necessary. To accomplish that we subtract
+/// 1 from the input frequency so that the integer rounding plays in our favor.
+///
+/// For example:
+/// Let the input frequency be 110 and the max frequency be 55.
+/// If we naiively do `110/55 = 2` the renult will indicate that we need a divider by 3
+/// which in reality will be rounded up to 4 as usually a 3 division is not available.
+/// In either case the resulting frequency will be either 36 or 27 which is lower than
+/// what we would want. The result should be 1.
+/// If we do the following instead `109/55 = 1` indicating that we need a divide by 2
+/// which will result in the correct 55.
+#[allow(unused)]
+pub(crate) fn raw_prescaler(freq_in: u32, freq_max: u32) -> u32 {
+    freq_in.saturating_sub(1) / freq_max
+}
diff --git a/embassy-stm32/src/rtc/low_power.rs b/embassy-stm32/src/rtc/low_power.rs
index e5bf30927..f049d6b12 100644
--- a/embassy-stm32/src/rtc/low_power.rs
+++ b/embassy-stm32/src/rtc/low_power.rs
@@ -3,6 +3,7 @@ use embassy_time::{Duration, TICK_HZ};
 
 use super::{DateTimeError, Rtc, RtcError, bcd2_to_byte};
 use crate::interrupt::typelevel::Interrupt;
+use crate::pac::rtc::vals::Wucksel;
 use crate::peripherals::RTC;
 use crate::rtc::{RtcTimeProvider, SealedInstance};
 
@@ -58,60 +59,16 @@ impl core::ops::Sub for RtcInstant {
     }
 }
 
-#[repr(u8)]
-#[derive(Clone, Copy, Debug)]
-pub(crate) enum WakeupPrescaler {
-    Div2 = 2,
-    Div4 = 4,
-    Div8 = 8,
-    Div16 = 16,
-}
-
-#[cfg(any(
-    stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0, stm32wba, stm32wlex
-))]
-impl From<WakeupPrescaler> for crate::pac::rtc::vals::Wucksel {
-    fn from(val: WakeupPrescaler) -> Self {
-        use crate::pac::rtc::vals::Wucksel;
-
-        match val {
-            WakeupPrescaler::Div2 => Wucksel::DIV2,
-            WakeupPrescaler::Div4 => Wucksel::DIV4,
-            WakeupPrescaler::Div8 => Wucksel::DIV8,
-            WakeupPrescaler::Div16 => Wucksel::DIV16,
-        }
-    }
-}
-
-#[cfg(any(
-    stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0, stm32wba, stm32wlex
-))]
-impl From<crate::pac::rtc::vals::Wucksel> for WakeupPrescaler {
-    fn from(val: crate::pac::rtc::vals::Wucksel) -> Self {
-        use crate::pac::rtc::vals::Wucksel;
-
-        match val {
-            Wucksel::DIV2 => WakeupPrescaler::Div2,
-            Wucksel::DIV4 => WakeupPrescaler::Div4,
-            Wucksel::DIV8 => WakeupPrescaler::Div8,
-            Wucksel::DIV16 => WakeupPrescaler::Div16,
-            _ => unreachable!(),
-        }
-    }
-}
-
-impl WakeupPrescaler {
-    pub fn compute_min(val: u32) -> Self {
-        *[
-            WakeupPrescaler::Div2,
-            WakeupPrescaler::Div4,
-            WakeupPrescaler::Div8,
-            WakeupPrescaler::Div16,
-        ]
-        .iter()
-        .find(|psc| **psc as u32 > val)
-        .unwrap_or(&WakeupPrescaler::Div16)
-    }
+fn wucksel_compute_min(val: u32) -> (Wucksel, u32) {
+    *[
+        (Wucksel::DIV2, 2),
+        (Wucksel::DIV4, 4),
+        (Wucksel::DIV8, 8),
+        (Wucksel::DIV16, 16),
+    ]
+    .iter()
+    .find(|(_, psc)| *psc as u32 > val)
+    .unwrap_or(&(Wucksel::DIV16, 16))
 }
 
 impl Rtc {
@@ -138,7 +95,7 @@ impl Rtc {
         let requested_duration = requested_duration.as_ticks().clamp(0, u32::MAX as u64);
         let rtc_hz = Self::frequency().0 as u64;
         let rtc_ticks = requested_duration * rtc_hz / TICK_HZ;
-        let prescaler = WakeupPrescaler::compute_min((rtc_ticks / u16::MAX as u64) as u32);
+        let (wucksel, prescaler) = wucksel_compute_min((rtc_ticks / u16::MAX as u64) as u32);
 
         // adjust the rtc ticks to the prescaler and subtract one rtc tick
         let rtc_ticks = rtc_ticks / prescaler as u64;
@@ -159,7 +116,7 @@ impl Rtc {
                 while !regs.icsr().read().wutwf() {}
             }
 
-            regs.cr().modify(|w| w.set_wucksel(prescaler.into()));
+            regs.cr().modify(|w| w.set_wucksel(wucksel));
             regs.wutr().write(|w| w.set_wut(rtc_ticks));
             regs.cr().modify(|w| w.set_wute(true));
             regs.cr().modify(|w| w.set_wutie(true));
diff --git a/embassy-stm32/src/rtc/mod.rs b/embassy-stm32/src/rtc/mod.rs
index 116b3c7ed..e88bd7ab2 100644
--- a/embassy-stm32/src/rtc/mod.rs
+++ b/embassy-stm32/src/rtc/mod.rs
@@ -379,13 +379,16 @@ trait SealedInstance {
 }
 
 #[cfg(feature = "low-power")]
-pub(crate) fn init_rtc(cs: CriticalSection, config: RtcConfig) {
+pub(crate) fn init_rtc(cs: CriticalSection, config: RtcConfig, min_stop_pause: embassy_time::Duration) {
+    use crate::time_driver::get_driver;
+
     #[cfg(feature = "_allow-disable-rtc")]
     if config._disable_rtc {
         return;
     }
 
-    crate::time_driver::get_driver().set_rtc(cs, Rtc::new_inner(config));
+    get_driver().set_rtc(cs, Rtc::new_inner(config));
+    get_driver().set_min_stop_pause(cs, min_stop_pause);
 
     trace!("low power: stop with rtc configured");
 }
diff --git a/embassy-stm32/src/sai/mod.rs b/embassy-stm32/src/sai/mod.rs
index 726d1729a..ce4bc43c3 100644
--- a/embassy-stm32/src/sai/mod.rs
+++ b/embassy-stm32/src/sai/mod.rs
@@ -391,7 +391,7 @@ pub struct Config {
     pub frame_sync_polarity: FrameSyncPolarity,
     pub frame_sync_active_level_length: word::U7,
     pub frame_sync_definition: FrameSyncDefinition,
-    pub frame_length: u8,
+    pub frame_length: u16,
     pub clock_strobe: ClockStrobe,
     pub output_drive: OutputDrive,
     pub master_clock_divider: Option<MasterClockDivider>,
@@ -696,7 +696,7 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
             w.set_fspol(config.frame_sync_polarity.fspol());
             w.set_fsdef(config.frame_sync_definition.fsdef());
             w.set_fsall(config.frame_sync_active_level_length.0 as u8 - 1);
-            w.set_frl(config.frame_length - 1);
+            w.set_frl((config.frame_length - 1).try_into().unwrap());
         });
 
         ch.slotr().modify(|w| {
diff --git a/embassy-stm32/src/time_driver.rs b/embassy-stm32/src/time_driver.rs
index 7db51d72e..0b75aef92 100644
--- a/embassy-stm32/src/time_driver.rs
+++ b/embassy-stm32/src/time_driver.rs
@@ -196,6 +196,11 @@ fn calc_now(period: u32, counter: u16) -> u64 {
     ((period as u64) << 15) + ((counter as u32 ^ ((period & 1) << 15)) as u64)
 }
 
+#[cfg(feature = "low-power")]
+fn calc_period_counter(ticks: u64) -> (u32, u16) {
+    (2 * (ticks >> 16) as u32 + (ticks as u16 >= 0x8000) as u32, ticks as u16)
+}
+
 struct AlarmState {
     timestamp: Cell<u64>,
 }
@@ -240,7 +245,7 @@ embassy_time_driver::time_driver_impl!(static DRIVER: RtcDriver = RtcDriver {
 impl RtcDriver {
     /// initialize the timer, but don't start it.  Used for chips like stm32wle5
     /// for low power where the timer config is lost in STOP2.
-    fn init_timer(&'static self, cs: critical_section::CriticalSection) {
+    pub(crate) fn init_timer(&'static self, cs: critical_section::CriticalSection) {
         let r = regs_gp16();
 
         rcc::enable_and_reset_with_cs::<T>(cs);
@@ -358,34 +363,10 @@ impl RtcDriver {
     #[cfg(feature = "low-power")]
     /// Add the given offset to the current time
     fn add_time(&self, offset: embassy_time::Duration, cs: CriticalSection) {
-        let offset = offset.as_ticks();
-        let cnt = regs_gp16().cnt().read().cnt() as u32;
-        let period = self.period.load(Ordering::SeqCst);
-
-        // Correct the race, if it exists
-        let period = if period & 1 == 1 && cnt < u16::MAX as u32 / 2 {
-            period + 1
-        } else {
-            period
-        };
-
-        // Normalize to the full overflow
-        let period = (period / 2) * 2;
-
-        // Add the offset
-        let period = period + 2 * (offset / u16::MAX as u64) as u32;
-        let cnt = cnt + (offset % u16::MAX as u64) as u32;
-
-        let (cnt, period) = if cnt > u16::MAX as u32 {
-            (cnt - u16::MAX as u32, period + 2)
-        } else {
-            (cnt, period)
-        };
-
-        let period = if cnt > u16::MAX as u32 / 2 { period + 1 } else { period };
+        let (period, counter) = calc_period_counter(self.now() + offset.as_ticks());
 
         self.period.store(period, Ordering::SeqCst);
-        regs_gp16().cnt().write(|w| w.set_cnt(cnt as u16));
+        regs_gp16().cnt().write(|w| w.set_cnt(counter));
 
         // Now, recompute alarm
         let alarm = self.alarm.borrow(cs);
@@ -399,13 +380,15 @@ impl RtcDriver {
     #[cfg(feature = "low-power")]
     /// Stop the wakeup alarm, if enabled, and add the appropriate offset
     fn stop_wakeup_alarm(&self, cs: CriticalSection) {
-        if let Some(offset) = self.rtc.borrow(cs).borrow_mut().as_mut().unwrap().stop_wakeup_alarm(cs) {
+        if !regs_gp16().cr1().read().cen()
+            && let Some(offset) = self.rtc.borrow(cs).borrow_mut().as_mut().unwrap().stop_wakeup_alarm(cs)
+        {
             self.add_time(offset, cs);
         }
     }
 
     /*
-        Low-power public functions: all create or require a critical section
+        Low-power public functions: all require a critical section
     */
     #[cfg(feature = "low-power")]
     pub(crate) fn set_min_stop_pause(&self, cs: CriticalSection, min_stop_pause: embassy_time::Duration) {
@@ -422,49 +405,36 @@ impl RtcDriver {
 
     #[cfg(feature = "low-power")]
     /// Pause the timer if ready; return err if not
-    pub(crate) fn pause_time(&self) -> Result<(), ()> {
-        critical_section::with(|cs| {
-            /*
-                If the wakeup timer is currently running, then we need to stop it and
-                add the elapsed time to the current time, as this will impact the result
-                of `time_until_next_alarm`.
-            */
-            self.stop_wakeup_alarm(cs);
-
-            let time_until_next_alarm = self.time_until_next_alarm(cs);
-            if time_until_next_alarm < self.min_stop_pause.borrow(cs).get() {
-                trace!(
-                    "time_until_next_alarm < self.min_stop_pause ({})",
-                    time_until_next_alarm
-                );
-                Err(())
-            } else {
-                self.rtc
-                    .borrow(cs)
-                    .borrow_mut()
-                    .as_mut()
-                    .unwrap()
-                    .start_wakeup_alarm(time_until_next_alarm, cs);
-
-                regs_gp16().cr1().modify(|w| w.set_cen(false));
-                // save the count for the timer as its lost in STOP2 for stm32wlex
-                #[cfg(stm32wlex)]
-                self.saved_count
-                    .store(regs_gp16().cnt().read().cnt() as u16, Ordering::SeqCst);
-                Ok(())
-            }
-        })
+    pub(crate) fn pause_time(&self, cs: CriticalSection) -> Result<(), ()> {
+        self.stop_wakeup_alarm(cs);
+
+        let time_until_next_alarm = self.time_until_next_alarm(cs);
+        if time_until_next_alarm < self.min_stop_pause.borrow(cs).get() {
+            trace!(
+                "time_until_next_alarm < self.min_stop_pause ({})",
+                time_until_next_alarm
+            );
+            Err(())
+        } else {
+            self.rtc
+                .borrow(cs)
+                .borrow_mut()
+                .as_mut()
+                .unwrap()
+                .start_wakeup_alarm(time_until_next_alarm, cs);
+
+            regs_gp16().cr1().modify(|w| w.set_cen(false));
+            // save the count for the timer as its lost in STOP2 for stm32wlex
+            #[cfg(stm32wlex)]
+            self.saved_count
+                .store(regs_gp16().cnt().read().cnt() as u16, Ordering::SeqCst);
+            Ok(())
+        }
     }
 
     #[cfg(feature = "low-power")]
     /// Resume the timer with the given offset
     pub(crate) fn resume_time(&self, cs: CriticalSection) {
-        if regs_gp16().cr1().read().cen() {
-            // Time isn't currently stopped
-
-            return;
-        }
-
         self.stop_wakeup_alarm(cs);
 
         regs_gp16().cr1().modify(|w| w.set_cen(true));
@@ -546,8 +516,3 @@ pub(crate) const fn get_driver() -> &'static RtcDriver {
 pub(crate) fn init(cs: CriticalSection) {
     DRIVER.init(cs)
 }
-
-#[cfg(all(feature = "low-power", stm32wlex))]
-pub(crate) fn init_timer(cs: CriticalSection) {
-    DRIVER.init_timer(cs)
-}
diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs
index 9a56a41fb..77f19a37b 100644
--- a/embassy-stm32/src/timer/complementary_pwm.rs
+++ b/embassy-stm32/src/timer/complementary_pwm.rs
@@ -77,8 +77,6 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
 
         this.inner.set_counting_mode(counting_mode);
         this.set_frequency(freq);
-        this.inner.start();
-
         this.inner.enable_outputs();
 
         [Channel::Ch1, Channel::Ch2, Channel::Ch3, Channel::Ch4]
@@ -89,6 +87,10 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
             });
         this.inner.set_autoreload_preload(true);
 
+        // Generate update event so pre-load registers are written to the shadow registers
+        this.inner.generate_update_event();
+        this.inner.start();
+
         this
     }
 
@@ -160,8 +162,8 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
 
     /// Set PWM frequency.
     ///
-    /// Note: when you call this, the max duty value changes, so you will have to
-    /// call `set_duty` on all channels with the duty calculated based on the new max duty.
+    /// Note: that the frequency will not be applied in the timer until an update event
+    /// occurs.
     pub fn set_frequency(&mut self, freq: Hertz) {
         let multiplier = if self.inner.get_counting_mode().is_center_aligned() {
             2u8
@@ -219,59 +221,53 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
     /// Note:
     /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
     pub async fn waveform_up(&mut self, dma: Peri<'_, impl super::UpDma<T>>, channel: Channel, duty: &[u16]) {
-        #[allow(clippy::let_unit_value)] // eg. stm32f334
-        let req = dma.request();
-
-        let original_duty_state = self.inner.get_compare_value(channel);
-        let original_enable_state = self.inner.get_channel_enable_state(channel);
-        let original_update_dma_state = self.inner.get_update_dma_state();
-
-        if !original_update_dma_state {
-            self.inner.enable_update_dma(true);
-        }
-
-        if !original_enable_state {
-            self.inner.enable_channel(channel, true);
-        }
-
-        unsafe {
-            #[cfg(not(any(bdma, gpdma)))]
-            use crate::dma::{Burst, FifoThreshold};
-            use crate::dma::{Transfer, TransferOptions};
-
-            let dma_transfer_option = TransferOptions {
-                #[cfg(not(any(bdma, gpdma)))]
-                fifo_threshold: Some(FifoThreshold::Full),
-                #[cfg(not(any(bdma, gpdma)))]
-                mburst: Burst::Incr8,
-                ..Default::default()
-            };
-
-            Transfer::new_write(
-                dma,
-                req,
-                duty,
-                self.inner.regs_gp16().ccr(channel.index()).as_ptr() as *mut u16,
-                dma_transfer_option,
-            )
-            .await
-        };
-
-        // restore output compare state
-        if !original_enable_state {
-            self.inner.enable_channel(channel, false);
-        }
-
-        self.inner.set_compare_value(channel, original_duty_state);
+        self.inner.enable_channel(channel, true);
+        self.inner.enable_update_dma(true);
+        self.inner.setup_update_dma(dma, channel, duty).await;
+        self.inner.enable_update_dma(false);
+    }
 
-        // Since DMA is closed before timer update event trigger DMA is turn off,
-        // this can almost always trigger a DMA FIFO error.
-        //
-        // optional TODO:
-        // clean FEIF after disable UDE
-        if !original_update_dma_state {
-            self.inner.enable_update_dma(false);
-        }
+    /// Generate a multichannel sequence of PWM waveforms using DMA triggered by timer update events.
+    ///
+    /// This method utilizes the timer's DMA burst transfer capability to update multiple CCRx registers
+    /// in sequence on each update event (UEV). The data is written via the DMAR register using the
+    /// DMA base address (DBA) and burst length (DBL) configured in the DCR register.
+    ///
+    /// The `duty` buffer must be structured as a flattened 2D array in row-major order, where each row
+    /// represents a single update event and each column corresponds to a specific timer channel (starting
+    /// from `starting_channel` up to and including `ending_channel`).
+    ///
+    /// For example, if using channels 1 through 4, a buffer of 4 update steps might look like:
+    ///
+    /// ```rust,ignore
+    /// let dma_buf: [u16; 16] = [
+    ///     ch1_duty_1, ch2_duty_1, ch3_duty_1, ch4_duty_1, // update 1
+    ///     ch1_duty_2, ch2_duty_2, ch3_duty_2, ch4_duty_2, // update 2
+    ///     ch1_duty_3, ch2_duty_3, ch3_duty_3, ch4_duty_3, // update 3
+    ///     ch1_duty_4, ch2_duty_4, ch3_duty_4, ch4_duty_4, // update 4
+    /// ];
+    /// ```
+    ///
+    /// Each group of `N` values (where `N` is number of channels) is transferred on one update event,
+    /// updating the duty cycles of all selected channels simultaneously.
+    ///
+    /// Note:
+    /// You will need to provide corresponding `TIMx_UP` DMA channel to use this method.
+    /// Also be aware that embassy timers use one of timers internally. It is possible to
+    /// switch this timer by using `time-driver-timX` feature.
+    ///
+    pub async fn waveform_up_multi_channel(
+        &mut self,
+        dma: Peri<'_, impl super::UpDma<T>>,
+        starting_channel: Channel,
+        ending_channel: Channel,
+        duty: &[u16],
+    ) {
+        self.inner.enable_update_dma(true);
+        self.inner
+            .setup_update_dma_burst(dma, starting_channel, ending_channel, duty)
+            .await;
+        self.inner.enable_update_dma(false);
     }
 }
 
diff --git a/embassy-stm32/src/timer/input_capture.rs b/embassy-stm32/src/timer/input_capture.rs
index 2a4ec2db0..9cf0f8c34 100644
--- a/embassy-stm32/src/timer/input_capture.rs
+++ b/embassy-stm32/src/timer/input_capture.rs
@@ -60,6 +60,7 @@ impl<'d, T: GeneralInstance4Channel> InputCapture<'d, T> {
         this.inner.set_counting_mode(counting_mode);
         this.inner.set_tick_freq(freq);
         this.inner.enable_outputs(); // Required for advanced timers, see GeneralInstance4Channel for details
+        this.inner.generate_update_event();
         this.inner.start();
 
         // enable NVIC interrupt
diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs
index 0122fe4f7..aba08081f 100644
--- a/embassy-stm32/src/timer/low_level.rs
+++ b/embassy-stm32/src/timer/low_level.rs
@@ -13,6 +13,7 @@ use embassy_hal_internal::Peri;
 pub use stm32_metapac::timer::vals::{FilterValue, Mms as MasterMode, Sms as SlaveMode, Ts as TriggerSource};
 
 use super::*;
+use crate::dma::{Transfer, WritableRingBuffer};
 use crate::pac::timer::vals;
 use crate::rcc;
 use crate::time::Hertz;
@@ -272,6 +273,17 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
         self.regs_core().cr1().modify(|r| r.set_cen(true));
     }
 
+    /// Generate timer update event from software.
+    ///
+    /// Set URS to avoid generating interrupt or DMA request. This update event is only
+    /// used to load value from pre-load registers. If called when the timer is running,
+    /// it may disrupt the output waveform.
+    pub fn generate_update_event(&self) {
+        self.regs_core().cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
+        self.regs_core().egr().write(|r| r.set_ug(true));
+        self.regs_core().cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
+    }
+
     /// Stop the timer.
     pub fn stop(&self) {
         self.regs_core().cr1().modify(|r| r.set_cen(false));
@@ -322,10 +334,6 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
                 let regs = self.regs_core();
                 regs.psc().write_value(psc);
                 regs.arr().write(|r| r.set_arr(arr));
-
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
-                regs.egr().write(|r| r.set_ug(true));
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
             }
             #[cfg(not(stm32l0))]
             TimerBits::Bits32 => {
@@ -335,10 +343,6 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
                 let regs = self.regs_gp32_unchecked();
                 regs.psc().write_value(psc);
                 regs.arr().write_value(arr);
-
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
-                regs.egr().write(|r| r.set_ug(true));
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
             }
         }
     }
@@ -656,6 +660,167 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
         }
     }
 
+    /// Setup a ring buffer for the channel
+    pub fn setup_ring_buffer<'a>(
+        &mut self,
+        dma: Peri<'a, impl super::UpDma<T>>,
+        channel: Channel,
+        dma_buf: &'a mut [u16],
+    ) -> WritableRingBuffer<'a, u16> {
+        #[allow(clippy::let_unit_value)] // eg. stm32f334
+        let req = dma.request();
+
+        unsafe {
+            use crate::dma::TransferOptions;
+            #[cfg(not(any(bdma, gpdma)))]
+            use crate::dma::{Burst, FifoThreshold};
+
+            let dma_transfer_option = TransferOptions {
+                #[cfg(not(any(bdma, gpdma)))]
+                fifo_threshold: Some(FifoThreshold::Full),
+                #[cfg(not(any(bdma, gpdma)))]
+                mburst: Burst::Incr8,
+                ..Default::default()
+            };
+
+            WritableRingBuffer::new(
+                dma,
+                req,
+                self.regs_1ch().ccr(channel.index()).as_ptr() as *mut u16,
+                dma_buf,
+                dma_transfer_option,
+            )
+        }
+    }
+
+    /// Generate a sequence of PWM waveform
+    ///
+    /// Note:
+    /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
+    pub fn setup_update_dma<'a>(
+        &mut self,
+        dma: Peri<'a, impl super::UpDma<T>>,
+        channel: Channel,
+        duty: &'a [u16],
+    ) -> Transfer<'a> {
+        #[allow(clippy::let_unit_value)] // eg. stm32f334
+        let req = dma.request();
+
+        unsafe {
+            #[cfg(not(any(bdma, gpdma)))]
+            use crate::dma::{Burst, FifoThreshold};
+            use crate::dma::{Transfer, TransferOptions};
+
+            let dma_transfer_option = TransferOptions {
+                #[cfg(not(any(bdma, gpdma)))]
+                fifo_threshold: Some(FifoThreshold::Full),
+                #[cfg(not(any(bdma, gpdma)))]
+                mburst: Burst::Incr8,
+                ..Default::default()
+            };
+
+            match self.bits() {
+                TimerBits::Bits16 => Transfer::new_write(
+                    dma,
+                    req,
+                    duty,
+                    self.regs_1ch().ccr(channel.index()).as_ptr() as *mut u16,
+                    dma_transfer_option,
+                ),
+                #[cfg(not(any(stm32l0)))]
+                TimerBits::Bits32 => {
+                    #[cfg(not(any(bdma, gpdma)))]
+                    panic!("unsupported timer bits");
+
+                    #[cfg(any(bdma, gpdma))]
+                    Transfer::new_write(
+                        dma,
+                        req,
+                        duty,
+                        self.regs_1ch().ccr(channel.index()).as_ptr() as *mut u32,
+                        dma_transfer_option,
+                    )
+                }
+            }
+        }
+    }
+
+    /// Generate a multichannel sequence of PWM waveforms using DMA triggered by timer update events.
+    ///
+    /// This method utilizes the timer's DMA burst transfer capability to update multiple CCRx registers
+    /// in sequence on each update event (UEV). The data is written via the DMAR register using the
+    /// DMA base address (DBA) and burst length (DBL) configured in the DCR register.
+    ///
+    /// The `duty` buffer must be structured as a flattened 2D array in row-major order, where each row
+    /// represents a single update event and each column corresponds to a specific timer channel (starting
+    /// from `starting_channel` up to and including `ending_channel`).
+    ///
+    /// For example, if using channels 1 through 4, a buffer of 4 update steps might look like:
+    ///
+    /// ```rust,ignore
+    /// let dma_buf: [u16; 16] = [
+    ///     ch1_duty_1, ch2_duty_1, ch3_duty_1, ch4_duty_1, // update 1
+    ///     ch1_duty_2, ch2_duty_2, ch3_duty_2, ch4_duty_2, // update 2
+    ///     ch1_duty_3, ch2_duty_3, ch3_duty_3, ch4_duty_3, // update 3
+    ///     ch1_duty_4, ch2_duty_4, ch3_duty_4, ch4_duty_4, // update 4
+    /// ];
+    /// ```
+    ///
+    /// Each group of `N` values (where `N` is number of channels) is transferred on one update event,
+    /// updating the duty cycles of all selected channels simultaneously.
+    ///
+    /// Note:
+    /// You will need to provide corresponding `TIMx_UP` DMA channel to use this method.
+    /// Also be aware that embassy timers use one of timers internally. It is possible to
+    /// switch this timer by using `time-driver-timX` feature.
+    ///
+    pub fn setup_update_dma_burst<'a>(
+        &mut self,
+        dma: Peri<'a, impl super::UpDma<T>>,
+        starting_channel: Channel,
+        ending_channel: Channel,
+        duty: &'a [u16],
+    ) -> Transfer<'a> {
+        let cr1_addr = self.regs_gp16().cr1().as_ptr() as u32;
+        let start_ch_index = starting_channel.index();
+        let end_ch_index = ending_channel.index();
+
+        assert!(start_ch_index <= end_ch_index);
+
+        let ccrx_addr = self.regs_gp16().ccr(start_ch_index).as_ptr() as u32;
+        self.regs_gp16()
+            .dcr()
+            .modify(|w| w.set_dba(((ccrx_addr - cr1_addr) / 4) as u8));
+        self.regs_gp16()
+            .dcr()
+            .modify(|w| w.set_dbl((end_ch_index - start_ch_index) as u8));
+
+        #[allow(clippy::let_unit_value)] // eg. stm32f334
+        let req = dma.request();
+
+        unsafe {
+            #[cfg(not(any(bdma, gpdma)))]
+            use crate::dma::{Burst, FifoThreshold};
+            use crate::dma::{Transfer, TransferOptions};
+
+            let dma_transfer_option = TransferOptions {
+                #[cfg(not(any(bdma, gpdma)))]
+                fifo_threshold: Some(FifoThreshold::Full),
+                #[cfg(not(any(bdma, gpdma)))]
+                mburst: Burst::Incr4,
+                ..Default::default()
+            };
+
+            Transfer::new_write(
+                dma,
+                req,
+                duty,
+                self.regs_gp16().dmar().as_ptr() as *mut u16,
+                dma_transfer_option,
+            )
+        }
+    }
+
     /// Get capture value for a channel.
     pub fn get_capture_value(&self, channel: Channel) -> u32 {
         self.get_compare_value(channel)
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index 804d1ef37..3fa363881 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -12,6 +12,7 @@ pub mod low_level;
 pub mod one_pulse;
 pub mod pwm_input;
 pub mod qei;
+pub mod ringbuffered;
 pub mod simple_pwm;
 
 use crate::interrupt;
diff --git a/embassy-stm32/src/timer/pwm_input.rs b/embassy-stm32/src/timer/pwm_input.rs
index da8a79b09..057ab011a 100644
--- a/embassy-stm32/src/timer/pwm_input.rs
+++ b/embassy-stm32/src/timer/pwm_input.rs
@@ -47,6 +47,7 @@ impl<'d, T: GeneralInstance4Channel> PwmInput<'d, T> {
         inner.set_counting_mode(CountingMode::EdgeAlignedUp);
         inner.set_tick_freq(freq);
         inner.enable_outputs(); // Required for advanced timers, see GeneralInstance4Channel for details
+        inner.generate_update_event();
         inner.start();
 
         // Configuration steps from ST RM0390 (STM32F446) chapter 17.3.6
diff --git a/embassy-stm32/src/timer/ringbuffered.rs b/embassy-stm32/src/timer/ringbuffered.rs
new file mode 100644
index 000000000..e8f97bf59
--- /dev/null
+++ b/embassy-stm32/src/timer/ringbuffered.rs
@@ -0,0 +1,169 @@
+//! RingBuffered PWM driver.
+
+use core::mem::ManuallyDrop;
+use core::task::Waker;
+
+use super::low_level::Timer;
+use super::{Channel, GeneralInstance4Channel};
+use crate::dma::WritableRingBuffer;
+use crate::dma::ringbuffer::Error;
+
+/// A PWM channel that uses a DMA ring buffer for continuous waveform generation.
+///
+/// This allows you to continuously update PWM duty cycles via DMA without blocking the CPU.
+/// The ring buffer enables smooth, uninterrupted waveform generation by automatically cycling
+/// through duty cycle values stored in memory.
+///
+/// You can write new duty cycle values to the ring buffer while it's running, enabling
+/// dynamic waveform generation for applications like motor control, LED dimming, or audio output.
+///
+/// # Example
+/// ```ignore
+/// let mut channel = pwm.ch1().into_ring_buffered_channel(dma_ch, &mut buffer);
+/// channel.start(); // Start DMA transfer
+/// channel.write(&[100, 200, 300]).ok(); // Update duty cycles
+/// ```
+pub struct RingBufferedPwmChannel<'d, T: GeneralInstance4Channel> {
+    timer: ManuallyDrop<Timer<'d, T>>,
+    ring_buf: WritableRingBuffer<'d, u16>,
+    channel: Channel,
+}
+
+impl<'d, T: GeneralInstance4Channel> RingBufferedPwmChannel<'d, T> {
+    pub(crate) fn new(
+        timer: ManuallyDrop<Timer<'d, T>>,
+        channel: Channel,
+        ring_buf: WritableRingBuffer<'d, u16>,
+    ) -> Self {
+        Self {
+            timer,
+            ring_buf,
+            channel,
+        }
+    }
+
+    /// Start the ring buffer operation.
+    ///
+    /// You must call this after creating it for it to work.
+    pub fn start(&mut self) {
+        self.ring_buf.start()
+    }
+
+    /// Clear all data in the ring buffer.
+    pub fn clear(&mut self) {
+        self.ring_buf.clear()
+    }
+
+    /// Write elements directly to the raw buffer. This can be used to fill the buffer before starting the DMA transfer.
+    pub fn write_immediate(&mut self, buf: &[u16]) -> Result<(usize, usize), Error> {
+        self.ring_buf.write_immediate(buf)
+    }
+
+    /// Write elements from the ring buffer
+    /// Return a tuple of the length written and the length remaining in the buffer
+    pub fn write(&mut self, buf: &[u16]) -> Result<(usize, usize), Error> {
+        self.ring_buf.write(buf)
+    }
+
+    /// Write an exact number of elements to the ringbuffer.
+    pub async fn write_exact(&mut self, buffer: &[u16]) -> Result<usize, Error> {
+        self.ring_buf.write_exact(buffer).await
+    }
+
+    /// Wait for any ring buffer write error.
+    pub async fn wait_write_error(&mut self) -> Result<usize, Error> {
+        self.ring_buf.wait_write_error().await
+    }
+
+    /// The current length of the ringbuffer
+    pub fn len(&mut self) -> Result<usize, Error> {
+        self.ring_buf.len()
+    }
+
+    /// The capacity of the ringbuffer
+    pub const fn capacity(&self) -> usize {
+        self.ring_buf.capacity()
+    }
+
+    /// Set a waker to be woken when at least one byte is send.
+    pub fn set_waker(&mut self, waker: &Waker) {
+        self.ring_buf.set_waker(waker)
+    }
+
+    /// Request the DMA to reset. The configuration for this channel will not be preserved.
+    ///
+    /// This doesn't immediately stop the transfer, you have to wait until is_running returns false.
+    pub fn request_reset(&mut self) {
+        self.ring_buf.request_reset()
+    }
+
+    /// Request the transfer to pause, keeping the existing configuration for this channel.
+    /// To restart the transfer, call [`start`](Self::start) again.
+    ///
+    /// This doesn't immediately stop the transfer, you have to wait until is_running returns false.
+    pub fn request_pause(&mut self) {
+        self.ring_buf.request_pause()
+    }
+
+    /// Return whether DMA is still running.
+    ///
+    /// If this returns false, it can be because either the transfer finished, or it was requested to stop early with request_stop.
+    pub fn is_running(&mut self) -> bool {
+        self.ring_buf.is_running()
+    }
+
+    /// Stop the DMA transfer and await until the buffer is empty.
+    ///
+    /// This disables the DMA transfer's circular mode so that the transfer stops when all available data has been written.
+    ///
+    /// This is designed to be used with streaming output data such as the I2S/SAI or DAC.
+    pub async fn stop(&mut self) {
+        self.ring_buf.stop().await
+    }
+
+    /// Enable the given channel.
+    pub fn enable(&mut self) {
+        self.timer.enable_channel(self.channel, true);
+    }
+
+    /// Disable the given channel.
+    pub fn disable(&mut self) {
+        self.timer.enable_channel(self.channel, false);
+    }
+
+    /// Check whether given channel is enabled
+    pub fn is_enabled(&self) -> bool {
+        self.timer.get_channel_enable_state(self.channel)
+    }
+
+    /// Get max duty value.
+    ///
+    /// This value depends on the configured frequency and the timer's clock rate from RCC.
+    pub fn max_duty_cycle(&self) -> u16 {
+        let max = self.timer.get_max_compare_value();
+        assert!(max < u16::MAX as u32);
+        max as u16 + 1
+    }
+
+    /// Set the output polarity for a given channel.
+    pub fn set_polarity(&mut self, polarity: super::low_level::OutputPolarity) {
+        self.timer.set_output_polarity(self.channel, polarity);
+    }
+
+    /// Set the output compare mode for a given channel.
+    pub fn set_output_compare_mode(&mut self, mode: super::low_level::OutputCompareMode) {
+        self.timer.set_output_compare_mode(self.channel, mode);
+    }
+}
+
+/// A group of four [`SimplePwmChannel`]s, obtained from [`SimplePwm::split`].
+pub struct RingBufferedPwmChannels<'d, T: GeneralInstance4Channel> {
+    /// Channel 1
+    pub ch1: RingBufferedPwmChannel<'d, T>,
+    /// Channel 2
+    pub ch2: RingBufferedPwmChannel<'d, T>,
+    /// Channel 3
+    pub ch3: RingBufferedPwmChannel<'d, T>,
+    /// Channel 4
+    pub ch4: RingBufferedPwmChannel<'d, T>,
+}
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index 36303aeb4..484e9fd81 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -4,7 +4,8 @@ use core::marker::PhantomData;
 use core::mem::ManuallyDrop;
 
 use super::low_level::{CountingMode, OutputCompareMode, OutputPolarity, Timer};
-use super::{Ch1, Ch2, Ch3, Ch4, Channel, GeneralInstance4Channel, TimerBits, TimerChannel, TimerPin};
+use super::ringbuffered::RingBufferedPwmChannel;
+use super::{Ch1, Ch2, Ch3, Ch4, Channel, GeneralInstance4Channel, TimerChannel, TimerPin};
 use crate::Peri;
 #[cfg(gpio_v2)]
 use crate::gpio::Pull;
@@ -158,6 +159,33 @@ impl<'d, T: GeneralInstance4Channel> SimplePwmChannel<'d, T> {
     pub fn set_output_compare_mode(&mut self, mode: OutputCompareMode) {
         self.timer.set_output_compare_mode(self.channel, mode);
     }
+
+    /// Convert this PWM channel into a ring-buffered PWM channel.
+    ///
+    /// This allows continuous PWM waveform generation using a DMA ring buffer.
+    /// The ring buffer enables dynamic updates to the PWM duty cycle without blocking.
+    ///
+    /// # Arguments
+    /// * `tx_dma` - The DMA channel to use for transferring duty cycle values
+    /// * `dma_buf` - The buffer to use as a ring buffer (must be non-empty and <= 65535 elements)
+    ///
+    /// # Panics
+    /// Panics if `dma_buf` is empty or longer than 65535 elements.
+    pub fn into_ring_buffered_channel(
+        mut self,
+        tx_dma: Peri<'d, impl super::UpDma<T>>,
+        dma_buf: &'d mut [u16],
+    ) -> RingBufferedPwmChannel<'d, T> {
+        assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
+
+        self.timer.enable_update_dma(true);
+
+        RingBufferedPwmChannel::new(
+            unsafe { self.timer.clone_unchecked() },
+            self.channel,
+            self.timer.setup_ring_buffer(tx_dma, self.channel, dma_buf),
+        )
+    }
 }
 
 /// A group of four [`SimplePwmChannel`]s, obtained from [`SimplePwm::split`].
@@ -198,7 +226,6 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
         this.inner.set_counting_mode(counting_mode);
         this.set_frequency(freq);
         this.inner.enable_outputs(); // Required for advanced timers, see GeneralInstance4Channel for details
-        this.inner.start();
 
         [Channel::Ch1, Channel::Ch2, Channel::Ch3, Channel::Ch4]
             .iter()
@@ -207,6 +234,11 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
 
                 this.inner.set_output_compare_preload(channel, true);
             });
+        this.inner.set_autoreload_preload(true);
+
+        // Generate update event so pre-load registers are written to the shadow registers
+        this.inner.generate_update_event();
+        this.inner.start();
 
         this
     }
@@ -285,8 +317,8 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
 
     /// Set PWM frequency.
     ///
-    /// Note: when you call this, the max duty value changes, so you will have to
-    /// call `set_duty` on all channels with the duty calculated based on the new max duty.
+    /// Note: that the frequency will not be applied in the timer until an update event
+    /// occurs.
     pub fn set_frequency(&mut self, freq: Hertz) {
         // TODO: prevent ARR = u16::MAX?
         let multiplier = if self.inner.get_counting_mode().is_center_aligned() {
@@ -309,80 +341,14 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
     /// Generate a sequence of PWM waveform
     ///
     /// Note:
-    /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
+    /// You will need to provide corresponding `TIMx_UP` DMA channel to use this method.
+    /// Also be aware that embassy timers use one of timers internally. It is possible to
+    /// switch this timer by using `time-driver-timX` feature.
     pub async fn waveform_up(&mut self, dma: Peri<'_, impl super::UpDma<T>>, channel: Channel, duty: &[u16]) {
-        #[allow(clippy::let_unit_value)] // eg. stm32f334
-        let req = dma.request();
-
-        let original_duty_state = self.channel(channel).current_duty_cycle();
-        let original_enable_state = self.channel(channel).is_enabled();
-        let original_update_dma_state = self.inner.get_update_dma_state();
-
-        if !original_update_dma_state {
-            self.inner.enable_update_dma(true);
-        }
-
-        if !original_enable_state {
-            self.channel(channel).enable();
-        }
-
-        unsafe {
-            #[cfg(not(any(bdma, gpdma)))]
-            use crate::dma::{Burst, FifoThreshold};
-            use crate::dma::{Transfer, TransferOptions};
-
-            let dma_transfer_option = TransferOptions {
-                #[cfg(not(any(bdma, gpdma)))]
-                fifo_threshold: Some(FifoThreshold::Full),
-                #[cfg(not(any(bdma, gpdma)))]
-                mburst: Burst::Incr8,
-                ..Default::default()
-            };
-
-            match self.inner.bits() {
-                TimerBits::Bits16 => {
-                    Transfer::new_write(
-                        dma,
-                        req,
-                        duty,
-                        self.inner.regs_1ch().ccr(channel.index()).as_ptr() as *mut u16,
-                        dma_transfer_option,
-                    )
-                    .await
-                }
-                #[cfg(not(any(stm32l0)))]
-                TimerBits::Bits32 => {
-                    #[cfg(not(any(bdma, gpdma)))]
-                    panic!("unsupported timer bits");
-
-                    #[cfg(any(bdma, gpdma))]
-                    Transfer::new_write(
-                        dma,
-                        req,
-                        duty,
-                        self.inner.regs_1ch().ccr(channel.index()).as_ptr() as *mut u32,
-                        dma_transfer_option,
-                    )
-                    .await
-                }
-            };
-        };
-
-        // restore output compare state
-        if !original_enable_state {
-            self.channel(channel).disable();
-        }
-
-        self.channel(channel).set_duty_cycle(original_duty_state);
-
-        // Since DMA is closed before timer update event trigger DMA is turn off,
-        // this can almost always trigger a DMA FIFO error.
-        //
-        // optional TODO:
-        // clean FEIF after disable UDE
-        if !original_update_dma_state {
-            self.inner.enable_update_dma(false);
-        }
+        self.inner.enable_channel(channel, true);
+        self.inner.enable_update_dma(true);
+        self.inner.setup_update_dma(dma, channel, duty).await;
+        self.inner.enable_update_dma(false);
     }
 
     /// Generate a multichannel sequence of PWM waveforms using DMA triggered by timer update events.
@@ -397,18 +363,23 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
     ///
     /// For example, if using channels 1 through 4, a buffer of 4 update steps might look like:
     ///
+    /// ```rust,ignore
     /// let dma_buf: [u16; 16] = [
     ///     ch1_duty_1, ch2_duty_1, ch3_duty_1, ch4_duty_1, // update 1
     ///     ch1_duty_2, ch2_duty_2, ch3_duty_2, ch4_duty_2, // update 2
     ///     ch1_duty_3, ch2_duty_3, ch3_duty_3, ch4_duty_3, // update 3
     ///     ch1_duty_4, ch2_duty_4, ch3_duty_4, ch4_duty_4, // update 4
     /// ];
+    /// ```
     ///
-    /// Each group of N values (where N = number of channels) is transferred on one update event,
+    /// Each group of `N` values (where `N` is number of channels) is transferred on one update event,
     /// updating the duty cycles of all selected channels simultaneously.
     ///
     /// Note:
-    /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
+    /// You will need to provide corresponding `TIMx_UP` DMA channel to use this method.
+    /// Also be aware that embassy timers use one of timers internally. It is possible to
+    /// switch this timer by using `time-driver-timX` feature.
+    ///
     pub async fn waveform_up_multi_channel(
         &mut self,
         dma: Peri<'_, impl super::UpDma<T>>,
@@ -416,148 +387,11 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
         ending_channel: Channel,
         duty: &[u16],
     ) {
-        let cr1_addr = self.inner.regs_gp16().cr1().as_ptr() as u32;
-        let start_ch_index = starting_channel.index();
-        let end_ch_index = ending_channel.index();
-
-        assert!(start_ch_index <= end_ch_index);
-
-        let ccrx_addr = self.inner.regs_gp16().ccr(start_ch_index).as_ptr() as u32;
-        self.inner
-            .regs_gp16()
-            .dcr()
-            .modify(|w| w.set_dba(((ccrx_addr - cr1_addr) / 4) as u8));
+        self.inner.enable_update_dma(true);
         self.inner
-            .regs_gp16()
-            .dcr()
-            .modify(|w| w.set_dbl((end_ch_index - start_ch_index) as u8));
-
-        #[allow(clippy::let_unit_value)] // eg. stm32f334
-        let req = dma.request();
-
-        let original_update_dma_state = self.inner.get_update_dma_state();
-        if !original_update_dma_state {
-            self.inner.enable_update_dma(true);
-        }
-
-        unsafe {
-            #[cfg(not(any(bdma, gpdma)))]
-            use crate::dma::{Burst, FifoThreshold};
-            use crate::dma::{Transfer, TransferOptions};
-
-            let dma_transfer_option = TransferOptions {
-                #[cfg(not(any(bdma, gpdma)))]
-                fifo_threshold: Some(FifoThreshold::Full),
-                #[cfg(not(any(bdma, gpdma)))]
-                mburst: Burst::Incr4,
-                ..Default::default()
-            };
-
-            Transfer::new_write(
-                dma,
-                req,
-                duty,
-                self.inner.regs_gp16().dmar().as_ptr() as *mut u16,
-                dma_transfer_option,
-            )
-            .await
-        };
-
-        if !original_update_dma_state {
-            self.inner.enable_update_dma(false);
-        }
-    }
-}
-
-impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
-    /// Generate a sequence of PWM waveform
-    pub async fn waveform<C: TimerChannel>(&mut self, dma: Peri<'_, impl super::Dma<T, C>>, duty: &[u16]) {
-        use crate::pac::timer::vals::Ccds;
-
-        #[allow(clippy::let_unit_value)] // eg. stm32f334
-        let req = dma.request();
-
-        let cc_channel = C::CHANNEL;
-
-        let original_duty_state = self.channel(cc_channel).current_duty_cycle();
-        let original_enable_state = self.channel(cc_channel).is_enabled();
-        let original_cc_dma_on_update = self.inner.get_cc_dma_selection() == Ccds::ON_UPDATE;
-        let original_cc_dma_enabled = self.inner.get_cc_dma_enable_state(cc_channel);
-
-        // redirect CC DMA request onto Update Event
-        if !original_cc_dma_on_update {
-            self.inner.set_cc_dma_selection(Ccds::ON_UPDATE)
-        }
-
-        if !original_cc_dma_enabled {
-            self.inner.set_cc_dma_enable_state(cc_channel, true);
-        }
-
-        if !original_enable_state {
-            self.channel(cc_channel).enable();
-        }
-
-        unsafe {
-            #[cfg(not(any(bdma, gpdma)))]
-            use crate::dma::{Burst, FifoThreshold};
-            use crate::dma::{Transfer, TransferOptions};
-
-            let dma_transfer_option = TransferOptions {
-                #[cfg(not(any(bdma, gpdma)))]
-                fifo_threshold: Some(FifoThreshold::Full),
-                #[cfg(not(any(bdma, gpdma)))]
-                mburst: Burst::Incr8,
-                ..Default::default()
-            };
-
-            match self.inner.bits() {
-                TimerBits::Bits16 => {
-                    Transfer::new_write(
-                        dma,
-                        req,
-                        duty,
-                        self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u16,
-                        dma_transfer_option,
-                    )
-                    .await
-                }
-                #[cfg(not(any(stm32l0)))]
-                TimerBits::Bits32 => {
-                    #[cfg(not(any(bdma, gpdma)))]
-                    panic!("unsupported timer bits");
-
-                    #[cfg(any(bdma, gpdma))]
-                    Transfer::new_write(
-                        dma,
-                        req,
-                        duty,
-                        self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u32,
-                        dma_transfer_option,
-                    )
-                    .await
-                }
-            };
-        };
-
-        // restore output compare state
-        if !original_enable_state {
-            self.channel(cc_channel).disable();
-        }
-
-        self.channel(cc_channel).set_duty_cycle(original_duty_state);
-
-        // Since DMA is closed before timer Capture Compare Event trigger DMA is turn off,
-        // this can almost always trigger a DMA FIFO error.
-        //
-        // optional TODO:
-        // clean FEIF after disable UDE
-        if !original_cc_dma_enabled {
-            self.inner.set_cc_dma_enable_state(cc_channel, false);
-        }
-
-        if !original_cc_dma_on_update {
-            self.inner.set_cc_dma_selection(Ccds::ON_COMPARE)
-        }
+            .setup_update_dma_burst(dma, starting_channel, ending_channel, duty)
+            .await;
+        self.inner.enable_update_dma(false);
     }
 }
 
diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs
index 69c3a740f..26d2b8991 100644
--- a/embassy-stm32/src/usart/buffered.rs
+++ b/embassy-stm32/src/usart/buffered.rs
@@ -87,7 +87,7 @@ unsafe fn on_interrupt(r: Regs, state: &'static State) {
     // With `usart_v4` hardware FIFO is enabled and Transmission complete (TC)
     // indicates that all bytes are pushed out from the FIFO.
     // For other usart variants it shows that last byte from the buffer was just sent.
-    if sr_val.tc() {
+    if sr_val.tc() && r.cr1().read().tcie() {
         // For others it is cleared above with `clear_interrupt_flags`.
         #[cfg(any(usart_v1, usart_v2))]
         sr(r).modify(|w| w.set_tc(false));
diff --git a/embassy-stm32/src/xspi/mod.rs b/embassy-stm32/src/xspi/mod.rs
index a80a2692b..466e1a9b4 100644
--- a/embassy-stm32/src/xspi/mod.rs
+++ b/embassy-stm32/src/xspi/mod.rs
@@ -420,9 +420,9 @@ impl<'d, T: Instance, M: PeriMode> Xspi<'d, T, M> {
             return Err(XspiError::InvalidCommand);
         }
 
-        T::REGS.cr().modify(|w| {
-            w.set_fmode(0.into());
-        });
+        T::REGS
+            .cr()
+            .modify(|w| w.set_fmode(Fmode::from_bits(XspiMode::IndirectWrite.into())));
 
         // Configure alternate bytes
         if let Some(ab) = command.alternate_bytes {
@@ -538,8 +538,8 @@ impl<'d, T: Instance, M: PeriMode> Xspi<'d, T, M> {
             w.set_dmaen(false);
         });
 
-        // self.configure_command(&transaction, Some(buf.len()))?;
-        self.configure_command(&transaction, Some(buf.len())).unwrap();
+        let transfer_size_bytes = buf.len() * W::size().bytes();
+        self.configure_command(&transaction, Some(transfer_size_bytes))?;
 
         let current_address = T::REGS.ar().read().address();
         let current_instruction = T::REGS.ir().read().instruction();
@@ -578,7 +578,8 @@ impl<'d, T: Instance, M: PeriMode> Xspi<'d, T, M> {
             w.set_dmaen(false);
         });
 
-        self.configure_command(&transaction, Some(buf.len()))?;
+        let transfer_size_bytes = buf.len() * W::size().bytes();
+        self.configure_command(&transaction, Some(transfer_size_bytes))?;
 
         T::REGS
             .cr()
@@ -1145,7 +1146,8 @@ impl<'d, T: Instance> Xspi<'d, T, Async> {
         // Wait for peripheral to be free
         while T::REGS.sr().read().busy() {}
 
-        self.configure_command(&transaction, Some(buf.len()))?;
+        let transfer_size_bytes = buf.len() * W::size().bytes();
+        self.configure_command(&transaction, Some(transfer_size_bytes))?;
 
         let current_address = T::REGS.ar().read().address();
         let current_instruction = T::REGS.ir().read().instruction();
@@ -1160,16 +1162,18 @@ impl<'d, T: Instance> Xspi<'d, T, Async> {
             T::REGS.ar().write(|v| v.set_address(current_address));
         }
 
-        let transfer = unsafe {
-            self.dma
-                .as_mut()
-                .unwrap()
-                .read(T::REGS.dr().as_ptr() as *mut W, buf, Default::default())
-        };
+        for chunk in buf.chunks_mut(0xFFFF / W::size().bytes()) {
+            let transfer = unsafe {
+                self.dma
+                    .as_mut()
+                    .unwrap()
+                    .read(T::REGS.dr().as_ptr() as *mut W, chunk, Default::default())
+            };
 
-        T::REGS.cr().modify(|w| w.set_dmaen(true));
+            T::REGS.cr().modify(|w| w.set_dmaen(true));
 
-        transfer.blocking_wait();
+            transfer.blocking_wait();
+        }
 
         finish_dma(T::REGS);
 
@@ -1185,21 +1189,24 @@ impl<'d, T: Instance> Xspi<'d, T, Async> {
         // Wait for peripheral to be free
         while T::REGS.sr().read().busy() {}
 
-        self.configure_command(&transaction, Some(buf.len()))?;
+        let transfer_size_bytes = buf.len() * W::size().bytes();
+        self.configure_command(&transaction, Some(transfer_size_bytes))?;
         T::REGS
             .cr()
             .modify(|v| v.set_fmode(Fmode::from_bits(XspiMode::IndirectWrite.into())));
 
-        let transfer = unsafe {
-            self.dma
-                .as_mut()
-                .unwrap()
-                .write(buf, T::REGS.dr().as_ptr() as *mut W, Default::default())
-        };
+        for chunk in buf.chunks(0xFFFF / W::size().bytes()) {
+            let transfer = unsafe {
+                self.dma
+                    .as_mut()
+                    .unwrap()
+                    .write(chunk, T::REGS.dr().as_ptr() as *mut W, Default::default())
+            };
 
-        T::REGS.cr().modify(|w| w.set_dmaen(true));
+            T::REGS.cr().modify(|w| w.set_dmaen(true));
 
-        transfer.blocking_wait();
+            transfer.blocking_wait();
+        }
 
         finish_dma(T::REGS);
 
@@ -1215,7 +1222,8 @@ impl<'d, T: Instance> Xspi<'d, T, Async> {
         // Wait for peripheral to be free
         while T::REGS.sr().read().busy() {}
 
-        self.configure_command(&transaction, Some(buf.len()))?;
+        let transfer_size_bytes = buf.len() * W::size().bytes();
+        self.configure_command(&transaction, Some(transfer_size_bytes))?;
 
         let current_address = T::REGS.ar().read().address();
         let current_instruction = T::REGS.ir().read().instruction();
@@ -1230,16 +1238,18 @@ impl<'d, T: Instance> Xspi<'d, T, Async> {
             T::REGS.ar().write(|v| v.set_address(current_address));
         }
 
-        let transfer = unsafe {
-            self.dma
-                .as_mut()
-                .unwrap()
-                .read(T::REGS.dr().as_ptr() as *mut W, buf, Default::default())
-        };
+        for chunk in buf.chunks_mut(0xFFFF / W::size().bytes()) {
+            let transfer = unsafe {
+                self.dma
+                    .as_mut()
+                    .unwrap()
+                    .read(T::REGS.dr().as_ptr() as *mut W, chunk, Default::default())
+            };
 
-        T::REGS.cr().modify(|w| w.set_dmaen(true));
+            T::REGS.cr().modify(|w| w.set_dmaen(true));
 
-        transfer.await;
+            transfer.await;
+        }
 
         finish_dma(T::REGS);
 
@@ -1255,21 +1265,25 @@ impl<'d, T: Instance> Xspi<'d, T, Async> {
         // Wait for peripheral to be free
         while T::REGS.sr().read().busy() {}
 
-        self.configure_command(&transaction, Some(buf.len()))?;
+        let transfer_size_bytes = buf.len() * W::size().bytes();
+        self.configure_command(&transaction, Some(transfer_size_bytes))?;
         T::REGS
             .cr()
             .modify(|v| v.set_fmode(Fmode::from_bits(XspiMode::IndirectWrite.into())));
 
-        let transfer = unsafe {
-            self.dma
-                .as_mut()
-                .unwrap()
-                .write(buf, T::REGS.dr().as_ptr() as *mut W, Default::default())
-        };
+        // TODO: implement this using a LinkedList DMA to offload the whole transfer off the CPU.
+        for chunk in buf.chunks(0xFFFF / W::size().bytes()) {
+            let transfer = unsafe {
+                self.dma
+                    .as_mut()
+                    .unwrap()
+                    .write(chunk, T::REGS.dr().as_ptr() as *mut W, Default::default())
+            };
 
-        T::REGS.cr().modify(|w| w.set_dmaen(true));
+            T::REGS.cr().modify(|w| w.set_dmaen(true));
 
-        transfer.await;
+            transfer.await;
+        }
 
         finish_dma(T::REGS);
 
diff --git a/embassy-time-driver/CHANGELOG.md b/embassy-time-driver/CHANGELOG.md
index cdd432437..4951f8c3e 100644
--- a/embassy-time-driver/CHANGELOG.md
+++ b/embassy-time-driver/CHANGELOG.md
@@ -11,7 +11,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ## 0.2.1 - 2025-08-26
 
 - Allow inlining on time driver boundary
-- add 133MHz tick rate to support PR2040 @ 133MHz when `TIMERx`'s `SOURCE` is set to `SYSCLK`
+- Add 133MHz tick rate to support PR2040 @ 133MHz when `TIMERx`'s `SOURCE` is set to `SYSCLK`
+- Add 375KHz tick rate support
 
 ## 0.2.0 - 2025-01-02
 
diff --git a/embassy-time-driver/Cargo.toml b/embassy-time-driver/Cargo.toml
index a52e82433..cbb6168b9 100644
--- a/embassy-time-driver/Cargo.toml
+++ b/embassy-time-driver/Cargo.toml
@@ -118,6 +118,8 @@ tick-hz-256_000 = []
 tick-hz-262_144 = []
 ## 320.0kHz Tick Rate
 tick-hz-320_000 = []
+## 375.0kHz Tick Rate
+tick-hz-375_000 = []
 ## 512.0kHz Tick Rate
 tick-hz-512_000 = []
 ## 524.288kHz Tick Rate
diff --git a/embassy-time-driver/gen_tick.py b/embassy-time-driver/gen_tick.py
index 080434457..3cb6552df 100644
--- a/embassy-time-driver/gen_tick.py
+++ b/embassy-time-driver/gen_tick.py
@@ -1,5 +1,4 @@
 import os
-from glob import glob
 
 abspath = os.path.abspath(__file__)
 dname = os.path.dirname(abspath)
@@ -22,6 +21,8 @@ for i in range(1, 30):
     ticks.append(10 * i * 1_000_000)
 for i in range(15, 50):
     ticks.append(20 * i * 1_000_000)
+
+ticks.append(375 * 1000)
 ticks.append(133 * 1_000_000)
 
 seen = set()
diff --git a/embassy-time-driver/src/tick.rs b/embassy-time-driver/src/tick.rs
index 5059e1628..247ec9ab3 100644
--- a/embassy-time-driver/src/tick.rs
+++ b/embassy-time-driver/src/tick.rs
@@ -74,6 +74,8 @@ pub const TICK_HZ: u64 = 256_000;
 pub const TICK_HZ: u64 = 262_144;
 #[cfg(feature = "tick-hz-320_000")]
 pub const TICK_HZ: u64 = 320_000;
+#[cfg(feature = "tick-hz-375_000")]
+pub const TICK_HZ: u64 = 375_000;
 #[cfg(feature = "tick-hz-512_000")]
 pub const TICK_HZ: u64 = 512_000;
 #[cfg(feature = "tick-hz-524_288")]
@@ -358,6 +360,7 @@ pub const TICK_HZ: u64 = 5_242_880_000;
     feature = "tick-hz-256_000",
     feature = "tick-hz-262_144",
     feature = "tick-hz-320_000",
+    feature = "tick-hz-375_000",
     feature = "tick-hz-512_000",
     feature = "tick-hz-524_288",
     feature = "tick-hz-640_000",
diff --git a/embassy-time/CHANGELOG.md b/embassy-time/CHANGELOG.md
index 4a50da8ef..17f8a3837 100644
--- a/embassy-time/CHANGELOG.md
+++ b/embassy-time/CHANGELOG.md
@@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ## Unreleased - ReleaseDate
 
 - Add as_nanos and from_nanos where missing
+- Added 375KHz tick rate support
 
 ## 0.5.0 - 2025-08-26
 
diff --git a/embassy-time/Cargo.toml b/embassy-time/Cargo.toml
index 05614dbf5..a7ed51e78 100644
--- a/embassy-time/Cargo.toml
+++ b/embassy-time/Cargo.toml
@@ -178,6 +178,8 @@ tick-hz-256_000 = ["embassy-time-driver/tick-hz-256_000"]
 tick-hz-262_144 = ["embassy-time-driver/tick-hz-262_144"]
 ## 320.0kHz Tick Rate
 tick-hz-320_000 = ["embassy-time-driver/tick-hz-320_000"]
+## 375.0kHz Tick Rate
+tick-hz-375_000 = ["embassy-time-driver/tick-hz-375_000"]
 ## 512.0kHz Tick Rate
 tick-hz-512_000 = ["embassy-time-driver/tick-hz-512_000"]
 ## 524.288kHz Tick Rate
diff --git a/embassy-usb/CHANGELOG.md b/embassy-usb/CHANGELOG.md
index 0a30bc24b..cfb1bf021 100644
--- a/embassy-usb/CHANGELOG.md
+++ b/embassy-usb/CHANGELOG.md
@@ -8,6 +8,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 <!-- next-header -->
 ## Unreleased - ReleaseDate
 
+- Add support for USB HID Boot Protocol Mode 
+
 ## 0.5.1 - 2025-08-26
 
 ## 0.5.0 - 2025-07-16
diff --git a/embassy-usb/src/class/hid.rs b/embassy-usb/src/class/hid.rs
index 182e1f83f..64e8fd59f 100644
--- a/embassy-usb/src/class/hid.rs
+++ b/embassy-usb/src/class/hid.rs
@@ -15,8 +15,6 @@ use crate::types::InterfaceNumber;
 use crate::{Builder, Handler};
 
 const USB_CLASS_HID: u8 = 0x03;
-const USB_SUBCLASS_NONE: u8 = 0x00;
-const USB_PROTOCOL_NONE: u8 = 0x00;
 
 // HID
 const HID_DESC_DESCTYPE_HID: u8 = 0x21;
@@ -31,6 +29,52 @@ const HID_REQ_SET_REPORT: u8 = 0x09;
 const HID_REQ_GET_PROTOCOL: u8 = 0x03;
 const HID_REQ_SET_PROTOCOL: u8 = 0x0b;
 
+/// Get/Set Protocol mapping
+/// See (7.2.5 and 7.2.6): <https://www.usb.org/sites/default/files/hid1_11.pdf>
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[repr(u8)]
+pub enum HidProtocolMode {
+    /// Hid Boot Protocol Mode
+    Boot = 0,
+    /// Hid Report Protocol Mode
+    Report = 1,
+}
+
+impl From<u8> for HidProtocolMode {
+    fn from(mode: u8) -> HidProtocolMode {
+        if mode == HidProtocolMode::Boot as u8 {
+            HidProtocolMode::Boot
+        } else {
+            HidProtocolMode::Report
+        }
+    }
+}
+
+/// USB HID interface subclass values.
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[repr(u8)]
+pub enum HidSubclass {
+    /// No subclass, standard HID device.
+    No = 0,
+    /// Boot interface subclass, supports BIOS boot protocol.
+    Boot = 1,
+}
+
+/// USB HID protocol values.
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[repr(u8)]
+pub enum HidBootProtocol {
+    /// No boot protocol.
+    None = 0,
+    /// Keyboard boot protocol.
+    Keyboard = 1,
+    /// Mouse boot protocol.
+    Mouse = 2,
+}
+
 /// Configuration for the HID class.
 pub struct Config<'d> {
     /// HID report descriptor.
@@ -48,6 +92,12 @@ pub struct Config<'d> {
 
     /// Max packet size for both the IN and OUT endpoints.
     pub max_packet_size: u16,
+
+    /// The HID subclass of this interface
+    pub hid_subclass: HidSubclass,
+
+    /// The HID boot protocol of this interface
+    pub hid_boot_protocol: HidBootProtocol,
 }
 
 /// Report ID
@@ -109,10 +159,15 @@ fn build<'d, D: Driver<'d>>(
 ) -> (Option<D::EndpointOut>, D::EndpointIn, &'d AtomicUsize) {
     let len = config.report_descriptor.len();
 
-    let mut func = builder.function(USB_CLASS_HID, USB_SUBCLASS_NONE, USB_PROTOCOL_NONE);
+    let mut func = builder.function(USB_CLASS_HID, config.hid_subclass as u8, config.hid_boot_protocol as u8);
     let mut iface = func.interface();
     let if_num = iface.interface_number();
-    let mut alt = iface.alt_setting(USB_CLASS_HID, USB_SUBCLASS_NONE, USB_PROTOCOL_NONE, None);
+    let mut alt = iface.alt_setting(
+        USB_CLASS_HID,
+        config.hid_subclass as u8,
+        config.hid_boot_protocol as u8,
+        None,
+    );
 
     // HID descriptor
     alt.descriptor(
@@ -389,6 +444,23 @@ pub trait RequestHandler {
         OutResponse::Rejected
     }
 
+    /// Gets the current hid protocol.
+    ///
+    /// Returns `Report` protocol by default.
+    fn get_protocol(&self) -> HidProtocolMode {
+        HidProtocolMode::Report
+    }
+
+    /// Sets the current hid protocol to `protocol`.
+    ///
+    /// Accepts only `Report` protocol by default.
+    fn set_protocol(&mut self, protocol: HidProtocolMode) -> OutResponse {
+        match protocol {
+            HidProtocolMode::Report => OutResponse::Accepted,
+            HidProtocolMode::Boot => OutResponse::Rejected,
+        }
+    }
+
     /// Get the idle rate for `id`.
     ///
     /// If `id` is `None`, get the idle rate for all reports. Returning `None`
@@ -482,11 +554,14 @@ impl<'d> Handler for Control<'d> {
                 _ => Some(OutResponse::Rejected),
             },
             HID_REQ_SET_PROTOCOL => {
-                if req.value == 1 {
-                    Some(OutResponse::Accepted)
-                } else {
-                    warn!("HID Boot Protocol is unsupported.");
-                    Some(OutResponse::Rejected) // UNSUPPORTED: Boot Protocol
+                let hid_protocol = HidProtocolMode::from(req.value as u8);
+                match (self.request_handler.as_mut(), hid_protocol) {
+                    (Some(request_handler), hid_protocol) => Some(request_handler.set_protocol(hid_protocol)),
+                    (None, HidProtocolMode::Report) => Some(OutResponse::Accepted),
+                    (None, HidProtocolMode::Boot) => {
+                        info!("Received request to switch to Boot protocol mode, but it is disabled by default.");
+                        Some(OutResponse::Rejected)
+                    }
                 }
             }
             _ => Some(OutResponse::Rejected),
@@ -539,8 +614,12 @@ impl<'d> Handler for Control<'d> {
                         }
                     }
                     HID_REQ_GET_PROTOCOL => {
-                        // UNSUPPORTED: Boot Protocol
-                        buf[0] = 1;
+                        if let Some(request_handler) = self.request_handler.as_mut() {
+                            buf[0] = request_handler.get_protocol() as u8;
+                        } else {
+                            // Return `Report` protocol mode by default
+                            buf[0] = HidProtocolMode::Report as u8;
+                        }
                         Some(InResponse::Accepted(&buf[0..1]))
                     }
                     _ => Some(InResponse::Rejected),
diff --git a/examples/boot/application/stm32f3/src/bin/a.rs b/examples/boot/application/stm32f3/src/bin/a.rs
index b608b2e01..da3cbf1e6 100644
--- a/examples/boot/application/stm32f3/src/bin/a.rs
+++ b/examples/boot/application/stm32f3/src/bin/a.rs
@@ -6,12 +6,18 @@ use defmt_rtt::*;
 use embassy_boot_stm32::{AlignedBuffer, FirmwareUpdater, FirmwareUpdaterConfig};
 use embassy_embedded_hal::adapter::BlockingAsync;
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::flash::{Flash, WRITE_SIZE};
 use embassy_stm32::gpio::{Level, Output, Pull, Speed};
+use embassy_stm32::{bind_interrupts, interrupt};
 use embassy_sync::mutex::Mutex;
 use panic_reset as _;
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI15_10 => exti::InterruptHandler<interrupt::typelevel::EXTI15_10>;
+});
+
 #[cfg(feature = "skip-include")]
 static APP_B: &[u8] = &[0, 1, 2, 3];
 #[cfg(not(feature = "skip-include"))]
@@ -23,7 +29,7 @@ async fn main(_spawner: Spawner) {
     let flash = Flash::new_blocking(p.FLASH);
     let flash = Mutex::new(BlockingAsync::new(flash));
 
-    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up);
+    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up, Irqs);
 
     let mut led = Output::new(p.PA5, Level::Low, Speed::Low);
     led.set_high();
diff --git a/examples/boot/application/stm32f7/src/bin/a.rs b/examples/boot/application/stm32f7/src/bin/a.rs
index 172b4c235..62f1da269 100644
--- a/examples/boot/application/stm32f7/src/bin/a.rs
+++ b/examples/boot/application/stm32f7/src/bin/a.rs
@@ -7,9 +7,10 @@ use core::cell::RefCell;
 use defmt_rtt::*;
 use embassy_boot_stm32::{AlignedBuffer, BlockingFirmwareUpdater, FirmwareUpdaterConfig};
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::flash::{Flash, WRITE_SIZE};
 use embassy_stm32::gpio::{Level, Output, Pull, Speed};
+use embassy_stm32::{bind_interrupts, interrupt};
 use embassy_sync::blocking_mutex::Mutex;
 use embedded_storage::nor_flash::NorFlash;
 use panic_reset as _;
@@ -19,13 +20,18 @@ static APP_B: &[u8] = &[0, 1, 2, 3];
 #[cfg(not(feature = "skip-include"))]
 static APP_B: &[u8] = include_bytes!("../../b.bin");
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI15_10 => exti::InterruptHandler<interrupt::typelevel::EXTI15_10>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     let flash = Flash::new_blocking(p.FLASH);
     let flash = Mutex::new(RefCell::new(flash));
 
-    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down);
+    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down, Irqs);
 
     let mut led = Output::new(p.PB7, Level::Low, Speed::Low);
     led.set_high();
diff --git a/examples/boot/application/stm32h7/src/bin/a.rs b/examples/boot/application/stm32h7/src/bin/a.rs
index c1b1a267a..226971e02 100644
--- a/examples/boot/application/stm32h7/src/bin/a.rs
+++ b/examples/boot/application/stm32h7/src/bin/a.rs
@@ -7,13 +7,19 @@ use core::cell::RefCell;
 use defmt_rtt::*;
 use embassy_boot_stm32::{AlignedBuffer, BlockingFirmwareUpdater, FirmwareUpdaterConfig};
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::flash::{Flash, WRITE_SIZE};
 use embassy_stm32::gpio::{Level, Output, Pull, Speed};
+use embassy_stm32::{bind_interrupts, interrupt};
 use embassy_sync::blocking_mutex::Mutex;
 use embedded_storage::nor_flash::NorFlash;
 use panic_reset as _;
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI15_10 => exti::InterruptHandler<interrupt::typelevel::EXTI15_10>;
+});
+
 #[cfg(feature = "skip-include")]
 static APP_B: &[u8] = &[0, 1, 2, 3];
 #[cfg(not(feature = "skip-include"))]
@@ -25,7 +31,7 @@ async fn main(_spawner: Spawner) {
     let flash = Flash::new_blocking(p.FLASH);
     let flash = Mutex::new(RefCell::new(flash));
 
-    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down);
+    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down, Irqs);
 
     let mut led = Output::new(p.PB14, Level::Low, Speed::Low);
     led.set_high();
diff --git a/examples/boot/application/stm32l0/src/bin/a.rs b/examples/boot/application/stm32l0/src/bin/a.rs
index dcc10e5c6..0aa723eaa 100644
--- a/examples/boot/application/stm32l0/src/bin/a.rs
+++ b/examples/boot/application/stm32l0/src/bin/a.rs
@@ -6,13 +6,19 @@ use defmt_rtt::*;
 use embassy_boot_stm32::{AlignedBuffer, FirmwareUpdater, FirmwareUpdaterConfig};
 use embassy_embedded_hal::adapter::BlockingAsync;
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::flash::{Flash, WRITE_SIZE};
 use embassy_stm32::gpio::{Level, Output, Pull, Speed};
+use embassy_stm32::{bind_interrupts, interrupt};
 use embassy_sync::mutex::Mutex;
 use embassy_time::Timer;
 use panic_reset as _;
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI2_3 => exti::InterruptHandler<interrupt::typelevel::EXTI2_3>;
+});
+
 #[cfg(feature = "skip-include")]
 static APP_B: &[u8] = &[0, 1, 2, 3];
 #[cfg(not(feature = "skip-include"))]
@@ -24,7 +30,7 @@ async fn main(_spawner: Spawner) {
     let flash = Flash::new_blocking(p.FLASH);
     let flash = Mutex::new(BlockingAsync::new(flash));
 
-    let mut button = ExtiInput::new(p.PB2, p.EXTI2, Pull::Up);
+    let mut button = ExtiInput::new(p.PB2, p.EXTI2, Pull::Up, Irqs);
 
     let mut led = Output::new(p.PB5, Level::Low, Speed::Low);
 
diff --git a/examples/boot/application/stm32l1/src/bin/a.rs b/examples/boot/application/stm32l1/src/bin/a.rs
index dcc10e5c6..7ad7046fb 100644
--- a/examples/boot/application/stm32l1/src/bin/a.rs
+++ b/examples/boot/application/stm32l1/src/bin/a.rs
@@ -6,9 +6,10 @@ use defmt_rtt::*;
 use embassy_boot_stm32::{AlignedBuffer, FirmwareUpdater, FirmwareUpdaterConfig};
 use embassy_embedded_hal::adapter::BlockingAsync;
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::flash::{Flash, WRITE_SIZE};
 use embassy_stm32::gpio::{Level, Output, Pull, Speed};
+use embassy_stm32::{bind_interrupts, interrupt};
 use embassy_sync::mutex::Mutex;
 use embassy_time::Timer;
 use panic_reset as _;
@@ -18,13 +19,18 @@ static APP_B: &[u8] = &[0, 1, 2, 3];
 #[cfg(not(feature = "skip-include"))]
 static APP_B: &[u8] = include_bytes!("../../b.bin");
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI2 => exti::InterruptHandler<interrupt::typelevel::EXTI2>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     let flash = Flash::new_blocking(p.FLASH);
     let flash = Mutex::new(BlockingAsync::new(flash));
 
-    let mut button = ExtiInput::new(p.PB2, p.EXTI2, Pull::Up);
+    let mut button = ExtiInput::new(p.PB2, p.EXTI2, Pull::Up, Irqs);
 
     let mut led = Output::new(p.PB5, Level::Low, Speed::Low);
 
diff --git a/examples/boot/application/stm32l4/src/bin/a.rs b/examples/boot/application/stm32l4/src/bin/a.rs
index 7f8015c04..4edd338c5 100644
--- a/examples/boot/application/stm32l4/src/bin/a.rs
+++ b/examples/boot/application/stm32l4/src/bin/a.rs
@@ -6,9 +6,10 @@ use defmt_rtt::*;
 use embassy_boot_stm32::{AlignedBuffer, FirmwareUpdater, FirmwareUpdaterConfig};
 use embassy_embedded_hal::adapter::BlockingAsync;
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::flash::{Flash, WRITE_SIZE};
 use embassy_stm32::gpio::{Level, Output, Pull, Speed};
+use embassy_stm32::{bind_interrupts, interrupt};
 use embassy_sync::mutex::Mutex;
 use panic_reset as _;
 
@@ -17,13 +18,18 @@ static APP_B: &[u8] = &[0, 1, 2, 3];
 #[cfg(not(feature = "skip-include"))]
 static APP_B: &[u8] = include_bytes!("../../b.bin");
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI15_10 => exti::InterruptHandler<interrupt::typelevel::EXTI15_10>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     let flash = Flash::new_blocking(p.FLASH);
     let flash = Mutex::new(BlockingAsync::new(flash));
 
-    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up);
+    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up, Irqs);
 
     let mut led = Output::new(p.PB14, Level::Low, Speed::Low);
     led.set_high();
diff --git a/examples/boot/application/stm32wl/src/bin/a.rs b/examples/boot/application/stm32wl/src/bin/a.rs
index 3f381fd80..58063eb50 100644
--- a/examples/boot/application/stm32wl/src/bin/a.rs
+++ b/examples/boot/application/stm32wl/src/bin/a.rs
@@ -8,10 +8,10 @@ use defmt_rtt::*;
 use embassy_boot_stm32::{AlignedBuffer, FirmwareUpdater, FirmwareUpdaterConfig};
 use embassy_embedded_hal::adapter::BlockingAsync;
 use embassy_executor::Spawner;
-use embassy_stm32::SharedData;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::flash::{Flash, WRITE_SIZE};
 use embassy_stm32::gpio::{Level, Output, Pull, Speed};
+use embassy_stm32::{SharedData, bind_interrupts, interrupt};
 use embassy_sync::mutex::Mutex;
 use panic_reset as _;
 
@@ -20,6 +20,11 @@ static APP_B: &[u8] = &[0, 1, 2, 3];
 #[cfg(not(feature = "skip-include"))]
 static APP_B: &[u8] = include_bytes!("../../b.bin");
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI0 => exti::InterruptHandler<interrupt::typelevel::EXTI0>;
+});
+
 #[unsafe(link_section = ".shared_data")]
 static SHARED_DATA: MaybeUninit<SharedData> = MaybeUninit::uninit();
 
@@ -29,7 +34,7 @@ async fn main(_spawner: Spawner) {
     let flash = Flash::new_blocking(p.FLASH);
     let flash = Mutex::new(BlockingAsync::new(flash));
 
-    let mut button = ExtiInput::new(p.PA0, p.EXTI0, Pull::Up);
+    let mut button = ExtiInput::new(p.PA0, p.EXTI0, Pull::Up, Irqs);
 
     let mut led = Output::new(p.PB9, Level::Low, Speed::Low);
     led.set_high();
diff --git a/examples/lpc55s69/src/bin/pwm.rs b/examples/lpc55s69/src/bin/pwm.rs
index 93b898b9d..8a9894b94 100644
--- a/examples/lpc55s69/src/bin/pwm.rs
+++ b/examples/lpc55s69/src/bin/pwm.rs
@@ -10,7 +10,7 @@ use {defmt_rtt as _, panic_halt as _};
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_nxp::init(Default::default());
-    let pwm = Pwm::new_output(p.PWM_OUTPUT1, p.PIO0_18, Config::new(1_000_000_000, 2_000_000_000));
+    let pwm = Pwm::new_output(p.SCT0_OUT1, p.PIO0_18, Config::new(1_000_000_000, 2_000_000_000));
     loop {
         info!("Counter: {}", pwm.counter());
         Timer::after_millis(50).await;
diff --git a/examples/lpc55s69/src/bin/usart_async.rs b/examples/lpc55s69/src/bin/usart_async.rs
index b06abd477..a9815b920 100644
--- a/examples/lpc55s69/src/bin/usart_async.rs
+++ b/examples/lpc55s69/src/bin/usart_async.rs
@@ -38,8 +38,8 @@ async fn main(spawner: Spawner) {
         p.PIO0_27,
         p.PIO1_24,
         Irqs,
-        p.DMA_CH11,
-        p.DMA_CH10,
+        p.DMA0_CH11,
+        p.DMA0_CH10,
         Config::default(),
     );
     let led = Output::new(p.PIO1_6, Level::Low);
diff --git a/examples/mspm0g3507/src/bin/mathacl_ops.rs b/examples/mspm0g3507/src/bin/mathacl_ops.rs
new file mode 100644
index 000000000..25d74b29b
--- /dev/null
+++ b/examples/mspm0g3507/src/bin/mathacl_ops.rs
@@ -0,0 +1,39 @@
+//! Example of using mathematical calculations performed by the MSPM0G3507 chip.
+//!
+//! It prints the result of basics trigonometric calculation.
+
+#![no_std]
+#![no_main]
+
+use core::f32::consts::PI;
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_mspm0::mathacl::{Mathacl, Precision};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_halt as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) -> ! {
+    info!("Hello world!");
+
+    let d = embassy_mspm0::init(Default::default());
+
+    let mut macl = Mathacl::new(d.MATHACL);
+
+    // value radians [-PI; PI]
+    let rads = PI * 0.5;
+    match macl.sin(rads, Precision::High) {
+        Ok(res) => info!("sin({}) = {}", rads, res),
+        Err(e) => error!("sin Error: {:?}", e),
+    }
+
+    match macl.cos(rads, Precision::Medium) {
+        Ok(res) => info!("cos({}) = {}", rads, res),
+        Err(e) => error!("cos Error: {:?}", e),
+    }
+
+    loop {
+        Timer::after_millis(500).await;
+    }
+}
diff --git a/examples/nrf52840/src/bin/gpiote_channel.rs b/examples/nrf52840/src/bin/gpiote_channel.rs
index c7ddc1d8d..e358779b2 100644
--- a/examples/nrf52840/src/bin/gpiote_channel.rs
+++ b/examples/nrf52840/src/bin/gpiote_channel.rs
@@ -12,10 +12,10 @@ async fn main(_spawner: Spawner) {
     let p = embassy_nrf::init(Default::default());
     info!("Starting!");
 
-    let ch1 = InputChannel::new(p.GPIOTE_CH0, p.P0_11, Pull::Up, InputChannelPolarity::HiToLo);
-    let ch2 = InputChannel::new(p.GPIOTE_CH1, p.P0_12, Pull::Up, InputChannelPolarity::LoToHi);
-    let ch3 = InputChannel::new(p.GPIOTE_CH2, p.P0_24, Pull::Up, InputChannelPolarity::Toggle);
-    let ch4 = InputChannel::new(p.GPIOTE_CH3, p.P0_25, Pull::Up, InputChannelPolarity::Toggle);
+    let mut ch1 = InputChannel::new(p.GPIOTE_CH0, p.P0_11, Pull::Up, InputChannelPolarity::HiToLo);
+    let mut ch2 = InputChannel::new(p.GPIOTE_CH1, p.P0_12, Pull::Up, InputChannelPolarity::LoToHi);
+    let mut ch3 = InputChannel::new(p.GPIOTE_CH2, p.P0_24, Pull::Up, InputChannelPolarity::Toggle);
+    let mut ch4 = InputChannel::new(p.GPIOTE_CH3, p.P0_25, Pull::Up, InputChannelPolarity::Toggle);
 
     let button1 = async {
         loop {
diff --git a/examples/nrf52840/src/bin/usb_hid_keyboard.rs b/examples/nrf52840/src/bin/usb_hid_keyboard.rs
index 1cd730503..7b7303526 100644
--- a/examples/nrf52840/src/bin/usb_hid_keyboard.rs
+++ b/examples/nrf52840/src/bin/usb_hid_keyboard.rs
@@ -1,7 +1,7 @@
 #![no_std]
 #![no_main]
 
-use core::sync::atomic::{AtomicBool, Ordering};
+use core::sync::atomic::{AtomicBool, AtomicU8, Ordering};
 
 use defmt::*;
 use embassy_executor::Spawner;
@@ -13,7 +13,9 @@ use embassy_nrf::usb::vbus_detect::HardwareVbusDetect;
 use embassy_nrf::{bind_interrupts, pac, peripherals, usb};
 use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_sync::signal::Signal;
-use embassy_usb::class::hid::{HidReaderWriter, ReportId, RequestHandler, State};
+use embassy_usb::class::hid::{
+    HidBootProtocol, HidProtocolMode, HidReaderWriter, HidSubclass, ReportId, RequestHandler, State,
+};
 use embassy_usb::control::OutResponse;
 use embassy_usb::{Builder, Config, Handler};
 use usbd_hid::descriptor::{KeyboardReport, SerializedDescriptor};
@@ -26,6 +28,8 @@ bind_interrupts!(struct Irqs {
 
 static SUSPENDED: AtomicBool = AtomicBool::new(false);
 
+static HID_PROTOCOL_MODE: AtomicU8 = AtomicU8::new(HidProtocolMode::Boot as u8);
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_nrf::init(Default::default());
@@ -45,6 +49,10 @@ async fn main(_spawner: Spawner) {
     config.max_power = 100;
     config.max_packet_size_0 = 64;
     config.supports_remote_wakeup = true;
+    config.composite_with_iads = false;
+    config.device_class = 0;
+    config.device_sub_class = 0;
+    config.device_protocol = 0;
 
     // Create embassy-usb DeviceBuilder using the driver and config.
     // It needs some buffers for building the descriptors.
@@ -74,6 +82,8 @@ async fn main(_spawner: Spawner) {
         request_handler: None,
         poll_ms: 60,
         max_packet_size: 64,
+        hid_subclass: HidSubclass::Boot,
+        hid_boot_protocol: HidBootProtocol::Keyboard,
     };
     let hid = HidReaderWriter::<_, 1, 8>::new(&mut builder, &mut state, config);
 
@@ -106,6 +116,11 @@ async fn main(_spawner: Spawner) {
             if SUSPENDED.load(Ordering::Acquire) {
                 info!("Triggering remote wakeup");
                 remote_wakeup.signal(());
+            } else if HID_PROTOCOL_MODE.load(Ordering::Relaxed) == HidProtocolMode::Boot as u8 {
+                match writer.write(&[0, 0, 4, 0, 0, 0, 0, 0]).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send boot report: {:?}", e),
+                };
             } else {
                 let report = KeyboardReport {
                     keycodes: [4, 0, 0, 0, 0, 0],
@@ -121,16 +136,23 @@ async fn main(_spawner: Spawner) {
 
             button.wait_for_high().await;
             info!("RELEASED");
-            let report = KeyboardReport {
-                keycodes: [0, 0, 0, 0, 0, 0],
-                leds: 0,
-                modifier: 0,
-                reserved: 0,
-            };
-            match writer.write_serialize(&report).await {
-                Ok(()) => {}
-                Err(e) => warn!("Failed to send report: {:?}", e),
-            };
+            if HID_PROTOCOL_MODE.load(Ordering::Relaxed) == HidProtocolMode::Boot as u8 {
+                match writer.write(&[0, 0, 0, 0, 0, 0, 0, 0]).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send boot report: {:?}", e),
+                };
+            } else {
+                let report = KeyboardReport {
+                    keycodes: [0, 0, 0, 0, 0, 0],
+                    leds: 0,
+                    modifier: 0,
+                    reserved: 0,
+                };
+                match writer.write_serialize(&report).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send report: {:?}", e),
+                };
+            }
         }
     };
 
@@ -156,6 +178,18 @@ impl RequestHandler for MyRequestHandler {
         OutResponse::Accepted
     }
 
+    fn get_protocol(&self) -> HidProtocolMode {
+        let protocol = HidProtocolMode::from(HID_PROTOCOL_MODE.load(Ordering::Relaxed));
+        info!("The current HID protocol mode is: {}", protocol);
+        protocol
+    }
+
+    fn set_protocol(&mut self, protocol: HidProtocolMode) -> OutResponse {
+        info!("Switching to HID protocol mode: {}", protocol);
+        HID_PROTOCOL_MODE.store(protocol as u8, Ordering::Relaxed);
+        OutResponse::Accepted
+    }
+
     fn set_idle_ms(&mut self, id: Option<ReportId>, dur: u32) {
         info!("Set idle rate for {:?} to {:?}", id, dur);
     }
diff --git a/examples/nrf52840/src/bin/usb_hid_mouse.rs b/examples/nrf52840/src/bin/usb_hid_mouse.rs
index 3c0fc04e8..6bee4546b 100644
--- a/examples/nrf52840/src/bin/usb_hid_mouse.rs
+++ b/examples/nrf52840/src/bin/usb_hid_mouse.rs
@@ -1,6 +1,8 @@
 #![no_std]
 #![no_main]
 
+use core::sync::atomic::{AtomicU8, Ordering};
+
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_futures::join::join;
@@ -8,7 +10,9 @@ use embassy_nrf::usb::Driver;
 use embassy_nrf::usb::vbus_detect::HardwareVbusDetect;
 use embassy_nrf::{bind_interrupts, pac, peripherals, usb};
 use embassy_time::Timer;
-use embassy_usb::class::hid::{HidWriter, ReportId, RequestHandler, State};
+use embassy_usb::class::hid::{
+    HidBootProtocol, HidProtocolMode, HidSubclass, HidWriter, ReportId, RequestHandler, State,
+};
 use embassy_usb::control::OutResponse;
 use embassy_usb::{Builder, Config};
 use usbd_hid::descriptor::{MouseReport, SerializedDescriptor};
@@ -19,6 +23,8 @@ bind_interrupts!(struct Irqs {
     CLOCK_POWER => usb::vbus_detect::InterruptHandler;
 });
 
+static HID_PROTOCOL_MODE: AtomicU8 = AtomicU8::new(HidProtocolMode::Boot as u8);
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_nrf::init(Default::default());
@@ -37,6 +43,10 @@ async fn main(_spawner: Spawner) {
     config.serial_number = Some("12345678");
     config.max_power = 100;
     config.max_packet_size_0 = 64;
+    config.composite_with_iads = false;
+    config.device_class = 0;
+    config.device_sub_class = 0;
+    config.device_protocol = 0;
 
     // Create embassy-usb DeviceBuilder using the driver and config.
     // It needs some buffers for building the descriptors.
@@ -63,6 +73,8 @@ async fn main(_spawner: Spawner) {
         request_handler: Some(&mut request_handler),
         poll_ms: 60,
         max_packet_size: 8,
+        hid_subclass: HidSubclass::Boot,
+        hid_boot_protocol: HidBootProtocol::Mouse,
     };
 
     let mut writer = HidWriter::<_, 5>::new(&mut builder, &mut state, config);
@@ -80,16 +92,26 @@ async fn main(_spawner: Spawner) {
             Timer::after_millis(500).await;
 
             y = -y;
-            let report = MouseReport {
-                buttons: 0,
-                x: 0,
-                y,
-                wheel: 0,
-                pan: 0,
-            };
-            match writer.write_serialize(&report).await {
-                Ok(()) => {}
-                Err(e) => warn!("Failed to send report: {:?}", e),
+
+            if HID_PROTOCOL_MODE.load(Ordering::Relaxed) == HidProtocolMode::Boot as u8 {
+                let buttons = 0u8;
+                let x = 0i8;
+                match writer.write(&[buttons, x as u8, y as u8]).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send boot report: {:?}", e),
+                }
+            } else {
+                let report = MouseReport {
+                    buttons: 0,
+                    x: 0,
+                    y,
+                    wheel: 0,
+                    pan: 0,
+                };
+                match writer.write_serialize(&report).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send report: {:?}", e),
+                }
             }
         }
     };
@@ -112,6 +134,18 @@ impl RequestHandler for MyRequestHandler {
         OutResponse::Accepted
     }
 
+    fn get_protocol(&self) -> HidProtocolMode {
+        let protocol = HidProtocolMode::from(HID_PROTOCOL_MODE.load(Ordering::Relaxed));
+        info!("The current HID protocol mode is: {}", protocol);
+        protocol
+    }
+
+    fn set_protocol(&mut self, protocol: HidProtocolMode) -> OutResponse {
+        info!("Switching to HID protocol mode: {}", protocol);
+        HID_PROTOCOL_MODE.store(protocol as u8, Ordering::Relaxed);
+        OutResponse::Accepted
+    }
+
     fn set_idle_ms(&mut self, id: Option<ReportId>, dur: u32) {
         info!("Set idle rate for {:?} to {:?}", id, dur);
     }
diff --git a/examples/nrf5340/src/bin/gpiote_channel.rs b/examples/nrf5340/src/bin/gpiote_channel.rs
index a085310ce..41ee732c3 100644
--- a/examples/nrf5340/src/bin/gpiote_channel.rs
+++ b/examples/nrf5340/src/bin/gpiote_channel.rs
@@ -12,10 +12,10 @@ async fn main(_spawner: Spawner) {
     let p = embassy_nrf::init(Default::default());
     info!("Starting!");
 
-    let ch1 = InputChannel::new(p.GPIOTE_CH0, p.P0_23, Pull::Up, InputChannelPolarity::HiToLo);
-    let ch2 = InputChannel::new(p.GPIOTE_CH1, p.P0_24, Pull::Up, InputChannelPolarity::LoToHi);
-    let ch3 = InputChannel::new(p.GPIOTE_CH2, p.P0_08, Pull::Up, InputChannelPolarity::Toggle);
-    let ch4 = InputChannel::new(p.GPIOTE_CH3, p.P0_09, Pull::Up, InputChannelPolarity::Toggle);
+    let mut ch1 = InputChannel::new(p.GPIOTE_CH0, p.P0_23, Pull::Up, InputChannelPolarity::HiToLo);
+    let mut ch2 = InputChannel::new(p.GPIOTE_CH1, p.P0_24, Pull::Up, InputChannelPolarity::LoToHi);
+    let mut ch3 = InputChannel::new(p.GPIOTE_CH2, p.P0_08, Pull::Up, InputChannelPolarity::Toggle);
+    let mut ch4 = InputChannel::new(p.GPIOTE_CH3, p.P0_09, Pull::Up, InputChannelPolarity::Toggle);
 
     let button1 = async {
         loop {
diff --git a/examples/nrf54l15/memory.x b/examples/nrf54l15/memory.x
index 1064c8a5c..332200828 100644
--- a/examples/nrf54l15/memory.x
+++ b/examples/nrf54l15/memory.x
@@ -1,5 +1,5 @@
 MEMORY
 {
-  FLASH : ORIGIN = 0x00000000, LENGTH = 1536K
+  FLASH : ORIGIN = 0x00000000, LENGTH = 1524K
   RAM : ORIGIN = 0x20000000, LENGTH = 256K
 }
diff --git a/examples/nrf54l15/src/bin/gpiote_channel.rs b/examples/nrf54l15/src/bin/gpiote_channel.rs
index 6333250ba..cac8823f8 100644
--- a/examples/nrf54l15/src/bin/gpiote_channel.rs
+++ b/examples/nrf54l15/src/bin/gpiote_channel.rs
@@ -12,10 +12,10 @@ async fn main(_spawner: Spawner) {
     let p = embassy_nrf::init(Default::default());
     info!("Starting!");
 
-    let ch1 = InputChannel::new(p.GPIOTE20_CH0, p.P1_13, Pull::Up, InputChannelPolarity::HiToLo);
-    let ch2 = InputChannel::new(p.GPIOTE20_CH1, p.P1_09, Pull::Up, InputChannelPolarity::LoToHi);
-    let ch3 = InputChannel::new(p.GPIOTE20_CH2, p.P1_08, Pull::Up, InputChannelPolarity::Toggle);
-    let ch4 = InputChannel::new(p.GPIOTE30_CH0, p.P0_04, Pull::Up, InputChannelPolarity::Toggle);
+    let mut ch1 = InputChannel::new(p.GPIOTE20_CH0, p.P1_13, Pull::Up, InputChannelPolarity::HiToLo);
+    let mut ch2 = InputChannel::new(p.GPIOTE20_CH1, p.P1_09, Pull::Up, InputChannelPolarity::LoToHi);
+    let mut ch3 = InputChannel::new(p.GPIOTE20_CH2, p.P1_08, Pull::Up, InputChannelPolarity::Toggle);
+    let mut ch4 = InputChannel::new(p.GPIOTE30_CH0, p.P0_04, Pull::Up, InputChannelPolarity::Toggle);
 
     let button1 = async {
         loop {
diff --git a/examples/rp/src/bin/usb_hid_keyboard.rs b/examples/rp/src/bin/usb_hid_keyboard.rs
index a7cb322d8..2f6d169bf 100644
--- a/examples/rp/src/bin/usb_hid_keyboard.rs
+++ b/examples/rp/src/bin/usb_hid_keyboard.rs
@@ -1,7 +1,7 @@
 #![no_std]
 #![no_main]
 
-use core::sync::atomic::{AtomicBool, Ordering};
+use core::sync::atomic::{AtomicBool, AtomicU8, Ordering};
 
 use defmt::*;
 use embassy_executor::Spawner;
@@ -10,7 +10,9 @@ use embassy_rp::bind_interrupts;
 use embassy_rp::gpio::{Input, Pull};
 use embassy_rp::peripherals::USB;
 use embassy_rp::usb::{Driver, InterruptHandler};
-use embassy_usb::class::hid::{HidReaderWriter, ReportId, RequestHandler, State};
+use embassy_usb::class::hid::{
+    HidBootProtocol, HidProtocolMode, HidReaderWriter, HidSubclass, ReportId, RequestHandler, State,
+};
 use embassy_usb::control::OutResponse;
 use embassy_usb::{Builder, Config, Handler};
 use usbd_hid::descriptor::{KeyboardReport, SerializedDescriptor};
@@ -20,6 +22,8 @@ bind_interrupts!(struct Irqs {
     USBCTRL_IRQ => InterruptHandler<USB>;
 });
 
+static HID_PROTOCOL_MODE: AtomicU8 = AtomicU8::new(HidProtocolMode::Boot as u8);
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_rp::init(Default::default());
@@ -33,6 +37,10 @@ async fn main(_spawner: Spawner) {
     config.serial_number = Some("12345678");
     config.max_power = 100;
     config.max_packet_size_0 = 64;
+    config.composite_with_iads = false;
+    config.device_class = 0;
+    config.device_sub_class = 0;
+    config.device_protocol = 0;
 
     // Create embassy-usb DeviceBuilder using the driver and config.
     // It needs some buffers for building the descriptors.
@@ -63,6 +71,8 @@ async fn main(_spawner: Spawner) {
         request_handler: None,
         poll_ms: 60,
         max_packet_size: 64,
+        hid_subclass: HidSubclass::Boot,
+        hid_boot_protocol: HidBootProtocol::Keyboard,
     };
     let hid = HidReaderWriter::<_, 1, 8>::new(&mut builder, &mut state, config);
 
@@ -86,30 +96,46 @@ async fn main(_spawner: Spawner) {
             info!("Waiting for HIGH on pin 16");
             signal_pin.wait_for_high().await;
             info!("HIGH DETECTED");
-            // Create a report with the A key pressed. (no shift modifier)
-            let report = KeyboardReport {
-                keycodes: [4, 0, 0, 0, 0, 0],
-                leds: 0,
-                modifier: 0,
-                reserved: 0,
-            };
-            // Send the report.
-            match writer.write_serialize(&report).await {
-                Ok(()) => {}
-                Err(e) => warn!("Failed to send report: {:?}", e),
-            };
+
+            if HID_PROTOCOL_MODE.load(Ordering::Relaxed) == HidProtocolMode::Boot as u8 {
+                match writer.write(&[0, 0, 4, 0, 0, 0, 0, 0]).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send boot report: {:?}", e),
+                };
+            } else {
+                // Create a report with the A key pressed. (no shift modifier)
+                let report = KeyboardReport {
+                    keycodes: [4, 0, 0, 0, 0, 0],
+                    leds: 0,
+                    modifier: 0,
+                    reserved: 0,
+                };
+                // Send the report.
+                match writer.write_serialize(&report).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send report: {:?}", e),
+                };
+            }
+
             signal_pin.wait_for_low().await;
             info!("LOW DETECTED");
-            let report = KeyboardReport {
-                keycodes: [0, 0, 0, 0, 0, 0],
-                leds: 0,
-                modifier: 0,
-                reserved: 0,
-            };
-            match writer.write_serialize(&report).await {
-                Ok(()) => {}
-                Err(e) => warn!("Failed to send report: {:?}", e),
-            };
+            if HID_PROTOCOL_MODE.load(Ordering::Relaxed) == HidProtocolMode::Boot as u8 {
+                match writer.write(&[0, 0, 0, 0, 0, 0, 0, 0]).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send boot report: {:?}", e),
+                };
+            } else {
+                let report = KeyboardReport {
+                    keycodes: [0, 0, 0, 0, 0, 0],
+                    leds: 0,
+                    modifier: 0,
+                    reserved: 0,
+                };
+                match writer.write_serialize(&report).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send report: {:?}", e),
+                };
+            }
         }
     };
 
@@ -135,6 +161,18 @@ impl RequestHandler for MyRequestHandler {
         OutResponse::Accepted
     }
 
+    fn get_protocol(&self) -> HidProtocolMode {
+        let protocol = HidProtocolMode::from(HID_PROTOCOL_MODE.load(Ordering::Relaxed));
+        info!("The current HID protocol mode is: {}", protocol);
+        protocol
+    }
+
+    fn set_protocol(&mut self, protocol: HidProtocolMode) -> OutResponse {
+        info!("Switching to HID protocol mode: {}", protocol);
+        HID_PROTOCOL_MODE.store(protocol as u8, Ordering::Relaxed);
+        OutResponse::Accepted
+    }
+
     fn set_idle_ms(&mut self, id: Option<ReportId>, dur: u32) {
         info!("Set idle rate for {:?} to {:?}", id, dur);
     }
diff --git a/examples/rp/src/bin/usb_hid_mouse.rs b/examples/rp/src/bin/usb_hid_mouse.rs
index 4454c593c..dc331cbdd 100755
--- a/examples/rp/src/bin/usb_hid_mouse.rs
+++ b/examples/rp/src/bin/usb_hid_mouse.rs
@@ -1,7 +1,7 @@
 #![no_std]
 #![no_main]
 
-use core::sync::atomic::{AtomicBool, Ordering};
+use core::sync::atomic::{AtomicBool, AtomicU8, Ordering};
 
 use defmt::*;
 use embassy_executor::Spawner;
@@ -11,7 +11,9 @@ use embassy_rp::clocks::RoscRng;
 use embassy_rp::peripherals::USB;
 use embassy_rp::usb::{Driver, InterruptHandler};
 use embassy_time::Timer;
-use embassy_usb::class::hid::{HidReaderWriter, ReportId, RequestHandler, State};
+use embassy_usb::class::hid::{
+    HidBootProtocol, HidProtocolMode, HidReaderWriter, HidSubclass, ReportId, RequestHandler, State,
+};
 use embassy_usb::control::OutResponse;
 use embassy_usb::{Builder, Config, Handler};
 use rand::Rng;
@@ -22,6 +24,8 @@ bind_interrupts!(struct Irqs {
     USBCTRL_IRQ => InterruptHandler<USB>;
 });
 
+static HID_PROTOCOL_MODE: AtomicU8 = AtomicU8::new(HidProtocolMode::Boot as u8);
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_rp::init(Default::default());
@@ -35,6 +39,10 @@ async fn main(_spawner: Spawner) {
     config.serial_number = Some("12345678");
     config.max_power = 100;
     config.max_packet_size_0 = 64;
+    config.composite_with_iads = false;
+    config.device_class = 0;
+    config.device_sub_class = 0;
+    config.device_protocol = 0;
 
     // Create embassy-usb DeviceBuilder using the driver and config.
     // It needs some buffers for building the descriptors.
@@ -65,6 +73,8 @@ async fn main(_spawner: Spawner) {
         request_handler: None,
         poll_ms: 60,
         max_packet_size: 64,
+        hid_subclass: HidSubclass::Boot,
+        hid_boot_protocol: HidBootProtocol::Mouse,
     };
     let hid = HidReaderWriter::<_, 1, 8>::new(&mut builder, &mut state, config);
 
@@ -83,17 +93,29 @@ async fn main(_spawner: Spawner) {
         loop {
             // every 1 second
             _ = Timer::after_secs(1).await;
-            let report = MouseReport {
-                buttons: 0,
-                x: rng.random_range(-100..100), // random small x movement
-                y: rng.random_range(-100..100), // random small y movement
-                wheel: 0,
-                pan: 0,
-            };
-            // Send the report.
-            match writer.write_serialize(&report).await {
-                Ok(()) => {}
-                Err(e) => warn!("Failed to send report: {:?}", e),
+
+            let x = rng.random_range(-100..100); // random small x movement
+            let y = rng.random_range(-100..100); // random small y movement
+
+            if HID_PROTOCOL_MODE.load(Ordering::Relaxed) == HidProtocolMode::Boot as u8 {
+                let buttons = 0u8;
+                match writer.write(&[buttons, x as u8, y as u8]).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send boot report: {:?}", e),
+                }
+            } else {
+                let report = MouseReport {
+                    buttons: 0,
+                    x,
+                    y,
+                    wheel: 0,
+                    pan: 0,
+                };
+                // Send the report.
+                match writer.write_serialize(&report).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send report: {:?}", e),
+                }
             }
         }
     };
@@ -120,6 +142,18 @@ impl RequestHandler for MyRequestHandler {
         OutResponse::Accepted
     }
 
+    fn get_protocol(&self) -> HidProtocolMode {
+        let protocol = HidProtocolMode::from(HID_PROTOCOL_MODE.load(Ordering::Relaxed));
+        info!("The current HID protocol mode is: {}", protocol);
+        protocol
+    }
+
+    fn set_protocol(&mut self, protocol: HidProtocolMode) -> OutResponse {
+        info!("Switching to HID protocol mode: {}", protocol);
+        HID_PROTOCOL_MODE.store(protocol as u8, Ordering::Relaxed);
+        OutResponse::Accepted
+    }
+
     fn set_idle_ms(&mut self, id: Option<ReportId>, dur: u32) {
         info!("Set idle rate for {:?} to {:?}", id, dur);
     }
diff --git a/examples/rp/src/bin/wifi_webrequest.rs b/examples/rp/src/bin/wifi_webrequest.rs
index b618d2b38..ce85f4b9a 100644
--- a/examples/rp/src/bin/wifi_webrequest.rs
+++ b/examples/rp/src/bin/wifi_webrequest.rs
@@ -1,9 +1,8 @@
 //! This example uses the RP Pico W board Wifi chip (cyw43).
-//! Connects to Wifi network and makes a web request to get the current time.
+//! Connects to Wifi network and makes a web request to httpbin.org.
 
 #![no_std]
 #![no_main]
-#![allow(async_fn_in_trait)]
 
 use core::str::from_utf8;
 
@@ -20,11 +19,14 @@ use embassy_rp::gpio::{Level, Output};
 use embassy_rp::peripherals::{DMA_CH0, PIO0};
 use embassy_rp::pio::{InterruptHandler, Pio};
 use embassy_time::{Duration, Timer};
-use reqwless::client::{HttpClient, TlsConfig, TlsVerify};
+use reqwless::client::HttpClient;
+// Uncomment these for TLS requests:
+// use reqwless::client::{HttpClient, TlsConfig, TlsVerify};
 use reqwless::request::Method;
 use serde::Deserialize;
+use serde_json_core::from_slice;
 use static_cell::StaticCell;
-use {defmt_rtt as _, panic_probe as _, serde_json_core};
+use {defmt_rtt as _, panic_probe as _};
 
 bind_interrupts!(struct Irqs {
     PIO0_IRQ_0 => InterruptHandler<PIO0>;
@@ -119,64 +121,90 @@ async fn main(spawner: Spawner) {
     // And now we can use it!
 
     loop {
-        let mut rx_buffer = [0; 8192];
-        let mut tls_read_buffer = [0; 16640];
-        let mut tls_write_buffer = [0; 16640];
+        let mut rx_buffer = [0; 4096];
+        // Uncomment these for TLS requests:
+        // let mut tls_read_buffer = [0; 16640];
+        // let mut tls_write_buffer = [0; 16640];
 
-        let client_state = TcpClientState::<1, 1024, 1024>::new();
+        let client_state = TcpClientState::<1, 4096, 4096>::new();
         let tcp_client = TcpClient::new(stack, &client_state);
         let dns_client = DnsSocket::new(stack);
-        let tls_config = TlsConfig::new(seed, &mut tls_read_buffer, &mut tls_write_buffer, TlsVerify::None);
+        // Uncomment these for TLS requests:
+        // let tls_config = TlsConfig::new(seed, &mut tls_read_buffer, &mut tls_write_buffer, TlsVerify::None);
 
-        let mut http_client = HttpClient::new_with_tls(&tcp_client, &dns_client, tls_config);
-        let url = "https://worldtimeapi.org/api/timezone/Europe/Berlin";
-        // for non-TLS requests, use this instead:
-        // let mut http_client = HttpClient::new(&tcp_client, &dns_client);
-        // let url = "http://worldtimeapi.org/api/timezone/Europe/Berlin";
+        // Using non-TLS HTTP for this example
+        let mut http_client = HttpClient::new(&tcp_client, &dns_client);
+        let url = "http://httpbin.org/json";
+        // For TLS requests, use this instead:
+        // let mut http_client = HttpClient::new_with_tls(&tcp_client, &dns_client, tls_config);
+        // let url = "https://httpbin.org/json";
 
         info!("connecting to {}", &url);
 
-        let mut request = match http_client.request(Method::GET, &url).await {
+        let mut request = match http_client.request(Method::GET, url).await {
             Ok(req) => req,
             Err(e) => {
                 error!("Failed to make HTTP request: {:?}", e);
-                return; // handle the error
+                Timer::after(Duration::from_secs(5)).await;
+                continue;
             }
         };
 
         let response = match request.send(&mut rx_buffer).await {
             Ok(resp) => resp,
-            Err(_e) => {
-                error!("Failed to send HTTP request");
-                return; // handle the error;
+            Err(e) => {
+                error!("Failed to send HTTP request: {:?}", e);
+                Timer::after(Duration::from_secs(5)).await;
+                continue;
             }
         };
 
-        let body = match from_utf8(response.body().read_to_end().await.unwrap()) {
+        info!("Response status: {}", response.status.0);
+
+        let body_bytes = match response.body().read_to_end().await {
             Ok(b) => b,
             Err(_e) => {
                 error!("Failed to read response body");
-                return; // handle the error
+                Timer::after(Duration::from_secs(5)).await;
+                continue;
+            }
+        };
+
+        let body = match from_utf8(body_bytes) {
+            Ok(b) => b,
+            Err(_e) => {
+                error!("Failed to parse response body as UTF-8");
+                Timer::after(Duration::from_secs(5)).await;
+                continue;
             }
         };
-        info!("Response body: {:?}", &body);
+        info!("Response body length: {} bytes", body.len());
 
-        // parse the response body and update the RTC
+        // Parse the JSON response from httpbin.org/json
+        #[derive(Deserialize)]
+        struct SlideShow<'a> {
+            author: &'a str,
+            title: &'a str,
+        }
 
         #[derive(Deserialize)]
-        struct ApiResponse<'a> {
-            datetime: &'a str,
-            // other fields as needed
+        struct HttpBinResponse<'a> {
+            #[serde(borrow)]
+            slideshow: SlideShow<'a>,
         }
 
         let bytes = body.as_bytes();
-        match serde_json_core::de::from_slice::<ApiResponse>(bytes) {
+        match from_slice::<HttpBinResponse>(bytes) {
             Ok((output, _used)) => {
-                info!("Datetime: {:?}", output.datetime);
+                info!("Successfully parsed JSON response!");
+                info!("Slideshow title: {:?}", output.slideshow.title);
+                info!("Slideshow author: {:?}", output.slideshow.author);
             }
-            Err(_e) => {
-                error!("Failed to parse response body");
-                return; // handle the error
+            Err(e) => {
+                error!("Failed to parse JSON response: {}", Debug2Format(&e));
+                // Log preview of response for debugging
+                let preview = if body.len() > 200 { &body[..200] } else { body };
+                info!("Response preview: {:?}", preview);
             }
         }
 
diff --git a/examples/rp235x/src/bin/usb_hid_keyboard.rs b/examples/rp235x/src/bin/usb_hid_keyboard.rs
index 6f496e23a..d8f64c470 100644
--- a/examples/rp235x/src/bin/usb_hid_keyboard.rs
+++ b/examples/rp235x/src/bin/usb_hid_keyboard.rs
@@ -1,7 +1,7 @@
 #![no_std]
 #![no_main]
 
-use core::sync::atomic::{AtomicBool, Ordering};
+use core::sync::atomic::{AtomicBool, AtomicU8, Ordering};
 
 use defmt::*;
 use embassy_executor::Spawner;
@@ -10,7 +10,9 @@ use embassy_rp::bind_interrupts;
 use embassy_rp::gpio::{Input, Pull};
 use embassy_rp::peripherals::USB;
 use embassy_rp::usb::{Driver as UsbDriver, InterruptHandler};
-use embassy_usb::class::hid::{HidReaderWriter, ReportId, RequestHandler, State as HidState};
+use embassy_usb::class::hid::{
+    HidBootProtocol, HidProtocolMode, HidReaderWriter, HidSubclass, ReportId, RequestHandler, State as HidState,
+};
 use embassy_usb::control::OutResponse;
 use embassy_usb::{Builder, Config, Handler};
 use usbd_hid::descriptor::{KeyboardReport, SerializedDescriptor};
@@ -20,6 +22,8 @@ bind_interrupts!(struct Irqs {
     USBCTRL_IRQ => InterruptHandler<USB>;
 });
 
+static HID_PROTOCOL_MODE: AtomicU8 = AtomicU8::new(HidProtocolMode::Boot as u8);
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_rp::init(Default::default());
@@ -33,6 +37,10 @@ async fn main(_spawner: Spawner) {
     config.serial_number = Some("12345678");
     config.max_power = 100;
     config.max_packet_size_0 = 64;
+    config.composite_with_iads = false;
+    config.device_class = 0;
+    config.device_sub_class = 0;
+    config.device_protocol = 0;
 
     // Create embassy-usb DeviceBuilder using the driver and config.
     // It needs some buffers for building the descriptors.
@@ -63,6 +71,8 @@ async fn main(_spawner: Spawner) {
         request_handler: None,
         poll_ms: 60,
         max_packet_size: 64,
+        hid_subclass: HidSubclass::Boot,
+        hid_boot_protocol: HidBootProtocol::Keyboard,
     };
     let hid = HidReaderWriter::<_, 1, 8>::new(&mut builder, &mut state, config);
 
@@ -86,30 +96,45 @@ async fn main(_spawner: Spawner) {
             info!("Waiting for HIGH on pin 16");
             signal_pin.wait_for_high().await;
             info!("HIGH DETECTED");
-            // Create a report with the A key pressed. (no shift modifier)
-            let report = KeyboardReport {
-                keycodes: [4, 0, 0, 0, 0, 0],
-                leds: 0,
-                modifier: 0,
-                reserved: 0,
-            };
-            // Send the report.
-            match writer.write_serialize(&report).await {
-                Ok(()) => {}
-                Err(e) => warn!("Failed to send report: {:?}", e),
-            };
+
+            if HID_PROTOCOL_MODE.load(Ordering::Relaxed) == HidProtocolMode::Boot as u8 {
+                match writer.write(&[0, 0, 4, 0, 0, 0, 0, 0]).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send boot report: {:?}", e),
+                };
+            } else {
+                // Create a report with the A key pressed. (no shift modifier)
+                let report = KeyboardReport {
+                    keycodes: [4, 0, 0, 0, 0, 0],
+                    leds: 0,
+                    modifier: 0,
+                    reserved: 0,
+                };
+                // Send the report.
+                match writer.write_serialize(&report).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send report: {:?}", e),
+                };
+            }
             signal_pin.wait_for_low().await;
             info!("LOW DETECTED");
-            let report = KeyboardReport {
-                keycodes: [0, 0, 0, 0, 0, 0],
-                leds: 0,
-                modifier: 0,
-                reserved: 0,
-            };
-            match writer.write_serialize(&report).await {
-                Ok(()) => {}
-                Err(e) => warn!("Failed to send report: {:?}", e),
-            };
+            if HID_PROTOCOL_MODE.load(Ordering::Relaxed) == HidProtocolMode::Boot as u8 {
+                match writer.write(&[0, 0, 0, 0, 0, 0, 0, 0]).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send boot report: {:?}", e),
+                };
+            } else {
+                let report = KeyboardReport {
+                    keycodes: [0, 0, 0, 0, 0, 0],
+                    leds: 0,
+                    modifier: 0,
+                    reserved: 0,
+                };
+                match writer.write_serialize(&report).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send report: {:?}", e),
+                };
+            }
         }
     };
 
@@ -135,6 +160,18 @@ impl RequestHandler for MyRequestHandler {
         OutResponse::Accepted
     }
 
+    fn get_protocol(&self) -> HidProtocolMode {
+        let protocol = HidProtocolMode::from(HID_PROTOCOL_MODE.load(Ordering::Relaxed));
+        info!("The current HID protocol mode is: {}", protocol);
+        protocol
+    }
+
+    fn set_protocol(&mut self, protocol: HidProtocolMode) -> OutResponse {
+        info!("Switching to HID protocol mode: {}", protocol);
+        HID_PROTOCOL_MODE.store(protocol as u8, Ordering::Relaxed);
+        OutResponse::Accepted
+    }
+
     fn set_idle_ms(&mut self, id: Option<ReportId>, dur: u32) {
         info!("Set idle rate for {:?} to {:?}", id, dur);
     }
diff --git a/examples/stm32c0/src/bin/adc.rs b/examples/stm32c0/src/bin/adc.rs
index b52c9e7f8..ad597b63c 100644
--- a/examples/stm32c0/src/bin/adc.rs
+++ b/examples/stm32c0/src/bin/adc.rs
@@ -3,7 +3,6 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::adc::vals::Scandir;
 use embassy_stm32::adc::{Adc, AdcChannel, AnyAdcChannel, Resolution, SampleTime};
 use embassy_stm32::peripherals::ADC1;
 use embassy_time::Timer;
@@ -35,8 +34,12 @@ async fn main(_spawner: Spawner) {
             blocking_vref, blocking_temp, blocing_pin0
         );
 
-        let channels_seqence: [&mut AnyAdcChannel<ADC1>; 3] = [&mut vref, &mut temp, &mut pin0];
-        adc.read(dma.reborrow(), channels_seqence.into_iter(), &mut read_buffer)
+        let channels_sequence: [(&mut AnyAdcChannel<ADC1>, SampleTime); 3] = [
+            (&mut vref, SampleTime::CYCLES12_5),
+            (&mut temp, SampleTime::CYCLES12_5),
+            (&mut pin0, SampleTime::CYCLES12_5),
+        ];
+        adc.read(dma.reborrow(), channels_sequence.into_iter(), &mut read_buffer)
             .await;
         // Values are ordered according to hardware ADC channel number!
         info!(
@@ -44,15 +47,6 @@ async fn main(_spawner: Spawner) {
             read_buffer[0], read_buffer[1], read_buffer[2]
         );
 
-        let hw_channel_selection: u32 =
-            (1 << temp.get_hw_channel()) + (1 << vref.get_hw_channel()) + (1 << pin0.get_hw_channel());
-        adc.read_in_hw_order(dma.reborrow(), hw_channel_selection, Scandir::UP, &mut read_buffer)
-            .await;
-        info!(
-            "DMA ADC read in hardware order: vref = {}, temp = {}, pin0 = {}.",
-            read_buffer[2], read_buffer[1], read_buffer[0]
-        );
-
         Timer::after_millis(2000).await;
     }
 }
diff --git a/examples/stm32c0/src/bin/button_exti.rs b/examples/stm32c0/src/bin/button_exti.rs
index 34a08bbc6..9d54479da 100644
--- a/examples/stm32c0/src/bin/button_exti.rs
+++ b/examples/stm32c0/src/bin/button_exti.rs
@@ -3,16 +3,22 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::gpio::Pull;
+use embassy_stm32::{bind_interrupts, interrupt};
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI4_15 => exti::InterruptHandler<interrupt::typelevel::EXTI4_15>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Hello World!");
 
-    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up);
+    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up, Irqs);
 
     info!("Press the USER button...");
 
diff --git a/examples/stm32f0/Cargo.toml b/examples/stm32f0/Cargo.toml
index a78873d21..177dd0ac2 100644
--- a/examples/stm32f0/Cargo.toml
+++ b/examples/stm32f0/Cargo.toml
@@ -16,6 +16,7 @@ panic-probe = { version = "1.0.0", features = ["print-defmt"] }
 embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
+embedded-hal-1 = { package = "embedded-hal", version = "1.0" }
 static_cell = "2"
 portable-atomic = { version = "1.5", features = ["unsafe-assume-single-core"] }
 
diff --git a/examples/stm32f0/src/bin/button_controlled_blink.rs b/examples/stm32f0/src/bin/button_controlled_blink.rs
index 0b678af01..9c7bf8a95 100644
--- a/examples/stm32f0/src/bin/button_controlled_blink.rs
+++ b/examples/stm32f0/src/bin/button_controlled_blink.rs
@@ -7,14 +7,19 @@ use core::sync::atomic::{AtomicU32, Ordering};
 
 use defmt::info;
 use embassy_executor::Spawner;
-use embassy_stm32::Peri;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::gpio::{AnyPin, Level, Output, Pull, Speed};
+use embassy_stm32::{Peri, bind_interrupts, interrupt};
 use embassy_time::Timer;
 use {defmt_rtt as _, panic_probe as _};
 
 static BLINK_MS: AtomicU32 = AtomicU32::new(0);
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI4_15 => exti::InterruptHandler<interrupt::typelevel::EXTI4_15>;
+});
+
 #[embassy_executor::task]
 async fn led_task(led: Peri<'static, AnyPin>) {
     // Configure the LED pin as a push pull output and obtain handler.
@@ -37,7 +42,7 @@ async fn main(spawner: Spawner) {
 
     // Configure the button pin and obtain handler.
     // On the Nucleo F091RC there is a button connected to pin PC13.
-    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::None);
+    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::None, Irqs);
 
     // Create and initialize a delay variable to manage delay loop
     let mut del_var = 2000;
diff --git a/examples/stm32f0/src/bin/button_exti.rs b/examples/stm32f0/src/bin/button_exti.rs
index fd615a215..d1312e1be 100644
--- a/examples/stm32f0/src/bin/button_exti.rs
+++ b/examples/stm32f0/src/bin/button_exti.rs
@@ -3,17 +3,23 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::gpio::Pull;
+use embassy_stm32::{bind_interrupts, interrupt};
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI4_15 => exti::InterruptHandler<interrupt::typelevel::EXTI4_15>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     // Initialize and create handle for devicer peripherals
     let p = embassy_stm32::init(Default::default());
     // Configure the button pin and obtain handler.
     // On the Nucleo F091RC there is a button connected to pin PC13.
-    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down);
+    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down, Irqs);
 
     info!("Press the USER button...");
     loop {
diff --git a/examples/stm32f0/src/bin/i2c_master.rs b/examples/stm32f0/src/bin/i2c_master.rs
new file mode 100644
index 000000000..2e61ecdf7
--- /dev/null
+++ b/examples/stm32f0/src/bin/i2c_master.rs
@@ -0,0 +1,609 @@
+#![no_std]
+#![no_main]
+
+// Hardware Setup for NUCLEO-F072RB:
+// - I2C1 pins: PB8 (SCL), PB9 (SDA) on CN5 connector
+// - Connect to I2C slave device (e.g., Digilent Analog Discovery I2C slave, or EEPROM)
+// - Default slave address: 0x50
+// - Pull-up resistors: 4.7kΩ on both SCL and SDA
+// - CN5 Pin 10 (PB8/SCL) and CN5 Pin 9 (PB9/SDA)
+//
+// Analog Discovery - Waveforms Setup:
+// - Increase buffer size: Settings -> Device Manager -> Option 4
+// - Run Protocol Analyzer
+// - Configure as I2C Slave at address 0x50
+// - Connect and configure DIO pins for SCL and SDA
+// - Frequency: 100kHz - [✓] Clock Stretching
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::i2c::{Config, I2c, Master};
+use embassy_stm32::mode::{Async, Blocking};
+use embassy_stm32::time::Hertz;
+use embassy_stm32::{bind_interrupts, i2c, peripherals};
+use embassy_time::Timer;
+use embedded_hal_1::i2c::Operation;
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    I2C1 => i2c::EventInterruptHandler<peripherals::I2C1>, i2c::ErrorInterruptHandler<peripherals::I2C1>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = embassy_stm32::init(Default::default());
+    info!("Run stm32 I2C v2 Master Tests...");
+
+    let mut i2c_peri = p.I2C1;
+    let mut scl = p.PB8;
+    let mut sda = p.PB9;
+
+    let mut config = Config::default();
+    config.frequency = Hertz(100_000);
+
+    // I2C slave address for Analog Discovery or test EEPROM
+    let slave_addr = 0x50u8;
+
+    // Wait for slave device to be ready
+    Timer::after_millis(100).await;
+
+    // ========== BLOCKING DIRECT API TESTS ==========
+    info!("========== BLOCKING DIRECT API TESTS ==========");
+    {
+        let mut i2c = I2c::new_blocking(i2c_peri.reborrow(), scl.reborrow(), sda.reborrow(), config);
+
+        info!("=== Test 1: Direct blocking_write ===");
+        test_blocking_write(&mut i2c, slave_addr);
+
+        info!("=== Test 2: Direct blocking_read ===");
+        test_blocking_read(&mut i2c, slave_addr);
+
+        info!("=== Test 3: Direct blocking_write_read ===");
+        test_blocking_write_read(&mut i2c, slave_addr);
+
+        info!("=== Test 4: Direct blocking_write_vectored ===");
+        test_blocking_write_vectored(&mut i2c, slave_addr);
+
+        info!("=== Test 5: Large buffer (>255 bytes) ===");
+        test_blocking_large_buffer(&mut i2c, slave_addr);
+
+        info!("Blocking direct API tests OK");
+    }
+
+    Timer::after_millis(100).await;
+
+    // ========== BLOCKING TRANSACTION TESTS ==========
+    info!("========== BLOCKING TRANSACTION TESTS ==========");
+    {
+        let mut i2c = I2c::new_blocking(i2c_peri.reborrow(), scl.reborrow(), sda.reborrow(), config);
+
+        info!("=== Test 6: Consecutive Writes (Should Merge) ===");
+        test_consecutive_writes_blocking(&mut i2c, slave_addr);
+
+        info!("=== Test 7: Consecutive Reads (Should Merge) ===");
+        test_consecutive_reads_blocking(&mut i2c, slave_addr);
+
+        info!("=== Test 8: Write then Read (RESTART) ===");
+        test_write_then_read_blocking(&mut i2c, slave_addr);
+
+        info!("=== Test 9: Read then Write (RESTART) ===");
+        test_read_then_write_blocking(&mut i2c, slave_addr);
+
+        info!("=== Test 10: Complex Mixed Sequence ===");
+        test_mixed_sequence_blocking(&mut i2c, slave_addr);
+
+        info!("=== Test 11: Single Operations ===");
+        test_single_operations_blocking(&mut i2c, slave_addr);
+
+        info!("Blocking transaction tests OK");
+    }
+
+    Timer::after_millis(100).await;
+
+    // ========== ASYNC TESTS (DMA) ==========
+    info!("========== ASYNC TESTS (DMA) ==========");
+    {
+        let tx_dma = p.DMA1_CH2;
+        let rx_dma = p.DMA1_CH3;
+
+        let mut i2c = I2c::new(i2c_peri, scl, sda, Irqs, tx_dma, rx_dma, config);
+
+        // Direct API tests (reusing same I2C instance)
+        info!("=== Direct API Test 1: write() ===");
+        test_async_write(&mut i2c, slave_addr).await;
+
+        info!("=== Direct API Test 2: read() ===");
+        test_async_read(&mut i2c, slave_addr).await;
+
+        info!("=== Direct API Test 3: write_read() ===");
+        test_async_write_read(&mut i2c, slave_addr).await;
+
+        info!("=== Direct API Test 4: write_vectored() ===");
+        test_async_write_vectored(&mut i2c, slave_addr).await;
+
+        info!("=== Direct API Test 5: Large buffer (>255 bytes) ===");
+        test_async_large_buffer(&mut i2c, slave_addr).await;
+
+        info!("Async Direct API tests OK");
+
+        // Transaction tests
+        info!("=== Transaction Test 6: Consecutive Writes (Should Merge) ===");
+        test_consecutive_writes_async(&mut i2c, slave_addr).await;
+
+        info!("=== Transaction Test 7: Consecutive Reads (Should Merge) ===");
+        test_consecutive_reads_async(&mut i2c, slave_addr).await;
+
+        info!("=== Transaction Test 8: Write then Read (RESTART) ===");
+        test_write_then_read_async(&mut i2c, slave_addr).await;
+
+        info!("=== Transaction Test 9: Read then Write (RESTART) ===");
+        test_read_then_write_async(&mut i2c, slave_addr).await;
+
+        info!("=== Transaction Test 10: Complex Mixed Sequence ===");
+        test_mixed_sequence_async(&mut i2c, slave_addr).await;
+
+        info!("=== Transaction Test 11: Single Operations ===");
+        test_single_operations_async(&mut i2c, slave_addr).await;
+
+        info!("Async transaction tests OK");
+    }
+
+    info!("All tests OK");
+    cortex_m::asm::bkpt();
+}
+
+// ==================== BLOCKING DIRECT API TEST FUNCTIONS ====================
+
+fn test_blocking_write(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+    let write_data = [0x42, 0x43, 0x44, 0x45];
+
+    match i2c.blocking_write(addr, &write_data) {
+        Ok(_) => info!("✓ blocking_write succeeded: {:02x}", write_data),
+        Err(e) => {
+            error!("✗ blocking_write failed: {:?}", e);
+            defmt::panic!("Test failed: blocking_write");
+        }
+    }
+}
+
+fn test_blocking_read(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+    let mut read_buf = [0u8; 8];
+
+    match i2c.blocking_read(addr, &mut read_buf) {
+        Ok(_) => info!("✓ blocking_read succeeded: {:02x}", read_buf),
+        Err(e) => {
+            error!("✗ blocking_read failed: {:?}", e);
+            defmt::panic!("Test failed: blocking_read");
+        }
+    }
+}
+
+fn test_blocking_write_read(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+    let write_data = [0x50, 0x51];
+    let mut read_buf = [0u8; 6];
+
+    match i2c.blocking_write_read(addr, &write_data, &mut read_buf) {
+        Ok(_) => {
+            info!("✓ blocking_write_read succeeded");
+            info!("  Written: {:02x}", write_data);
+            info!("  Read: {:02x}", read_buf);
+        }
+        Err(e) => {
+            error!("✗ blocking_write_read failed: {:?}", e);
+            defmt::panic!("Test failed: blocking_write_read");
+        }
+    }
+}
+
+fn test_blocking_write_vectored(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+    let buf1 = [0x60, 0x61, 0x62];
+    let buf2 = [0x70, 0x71];
+    let buf3 = [0x80, 0x81, 0x82, 0x83];
+    let bufs = [&buf1[..], &buf2[..], &buf3[..]];
+
+    match i2c.blocking_write_vectored(addr, &bufs) {
+        Ok(_) => info!("✓ blocking_write_vectored succeeded (9 bytes total)"),
+        Err(e) => {
+            error!("✗ blocking_write_vectored failed: {:?}", e);
+            defmt::panic!("Test failed: blocking_write_vectored");
+        }
+    }
+}
+
+fn test_blocking_large_buffer(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+    // Test with 300 bytes to verify RELOAD mechanism works (needs chunking at 255 bytes)
+    let mut write_buf = [0u8; 300];
+    for (i, byte) in write_buf.iter_mut().enumerate() {
+        *byte = (i & 0xFF) as u8;
+    }
+
+    match i2c.blocking_write(addr, &write_buf) {
+        Ok(_) => info!("✓ Large buffer write succeeded (300 bytes, tests RELOAD)"),
+        Err(e) => {
+            error!("✗ Large buffer write failed: {:?}", e);
+            defmt::panic!("Test failed: large buffer write");
+        }
+    }
+
+    // Test large read
+    let mut read_buf = [0u8; 300];
+    match i2c.blocking_read(addr, &mut read_buf) {
+        Ok(_) => info!("✓ Large buffer read succeeded (300 bytes, tests RELOAD)"),
+        Err(e) => {
+            error!("✗ Large buffer read failed: {:?}", e);
+            defmt::panic!("Test failed: large buffer read");
+        }
+    }
+}
+
+// ==================== BLOCKING TRANSACTION TEST FUNCTIONS ====================
+
+fn test_consecutive_writes_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+    // Expected on bus: START, ADDR+W, data1, data2, data3, STOP
+    // NO intermediate RESTART/STOP between writes - they should be merged
+    let data1 = [0x10, 0x11, 0x12];
+    let data2 = [0x20, 0x21];
+    let data3 = [0x30, 0x31, 0x32, 0x33];
+
+    let mut ops = [
+        Operation::Write(&data1),
+        Operation::Write(&data2),
+        Operation::Write(&data3),
+    ];
+
+    match i2c.blocking_transaction(addr, &mut ops) {
+        Ok(_) => info!("✓ Consecutive writes succeeded (merged 9 bytes)"),
+        Err(e) => {
+            error!("✗ Consecutive writes failed: {:?}", e);
+            defmt::panic!("Test failed: consecutive writes");
+        }
+    }
+}
+
+fn test_consecutive_reads_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+    // Expected on bus: START, ADDR+R, data1, data2, data3, NACK, STOP
+    // NO intermediate RESTART/STOP between reads - they should be merged
+    let mut buf1 = [0u8; 4];
+    let mut buf2 = [0u8; 3];
+    let mut buf3 = [0u8; 2];
+
+    let mut ops = [
+        Operation::Read(&mut buf1),
+        Operation::Read(&mut buf2),
+        Operation::Read(&mut buf3),
+    ];
+
+    match i2c.blocking_transaction(addr, &mut ops) {
+        Ok(_) => {
+            info!("✓ Consecutive reads succeeded (merged 9 bytes)");
+            info!("  buf1: {:02x}", buf1);
+            info!("  buf2: {:02x}", buf2);
+            info!("  buf3: {:02x}", buf3);
+        }
+        Err(e) => {
+            error!("✗ Consecutive reads failed: {:?}", e);
+            defmt::panic!("Test failed: consecutive reads");
+        }
+    }
+}
+
+fn test_write_then_read_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+    // Expected: START, ADDR+W, data, RESTART, ADDR+R, data, NACK, STOP
+    let write_data = [0xAA, 0xBB];
+    let mut read_buf = [0u8; 4];
+
+    let mut ops = [Operation::Write(&write_data), Operation::Read(&mut read_buf)];
+
+    match i2c.blocking_transaction(addr, &mut ops) {
+        Ok(_) => {
+            info!("✓ Write-then-read succeeded with RESTART");
+            info!("  Written: {:02x}", write_data);
+            info!("  Read: {:02x}", read_buf);
+        }
+        Err(e) => {
+            error!("✗ Write-then-read failed: {:?}", e);
+            defmt::panic!("Test failed: write-then-read");
+        }
+    }
+}
+
+fn test_read_then_write_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+    // Expected: START, ADDR+R, data, NACK, RESTART, ADDR+W, data, STOP
+    let mut read_buf = [0u8; 3];
+    let write_data = [0xCC, 0xDD, 0xEE];
+
+    let mut ops = [Operation::Read(&mut read_buf), Operation::Write(&write_data)];
+
+    match i2c.blocking_transaction(addr, &mut ops) {
+        Ok(_) => {
+            info!("✓ Read-then-write succeeded with RESTART");
+            info!("  Read: {:02x}", read_buf);
+            info!("  Written: {:02x}", write_data);
+        }
+        Err(e) => {
+            error!("✗ Read-then-write failed: {:?}", e);
+            defmt::panic!("Test failed: read-then-write");
+        }
+    }
+}
+
+fn test_mixed_sequence_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+    // Complex: W, W, R, R, W, R
+    // Groups: [W,W] RESTART [R,R] RESTART [W] RESTART [R]
+    let w1 = [0x01, 0x02];
+    let w2 = [0x03, 0x04];
+    let mut r1 = [0u8; 2];
+    let mut r2 = [0u8; 2];
+    let w3 = [0x05];
+    let mut r3 = [0u8; 1];
+
+    let mut ops = [
+        Operation::Write(&w1),
+        Operation::Write(&w2),
+        Operation::Read(&mut r1),
+        Operation::Read(&mut r2),
+        Operation::Write(&w3),
+        Operation::Read(&mut r3),
+    ];
+
+    match i2c.blocking_transaction(addr, &mut ops) {
+        Ok(_) => {
+            info!("✓ Mixed sequence succeeded");
+            info!("  Groups: [W4] RESTART [R4] RESTART [W1] RESTART [R1]");
+        }
+        Err(e) => {
+            error!("✗ Mixed sequence failed: {:?}", e);
+            defmt::panic!("Test failed: mixed sequence");
+        }
+    }
+}
+
+fn test_single_operations_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+    // Test single write
+    let write_data = [0xFF];
+    let mut ops = [Operation::Write(&write_data)];
+
+    match i2c.blocking_transaction(addr, &mut ops) {
+        Ok(_) => info!("✓ Single write succeeded"),
+        Err(e) => {
+            error!("✗ Single write failed: {:?}", e);
+            defmt::panic!("Test failed: single write");
+        }
+    }
+
+    // Test single read
+    let mut read_buf = [0u8; 1];
+    let mut ops = [Operation::Read(&mut read_buf)];
+
+    match i2c.blocking_transaction(addr, &mut ops) {
+        Ok(_) => info!("✓ Single read succeeded, data: 0x{:02x}", read_buf[0]),
+        Err(e) => {
+            error!("✗ Single read failed: {:?}", e);
+            defmt::panic!("Test failed: single read");
+        }
+    }
+}
+
+// ==================== ASYNC DIRECT API TEST FUNCTIONS ====================
+
+async fn test_async_write(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let write_data = [0x42, 0x43, 0x44, 0x45];
+
+    match i2c.write(addr, &write_data).await {
+        Ok(_) => info!("✓ async write succeeded: {:02x}", write_data),
+        Err(e) => {
+            error!("✗ async write failed: {:?}", e);
+            defmt::panic!("Test failed: async write");
+        }
+    }
+}
+
+async fn test_async_read(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let mut read_buf = [0u8; 8];
+
+    match i2c.read(addr, &mut read_buf).await {
+        Ok(_) => info!("✓ async read succeeded: {:02x}", read_buf),
+        Err(e) => {
+            error!("✗ async read failed: {:?}", e);
+            defmt::panic!("Test failed: async read");
+        }
+    }
+}
+
+async fn test_async_write_read(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let write_data = [0x50, 0x51];
+    let mut read_buf = [0u8; 6];
+
+    match i2c.write_read(addr, &write_data, &mut read_buf).await {
+        Ok(_) => {
+            info!("✓ async write_read succeeded");
+            info!("  Written: {:02x}", write_data);
+            info!("  Read: {:02x}", read_buf);
+        }
+        Err(e) => {
+            error!("✗ async write_read failed: {:?}", e);
+            defmt::panic!("Test failed: async write_read");
+        }
+    }
+}
+
+async fn test_async_write_vectored(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let buf1 = [0x60, 0x61, 0x62];
+    let buf2 = [0x70, 0x71];
+    let buf3 = [0x80, 0x81, 0x82, 0x83];
+    let bufs = [&buf1[..], &buf2[..], &buf3[..]];
+
+    match i2c.write_vectored(addr.into(), &bufs).await {
+        Ok(_) => info!("✓ async write_vectored succeeded (9 bytes total)"),
+        Err(e) => {
+            error!("✗ async write_vectored failed: {:?}", e);
+            defmt::panic!("Test failed: async write_vectored");
+        }
+    }
+}
+
+async fn test_async_large_buffer(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    // Test with 300 bytes to verify RELOAD mechanism works with DMA (needs chunking at 255 bytes)
+    let mut write_buf = [0u8; 300];
+    for (i, byte) in write_buf.iter_mut().enumerate() {
+        *byte = (i & 0xFF) as u8;
+    }
+
+    match i2c.write(addr, &write_buf).await {
+        Ok(_) => info!("✓ Large buffer async write succeeded (300 bytes, tests RELOAD with DMA)"),
+        Err(e) => {
+            error!("✗ Large buffer async write failed: {:?}", e);
+            defmt::panic!("Test failed: large buffer async write");
+        }
+    }
+
+    // Test large read
+    let mut read_buf = [0u8; 300];
+    match i2c.read(addr, &mut read_buf).await {
+        Ok(_) => info!("✓ Large buffer async read succeeded (300 bytes, tests RELOAD with DMA)"),
+        Err(e) => {
+            error!("✗ Large buffer async read failed: {:?}", e);
+            defmt::panic!("Test failed: large buffer async read");
+        }
+    }
+}
+
+// ==================== ASYNC TRANSACTION TEST FUNCTIONS ====================
+
+async fn test_consecutive_writes_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let data1 = [0x10, 0x11, 0x12];
+    let data2 = [0x20, 0x21];
+    let data3 = [0x30, 0x31, 0x32, 0x33];
+
+    let mut ops = [
+        Operation::Write(&data1),
+        Operation::Write(&data2),
+        Operation::Write(&data3),
+    ];
+
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => info!("✓ Consecutive writes succeeded (merged 9 bytes)"),
+        Err(e) => {
+            error!("✗ Consecutive writes failed: {:?}", e);
+            defmt::panic!("Test failed: consecutive writes");
+        }
+    }
+}
+
+async fn test_consecutive_reads_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let mut buf1 = [0u8; 4];
+    let mut buf2 = [0u8; 3];
+    let mut buf3 = [0u8; 2];
+
+    let mut ops = [
+        Operation::Read(&mut buf1),
+        Operation::Read(&mut buf2),
+        Operation::Read(&mut buf3),
+    ];
+
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => {
+            info!("✓ Consecutive reads succeeded (merged 9 bytes)");
+            info!("  buf1: {:02x}", buf1);
+            info!("  buf2: {:02x}", buf2);
+            info!("  buf3: {:02x}", buf3);
+        }
+        Err(e) => {
+            error!("✗ Consecutive reads failed: {:?}", e);
+            defmt::panic!("Test failed: consecutive reads");
+        }
+    }
+}
+
+async fn test_write_then_read_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let write_data = [0xAA, 0xBB];
+    let mut read_buf = [0u8; 4];
+
+    let mut ops = [Operation::Write(&write_data), Operation::Read(&mut read_buf)];
+
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => {
+            info!("✓ Write-then-read succeeded with RESTART");
+            info!("  Written: {:02x}", write_data);
+            info!("  Read: {:02x}", read_buf);
+        }
+        Err(e) => {
+            error!("✗ Write-then-read failed: {:?}", e);
+            defmt::panic!("Test failed: write-then-read");
+        }
+    }
+}
+
+async fn test_read_then_write_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let mut read_buf = [0u8; 3];
+    let write_data = [0xCC, 0xDD, 0xEE];
+
+    let mut ops = [Operation::Read(&mut read_buf), Operation::Write(&write_data)];
+
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => {
+            info!("✓ Read-then-write succeeded with RESTART");
+            info!("  Read: {:02x}", read_buf);
+            info!("  Written: {:02x}", write_data);
+        }
+        Err(e) => {
+            error!("✗ Read-then-write failed: {:?}", e);
+            defmt::panic!("Test failed: read-then-write");
+        }
+    }
+}
+
+async fn test_mixed_sequence_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let w1 = [0x01, 0x02];
+    let w2 = [0x03, 0x04];
+    let mut r1 = [0u8; 2];
+    let mut r2 = [0u8; 2];
+    let w3 = [0x05];
+    let mut r3 = [0u8; 1];
+
+    let mut ops = [
+        Operation::Write(&w1),
+        Operation::Write(&w2),
+        Operation::Read(&mut r1),
+        Operation::Read(&mut r2),
+        Operation::Write(&w3),
+        Operation::Read(&mut r3),
+    ];
+
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => {
+            info!("✓ Mixed sequence succeeded");
+            info!("  Groups: [W4] RESTART [R4] RESTART [W1] RESTART [R1]");
+        }
+        Err(e) => {
+            error!("✗ Mixed sequence failed: {:?}", e);
+            defmt::panic!("Test failed: mixed sequence");
+        }
+    }
+}
+
+async fn test_single_operations_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    // Test single write
+    let write_data = [0xFF];
+    let mut ops = [Operation::Write(&write_data)];
+
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => info!("✓ Single write succeeded"),
+        Err(e) => {
+            error!("✗ Single write failed: {:?}", e);
+            defmt::panic!("Test failed: single write");
+        }
+    }
+
+    // Test single read
+    let mut read_buf = [0u8; 1];
+    let mut ops = [Operation::Read(&mut read_buf)];
+
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => info!("✓ Single read succeeded, data: 0x{:02x}", read_buf[0]),
+        Err(e) => {
+            error!("✗ Single read failed: {:?}", e);
+            defmt::panic!("Test failed: single read");
+        }
+    }
+}
diff --git a/examples/stm32f3/src/bin/button_events.rs b/examples/stm32f3/src/bin/button_events.rs
index 99957a641..643f499ed 100644
--- a/examples/stm32f3/src/bin/button_events.rs
+++ b/examples/stm32f3/src/bin/button_events.rs
@@ -11,13 +11,19 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::gpio::{Level, Output, Pull, Speed};
+use embassy_stm32::{bind_interrupts, interrupt};
 use embassy_sync::blocking_mutex::raw::ThreadModeRawMutex;
 use embassy_sync::channel::Channel;
 use embassy_time::{Duration, Timer, with_timeout};
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI0 => exti::InterruptHandler<interrupt::typelevel::EXTI0>;
+});
+
 struct Leds<'a> {
     leds: [Output<'a>; 8],
     direction: i8,
@@ -99,7 +105,7 @@ static CHANNEL: Channel<ThreadModeRawMutex, ButtonEvent, 4> = Channel::new();
 #[embassy_executor::main]
 async fn main(spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
-    let button = ExtiInput::new(p.PA0, p.EXTI0, Pull::Down);
+    let button = ExtiInput::new(p.PA0, p.EXTI0, Pull::Down, Irqs);
     info!("Press the USER button...");
     let leds = [
         Output::new(p.PE9, Level::Low, Speed::Low),
diff --git a/examples/stm32f3/src/bin/button_exti.rs b/examples/stm32f3/src/bin/button_exti.rs
index a55530e0e..1df4735ca 100644
--- a/examples/stm32f3/src/bin/button_exti.rs
+++ b/examples/stm32f3/src/bin/button_exti.rs
@@ -3,16 +3,22 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::gpio::Pull;
+use embassy_stm32::{bind_interrupts, interrupt};
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI0 => exti::InterruptHandler<interrupt::typelevel::EXTI0>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Hello World!");
 
-    let mut button = ExtiInput::new(p.PA0, p.EXTI0, Pull::Down);
+    let mut button = ExtiInput::new(p.PA0, p.EXTI0, Pull::Down, Irqs);
 
     info!("Press the USER button...");
 
diff --git a/examples/stm32f4/src/bin/adc.rs b/examples/stm32f4/src/bin/adc.rs
index 5628cb827..694e85657 100644
--- a/examples/stm32f4/src/bin/adc.rs
+++ b/examples/stm32f4/src/bin/adc.rs
@@ -14,7 +14,7 @@ async fn main(_spawner: Spawner) {
     info!("Hello World!");
 
     let mut delay = Delay;
-    let mut adc = Adc::new(p.ADC1);
+    let mut adc = Adc::new_with_config(p.ADC1, Default::default());
     let mut pin = p.PC1;
 
     let mut vrefint = adc.enable_vrefint();
diff --git a/examples/stm32f4/src/bin/adc_dma.rs b/examples/stm32f4/src/bin/adc_dma.rs
index 01b881c79..d61b1b2eb 100644
--- a/examples/stm32f4/src/bin/adc_dma.rs
+++ b/examples/stm32f4/src/bin/adc_dma.rs
@@ -4,7 +4,7 @@ use cortex_m::singleton;
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_stm32::Peripherals;
-use embassy_stm32::adc::{Adc, AdcChannel, RingBufferedAdc, SampleTime};
+use embassy_stm32::adc::{Adc, AdcChannel, RegularConversionMode, RingBufferedAdc, SampleTime};
 use embassy_time::Instant;
 use {defmt_rtt as _, panic_probe as _};
 
@@ -20,8 +20,8 @@ async fn adc_task(p: Peripherals) {
     let adc_data: &mut [u16; ADC_BUF_SIZE] = singleton!(ADCDAT : [u16; ADC_BUF_SIZE] = [0u16; ADC_BUF_SIZE]).unwrap();
     let adc_data2: &mut [u16; ADC_BUF_SIZE] = singleton!(ADCDAT2 : [u16; ADC_BUF_SIZE] = [0u16; ADC_BUF_SIZE]).unwrap();
 
-    let adc = Adc::new(p.ADC1);
-    let adc2 = Adc::new(p.ADC2);
+    let adc = Adc::new_with_config(p.ADC1, Default::default());
+    let adc2 = Adc::new_with_config(p.ADC2, Default::default());
 
     let mut adc: RingBufferedAdc<embassy_stm32::peripherals::ADC1> = adc.into_ring_buffered(
         p.DMA2_CH0,
@@ -31,6 +31,7 @@ async fn adc_task(p: Peripherals) {
             (p.PA2.degrade_adc(), SampleTime::CYCLES112),
         ]
         .into_iter(),
+        RegularConversionMode::Continuous,
     );
     let mut adc2: RingBufferedAdc<embassy_stm32::peripherals::ADC2> = adc2.into_ring_buffered(
         p.DMA2_CH2,
@@ -40,6 +41,7 @@ async fn adc_task(p: Peripherals) {
             (p.PA3.degrade_adc(), SampleTime::CYCLES112),
         ]
         .into_iter(),
+        RegularConversionMode::Continuous,
     );
 
     // Note that overrun is a big consideration in this implementation. Whatever task is running the adc.read() calls absolutely must circle back around
diff --git a/examples/stm32f4/src/bin/button_exti.rs b/examples/stm32f4/src/bin/button_exti.rs
index 2a546dac5..e7e1549a8 100644
--- a/examples/stm32f4/src/bin/button_exti.rs
+++ b/examples/stm32f4/src/bin/button_exti.rs
@@ -3,16 +3,22 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::gpio::Pull;
+use embassy_stm32::{bind_interrupts, interrupt};
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI15_10 => exti::InterruptHandler<interrupt::typelevel::EXTI15_10>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Hello World!");
 
-    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down);
+    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down, Irqs);
 
     info!("Press the USER button...");
 
diff --git a/examples/stm32f4/src/bin/eth.rs b/examples/stm32f4/src/bin/eth.rs
index 2d72b6b0b..8dfa0916d 100644
--- a/examples/stm32f4/src/bin/eth.rs
+++ b/examples/stm32f4/src/bin/eth.rs
@@ -5,8 +5,8 @@ use defmt::*;
 use embassy_executor::Spawner;
 use embassy_net::tcp::TcpSocket;
 use embassy_net::{Ipv4Address, StackResources};
-use embassy_stm32::eth::{Ethernet, GenericPhy, PacketQueue};
-use embassy_stm32::peripherals::ETH;
+use embassy_stm32::eth::{Ethernet, GenericPhy, PacketQueue, Sma};
+use embassy_stm32::peripherals::{ETH, ETH_SMA};
 use embassy_stm32::rng::Rng;
 use embassy_stm32::time::Hertz;
 use embassy_stm32::{Config, bind_interrupts, eth, peripherals, rng};
@@ -20,7 +20,7 @@ bind_interrupts!(struct Irqs {
     HASH_RNG => rng::InterruptHandler<peripherals::RNG>;
 });
 
-type Device = Ethernet<'static, ETH, GenericPhy>;
+type Device = Ethernet<'static, ETH, GenericPhy<Sma<'static, ETH_SMA>>>;
 
 #[embassy_executor::task]
 async fn net_task(mut runner: embassy_net::Runner<'static, Device>) -> ! {
@@ -67,16 +67,16 @@ async fn main(spawner: Spawner) -> ! {
         p.ETH,
         Irqs,
         p.PA1,
-        p.PA2,
-        p.PC1,
         p.PA7,
         p.PC4,
         p.PC5,
         p.PG13,
         p.PB13,
         p.PG11,
-        GenericPhy::new_auto(),
         mac_addr,
+        p.ETH_SMA,
+        p.PA2,
+        p.PC1,
     );
 
     let config = embassy_net::Config::dhcpv4(Default::default());
diff --git a/examples/stm32f4/src/bin/eth_compliance_test.rs b/examples/stm32f4/src/bin/eth_compliance_test.rs
index 734a14c2c..dc5d7dbb6 100644
--- a/examples/stm32f4/src/bin/eth_compliance_test.rs
+++ b/examples/stm32f4/src/bin/eth_compliance_test.rs
@@ -3,7 +3,7 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::eth::{Ethernet, GenericPhy, PacketQueue, StationManagement};
+use embassy_stm32::eth::{Ethernet, PacketQueue, StationManagement};
 use embassy_stm32::time::Hertz;
 use embassy_stm32::{Config, bind_interrupts, eth, peripherals, rng};
 use embassy_time::Timer;
@@ -43,27 +43,27 @@ async fn main(_spawner: Spawner) -> ! {
 
     let mac_addr = [0x00, 0x00, 0xDE, 0xAD, 0xBE, 0xEF];
 
-    const PHY_ADDR: u8 = 0;
     static PACKETS: StaticCell<PacketQueue<4, 4>> = StaticCell::new();
     let mut device = Ethernet::new(
         PACKETS.init(PacketQueue::<4, 4>::new()),
         p.ETH,
         Irqs,
         p.PA1,
-        p.PA2,
-        p.PC1,
         p.PA7,
         p.PC4,
         p.PC5,
         p.PG13,
         p.PB13,
         p.PG11,
-        GenericPhy::new(PHY_ADDR),
         mac_addr,
+        p.ETH_SMA,
+        p.PA2,
+        p.PC1,
     );
 
-    let sm = device.station_management();
+    let sm = device.phy_mut().station_management();
 
+    const PHY_ADDR: u8 = 0;
     // Just an example. Exact register settings depend on the specific PHY and test.
     sm.smi_write(PHY_ADDR, 0, 0x2100);
     sm.smi_write(PHY_ADDR, 11, 0xA000);
diff --git a/examples/stm32f4/src/bin/eth_w5500.rs b/examples/stm32f4/src/bin/eth_w5500.rs
index 0adcda614..e274d2a66 100644
--- a/examples/stm32f4/src/bin/eth_w5500.rs
+++ b/examples/stm32f4/src/bin/eth_w5500.rs
@@ -7,14 +7,14 @@ use embassy_net::tcp::TcpSocket;
 use embassy_net::{Ipv4Address, StackResources};
 use embassy_net_wiznet::chip::W5500;
 use embassy_net_wiznet::{Device, Runner, State};
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::gpio::{Level, Output, Pull, Speed};
 use embassy_stm32::mode::Async;
 use embassy_stm32::rng::Rng;
 use embassy_stm32::spi::Spi;
 use embassy_stm32::spi::mode::Master;
 use embassy_stm32::time::Hertz;
-use embassy_stm32::{Config, bind_interrupts, peripherals, rng, spi};
+use embassy_stm32::{Config, bind_interrupts, interrupt, peripherals, rng, spi};
 use embassy_time::{Delay, Timer};
 use embedded_hal_bus::spi::ExclusiveDevice;
 use embedded_io_async::Write;
@@ -23,6 +23,7 @@ use {defmt_rtt as _, panic_probe as _};
 
 bind_interrupts!(struct Irqs {
     HASH_RNG => rng::InterruptHandler<peripherals::RNG>;
+    EXTI0 => exti::InterruptHandler<interrupt::typelevel::EXTI0>;
 });
 
 type EthernetSPI = ExclusiveDevice<Spi<'static, Async, Master>, Output<'static>, Delay>;
@@ -75,7 +76,7 @@ async fn main(spawner: Spawner) -> ! {
     let cs = Output::new(p.PA4, Level::High, Speed::VeryHigh);
     let spi = unwrap!(ExclusiveDevice::new(spi, cs, Delay));
 
-    let w5500_int = ExtiInput::new(p.PB0, p.EXTI0, Pull::Up);
+    let w5500_int = ExtiInput::new(p.PB0, p.EXTI0, Pull::Up, Irqs);
     let w5500_reset = Output::new(p.PB1, Level::High, Speed::VeryHigh);
 
     let mac_addr = [0x02, 234, 3, 4, 82, 231];
diff --git a/examples/stm32f4/src/bin/usb_hid_keyboard.rs b/examples/stm32f4/src/bin/usb_hid_keyboard.rs
index a3afb887c..2d834dcf7 100644
--- a/examples/stm32f4/src/bin/usb_hid_keyboard.rs
+++ b/examples/stm32f4/src/bin/usb_hid_keyboard.rs
@@ -1,17 +1,19 @@
 #![no_std]
 #![no_main]
 
-use core::sync::atomic::{AtomicBool, Ordering};
+use core::sync::atomic::{AtomicBool, AtomicU8, Ordering};
 
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_futures::join::join;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::gpio::Pull;
 use embassy_stm32::time::Hertz;
 use embassy_stm32::usb::Driver;
-use embassy_stm32::{Config, bind_interrupts, peripherals, usb};
-use embassy_usb::class::hid::{HidReaderWriter, ReportId, RequestHandler, State};
+use embassy_stm32::{Config, bind_interrupts, interrupt, peripherals, usb};
+use embassy_usb::class::hid::{
+    HidBootProtocol, HidProtocolMode, HidReaderWriter, HidSubclass, ReportId, RequestHandler, State,
+};
 use embassy_usb::control::OutResponse;
 use embassy_usb::{Builder, Handler};
 use usbd_hid::descriptor::{KeyboardReport, SerializedDescriptor};
@@ -19,8 +21,11 @@ use {defmt_rtt as _, panic_probe as _};
 
 bind_interrupts!(struct Irqs {
     OTG_FS => usb::InterruptHandler<peripherals::USB_OTG_FS>;
+    EXTI15_10 => exti::InterruptHandler<interrupt::typelevel::EXTI15_10>;
 });
 
+static HID_PROTOCOL_MODE: AtomicU8 = AtomicU8::new(HidProtocolMode::Boot as u8);
+
 // If you are trying this and your USB device doesn't connect, the most
 // common issues are the RCC config and vbus_detection
 //
@@ -70,6 +75,10 @@ async fn main(_spawner: Spawner) {
     config.serial_number = Some("12345678");
     config.max_power = 100;
     config.max_packet_size_0 = 64;
+    config.composite_with_iads = false;
+    config.device_class = 0;
+    config.device_sub_class = 0;
+    config.device_protocol = 0;
 
     // Create embassy-usb DeviceBuilder using the driver and config.
     // It needs some buffers for building the descriptors.
@@ -101,6 +110,8 @@ async fn main(_spawner: Spawner) {
         request_handler: None,
         poll_ms: 60,
         max_packet_size: 8,
+        hid_subclass: HidSubclass::Boot,
+        hid_boot_protocol: HidBootProtocol::Keyboard,
     };
 
     let hid = HidReaderWriter::<_, 1, 8>::new(&mut builder, &mut state, config);
@@ -113,7 +124,7 @@ async fn main(_spawner: Spawner) {
 
     let (reader, mut writer) = hid.split();
 
-    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down);
+    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down, Irqs);
 
     // Do stuff with the class!
     let in_fut = async {
@@ -121,32 +132,46 @@ async fn main(_spawner: Spawner) {
             button.wait_for_rising_edge().await;
             // signal_pin.wait_for_high().await;
             info!("Button pressed!");
-            // Create a report with the A key pressed. (no shift modifier)
-            let report = KeyboardReport {
-                keycodes: [4, 0, 0, 0, 0, 0],
-                leds: 0,
-                modifier: 0,
-                reserved: 0,
-            };
-            // Send the report.
-            match writer.write_serialize(&report).await {
-                Ok(()) => {}
-                Err(e) => warn!("Failed to send report: {:?}", e),
-            };
+            if HID_PROTOCOL_MODE.load(Ordering::Relaxed) == HidProtocolMode::Boot as u8 {
+                match writer.write(&[0, 0, 4, 0, 0, 0, 0, 0]).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send boot report: {:?}", e),
+                };
+            } else {
+                // Create a report with the A key pressed. (no shift modifier)
+                let report = KeyboardReport {
+                    keycodes: [4, 0, 0, 0, 0, 0],
+                    leds: 0,
+                    modifier: 0,
+                    reserved: 0,
+                };
+                // Send the report.
+                match writer.write_serialize(&report).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send report: {:?}", e),
+                };
+            }
 
             button.wait_for_falling_edge().await;
             // signal_pin.wait_for_low().await;
             info!("Button released!");
-            let report = KeyboardReport {
-                keycodes: [0, 0, 0, 0, 0, 0],
-                leds: 0,
-                modifier: 0,
-                reserved: 0,
-            };
-            match writer.write_serialize(&report).await {
-                Ok(()) => {}
-                Err(e) => warn!("Failed to send report: {:?}", e),
-            };
+            if HID_PROTOCOL_MODE.load(Ordering::Relaxed) == HidProtocolMode::Boot as u8 {
+                match writer.write(&[0, 0, 0, 0, 0, 0, 0, 0]).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send boot report: {:?}", e),
+                };
+            } else {
+                let report = KeyboardReport {
+                    keycodes: [0, 0, 0, 0, 0, 0],
+                    leds: 0,
+                    modifier: 0,
+                    reserved: 0,
+                };
+                match writer.write_serialize(&report).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send report: {:?}", e),
+                };
+            }
         }
     };
 
@@ -172,6 +197,18 @@ impl RequestHandler for MyRequestHandler {
         OutResponse::Accepted
     }
 
+    fn get_protocol(&self) -> HidProtocolMode {
+        let protocol = HidProtocolMode::from(HID_PROTOCOL_MODE.load(Ordering::Relaxed));
+        info!("The current HID protocol mode is: {}", protocol);
+        protocol
+    }
+
+    fn set_protocol(&mut self, protocol: HidProtocolMode) -> OutResponse {
+        info!("Switching to HID protocol mode: {}", protocol);
+        HID_PROTOCOL_MODE.store(protocol as u8, Ordering::Relaxed);
+        OutResponse::Accepted
+    }
+
     fn set_idle_ms(&mut self, id: Option<ReportId>, dur: u32) {
         info!("Set idle rate for {:?} to {:?}", id, dur);
     }
diff --git a/examples/stm32f4/src/bin/usb_hid_mouse.rs b/examples/stm32f4/src/bin/usb_hid_mouse.rs
index 162a035f2..e83d01f88 100644
--- a/examples/stm32f4/src/bin/usb_hid_mouse.rs
+++ b/examples/stm32f4/src/bin/usb_hid_mouse.rs
@@ -1,6 +1,8 @@
 #![no_std]
 #![no_main]
 
+use core::sync::atomic::{AtomicU8, Ordering};
+
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_futures::join::join;
@@ -9,7 +11,9 @@ use embassy_stm32::usb::Driver;
 use embassy_stm32::{Config, bind_interrupts, peripherals, usb};
 use embassy_time::Timer;
 use embassy_usb::Builder;
-use embassy_usb::class::hid::{HidWriter, ReportId, RequestHandler, State};
+use embassy_usb::class::hid::{
+    HidBootProtocol, HidProtocolMode, HidSubclass, HidWriter, ReportId, RequestHandler, State,
+};
 use embassy_usb::control::OutResponse;
 use usbd_hid::descriptor::{MouseReport, SerializedDescriptor};
 use {defmt_rtt as _, panic_probe as _};
@@ -18,6 +22,8 @@ bind_interrupts!(struct Irqs {
     OTG_FS => usb::InterruptHandler<peripherals::USB_OTG_FS>;
 });
 
+static HID_PROTOCOL_MODE: AtomicU8 = AtomicU8::new(HidProtocolMode::Boot as u8);
+
 // If you are trying this and your USB device doesn't connect, the most
 // common issues are the RCC config and vbus_detection
 //
@@ -65,6 +71,10 @@ async fn main(_spawner: Spawner) {
     config.manufacturer = Some("Embassy");
     config.product = Some("HID mouse example");
     config.serial_number = Some("12345678");
+    config.composite_with_iads = false;
+    config.device_class = 0;
+    config.device_sub_class = 0;
+    config.device_protocol = 0;
 
     // Create embassy-usb DeviceBuilder using the driver and config.
     // It needs some buffers for building the descriptors.
@@ -91,6 +101,8 @@ async fn main(_spawner: Spawner) {
         request_handler: Some(&mut request_handler),
         poll_ms: 60,
         max_packet_size: 8,
+        hid_subclass: HidSubclass::Boot,
+        hid_boot_protocol: HidBootProtocol::Mouse,
     };
 
     let mut writer = HidWriter::<_, 5>::new(&mut builder, &mut state, config);
@@ -108,16 +120,26 @@ async fn main(_spawner: Spawner) {
             Timer::after_millis(500).await;
 
             y = -y;
-            let report = MouseReport {
-                buttons: 0,
-                x: 0,
-                y,
-                wheel: 0,
-                pan: 0,
-            };
-            match writer.write_serialize(&report).await {
-                Ok(()) => {}
-                Err(e) => warn!("Failed to send report: {:?}", e),
+
+            if HID_PROTOCOL_MODE.load(Ordering::Relaxed) == HidProtocolMode::Boot as u8 {
+                let buttons = 0u8;
+                let x = 0i8;
+                match writer.write(&[buttons, x as u8, y as u8]).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send boot report: {:?}", e),
+                }
+            } else {
+                let report = MouseReport {
+                    buttons: 0,
+                    x: 0,
+                    y,
+                    wheel: 0,
+                    pan: 0,
+                };
+                match writer.write_serialize(&report).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send report: {:?}", e),
+                }
             }
         }
     };
@@ -140,6 +162,18 @@ impl RequestHandler for MyRequestHandler {
         OutResponse::Accepted
     }
 
+    fn get_protocol(&self) -> HidProtocolMode {
+        let protocol = HidProtocolMode::from(HID_PROTOCOL_MODE.load(Ordering::Relaxed));
+        info!("The current HID protocol mode is: {}", protocol);
+        protocol
+    }
+
+    fn set_protocol(&mut self, protocol: HidProtocolMode) -> OutResponse {
+        info!("Switching to HID protocol mode: {}", protocol);
+        HID_PROTOCOL_MODE.store(protocol as u8, Ordering::Relaxed);
+        OutResponse::Accepted
+    }
+
     fn set_idle_ms(&mut self, id: Option<ReportId>, dur: u32) {
         info!("Set idle rate for {:?} to {:?}", id, dur);
     }
diff --git a/examples/stm32f469/src/bin/dsi_bsp.rs b/examples/stm32f469/src/bin/dsi_bsp.rs
index d659291ff..7ba4da72b 100644
--- a/examples/stm32f469/src/bin/dsi_bsp.rs
+++ b/examples/stm32f469/src/bin/dsi_bsp.rs
@@ -3,7 +3,7 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::dsihost::{DsiHost, PacketType, blocking_delay_ms};
+use embassy_stm32::dsihost::{DsiHost, PacketType};
 use embassy_stm32::gpio::{Level, Output, Speed};
 use embassy_stm32::ltdc::Ltdc;
 use embassy_stm32::pac::dsihost::regs::{Ier0, Ier1};
@@ -13,7 +13,7 @@ use embassy_stm32::rcc::{
     AHBPrescaler, APBPrescaler, Hse, HseMode, Pll, PllMul, PllPDiv, PllPreDiv, PllQDiv, PllRDiv, PllSource, Sysclk,
 };
 use embassy_stm32::time::mhz;
-use embassy_time::Timer;
+use embassy_time::{Duration, Timer, block_for};
 use {defmt_rtt as _, panic_probe as _};
 
 enum _Orientation {
@@ -444,7 +444,7 @@ async fn main(_spawner: Spawner) {
     dsi.enable_wrapper_dsi();
 
     // First, delay 120 ms (reason unknown, STM32 Cube Example does it)
-    blocking_delay_ms(120);
+    block_for(Duration::from_millis(120));
 
     // 1 to 26
     dsi.write_cmd(0, NT35510_WRITES_0[0], &NT35510_WRITES_0[1..]).unwrap();
@@ -480,7 +480,7 @@ async fn main(_spawner: Spawner) {
     dsi.write_cmd(0, NT35510_WRITES_37[0], &NT35510_WRITES_37[1..]).unwrap();
 
     // Add a delay, otherwise MADCTL not taken
-    blocking_delay_ms(200);
+    block_for(Duration::from_millis(200));
 
     // Configure orientation as landscape
     dsi.write_cmd(0, NT35510_MADCTL_LANDSCAPE[0], &NT35510_MADCTL_LANDSCAPE[1..])
@@ -494,7 +494,7 @@ async fn main(_spawner: Spawner) {
     dsi.write_cmd(0, NT35510_WRITES_27[0], &NT35510_WRITES_27[1..]).unwrap();
 
     // Wait for sleep out exit
-    blocking_delay_ms(120);
+    block_for(Duration::from_millis(120));
 
     // Configure COLOR_CODING
     dsi.write_cmd(0, NT35510_WRITES_37[0], &NT35510_WRITES_37[1..]).unwrap();
@@ -590,7 +590,7 @@ async fn main(_spawner: Spawner) {
     //LTDC->SRCR = LTDC_SRCR_IMR;
     LTDC.srcr().modify(|w| w.set_imr(Imr::RELOAD));
 
-    blocking_delay_ms(5000);
+    block_for(Duration::from_millis(5000));
 
     const READ_SIZE: u16 = 1;
     let mut data = [1u8; READ_SIZE as usize];
@@ -606,7 +606,7 @@ async fn main(_spawner: Spawner) {
         .unwrap();
     info!("Display ID3: {:#04x}", data);
 
-    blocking_delay_ms(500);
+    block_for(Duration::from_millis(500));
 
     info!("Config done, start blinking LED");
     loop {
diff --git a/examples/stm32f7/src/bin/button_exti.rs b/examples/stm32f7/src/bin/button_exti.rs
index 2a546dac5..e7e1549a8 100644
--- a/examples/stm32f7/src/bin/button_exti.rs
+++ b/examples/stm32f7/src/bin/button_exti.rs
@@ -3,16 +3,22 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::gpio::Pull;
+use embassy_stm32::{bind_interrupts, interrupt};
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI15_10 => exti::InterruptHandler<interrupt::typelevel::EXTI15_10>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Hello World!");
 
-    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down);
+    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down, Irqs);
 
     info!("Press the USER button...");
 
diff --git a/examples/stm32f7/src/bin/eth.rs b/examples/stm32f7/src/bin/eth.rs
index f8a129239..8613376b8 100644
--- a/examples/stm32f7/src/bin/eth.rs
+++ b/examples/stm32f7/src/bin/eth.rs
@@ -5,8 +5,8 @@ use defmt::*;
 use embassy_executor::Spawner;
 use embassy_net::tcp::TcpSocket;
 use embassy_net::{Ipv4Address, StackResources};
-use embassy_stm32::eth::{Ethernet, GenericPhy, PacketQueue};
-use embassy_stm32::peripherals::ETH;
+use embassy_stm32::eth::{Ethernet, GenericPhy, PacketQueue, Sma};
+use embassy_stm32::peripherals::{ETH, ETH_SMA};
 use embassy_stm32::rng::Rng;
 use embassy_stm32::time::Hertz;
 use embassy_stm32::{Config, bind_interrupts, eth, peripherals, rng};
@@ -20,7 +20,7 @@ bind_interrupts!(struct Irqs {
     HASH_RNG => rng::InterruptHandler<peripherals::RNG>;
 });
 
-type Device = Ethernet<'static, ETH, GenericPhy>;
+type Device = Ethernet<'static, ETH, GenericPhy<Sma<'static, ETH_SMA>>>;
 
 #[embassy_executor::task]
 async fn net_task(mut runner: embassy_net::Runner<'static, Device>) -> ! {
@@ -67,16 +67,16 @@ async fn main(spawner: Spawner) -> ! {
         p.ETH,
         Irqs,
         p.PA1,
-        p.PA2,
-        p.PC1,
         p.PA7,
         p.PC4,
         p.PC5,
         p.PG13,
         p.PB13,
         p.PG11,
-        GenericPhy::new_auto(),
         mac_addr,
+        p.ETH_SMA,
+        p.PA2,
+        p.PC1,
     );
 
     let config = embassy_net::Config::dhcpv4(Default::default());
diff --git a/examples/stm32f7/src/bin/pwm.rs b/examples/stm32f7/src/bin/pwm.rs
new file mode 100644
index 000000000..b071eb597
--- /dev/null
+++ b/examples/stm32f7/src/bin/pwm.rs
@@ -0,0 +1,61 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::Config;
+use embassy_stm32::gpio::OutputType;
+use embassy_stm32::time::{Hertz, mhz};
+use embassy_stm32::timer::simple_pwm::{PwmPin, SimplePwm};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+// If you are trying this and your USB device doesn't connect, the most
+// common issues are the RCC config and vbus_detection
+//
+// See https://embassy.dev/book/#_the_usb_examples_are_not_working_on_my_board_is_there_anything_else_i_need_to_configure
+// for more information.
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    info!("Hello World!");
+
+    let mut config = Config::default();
+    {
+        use embassy_stm32::rcc::*;
+        config.rcc.hse = Some(Hse {
+            freq: Hertz(8_000_000),
+            mode: HseMode::Bypass,
+        });
+        config.rcc.pll_src = PllSource::HSE;
+        config.rcc.pll = Some(Pll {
+            prediv: PllPreDiv::DIV4,
+            mul: PllMul::MUL200,
+            divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 200 / 2 = 200Mhz
+            divq: Some(PllQDiv::DIV4), // 8mhz / 4 * 200 / 4 = 100Mhz
+            divr: None,
+        });
+        config.rcc.ahb_pre = AHBPrescaler::DIV1;
+        config.rcc.apb1_pre = APBPrescaler::DIV4;
+        config.rcc.apb2_pre = APBPrescaler::DIV2;
+        config.rcc.sys = Sysclk::PLL1_P;
+    }
+    let p = embassy_stm32::init(config);
+    let ch1_pin = PwmPin::new(p.PE9, OutputType::PushPull);
+    let mut pwm = SimplePwm::new(p.TIM1, Some(ch1_pin), None, None, None, mhz(1), Default::default());
+    let mut ch1 = pwm.ch1();
+    ch1.enable();
+
+    info!("PWM initialized");
+    info!("PWM max duty {}", ch1.max_duty_cycle());
+
+    loop {
+        ch1.set_duty_cycle_fully_off();
+        Timer::after_millis(300).await;
+        ch1.set_duty_cycle_fraction(1, 4);
+        Timer::after_millis(300).await;
+        ch1.set_duty_cycle_fraction(1, 2);
+        Timer::after_millis(300).await;
+        ch1.set_duty_cycle(ch1.max_duty_cycle() - 1);
+        Timer::after_millis(300).await;
+    }
+}
diff --git a/examples/stm32f7/src/bin/pwm_ringbuffer.rs b/examples/stm32f7/src/bin/pwm_ringbuffer.rs
new file mode 100644
index 000000000..4d191ac13
--- /dev/null
+++ b/examples/stm32f7/src/bin/pwm_ringbuffer.rs
@@ -0,0 +1,153 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::Config;
+use embassy_stm32::gpio::OutputType;
+use embassy_stm32::time::mhz;
+use embassy_stm32::timer::simple_pwm::{PwmPin, SimplePwm};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+// If you are trying this and your USB device doesn't connect, the most
+// common issues are the RCC config and vbus_detection
+//
+// See https://embassy.dev/book/#_the_usb_examples_are_not_working_on_my_board_is_there_anything_else_i_need_to_configure
+// for more information.
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    info!("PWM Ring Buffer Example");
+
+    let mut config = Config::default();
+    {
+        use embassy_stm32::rcc::*;
+        use embassy_stm32::time::Hertz;
+        config.rcc.hse = Some(Hse {
+            freq: Hertz(8_000_000),
+            mode: HseMode::Bypass,
+        });
+        config.rcc.pll_src = PllSource::HSE;
+        config.rcc.pll = Some(Pll {
+            prediv: PllPreDiv::DIV4,
+            mul: PllMul::MUL200,
+            divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 200 / 2 = 200Mhz
+            divq: Some(PllQDiv::DIV4), // 8mhz / 4 * 200 / 4 = 100Mhz
+            divr: None,
+        });
+        config.rcc.ahb_pre = AHBPrescaler::DIV1;
+        config.rcc.apb1_pre = APBPrescaler::DIV4;
+        config.rcc.apb2_pre = APBPrescaler::DIV2;
+        config.rcc.sys = Sysclk::PLL1_P;
+    }
+    let p = embassy_stm32::init(config);
+
+    // Initialize PWM on TIM1
+    let ch1_pin = PwmPin::new(p.PE9, OutputType::PushPull);
+    let ch2_pin = PwmPin::new(p.PE11, OutputType::PushPull);
+    let mut pwm = SimplePwm::new(
+        p.TIM1,
+        Some(ch1_pin),
+        Some(ch2_pin),
+        None,
+        None,
+        mhz(1),
+        Default::default(),
+    );
+
+    // Use channel 1 for static PWM at 50%
+    let mut ch1 = pwm.ch1();
+    ch1.enable();
+    ch1.set_duty_cycle_fraction(1, 2);
+    info!("Channel 1 (PE9/D6): Static 50% duty cycle");
+
+    // Get max duty from channel 1 before converting channel 2
+    let max_duty = ch1.max_duty_cycle();
+    info!("PWM max duty: {}", max_duty);
+
+    // Create a DMA ring buffer for channel 2
+    const BUFFER_SIZE: usize = 128;
+    static mut DMA_BUFFER: [u16; BUFFER_SIZE] = [0u16; BUFFER_SIZE];
+    let dma_buffer = unsafe { &mut *core::ptr::addr_of_mut!(DMA_BUFFER) };
+
+    // Pre-fill buffer with initial sine wave using lookup table approach
+    for i in 0..BUFFER_SIZE {
+        // Simple sine approximation using triangle wave
+        let phase = (i * 256) / BUFFER_SIZE;
+        let sine_approx = if phase < 128 {
+            phase as u16 * 2
+        } else {
+            (255 - phase) as u16 * 2
+        };
+        dma_buffer[i] = (sine_approx as u32 * max_duty as u32 / 256) as u16;
+    }
+
+    // Convert channel 2 to ring-buffered PWM
+    let mut ring_pwm = pwm.ch1().into_ring_buffered_channel(p.DMA2_CH5, dma_buffer);
+
+    info!("Ring buffer capacity: {}", ring_pwm.capacity());
+
+    // Pre-write some initial data to the buffer before starting
+    info!("Pre-writing initial waveform data...");
+
+    ring_pwm.write(&[0; BUFFER_SIZE]).unwrap();
+
+    // Enable the PWM channel output
+    ring_pwm.enable();
+
+    // Start the DMA ring buffer
+    ring_pwm.start();
+    info!("Channel 2 (PE11/D5): Ring buffered sine wave started");
+
+    // Give DMA time to start consuming
+    Timer::after_millis(10).await;
+
+    // Continuously update the waveform
+    let mut phase: f32 = 0.0;
+    let mut amplitude: f32 = 1.0;
+    let mut amplitude_direction = -0.05;
+
+    loop {
+        // Generate new waveform data with varying amplitude
+        let mut new_data = [0u16; 32];
+        for i in 0..new_data.len() {
+            // Triangle wave approximation for sine
+            let pos = ((i as u32 + phase as u32) * 4) % 256;
+            let sine_approx = if pos < 128 {
+                pos as u16 * 2
+            } else {
+                (255 - pos) as u16 * 2
+            };
+            let scaled = (sine_approx as u32 * (amplitude * 256.0) as u32) / (256 * 256);
+            new_data[i] = ((scaled * max_duty as u32) / 256) as u16;
+        }
+
+        // Write new data to the ring buffer
+        match ring_pwm.write_exact(&new_data).await {
+            Ok(_remaining) => {}
+            Err(e) => {
+                info!("Write error: {:?}", e);
+            }
+        }
+
+        // Update phase for animation effect
+        phase += 2.0;
+        if phase >= 64.0 {
+            phase = 0.0;
+        }
+
+        // Vary amplitude for breathing effect
+        amplitude += amplitude_direction;
+        if amplitude <= 0.2 || amplitude >= 1.0 {
+            amplitude_direction = -amplitude_direction;
+        }
+
+        // Log buffer status periodically
+        if (phase as u32) % 10 == 0 {
+            match ring_pwm.len() {
+                Ok(len) => info!("Ring buffer fill: {}/{}", len, ring_pwm.capacity()),
+                Err(_) => info!("Error reading buffer length"),
+            }
+        }
+    }
+}
diff --git a/examples/stm32g0/src/bin/adc_oversampling.rs b/examples/stm32g0/src/bin/adc_oversampling.rs
index f6979889d..aa8b1771b 100644
--- a/examples/stm32g0/src/bin/adc_oversampling.rs
+++ b/examples/stm32g0/src/bin/adc_oversampling.rs
@@ -7,7 +7,7 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::adc::{Adc, Clock, Ovsr, Ovss, Presc, SampleTime};
+use embassy_stm32::adc::{Adc, AdcConfig, Clock, Ovsr, Ovss, Presc, SampleTime};
 use embassy_time::Timer;
 use {defmt_rtt as _, panic_probe as _};
 
@@ -16,12 +16,14 @@ async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Adc oversample test");
 
-    let mut adc = Adc::new_with_clock(p.ADC1, Clock::Async { div: Presc::DIV1 });
-    let mut pin = p.PA1;
+    let mut config = AdcConfig::default();
+    config.clock = Some(Clock::Async { div: Presc::DIV1 });
+    config.oversampling_ratio = Some(Ovsr::MUL16);
+    config.oversampling_shift = Some(Ovss::NO_SHIFT);
+    config.oversampling_enable = Some(true);
 
-    adc.set_oversampling_ratio(Ovsr::MUL16);
-    adc.set_oversampling_shift(Ovss::NO_SHIFT);
-    adc.oversampling_enable(true);
+    let mut adc = Adc::new_with_config(p.ADC1, config);
+    let mut pin = p.PA1;
 
     loop {
         let v = adc.blocking_read(&mut pin, SampleTime::CYCLES1_5);
diff --git a/examples/stm32g0/src/bin/button_exti.rs b/examples/stm32g0/src/bin/button_exti.rs
index 34a08bbc6..9d54479da 100644
--- a/examples/stm32g0/src/bin/button_exti.rs
+++ b/examples/stm32g0/src/bin/button_exti.rs
@@ -3,16 +3,22 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::gpio::Pull;
+use embassy_stm32::{bind_interrupts, interrupt};
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI4_15 => exti::InterruptHandler<interrupt::typelevel::EXTI4_15>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Hello World!");
 
-    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up);
+    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up, Irqs);
 
     info!("Press the USER button...");
 
diff --git a/examples/stm32g4/src/bin/adc.rs b/examples/stm32g4/src/bin/adc.rs
index 94315141c..2149e0748 100644
--- a/examples/stm32g4/src/bin/adc.rs
+++ b/examples/stm32g4/src/bin/adc.rs
@@ -28,9 +28,9 @@ async fn main(_spawner: Spawner) {
     let mut p = embassy_stm32::init(config);
     info!("Hello World!");
 
-    let mut adc = Adc::new(p.ADC2);
+    let mut adc = Adc::new(p.ADC2, Default::default());
 
-    let mut adc_temp = Adc::new(p.ADC1);
+    let mut adc_temp = Adc::new(p.ADC1, Default::default());
     let mut temperature = adc_temp.enable_temperature();
 
     loop {
diff --git a/examples/stm32g4/src/bin/adc_differential.rs b/examples/stm32g4/src/bin/adc_differential.rs
index 2773723e9..6dedf88d6 100644
--- a/examples/stm32g4/src/bin/adc_differential.rs
+++ b/examples/stm32g4/src/bin/adc_differential.rs
@@ -32,7 +32,7 @@ async fn main(_spawner: Spawner) {
     }
     let p = embassy_stm32::init(config);
 
-    let mut adc = Adc::new(p.ADC1);
+    let mut adc = Adc::new(p.ADC1, Default::default());
     let mut differential_channel = (p.PA0, p.PA1);
 
     // can also use
diff --git a/examples/stm32g4/src/bin/adc_dma.rs b/examples/stm32g4/src/bin/adc_dma.rs
index ef8b0c3c2..478b6b2ca 100644
--- a/examples/stm32g4/src/bin/adc_dma.rs
+++ b/examples/stm32g4/src/bin/adc_dma.rs
@@ -33,7 +33,7 @@ async fn main(_spawner: Spawner) {
 
     info!("Hello World!");
 
-    let mut adc = Adc::new(p.ADC1);
+    let mut adc = Adc::new(p.ADC1, Default::default());
 
     let mut dma = p.DMA1_CH1;
     let mut vrefint_channel = adc.enable_vrefint().degrade_adc();
diff --git a/examples/stm32g4/src/bin/adc_injected_and_regular.rs b/examples/stm32g4/src/bin/adc_injected_and_regular.rs
index 3ae2ff064..1e97fa925 100644
--- a/examples/stm32g4/src/bin/adc_injected_and_regular.rs
+++ b/examples/stm32g4/src/bin/adc_injected_and_regular.rs
@@ -77,7 +77,7 @@ async fn main(_spawner: embassy_executor::Spawner) {
     pwm.set_mms2(Mms2::UPDATE);
 
     // Configure regular conversions with DMA
-    let adc1 = Adc::new(p.ADC1);
+    let adc1 = Adc::new(p.ADC1, Default::default());
 
     let vrefint_channel = adc1.enable_vrefint().degrade_adc();
     let pa0 = p.PC1.degrade_adc();
diff --git a/examples/stm32g4/src/bin/adc_oversampling.rs b/examples/stm32g4/src/bin/adc_oversampling.rs
index cb99ab2a7..87ffea4be 100644
--- a/examples/stm32g4/src/bin/adc_oversampling.rs
+++ b/examples/stm32g4/src/bin/adc_oversampling.rs
@@ -9,7 +9,7 @@ use defmt::*;
 use embassy_executor::Spawner;
 use embassy_stm32::Config;
 use embassy_stm32::adc::vals::{Rovsm, Trovs};
-use embassy_stm32::adc::{Adc, SampleTime};
+use embassy_stm32::adc::{Adc, AdcConfig, SampleTime};
 use embassy_time::Timer;
 use {defmt_rtt as _, panic_probe as _};
 
@@ -32,7 +32,8 @@ async fn main(_spawner: Spawner) {
     }
     let mut p = embassy_stm32::init(config);
 
-    let mut adc = Adc::new(p.ADC1);
+    let mut config = AdcConfig::default();
+
     // From https://www.st.com/resource/en/reference_manual/rm0440-stm32g4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
     // page652 Oversampler
     // Table 172. Maximum output results vs N and M. Grayed values indicates truncation
@@ -44,9 +45,11 @@ async fn main(_spawner: Spawner) {
     // 0x05 oversampling ratio X64
     // 0x06 oversampling ratio X128
     // 0x07 oversampling ratio X256
-    adc.set_oversampling_ratio(0x03); // ratio X3
-    adc.set_oversampling_shift(0b0000); // no shift
-    adc.enable_regular_oversampling_mode(Rovsm::RESUMED, Trovs::AUTOMATIC, true);
+    config.oversampling_ratio = Some(0x03); // ratio X3
+    config.oversampling_shift = Some(0b0000); // no shift
+    config.oversampling_mode = Some((Rovsm::RESUMED, Trovs::AUTOMATIC, true));
+
+    let mut adc = Adc::new(p.ADC1, config);
 
     loop {
         let measured = adc.blocking_read(&mut p.PA0, SampleTime::CYCLES6_5);
diff --git a/examples/stm32g4/src/bin/button_exti.rs b/examples/stm32g4/src/bin/button_exti.rs
index 2a546dac5..e7e1549a8 100644
--- a/examples/stm32g4/src/bin/button_exti.rs
+++ b/examples/stm32g4/src/bin/button_exti.rs
@@ -3,16 +3,22 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::gpio::Pull;
+use embassy_stm32::{bind_interrupts, interrupt};
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI15_10 => exti::InterruptHandler<interrupt::typelevel::EXTI15_10>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Hello World!");
 
-    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down);
+    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down, Irqs);
 
     info!("Press the USER button...");
 
diff --git a/examples/stm32h5/src/bin/adc_dma.rs b/examples/stm32h5/src/bin/adc_dma.rs
index fb9fcbc5c..2138257f7 100644
--- a/examples/stm32h5/src/bin/adc_dma.rs
+++ b/examples/stm32h5/src/bin/adc_dma.rs
@@ -6,7 +6,7 @@ use embassy_executor::Spawner;
 use embassy_stm32::adc::{self, Adc, AdcChannel, RxDma, SampleTime};
 use embassy_stm32::peripherals::{ADC1, ADC2, GPDMA1_CH0, GPDMA1_CH1, PA0, PA1, PA2, PA3};
 use embassy_stm32::{Config, Peri};
-use embassy_time::Instant;
+use embassy_time::{Duration, Instant, Ticker};
 use {defmt_rtt as _, panic_probe as _};
 
 #[embassy_executor::main]
@@ -76,6 +76,9 @@ async fn adc_task<'a, T: adc::Instance>(
     let mut pin1 = pin1.degrade_adc();
     let mut pin2 = pin2.degrade_adc();
 
+    info!("adc init");
+
+    let mut ticker = Ticker::every(Duration::from_millis(500));
     let mut tic = Instant::now();
     let mut buffer = [0u16; 512];
     loop {
@@ -84,11 +87,13 @@ async fn adc_task<'a, T: adc::Instance>(
         adc.read(
             dma.reborrow(),
             [(&mut pin1, SampleTime::CYCLES2_5), (&mut pin2, SampleTime::CYCLES2_5)].into_iter(),
-            &mut buffer,
+            &mut buffer[0..2],
         )
         .await;
         let toc = Instant::now();
         info!("\n adc1: {} dt = {}", buffer[0..16], (toc - tic).as_micros());
         tic = toc;
+
+        ticker.next().await;
     }
 }
diff --git a/examples/stm32h5/src/bin/button_exti.rs b/examples/stm32h5/src/bin/button_exti.rs
index 2a546dac5..220f89228 100644
--- a/examples/stm32h5/src/bin/button_exti.rs
+++ b/examples/stm32h5/src/bin/button_exti.rs
@@ -3,16 +3,22 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::gpio::Pull;
+use embassy_stm32::{bind_interrupts, interrupt};
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI13 => exti::InterruptHandler<interrupt::typelevel::EXTI13>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Hello World!");
 
-    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down);
+    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down, Irqs);
 
     info!("Press the USER button...");
 
diff --git a/examples/stm32h5/src/bin/eth.rs b/examples/stm32h5/src/bin/eth.rs
index a5c6cee26..6a3afb2d1 100644
--- a/examples/stm32h5/src/bin/eth.rs
+++ b/examples/stm32h5/src/bin/eth.rs
@@ -5,8 +5,8 @@ use defmt::*;
 use embassy_executor::Spawner;
 use embassy_net::tcp::TcpSocket;
 use embassy_net::{Ipv4Address, StackResources};
-use embassy_stm32::eth::{Ethernet, GenericPhy, PacketQueue};
-use embassy_stm32::peripherals::ETH;
+use embassy_stm32::eth::{Ethernet, GenericPhy, PacketQueue, Sma};
+use embassy_stm32::peripherals::{ETH, ETH_SMA};
 use embassy_stm32::rcc::{
     AHBPrescaler, APBPrescaler, Hse, HseMode, Pll, PllDiv, PllMul, PllPreDiv, PllSource, Sysclk, VoltageScale,
 };
@@ -23,7 +23,7 @@ bind_interrupts!(struct Irqs {
     RNG => rng::InterruptHandler<peripherals::RNG>;
 });
 
-type Device = Ethernet<'static, ETH, GenericPhy>;
+type Device = Ethernet<'static, ETH, GenericPhy<Sma<'static, ETH_SMA>>>;
 
 #[embassy_executor::task]
 async fn net_task(mut runner: embassy_net::Runner<'static, Device>) -> ! {
@@ -70,16 +70,16 @@ async fn main(spawner: Spawner) -> ! {
         p.ETH,
         Irqs,
         p.PA1,
-        p.PA2,
-        p.PC1,
         p.PA7,
         p.PC4,
         p.PC5,
         p.PG13,
         p.PB15,
         p.PG11,
-        GenericPhy::new_auto(),
         mac_addr,
+        p.ETH_SMA,
+        p.PA2,
+        p.PC1,
     );
 
     let config = embassy_net::Config::dhcpv4(Default::default());
diff --git a/examples/stm32h5/src/bin/stop.rs b/examples/stm32h5/src/bin/stop.rs
index caebc9daf..8d5456b80 100644
--- a/examples/stm32h5/src/bin/stop.rs
+++ b/examples/stm32h5/src/bin/stop.rs
@@ -7,20 +7,12 @@
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_stm32::gpio::{AnyPin, Level, Output, Speed};
-use embassy_stm32::low_power::Executor;
 use embassy_stm32::rcc::{HSIPrescaler, LsConfig};
-use embassy_stm32::{Config, Peri};
+use embassy_stm32::{Config, Peri, low_power};
 use embassy_time::Timer;
 use {defmt_rtt as _, panic_probe as _};
 
-#[cortex_m_rt::entry]
-fn main() -> ! {
-    Executor::take().run(|spawner| {
-        spawner.spawn(unwrap!(async_main(spawner)));
-    })
-}
-
-#[embassy_executor::task]
+#[embassy_executor::main(executor = "low_power::Executor")]
 async fn async_main(spawner: Spawner) {
     defmt::info!("Program Start");
 
diff --git a/examples/stm32h7/src/bin/button_exti.rs b/examples/stm32h7/src/bin/button_exti.rs
index 2a546dac5..e7e1549a8 100644
--- a/examples/stm32h7/src/bin/button_exti.rs
+++ b/examples/stm32h7/src/bin/button_exti.rs
@@ -3,16 +3,22 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::gpio::Pull;
+use embassy_stm32::{bind_interrupts, interrupt};
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI15_10 => exti::InterruptHandler<interrupt::typelevel::EXTI15_10>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Hello World!");
 
-    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down);
+    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down, Irqs);
 
     info!("Press the USER button...");
 
diff --git a/examples/stm32h7/src/bin/eth.rs b/examples/stm32h7/src/bin/eth.rs
index 589f4426e..09915799b 100644
--- a/examples/stm32h7/src/bin/eth.rs
+++ b/examples/stm32h7/src/bin/eth.rs
@@ -5,8 +5,8 @@ use defmt::*;
 use embassy_executor::Spawner;
 use embassy_net::tcp::TcpSocket;
 use embassy_net::{Ipv4Address, StackResources};
-use embassy_stm32::eth::{Ethernet, GenericPhy, PacketQueue};
-use embassy_stm32::peripherals::ETH;
+use embassy_stm32::eth::{Ethernet, GenericPhy, PacketQueue, Sma};
+use embassy_stm32::peripherals::{ETH, ETH_SMA};
 use embassy_stm32::rng::Rng;
 use embassy_stm32::{Config, bind_interrupts, eth, peripherals, rng};
 use embassy_time::Timer;
@@ -19,7 +19,7 @@ bind_interrupts!(struct Irqs {
     RNG => rng::InterruptHandler<peripherals::RNG>;
 });
 
-type Device = Ethernet<'static, ETH, GenericPhy>;
+type Device = Ethernet<'static, ETH, GenericPhy<Sma<'static, ETH_SMA>>>;
 
 #[embassy_executor::task]
 async fn net_task(mut runner: embassy_net::Runner<'static, Device>) -> ! {
@@ -69,16 +69,16 @@ async fn main(spawner: Spawner) -> ! {
         p.ETH,
         Irqs,
         p.PA1,  // ref_clk
-        p.PA2,  // mdio
-        p.PC1,  // eth_mdc
         p.PA7,  // CRS_DV: Carrier Sense
         p.PC4,  // RX_D0: Received Bit 0
         p.PC5,  // RX_D1: Received Bit 1
         p.PG13, // TX_D0: Transmit Bit 0
         p.PB13, // TX_D1: Transmit Bit 1
         p.PG11, // TX_EN: Transmit Enable
-        GenericPhy::new_auto(),
         mac_addr,
+        p.ETH_SMA,
+        p.PA2, // mdio
+        p.PC1, // mdc
     );
 
     let config = embassy_net::Config::dhcpv4(Default::default());
diff --git a/examples/stm32h7/src/bin/eth_client.rs b/examples/stm32h7/src/bin/eth_client.rs
index fed8f1a9c..189c99686 100644
--- a/examples/stm32h7/src/bin/eth_client.rs
+++ b/examples/stm32h7/src/bin/eth_client.rs
@@ -7,8 +7,8 @@ use defmt::*;
 use embassy_executor::Spawner;
 use embassy_net::StackResources;
 use embassy_net::tcp::client::{TcpClient, TcpClientState};
-use embassy_stm32::eth::{Ethernet, GenericPhy, PacketQueue};
-use embassy_stm32::peripherals::ETH;
+use embassy_stm32::eth::{Ethernet, GenericPhy, PacketQueue, Sma};
+use embassy_stm32::peripherals::{ETH, ETH_SMA};
 use embassy_stm32::rng::Rng;
 use embassy_stm32::{Config, bind_interrupts, eth, peripherals, rng};
 use embassy_time::Timer;
@@ -22,7 +22,7 @@ bind_interrupts!(struct Irqs {
     RNG => rng::InterruptHandler<peripherals::RNG>;
 });
 
-type Device = Ethernet<'static, ETH, GenericPhy>;
+type Device = Ethernet<'static, ETH, GenericPhy<Sma<'static, ETH_SMA>>>;
 
 #[embassy_executor::task]
 async fn net_task(mut runner: embassy_net::Runner<'static, Device>) -> ! {
@@ -71,16 +71,16 @@ async fn main(spawner: Spawner) -> ! {
         p.ETH,
         Irqs,
         p.PA1,
-        p.PA2,
-        p.PC1,
         p.PA7,
         p.PC4,
         p.PC5,
         p.PG13,
         p.PB13,
         p.PG11,
-        GenericPhy::new_auto(),
         mac_addr,
+        p.ETH_SMA,
+        p.PA2,
+        p.PC1,
     );
 
     let config = embassy_net::Config::dhcpv4(Default::default());
diff --git a/examples/stm32h7/src/bin/eth_client_mii.rs b/examples/stm32h7/src/bin/eth_client_mii.rs
index c3c631f0f..92c823567 100644
--- a/examples/stm32h7/src/bin/eth_client_mii.rs
+++ b/examples/stm32h7/src/bin/eth_client_mii.rs
@@ -7,8 +7,8 @@ use defmt::*;
 use embassy_executor::Spawner;
 use embassy_net::StackResources;
 use embassy_net::tcp::client::{TcpClient, TcpClientState};
-use embassy_stm32::eth::{Ethernet, GenericPhy, PacketQueue};
-use embassy_stm32::peripherals::ETH;
+use embassy_stm32::eth::{Ethernet, GenericPhy, PacketQueue, Sma};
+use embassy_stm32::peripherals::{ETH, ETH_SMA};
 use embassy_stm32::rng::Rng;
 use embassy_stm32::{Config, bind_interrupts, eth, peripherals, rng};
 use embassy_time::Timer;
@@ -22,7 +22,7 @@ bind_interrupts!(struct Irqs {
     RNG => rng::InterruptHandler<peripherals::RNG>;
 });
 
-type Device = Ethernet<'static, ETH, GenericPhy>;
+type Device = Ethernet<'static, ETH, GenericPhy<Sma<'static, ETH_SMA>>>;
 
 #[embassy_executor::task]
 async fn net_task(mut runner: embassy_net::Runner<'static, Device>) -> ! {
@@ -72,8 +72,6 @@ async fn main(spawner: Spawner) -> ! {
         Irqs,
         p.PA1,
         p.PC3,
-        p.PA2,
-        p.PC1,
         p.PA7,
         p.PC4,
         p.PC5,
@@ -84,8 +82,10 @@ async fn main(spawner: Spawner) -> ! {
         p.PC2,
         p.PE2,
         p.PG11,
-        GenericPhy::new_auto(),
         mac_addr,
+        p.ETH_SMA,
+        p.PA2,
+        p.PC1,
     );
     info!("Device created");
 
diff --git a/examples/stm32h7/src/bin/flash_async.rs b/examples/stm32h7/src/bin/flash_async.rs
new file mode 100644
index 000000000..96d1936f3
--- /dev/null
+++ b/examples/stm32h7/src/bin/flash_async.rs
@@ -0,0 +1,84 @@
+#![no_std]
+#![no_main]
+
+use defmt::{info, unwrap};
+use embassy_executor::Spawner;
+use embassy_stm32::flash::{Flash, InterruptHandler};
+use embassy_stm32::gpio::{AnyPin, Level, Output, Speed};
+use embassy_stm32::{Peri, bind_interrupts};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    FLASH => InterruptHandler;
+});
+
+#[embassy_executor::main]
+async fn main(spawner: Spawner) {
+    let p = embassy_stm32::init(Default::default());
+    info!("Hello Flash!");
+
+    let mut f = Flash::new(p.FLASH, Irqs);
+
+    // Led should blink uninterrupted during ~2sec erase operation
+    spawner.spawn(blinky(p.PB14.into()).unwrap());
+
+    // Test on bank 2 in order not to stall CPU.
+    test_flash(&mut f, 1024 * 1024, 128 * 1024).await;
+}
+
+#[embassy_executor::task]
+async fn blinky(p: Peri<'static, AnyPin>) {
+    let mut led = Output::new(p, Level::High, Speed::Low);
+
+    loop {
+        info!("high");
+        led.set_high();
+        Timer::after_millis(300).await;
+
+        info!("low");
+        led.set_low();
+        Timer::after_millis(300).await;
+    }
+}
+
+async fn test_flash<'a>(f: &mut Flash<'a>, offset: u32, size: u32) {
+    info!("Testing offset: {=u32:#X}, size: {=u32:#X}", offset, size);
+
+    info!("Reading...");
+    let mut buf = [0u8; 32];
+    unwrap!(f.blocking_read(offset, &mut buf));
+    info!("Read: {=[u8]:x}", buf);
+
+    info!("Erasing...");
+    unwrap!(f.erase(offset, offset + size).await);
+
+    info!("Reading...");
+    let mut buf = [0u8; 32];
+    unwrap!(f.blocking_read(offset, &mut buf));
+    info!("Read after erase: {=[u8]:x}", buf);
+
+    info!("Writing...");
+    unwrap!(
+        f.write(
+            offset,
+            &[
+                1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28,
+                29, 30, 31, 32
+            ]
+        )
+        .await
+    );
+
+    info!("Reading...");
+    let mut buf = [0u8; 32];
+    unwrap!(f.blocking_read(offset, &mut buf));
+    info!("Read: {=[u8]:x}", buf);
+    assert_eq!(
+        &buf[..],
+        &[
+            1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+            30, 31, 32
+        ]
+    );
+}
diff --git a/examples/stm32h723/src/bin/spdifrx.rs b/examples/stm32h723/src/bin/spdifrx.rs
index cdbd69b89..5c29602c6 100644
--- a/examples/stm32h723/src/bin/spdifrx.rs
+++ b/examples/stm32h723/src/bin/spdifrx.rs
@@ -167,7 +167,7 @@ fn new_sai_transmitter<'d>(
     sai_config.slot_count = hal::sai::word::U4(CHANNEL_COUNT as u8);
     sai_config.slot_enable = 0xFFFF; // All slots
     sai_config.data_size = sai::DataSize::Data32;
-    sai_config.frame_length = (CHANNEL_COUNT * 32) as u8;
+    sai_config.frame_length = (CHANNEL_COUNT * 32) as u16;
     sai_config.master_clock_divider = None;
 
     let (sub_block_tx, _) = hal::sai::split_subblocks(sai);
diff --git a/examples/stm32h7rs/src/bin/button_exti.rs b/examples/stm32h7rs/src/bin/button_exti.rs
index 34a08bbc6..d63290d42 100644
--- a/examples/stm32h7rs/src/bin/button_exti.rs
+++ b/examples/stm32h7rs/src/bin/button_exti.rs
@@ -3,16 +3,22 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::gpio::Pull;
+use embassy_stm32::{bind_interrupts, interrupt};
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI13 => exti::InterruptHandler<interrupt::typelevel::EXTI13>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Hello World!");
 
-    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up);
+    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up, Irqs);
 
     info!("Press the USER button...");
 
diff --git a/examples/stm32h7rs/src/bin/eth.rs b/examples/stm32h7rs/src/bin/eth.rs
index 5ce1d4765..8e07d0a67 100644
--- a/examples/stm32h7rs/src/bin/eth.rs
+++ b/examples/stm32h7rs/src/bin/eth.rs
@@ -5,8 +5,8 @@ use defmt::*;
 use embassy_executor::Spawner;
 use embassy_net::udp::{PacketMetadata, UdpSocket};
 use embassy_net::{Ipv4Address, Ipv4Cidr, StackResources};
-use embassy_stm32::eth::{Ethernet, GenericPhy, PacketQueue};
-use embassy_stm32::peripherals::ETH;
+use embassy_stm32::eth::{Ethernet, GenericPhy, PacketQueue, Sma};
+use embassy_stm32::peripherals::{ETH, ETH_SMA};
 use embassy_stm32::rng::Rng;
 use embassy_stm32::{Config, bind_interrupts, eth, peripherals, rng};
 use embassy_time::Timer;
@@ -19,7 +19,7 @@ bind_interrupts!(struct Irqs {
     RNG => rng::InterruptHandler<peripherals::RNG>;
 });
 
-type Device = Ethernet<'static, ETH, GenericPhy>;
+type Device = Ethernet<'static, ETH, GenericPhy<Sma<'static, ETH_SMA>>>;
 
 #[embassy_executor::task]
 async fn net_task(mut runner: embassy_net::Runner<'static, Device>) -> ! {
@@ -69,16 +69,16 @@ async fn main(spawner: Spawner) -> ! {
         p.ETH,
         Irqs,
         p.PB6,
-        p.PA2,
-        p.PG6,
         p.PA7,
         p.PG4,
         p.PG5,
         p.PG13,
         p.PG12,
         p.PG11,
-        GenericPhy::new(0),
         mac_addr,
+        p.ETH_SMA,
+        p.PA2,
+        p.PG6,
     );
 
     // Have to use UDP w/ static config to fit in internal flash
diff --git a/examples/stm32l0/src/bin/button_exti.rs b/examples/stm32l0/src/bin/button_exti.rs
index 7ff4a7d52..a118c7a5a 100644
--- a/examples/stm32l0/src/bin/button_exti.rs
+++ b/examples/stm32l0/src/bin/button_exti.rs
@@ -3,17 +3,22 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::Config;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::gpio::Pull;
+use embassy_stm32::{Config, bind_interrupts, interrupt};
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI2_3 => exti::InterruptHandler<interrupt::typelevel::EXTI2_3>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let config = Config::default();
     let p = embassy_stm32::init(config);
 
-    let mut button = ExtiInput::new(p.PB2, p.EXTI2, Pull::Up);
+    let mut button = ExtiInput::new(p.PB2, p.EXTI2, Pull::Up, Irqs);
 
     info!("Press the USER button...");
 
diff --git a/examples/stm32l4/src/bin/adc.rs b/examples/stm32l4/src/bin/adc.rs
index 835bf5411..42766a5e3 100644
--- a/examples/stm32l4/src/bin/adc.rs
+++ b/examples/stm32l4/src/bin/adc.rs
@@ -3,7 +3,7 @@
 
 use defmt::*;
 use embassy_stm32::Config;
-use embassy_stm32::adc::{Adc, Resolution, SampleTime};
+use embassy_stm32::adc::{Adc, AdcConfig, Resolution, SampleTime};
 use {defmt_rtt as _, panic_probe as _};
 
 #[cortex_m_rt::entry]
@@ -17,9 +17,12 @@ fn main() -> ! {
     }
     let p = embassy_stm32::init(config);
 
-    let mut adc = Adc::new(p.ADC1);
+    let mut config = AdcConfig::default();
+    config.resolution = Some(Resolution::BITS8);
+
+    let mut adc = Adc::new_with_config(p.ADC1, config);
     //adc.enable_vref();
-    adc.set_resolution(Resolution::BITS8);
+
     let mut channel = p.PC0;
 
     loop {
diff --git a/examples/stm32l4/src/bin/adc_dma.rs b/examples/stm32l4/src/bin/adc_dma.rs
index ab1e9d2e9..550da95a4 100644
--- a/examples/stm32l4/src/bin/adc_dma.rs
+++ b/examples/stm32l4/src/bin/adc_dma.rs
@@ -4,7 +4,7 @@
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_stm32::Config;
-use embassy_stm32::adc::{Adc, AdcChannel, SampleTime};
+use embassy_stm32::adc::{Adc, AdcChannel, RegularConversionMode, SampleTime};
 use {defmt_rtt as _, panic_probe as _};
 
 const DMA_BUF_LEN: usize = 512;
@@ -20,7 +20,7 @@ async fn main(_spawner: Spawner) {
     }
     let p = embassy_stm32::init(config);
 
-    let mut adc = Adc::new(p.ADC1);
+    let adc = Adc::new(p.ADC1);
     let adc_pin0 = p.PA0.degrade_adc();
     let adc_pin1 = p.PA1.degrade_adc();
     let mut adc_dma_buf = [0u16; DMA_BUF_LEN];
@@ -29,6 +29,7 @@ async fn main(_spawner: Spawner) {
         p.DMA1_CH1,
         &mut adc_dma_buf,
         [(adc_pin0, SampleTime::CYCLES640_5), (adc_pin1, SampleTime::CYCLES640_5)].into_iter(),
+        RegularConversionMode::Continuous,
     );
 
     info!("starting measurement loop");
diff --git a/examples/stm32l4/src/bin/button_exti.rs b/examples/stm32l4/src/bin/button_exti.rs
index 34a08bbc6..c84b11dab 100644
--- a/examples/stm32l4/src/bin/button_exti.rs
+++ b/examples/stm32l4/src/bin/button_exti.rs
@@ -3,16 +3,22 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::gpio::Pull;
+use embassy_stm32::{bind_interrupts, interrupt};
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI15_10 => exti::InterruptHandler<interrupt::typelevel::EXTI15_10>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Hello World!");
 
-    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up);
+    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up, Irqs);
 
     info!("Press the USER button...");
 
diff --git a/examples/stm32l4/src/bin/spe_adin1110_http_server.rs b/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
index 0dbf515cf..8f2510cdc 100644
--- a/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
+++ b/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
@@ -24,6 +24,7 @@ use embassy_futures::yield_now;
 use embassy_net::tcp::TcpSocket;
 use embassy_net::{Ipv4Address, Ipv4Cidr, Stack, StackResources, StaticConfigV4};
 use embassy_net_adin1110::{ADIN1110, Device, Runner};
+use embassy_stm32::exti::ExtiInput;
 use embassy_stm32::gpio::{Input, Level, Output, Pull, Speed};
 use embassy_stm32::i2c::{self, Config as I2C_Config, I2c};
 use embassy_stm32::mode::Async;
@@ -31,7 +32,7 @@ use embassy_stm32::rng::{self, Rng};
 use embassy_stm32::spi::mode::Master;
 use embassy_stm32::spi::{Config as SPI_Config, Spi};
 use embassy_stm32::time::Hertz;
-use embassy_stm32::{bind_interrupts, exti, pac, peripherals};
+use embassy_stm32::{bind_interrupts, exti, interrupt, pac, peripherals};
 use embassy_time::{Delay, Duration, Ticker, Timer};
 use embedded_hal_async::i2c::I2c as I2cBus;
 use embedded_hal_bus::spi::ExclusiveDevice;
@@ -45,6 +46,7 @@ bind_interrupts!(struct Irqs {
     I2C3_EV => i2c::EventInterruptHandler<peripherals::I2C3>;
     I2C3_ER => i2c::ErrorInterruptHandler<peripherals::I2C3>;
     RNG => rng::InterruptHandler<peripherals::RNG>;
+    EXTI15_10 => exti::InterruptHandler<interrupt::typelevel::EXTI15_10>;
 });
 
 // Basic settings
@@ -125,7 +127,7 @@ async fn main(spawner: Spawner) {
     let spe_cfg1 = Input::new(dp.PC9, Pull::None);
     let _spe_ts_capt = Output::new(dp.PC6, Level::Low, Speed::Low);
 
-    let spe_int = exti::ExtiInput::new(dp.PB11, dp.EXTI11, Pull::None);
+    let spe_int = ExtiInput::new(dp.PB11, dp.EXTI11, Pull::None, Irqs);
 
     let spe_spi_cs_n = Output::new(dp.PB12, Level::High, Speed::High);
     let spe_spi_sclk = dp.PB13;
diff --git a/examples/stm32l4/src/bin/spi_dma.rs b/examples/stm32l4/src/bin/spi_dma.rs
index 946a759b1..970a0c608 100644
--- a/examples/stm32l4/src/bin/spi_dma.rs
+++ b/examples/stm32l4/src/bin/spi_dma.rs
@@ -34,8 +34,8 @@ async fn main(_spawner: Spawner) {
         info!("waiting for ready");
     }
 
-    let write = [0x0A; 10];
-    let mut read = [0; 10];
+    let write = [0x0Au8; 10];
+    let mut read = [0u8; 10];
     cs.set_low();
     spi.transfer(&mut read, &write).await.ok();
     cs.set_high();
diff --git a/examples/stm32l5/src/bin/button_exti.rs b/examples/stm32l5/src/bin/button_exti.rs
index e6639d22b..225a7b3fd 100644
--- a/examples/stm32l5/src/bin/button_exti.rs
+++ b/examples/stm32l5/src/bin/button_exti.rs
@@ -3,16 +3,22 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::gpio::Pull;
+use embassy_stm32::{bind_interrupts, interrupt};
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI13 => exti::InterruptHandler<interrupt::typelevel::EXTI13>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Hello World!");
 
-    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down);
+    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down, Irqs);
 
     info!("Press the USER button...");
 
diff --git a/examples/stm32l5/src/bin/stop.rs b/examples/stm32l5/src/bin/stop.rs
index 3d119f90f..fde804fb7 100644
--- a/examples/stm32l5/src/bin/stop.rs
+++ b/examples/stm32l5/src/bin/stop.rs
@@ -4,20 +4,12 @@
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_stm32::gpio::{AnyPin, Level, Output, Speed};
-use embassy_stm32::low_power::Executor;
 use embassy_stm32::rcc::LsConfig;
-use embassy_stm32::{Config, Peri};
+use embassy_stm32::{Config, Peri, low_power};
 use embassy_time::Timer;
 use {defmt_rtt as _, panic_probe as _};
 
-#[cortex_m_rt::entry]
-fn main() -> ! {
-    Executor::take().run(|spawner| {
-        spawner.spawn(unwrap!(async_main(spawner)));
-    })
-}
-
-#[embassy_executor::task]
+#[embassy_executor::main(executor = "low_power::Executor")]
 async fn async_main(spawner: Spawner) {
     let mut config = Config::default();
     config.rcc.ls = LsConfig::default_lsi();
diff --git a/examples/stm32l5/src/bin/usb_hid_mouse.rs b/examples/stm32l5/src/bin/usb_hid_mouse.rs
index b721f5b2e..d8f2de941 100644
--- a/examples/stm32l5/src/bin/usb_hid_mouse.rs
+++ b/examples/stm32l5/src/bin/usb_hid_mouse.rs
@@ -1,6 +1,8 @@
 #![no_std]
 #![no_main]
 
+use core::sync::atomic::{AtomicU8, Ordering};
+
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_futures::join::join;
@@ -8,7 +10,9 @@ use embassy_stm32::usb::Driver;
 use embassy_stm32::{Config, bind_interrupts, peripherals, usb};
 use embassy_time::Timer;
 use embassy_usb::Builder;
-use embassy_usb::class::hid::{HidWriter, ReportId, RequestHandler, State};
+use embassy_usb::class::hid::{
+    HidBootProtocol, HidProtocolMode, HidSubclass, HidWriter, ReportId, RequestHandler, State,
+};
 use embassy_usb::control::OutResponse;
 use usbd_hid::descriptor::{MouseReport, SerializedDescriptor};
 use {defmt_rtt as _, panic_probe as _};
@@ -17,6 +21,8 @@ bind_interrupts!(struct Irqs {
     USB_FS => usb::InterruptHandler<peripherals::USB>;
 });
 
+static HID_PROTOCOL_MODE: AtomicU8 = AtomicU8::new(HidProtocolMode::Boot as u8);
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let mut config = Config::default();
@@ -48,6 +54,10 @@ async fn main(_spawner: Spawner) {
     config.serial_number = Some("12345678");
     config.max_power = 100;
     config.max_packet_size_0 = 64;
+    config.composite_with_iads = false;
+    config.device_class = 0;
+    config.device_sub_class = 0;
+    config.device_protocol = 0;
 
     // Create embassy-usb DeviceBuilder using the driver and config.
     // It needs some buffers for building the descriptors.
@@ -73,6 +83,8 @@ async fn main(_spawner: Spawner) {
         request_handler: Some(&mut request_handler),
         poll_ms: 60,
         max_packet_size: 8,
+        hid_subclass: HidSubclass::Boot,
+        hid_boot_protocol: HidBootProtocol::Mouse,
     };
 
     let mut writer = HidWriter::<_, 5>::new(&mut builder, &mut state, config);
@@ -90,16 +102,26 @@ async fn main(_spawner: Spawner) {
             Timer::after_millis(500).await;
 
             y = -y;
-            let report = MouseReport {
-                buttons: 0,
-                x: 0,
-                y,
-                wheel: 0,
-                pan: 0,
-            };
-            match writer.write_serialize(&report).await {
-                Ok(()) => {}
-                Err(e) => warn!("Failed to send report: {:?}", e),
+
+            if HID_PROTOCOL_MODE.load(Ordering::Relaxed) == HidProtocolMode::Boot as u8 {
+                let buttons = 0u8;
+                let x = 0i8;
+                match writer.write(&[buttons, x as u8, y as u8]).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send boot report: {:?}", e),
+                }
+            } else {
+                let report = MouseReport {
+                    buttons: 0,
+                    x: 0,
+                    y,
+                    wheel: 0,
+                    pan: 0,
+                };
+                match writer.write_serialize(&report).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send report: {:?}", e),
+                }
             }
         }
     };
@@ -122,6 +144,18 @@ impl RequestHandler for MyRequestHandler {
         OutResponse::Accepted
     }
 
+    fn get_protocol(&self) -> HidProtocolMode {
+        let protocol = HidProtocolMode::from(HID_PROTOCOL_MODE.load(Ordering::Relaxed));
+        info!("The current HID protocol mode is: {}", protocol);
+        protocol
+    }
+
+    fn set_protocol(&mut self, protocol: HidProtocolMode) -> OutResponse {
+        info!("Switching to HID protocol mode: {}", protocol);
+        HID_PROTOCOL_MODE.store(protocol as u8, Ordering::Relaxed);
+        OutResponse::Accepted
+    }
+
     fn set_idle_ms(&mut self, id: Option<ReportId>, dur: u32) {
         info!("Set idle rate for {:?} to {:?}", id, dur);
     }
diff --git a/examples/stm32n6/src/bin/blinky.rs b/examples/stm32n6/src/bin/blinky.rs
index 018967f08..a8baf16af 100644
--- a/examples/stm32n6/src/bin/blinky.rs
+++ b/examples/stm32n6/src/bin/blinky.rs
@@ -3,11 +3,17 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::gpio::{Level, Output, Pull, Speed};
+use embassy_stm32::{bind_interrupts, interrupt};
 use embassy_time::Timer;
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI13 => exti::InterruptHandler<interrupt::typelevel::EXTI13>;
+});
+
 #[embassy_executor::task]
 async fn button_task(mut p: ExtiInput<'static>) {
     loop {
@@ -22,7 +28,7 @@ async fn main(spawner: Spawner) {
     info!("Hello World!");
 
     let mut led = Output::new(p.PG10, Level::High, Speed::Low);
-    let button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up);
+    let button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up, Irqs);
 
     spawner.spawn(button_task(button).unwrap());
 
diff --git a/examples/stm32u0/.cargo/config.toml b/examples/stm32u0/.cargo/config.toml
index 688347084..e9212cacb 100644
--- a/examples/stm32u0/.cargo/config.toml
+++ b/examples/stm32u0/.cargo/config.toml
@@ -1,6 +1,6 @@
 [target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace stm32u083rctx with your chip as listed in `probe-rs chip list`
-runner = "probe-rs run --chip stm32u083rctx"
+# replace stm32u083mctx with your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip stm32u083mctx"
 
 [build]
 target = "thumbv6m-none-eabi"
diff --git a/examples/stm32u0/Cargo.toml b/examples/stm32u0/Cargo.toml
index 9f5227e3f..8cc894cb3 100644
--- a/examples/stm32u0/Cargo.toml
+++ b/examples/stm32u0/Cargo.toml
@@ -6,8 +6,8 @@ license = "MIT OR Apache-2.0"
 publish = false
 
 [dependencies]
-# Change stm32u083rc to your chip name, if necessary.
-embassy-stm32 = { version = "0.4.0", path = "../../embassy-stm32", features = [ "defmt", "time-driver-any", "stm32u083rc", "memory-x", "unstable-pac", "exti", "chrono"]  }
+# Change stm32u083mc to your chip name, if necessary.
+embassy-stm32 = { version = "0.4.0", path = "../../embassy-stm32", features = [ "defmt", "time-driver-any", "stm32u083mc", "memory-x", "unstable-pac", "exti", "chrono"]  }
 embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
 embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
@@ -19,9 +19,7 @@ defmt-rtt = "1.0.0"
 
 cortex-m = { version = "0.7.6", features = ["critical-section-single-core"] }
 cortex-m-rt = "0.7.0"
-embedded-hal = "0.2.6"
 panic-probe = { version = "1.0.0", features = ["print-defmt"] }
-heapless = { version = "0.8", default-features = false }
 
 micromath = "2.0.0"
 chrono = { version = "0.4.38", default-features = false }
diff --git a/examples/stm32u0/src/bin/adc.rs b/examples/stm32u0/src/bin/adc.rs
index 4fbc6f17f..53bd37303 100644
--- a/examples/stm32u0/src/bin/adc.rs
+++ b/examples/stm32u0/src/bin/adc.rs
@@ -3,7 +3,7 @@
 
 use defmt::*;
 use embassy_stm32::Config;
-use embassy_stm32::adc::{Adc, Resolution, SampleTime};
+use embassy_stm32::adc::{Adc, AdcConfig, Resolution, SampleTime};
 use embassy_time::Duration;
 use {defmt_rtt as _, panic_probe as _};
 
@@ -18,8 +18,9 @@ fn main() -> ! {
     }
     let p = embassy_stm32::init(config);
 
-    let mut adc = Adc::new(p.ADC1);
-    adc.set_resolution(Resolution::BITS8);
+    let mut config = AdcConfig::default();
+    config.resolution = Some(Resolution::BITS8);
+    let mut adc = Adc::new_with_config(p.ADC1, config);
     let mut channel = p.PC0;
 
     loop {
diff --git a/examples/stm32u0/src/bin/button_exti.rs b/examples/stm32u0/src/bin/button_exti.rs
index 34a08bbc6..9d54479da 100644
--- a/examples/stm32u0/src/bin/button_exti.rs
+++ b/examples/stm32u0/src/bin/button_exti.rs
@@ -3,16 +3,22 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::gpio::Pull;
+use embassy_stm32::{bind_interrupts, interrupt};
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI4_15 => exti::InterruptHandler<interrupt::typelevel::EXTI4_15>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Hello World!");
 
-    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up);
+    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up, Irqs);
 
     info!("Press the USER button...");
 
diff --git a/examples/stm32u0/src/bin/lcd.rs b/examples/stm32u0/src/bin/lcd.rs
new file mode 100644
index 000000000..2b34d4ef1
--- /dev/null
+++ b/examples/stm32u0/src/bin/lcd.rs
@@ -0,0 +1,412 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::lcd::{Bias, BlinkFreq, BlinkSelector, Config, Duty, Lcd, LcdPin};
+use embassy_stm32::peripherals::LCD;
+use embassy_stm32::time::Hertz;
+use embassy_time::Duration;
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut config = embassy_stm32::Config::default();
+    // The RTC clock = the LCD clock and must be running
+    {
+        use embassy_stm32::rcc::*;
+        config.rcc.sys = Sysclk::PLL1_R;
+        config.rcc.hsi = true;
+        config.rcc.pll = Some(Pll {
+            source: PllSource::HSI, // 16 MHz
+            prediv: PllPreDiv::DIV1,
+            mul: PllMul::MUL7, // 16 * 7 = 112 MHz
+            divp: None,
+            divq: None,
+            divr: Some(PllRDiv::DIV2), // 112 / 2 = 56 MHz
+        });
+        config.rcc.ls = LsConfig::default_lsi();
+    }
+
+    let p = embassy_stm32::init(config);
+    info!("Hello World!");
+
+    let mut config = Config::default();
+    config.bias = Bias::Third;
+    config.duty = Duty::Quarter;
+    config.target_fps = Hertz(100);
+
+    let mut lcd = Lcd::new(
+        p.LCD,
+        config,
+        p.PC3,
+        [
+            LcdPin::new_com(p.PA8),
+            LcdPin::new_com(p.PA9),
+            LcdPin::new_com(p.PA10),
+            LcdPin::new_seg(p.PB1),
+            LcdPin::new_com(p.PB9),
+            LcdPin::new_seg(p.PB11),
+            LcdPin::new_seg(p.PB14),
+            LcdPin::new_seg(p.PB15),
+            LcdPin::new_seg(p.PC4),
+            LcdPin::new_seg(p.PC5),
+            LcdPin::new_seg(p.PC6),
+            LcdPin::new_seg(p.PC8),
+            LcdPin::new_seg(p.PC9),
+            LcdPin::new_seg(p.PC10),
+            LcdPin::new_seg(p.PC11),
+            LcdPin::new_seg(p.PD8),
+            LcdPin::new_seg(p.PD9),
+            LcdPin::new_seg(p.PD12),
+            LcdPin::new_seg(p.PD13),
+            LcdPin::new_seg(p.PD0),
+            LcdPin::new_seg(p.PD1),
+            LcdPin::new_seg(p.PD3),
+            LcdPin::new_seg(p.PD4),
+            LcdPin::new_seg(p.PD5),
+            LcdPin::new_seg(p.PD6),
+            LcdPin::new_seg(p.PE7),
+            LcdPin::new_seg(p.PE8),
+            LcdPin::new_seg(p.PE9),
+        ],
+    );
+
+    lcd.set_blink(BlinkSelector::All, BlinkFreq::Hz4);
+    {
+        let mut buffer = DisplayBuffer::new();
+        for i in 0..4 {
+            buffer.write_colon(i);
+            buffer.write(&mut lcd);
+            embassy_time::Timer::after_millis(200).await;
+            buffer.write_dot(i);
+            buffer.write(&mut lcd);
+            embassy_time::Timer::after_millis(200).await;
+        }
+        for i in 0..4 {
+            buffer.write_bar(i);
+            buffer.write(&mut lcd);
+            embassy_time::Timer::after_millis(200).await;
+        }
+    }
+
+    embassy_time::Timer::after_millis(1000).await;
+
+    lcd.set_blink(BlinkSelector::None, BlinkFreq::Hz4);
+
+    const MESSAGE: &str = "Hello embassy people. Hope you like this LCD demo :}      ";
+    loop {
+        print_message(MESSAGE, &mut lcd, Duration::from_millis(250)).await;
+        print_message(characters::ALL_CHARS, &mut lcd, Duration::from_millis(500)).await;
+    }
+}
+
+async fn print_message(message: &str, lcd: &mut Lcd<'_, LCD>, delay: Duration) {
+    let mut display_buffer = DisplayBuffer::new();
+
+    let mut char_buffer = [' '; 6];
+    for char in message.chars() {
+        char_buffer.copy_within(1.., 0);
+        char_buffer[5] = char;
+
+        display_buffer.clear();
+        for (i, char) in char_buffer.iter().enumerate() {
+            display_buffer.write_char(i, *char);
+        }
+        display_buffer.write(lcd);
+
+        embassy_time::Timer::after(delay).await;
+    }
+}
+
+/// Display layout for the U0-DK
+mod display_layout {
+    // Character layout. There are 6 characters, left-to-right
+    //         T
+    //     ─────────
+    //    │    N    │
+    //    │ │  │  │ │
+    // TL │ └┐ │ ┌┘ │ TR
+    //    │NW│ │ │NE│
+    //    │    │    │
+    //     W─── ───E
+    //    │    │    │
+    //    │SW│ │ │SE│
+    // BL │ ┌┘ │ └┐ │ BR
+    //    │ │  │  │ │
+    //    │    S    │
+    //     ─────────
+    //         B
+
+    pub const CHAR_N_COM: u8 = 3;
+    pub const CHAR_N_SEG: [u8; 6] = [39, 37, 35, 48, 26, 33];
+    pub const CHAR_NW_COM: u8 = 3;
+    pub const CHAR_NW_SEG: [u8; 6] = [49, 38, 36, 34, 27, 24];
+    pub const CHAR_W_COM: u8 = 0;
+    pub const CHAR_W_SEG: [u8; 6] = CHAR_NW_SEG;
+    pub const CHAR_SW_COM: u8 = 2;
+    pub const CHAR_SW_SEG: [u8; 6] = CHAR_NW_SEG;
+    pub const CHAR_S_COM: u8 = 2;
+    pub const CHAR_S_SEG: [u8; 6] = [22, 6, 46, 11, 15, 29];
+    pub const CHAR_SE_COM: u8 = 3;
+    pub const CHAR_SE_SEG: [u8; 6] = CHAR_S_SEG;
+    pub const CHAR_E_COM: u8 = 0;
+    pub const CHAR_E_SEG: [u8; 6] = [23, 45, 47, 14, 28, 32];
+    pub const CHAR_NE_COM: u8 = 2;
+    pub const CHAR_NE_SEG: [u8; 6] = CHAR_N_SEG;
+    pub const CHAR_T_COM: u8 = 1;
+    pub const CHAR_T_SEG: [u8; 6] = CHAR_N_SEG;
+    pub const CHAR_TL_COM: u8 = 1;
+    pub const CHAR_TL_SEG: [u8; 6] = CHAR_NW_SEG;
+    pub const CHAR_BL_COM: u8 = 0;
+    pub const CHAR_BL_SEG: [u8; 6] = CHAR_S_SEG;
+    pub const CHAR_B_COM: u8 = 1;
+    pub const CHAR_B_SEG: [u8; 6] = CHAR_S_SEG;
+    pub const CHAR_BR_COM: u8 = 1;
+    pub const CHAR_BR_SEG: [u8; 6] = CHAR_E_SEG;
+    pub const CHAR_TR_COM: u8 = 0;
+    pub const CHAR_TR_SEG: [u8; 6] = CHAR_N_SEG;
+
+    pub const COLON_COM: u8 = 2;
+    pub const COLON_SEG: [u8; 4] = [23, 45, 47, 14];
+    pub const DOT_COM: u8 = 3;
+    pub const DOT_SEG: [u8; 4] = COLON_SEG;
+    /// COM + SEG, bar from top to bottom
+    pub const BAR: [(u8, u8); 4] = [(2, 28), (3, 28), (2, 32), (3, 32)];
+}
+
+mod characters {
+    use super::CharSegment::{self, *};
+
+    pub const CHAR_0: &[CharSegment] = &[T, TL, BL, B, BR, TR, NW, SE];
+    pub const CHAR_1: &[CharSegment] = &[NE, TR, BR];
+    pub const CHAR_2: &[CharSegment] = &[T, BL, B, TR, E, W];
+    pub const CHAR_3: &[CharSegment] = &[T, B, BR, TR, E];
+    pub const CHAR_4: &[CharSegment] = &[TL, BR, TR, E, W];
+    pub const CHAR_5: &[CharSegment] = &[T, TL, B, BR, E, W];
+    pub const CHAR_6: &[CharSegment] = &[T, TL, BL, B, BR, E, W];
+    pub const CHAR_7: &[CharSegment] = &[T, NE, S];
+    pub const CHAR_8: &[CharSegment] = &[T, TL, BL, B, BR, TR, E, W];
+    pub const CHAR_9: &[CharSegment] = &[T, TL, BR, TR, E, W];
+
+    pub const CHAR_COLON: &[CharSegment] = &[N, S];
+    pub const CHAR_SEMICOLON: &[CharSegment] = &[N, SW];
+    pub const CHAR_EQUALS: &[CharSegment] = &[E, W, B];
+    pub const CHAR_SLASH: &[CharSegment] = &[SW, NE];
+    pub const CHAR_BACKSLASH: &[CharSegment] = &[SE, NW];
+    pub const CHAR_PLUS: &[CharSegment] = &[N, E, S, W];
+    pub const CHAR_STAR: &[CharSegment] = &[NE, N, NW, SE, S, SW];
+    pub const CHAR_QUOTE: &[CharSegment] = &[N];
+    pub const CHAR_BACKTICK: &[CharSegment] = &[NW];
+    pub const CHAR_DASH: &[CharSegment] = &[W, E];
+    pub const CHAR_COMMA: &[CharSegment] = &[SW];
+    pub const CHAR_DOT: &[CharSegment] = &[S];
+    pub const CHAR_CURLYOPEN: &[CharSegment] = &[T, NW, W, SW, B];
+    pub const CHAR_CURLYCLOSE: &[CharSegment] = &[T, NE, E, SE, B];
+    pub const CHAR_AMPERSAND: &[CharSegment] = &[T, NE, NW, W, BL, B, SE];
+
+    pub const CHAR_A: &[CharSegment] = &[T, TL, TR, E, W, BL, BR];
+    pub const CHAR_B: &[CharSegment] = &[T, TR, BR, B, N, S, E];
+    pub const CHAR_C: &[CharSegment] = &[T, TL, BL, B];
+    pub const CHAR_D: &[CharSegment] = &[T, TR, BR, B, N, S];
+    pub const CHAR_E: &[CharSegment] = &[T, TL, BL, B, W];
+    pub const CHAR_F: &[CharSegment] = &[T, TL, BL, W];
+    pub const CHAR_G: &[CharSegment] = &[T, TL, BL, B, BR, E];
+    pub const CHAR_H: &[CharSegment] = &[TL, BL, E, W, TR, BR];
+    pub const CHAR_I: &[CharSegment] = &[T, N, S, B];
+    pub const CHAR_J: &[CharSegment] = &[TR, BR, B, BL];
+    pub const CHAR_K: &[CharSegment] = &[TL, BL, W, NE, SE];
+    pub const CHAR_L: &[CharSegment] = &[TL, BL, B];
+    pub const CHAR_M: &[CharSegment] = &[BL, TL, NW, NE, TR, BR];
+    pub const CHAR_N: &[CharSegment] = &[BL, TL, NW, SE, BR, TR];
+    pub const CHAR_O: &[CharSegment] = &[T, TL, BL, B, BR, TR];
+    pub const CHAR_P: &[CharSegment] = &[BL, TL, T, TR, E, W];
+    pub const CHAR_Q: &[CharSegment] = &[T, TL, BL, B, BR, TR, SE];
+    pub const CHAR_R: &[CharSegment] = &[BL, TL, T, TR, E, W, SE];
+    pub const CHAR_S: &[CharSegment] = &[T, NW, E, BR, B];
+    pub const CHAR_T: &[CharSegment] = &[T, N, S];
+    pub const CHAR_U: &[CharSegment] = &[TL, BL, B, BR, TR];
+    pub const CHAR_V: &[CharSegment] = &[TL, BL, SW, NE];
+    pub const CHAR_W: &[CharSegment] = &[TL, BL, SW, SE, BR, TR];
+    pub const CHAR_X: &[CharSegment] = &[NE, NW, SE, SW];
+    pub const CHAR_Y: &[CharSegment] = &[NE, NW, S];
+    pub const CHAR_Z: &[CharSegment] = &[T, NE, SW, B];
+
+    pub const CHAR_UNKNOWN: &[CharSegment] = &[N, NW, W, SW, S, SE, E, NE, T, TL, BL, B, BR, TR];
+
+    pub const ALL_CHARS: &str =
+        "0 1 2 3 4 5 6 7 8 9 : ; = / \\ + * ' ` - , . { } & A B C D E F G H I J K L M N O P Q R S T U V W X Y Z � ";
+
+    pub fn get_char_segments(val: char) -> &'static [CharSegment] {
+        match val {
+            val if val.is_whitespace() => &[],
+
+            '0' => CHAR_0,
+            '1' => CHAR_1,
+            '2' => CHAR_2,
+            '3' => CHAR_3,
+            '4' => CHAR_4,
+            '5' => CHAR_5,
+            '6' => CHAR_6,
+            '7' => CHAR_7,
+            '8' => CHAR_8,
+            '9' => CHAR_9,
+
+            ':' => CHAR_COLON,
+            ';' => CHAR_SEMICOLON,
+            '=' => CHAR_EQUALS,
+            '/' => CHAR_SLASH,
+            '\\' => CHAR_BACKSLASH,
+            '+' => CHAR_PLUS,
+            '*' => CHAR_STAR,
+            '\'' => CHAR_QUOTE,
+            '`' => CHAR_BACKTICK,
+            '-' => CHAR_DASH,
+            ',' => CHAR_COMMA,
+            '.' => CHAR_DOT,
+            '{' => CHAR_CURLYOPEN,
+            '}' => CHAR_CURLYCLOSE,
+            '&' => CHAR_AMPERSAND,
+
+            'A' | 'a' => CHAR_A,
+            'B' | 'b' => CHAR_B,
+            'C' | 'c' => CHAR_C,
+            'D' | 'd' => CHAR_D,
+            'E' | 'e' => CHAR_E,
+            'F' | 'f' => CHAR_F,
+            'G' | 'g' => CHAR_G,
+            'H' | 'h' => CHAR_H,
+            'I' | 'i' => CHAR_I,
+            'J' | 'j' => CHAR_J,
+            'K' | 'k' => CHAR_K,
+            'L' | 'l' => CHAR_L,
+            'M' | 'm' => CHAR_M,
+            'N' | 'n' => CHAR_N,
+            'O' | 'o' => CHAR_O,
+            'P' | 'p' => CHAR_P,
+            'Q' | 'q' => CHAR_Q,
+            'R' | 'r' => CHAR_R,
+            'S' | 's' => CHAR_S,
+            'T' | 't' => CHAR_T,
+            'U' | 'u' => CHAR_U,
+            'V' | 'v' => CHAR_V,
+            'W' | 'w' => CHAR_W,
+            'X' | 'x' => CHAR_X,
+            'Y' | 'y' => CHAR_Y,
+            'Z' | 'z' => CHAR_Z,
+
+            _ => CHAR_UNKNOWN,
+        }
+    }
+}
+
+pub struct DisplayBuffer {
+    pixels: [u64; 4],
+}
+
+impl DisplayBuffer {
+    pub const fn new() -> Self {
+        Self { pixels: [0; 4] }
+    }
+
+    pub fn clear(&mut self) {
+        *self = Self::new();
+    }
+
+    fn write_char_segment(&mut self, index: usize, value: CharSegment) {
+        defmt::assert!(index < 6);
+        let (com, segments) = value.get_com_seg();
+        self.pixels[com as usize] |= 1 << segments[index];
+    }
+
+    pub fn write_char(&mut self, index: usize, val: char) {
+        let segments = characters::get_char_segments(val);
+
+        for segment in segments {
+            self.write_char_segment(index, *segment);
+        }
+    }
+
+    pub fn write(&self, lcd: &mut Lcd<'_, LCD>) {
+        lcd.write_com_segments(0, self.pixels[0]);
+        lcd.write_com_segments(1, self.pixels[1]);
+        lcd.write_com_segments(2, self.pixels[2]);
+        lcd.write_com_segments(3, self.pixels[3]);
+        lcd.submit_frame();
+    }
+
+    pub fn write_colon(&mut self, index: usize) {
+        defmt::assert!(index < 4);
+        self.pixels[display_layout::COLON_COM as usize] |= 1 << display_layout::COLON_SEG[index];
+    }
+
+    pub fn write_dot(&mut self, index: usize) {
+        defmt::assert!(index < 4);
+        self.pixels[display_layout::DOT_COM as usize] |= 1 << display_layout::DOT_SEG[index];
+    }
+
+    pub fn write_bar(&mut self, index: usize) {
+        defmt::assert!(index < 4);
+        let (bar_com, bar_seg) = display_layout::BAR[index];
+        self.pixels[bar_com as usize] |= 1 << bar_seg;
+    }
+}
+
+impl Default for DisplayBuffer {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+#[derive(Debug, Clone, Copy)]
+enum CharSegment {
+    /// North
+    N,
+    /// North west
+    NW,
+    /// West
+    W,
+    /// South west
+    SW,
+    /// South
+    S,
+    /// South East
+    SE,
+    /// East
+    E,
+    /// North East
+    NE,
+    /// Top
+    T,
+    /// Top left
+    TL,
+    /// Bottom left
+    BL,
+    /// Bottom
+    B,
+    /// Bottom right
+    BR,
+    /// Top right
+    TR,
+}
+
+impl CharSegment {
+    fn get_com_seg(&self) -> (u8, [u8; 6]) {
+        match self {
+            CharSegment::N => (display_layout::CHAR_N_COM, display_layout::CHAR_N_SEG),
+            CharSegment::NW => (display_layout::CHAR_NW_COM, display_layout::CHAR_NW_SEG),
+            CharSegment::W => (display_layout::CHAR_W_COM, display_layout::CHAR_W_SEG),
+            CharSegment::SW => (display_layout::CHAR_SW_COM, display_layout::CHAR_SW_SEG),
+            CharSegment::S => (display_layout::CHAR_S_COM, display_layout::CHAR_S_SEG),
+            CharSegment::SE => (display_layout::CHAR_SE_COM, display_layout::CHAR_SE_SEG),
+            CharSegment::E => (display_layout::CHAR_E_COM, display_layout::CHAR_E_SEG),
+            CharSegment::NE => (display_layout::CHAR_NE_COM, display_layout::CHAR_NE_SEG),
+            CharSegment::T => (display_layout::CHAR_T_COM, display_layout::CHAR_T_SEG),
+            CharSegment::TL => (display_layout::CHAR_TL_COM, display_layout::CHAR_TL_SEG),
+            CharSegment::BL => (display_layout::CHAR_BL_COM, display_layout::CHAR_BL_SEG),
+            CharSegment::B => (display_layout::CHAR_B_COM, display_layout::CHAR_B_SEG),
+            CharSegment::BR => (display_layout::CHAR_BR_COM, display_layout::CHAR_BR_SEG),
+            CharSegment::TR => (display_layout::CHAR_TR_COM, display_layout::CHAR_TR_SEG),
+        }
+    }
+}
diff --git a/examples/stm32u5/src/bin/adc.rs b/examples/stm32u5/src/bin/adc.rs
index 99944f7c7..4d2d93aa2 100644
--- a/examples/stm32u5/src/bin/adc.rs
+++ b/examples/stm32u5/src/bin/adc.rs
@@ -2,7 +2,7 @@
 #![no_main]
 
 use defmt::*;
-use embassy_stm32::adc::{self, AdcChannel, SampleTime, adc4};
+use embassy_stm32::adc::{self, Adc, AdcChannel, AdcConfig, SampleTime, adc4};
 use {defmt_rtt as _, panic_probe as _};
 
 #[embassy_executor::main]
@@ -12,27 +12,29 @@ async fn main(_spawner: embassy_executor::Spawner) {
     let mut p = embassy_stm32::init(config);
 
     // **** ADC1 init ****
-    let mut adc1 = adc::Adc::new(p.ADC1);
+    let mut config = AdcConfig::default();
+    config.averaging = Some(adc::Averaging::Samples1024);
+    config.resolution = Some(adc::Resolution::BITS14);
+    let mut adc1 = Adc::new_with_config(p.ADC1, config);
     let mut adc1_pin1 = p.PA3; // A0 on nucleo u5a5
     let mut adc1_pin2 = p.PA2; // A1
-    adc1.set_resolution(adc::Resolution::BITS14);
-    adc1.set_averaging(adc::Averaging::Samples1024);
     let max1 = adc::resolution_to_max_count(adc::Resolution::BITS14);
 
     // **** ADC2 init ****
-    let mut adc2 = adc::Adc::new(p.ADC2);
+    let mut config = AdcConfig::default();
+    config.averaging = Some(adc::Averaging::Samples1024);
+    config.resolution = Some(adc::Resolution::BITS14);
+    let mut adc2 = Adc::new_with_config(p.ADC2, config);
     let mut adc2_pin1 = p.PC3; // A2
     let mut adc2_pin2 = p.PB0; // A3
-    adc2.set_resolution(adc::Resolution::BITS14);
-    adc2.set_averaging(adc::Averaging::Samples1024);
     let max2 = adc::resolution_to_max_count(adc::Resolution::BITS14);
 
     // **** ADC4 init ****
-    let mut adc4 = adc4::Adc4::new(p.ADC4);
-    let mut adc4_pin1 = p.PC1; // A4
+    let mut adc4 = Adc::new_adc4(p.ADC4);
+    let mut adc4_pin1 = p.PC1.degrade_adc(); // A4
     let mut adc4_pin2 = p.PC0; // A5
-    adc4.set_resolution(adc4::Resolution::BITS12);
-    adc4.set_averaging(adc4::Averaging::Samples256);
+    adc4.set_resolution_adc4(adc4::Resolution::BITS12);
+    adc4.set_averaging_adc4(adc4::Averaging::Samples256);
     let max4 = adc4::resolution_to_max_count(adc4::Resolution::BITS12);
 
     // **** ADC1 blocking read ****
@@ -93,11 +95,14 @@ async fn main(_spawner: embassy_executor::Spawner) {
     // The channels must be in ascending order and can't repeat for ADC4
     adc4.read(
         p.GPDMA1_CH1.reborrow(),
-        [&mut degraded42, &mut degraded41].into_iter(),
+        [
+            (&mut degraded42, adc4::SampleTime::CYCLES1_5),
+            (&mut degraded41, adc4::SampleTime::CYCLES1_5),
+        ]
+        .into_iter(),
         &mut measurements,
     )
-    .await
-    .unwrap();
+    .await;
     let volt2: f32 = 3.3 * measurements[0] as f32 / max4 as f32;
     let volt1: f32 = 3.3 * measurements[1] as f32 / max4 as f32;
     info!("Async read 4 pin 1 {}", volt1);
diff --git a/examples/stm32wb/Cargo.toml b/examples/stm32wb/Cargo.toml
index 783690c11..83119e3a0 100644
--- a/examples/stm32wb/Cargo.toml
+++ b/examples/stm32wb/Cargo.toml
@@ -7,7 +7,7 @@ publish = false
 
 [dependencies]
 # Change stm32wb55rg to your chip name in both dependencies, if necessary.
-embassy-stm32 = { version = "0.4.0", path = "../../embassy-stm32", features = [ "defmt", "stm32wb55rg", "time-driver-any", "memory-x", "exti"]  }
+embassy-stm32 = { version = "0.4.0", path = "../../embassy-stm32", features = [ "defmt", "stm32wb55rg", "time-driver-any", "memory-x", "exti", "low-power"]  }
 embassy-stm32-wpan = { version = "0.1.0", path = "../../embassy-stm32-wpan", features = ["defmt", "stm32wb55rg"] }
 embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
diff --git a/examples/stm32wb/src/bin/button_exti.rs b/examples/stm32wb/src/bin/button_exti.rs
index 2871fd55f..3c58eb556 100644
--- a/examples/stm32wb/src/bin/button_exti.rs
+++ b/examples/stm32wb/src/bin/button_exti.rs
@@ -3,16 +3,22 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::gpio::Pull;
+use embassy_stm32::{bind_interrupts, interrupt};
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI4 => exti::InterruptHandler<interrupt::typelevel::EXTI4>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Hello World!");
 
-    let mut button = ExtiInput::new(p.PC4, p.EXTI4, Pull::Up);
+    let mut button = ExtiInput::new(p.PC4, p.EXTI4, Pull::Up, Irqs);
 
     info!("Press the USER button...");
 
diff --git a/examples/stm32wb/src/bin/eddystone_beacon.rs b/examples/stm32wb/src/bin/eddystone_beacon.rs
index f309ca3a2..413b1ac8f 100644
--- a/examples/stm32wb/src/bin/eddystone_beacon.rs
+++ b/examples/stm32wb/src/bin/eddystone_beacon.rs
@@ -57,126 +57,112 @@ async fn main(_spawner: Spawner) {
     info!("Hello World!");
 
     let config = Config::default();
-    let mut mbox = TlMbox::init(p.IPCC, Irqs, config);
+    let mbox = TlMbox::init(p.IPCC, Irqs, config).await;
+    let mut sys = mbox.sys_subsystem;
+    let mut ble = mbox.ble_subsystem;
 
-    let sys_event = mbox.sys_subsystem.read().await;
-    info!("sys event: {}", sys_event.payload());
-
-    let _ = mbox.sys_subsystem.shci_c2_ble_init(Default::default()).await;
+    let _ = sys.shci_c2_ble_init(Default::default()).await;
 
     info!("resetting BLE...");
-    mbox.ble_subsystem.reset().await;
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    ble.reset().await;
+    let response = ble.read().await.unwrap();
     defmt::info!("{}", response);
 
     info!("config public address...");
-    mbox.ble_subsystem
-        .write_config_data(&ConfigData::public_address(get_bd_addr()).build())
+    ble.write_config_data(&ConfigData::public_address(get_bd_addr()).build())
         .await;
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    let response = ble.read().await.unwrap();
     defmt::info!("{}", response);
 
     info!("config random address...");
-    mbox.ble_subsystem
-        .write_config_data(&ConfigData::random_address(get_random_addr()).build())
+    ble.write_config_data(&ConfigData::random_address(get_random_addr()).build())
         .await;
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    let response = ble.read().await.unwrap();
     defmt::info!("{}", response);
 
     info!("config identity root...");
-    mbox.ble_subsystem
-        .write_config_data(&ConfigData::identity_root(&get_irk()).build())
+    ble.write_config_data(&ConfigData::identity_root(&get_irk()).build())
         .await;
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    let response = ble.read().await.unwrap();
     defmt::info!("{}", response);
 
     info!("config encryption root...");
-    mbox.ble_subsystem
-        .write_config_data(&ConfigData::encryption_root(&get_erk()).build())
+    ble.write_config_data(&ConfigData::encryption_root(&get_erk()).build())
         .await;
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    let response = ble.read().await.unwrap();
     defmt::info!("{}", response);
 
     info!("config tx power level...");
-    mbox.ble_subsystem.set_tx_power_level(PowerLevel::ZerodBm).await;
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    ble.set_tx_power_level(PowerLevel::ZerodBm).await;
+    let response = ble.read().await.unwrap();
     defmt::info!("{}", response);
 
     info!("GATT init...");
-    mbox.ble_subsystem.init_gatt().await;
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    ble.init_gatt().await;
+    let response = ble.read().await.unwrap();
     defmt::info!("{}", response);
 
     info!("GAP init...");
-    mbox.ble_subsystem
-        .init_gap(Role::PERIPHERAL, false, BLE_GAP_DEVICE_NAME_LENGTH)
-        .await;
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    ble.init_gap(Role::PERIPHERAL, false, BLE_GAP_DEVICE_NAME_LENGTH).await;
+    let response = ble.read().await.unwrap();
     defmt::info!("{}", response);
 
     // info!("set scan response...");
-    // mbox.ble_subsystem.le_set_scan_response_data(&[]).await.unwrap();
-    // let response = mbox.ble_subsystem.read().await.unwrap();
+    // ble.le_set_scan_response_data(&[]).await.unwrap();
+    // let response = ble.read().await.unwrap();
     // defmt::info!("{}", response);
 
     info!("set discoverable...");
-    mbox.ble_subsystem
-        .set_discoverable(&DiscoverableParameters {
-            advertising_type: AdvertisingType::NonConnectableUndirected,
-            advertising_interval: Some((Duration::from_millis(250), Duration::from_millis(250))),
-            address_type: OwnAddressType::Public,
-            filter_policy: AdvertisingFilterPolicy::AllowConnectionAndScan,
-            local_name: None,
-            advertising_data: &[],
-            conn_interval: (None, None),
-        })
-        .await
-        .unwrap();
-
-    let response = mbox.ble_subsystem.read().await;
+    ble.set_discoverable(&DiscoverableParameters {
+        advertising_type: AdvertisingType::NonConnectableUndirected,
+        advertising_interval: Some((Duration::from_millis(250), Duration::from_millis(250))),
+        address_type: OwnAddressType::Public,
+        filter_policy: AdvertisingFilterPolicy::AllowConnectionAndScan,
+        local_name: None,
+        advertising_data: &[],
+        conn_interval: (None, None),
+    })
+    .await
+    .unwrap();
+
+    let response = ble.read().await;
     defmt::info!("{}", response);
 
     // remove some advertisement to decrease the packet size
     info!("delete tx power ad type...");
-    mbox.ble_subsystem
-        .delete_ad_type(AdvertisingDataType::TxPowerLevel)
-        .await;
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    ble.delete_ad_type(AdvertisingDataType::TxPowerLevel).await;
+    let response = ble.read().await.unwrap();
     defmt::info!("{}", response);
 
     info!("delete conn interval ad type...");
-    mbox.ble_subsystem
-        .delete_ad_type(AdvertisingDataType::PeripheralConnectionInterval)
+    ble.delete_ad_type(AdvertisingDataType::PeripheralConnectionInterval)
         .await;
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    let response = ble.read().await.unwrap();
     defmt::info!("{}", response);
 
     info!("update advertising data...");
-    mbox.ble_subsystem
-        .update_advertising_data(&eddystone_advertising_data())
+    ble.update_advertising_data(&eddystone_advertising_data())
         .await
         .unwrap();
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    let response = ble.read().await.unwrap();
     defmt::info!("{}", response);
 
     info!("update advertising data type...");
-    mbox.ble_subsystem
-        .update_advertising_data(&[3, AdvertisingDataType::UuidCompleteList16 as u8, 0xaa, 0xfe])
+    ble.update_advertising_data(&[3, AdvertisingDataType::UuidCompleteList16 as u8, 0xaa, 0xfe])
         .await
         .unwrap();
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    let response = ble.read().await.unwrap();
     defmt::info!("{}", response);
 
     info!("update advertising data flags...");
-    mbox.ble_subsystem
-        .update_advertising_data(&[
-            2,
-            AdvertisingDataType::Flags as u8,
-            (0x02 | 0x04) as u8, // BLE general discoverable, without BR/EDR support
-        ])
-        .await
-        .unwrap();
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    ble.update_advertising_data(&[
+        2,
+        AdvertisingDataType::Flags as u8,
+        (0x02 | 0x04) as u8, // BLE general discoverable, without BR/EDR support
+    ])
+    .await
+    .unwrap();
+    let response = ble.read().await.unwrap();
     defmt::info!("{}", response);
 
     cortex_m::asm::wfi();
diff --git a/examples/stm32wb/src/bin/gatt_server.rs b/examples/stm32wb/src/bin/gatt_server.rs
index 2ed257566..3484f1844 100644
--- a/examples/stm32wb/src/bin/gatt_server.rs
+++ b/examples/stm32wb/src/bin/gatt_server.rs
@@ -69,92 +69,85 @@ async fn main(spawner: Spawner) {
     info!("Hello World!");
 
     let config = Config::default();
-    let mut mbox = TlMbox::init(p.IPCC, Irqs, config);
+    let mbox = TlMbox::init(p.IPCC, Irqs, config).await;
+    let mut sys = mbox.sys_subsystem;
+    let mut ble = mbox.ble_subsystem;
 
     spawner.spawn(run_mm_queue(mbox.mm_subsystem).unwrap());
-    let sys_event = mbox.sys_subsystem.read().await;
-    info!("sys event: {}", sys_event.payload());
 
-    let _ = mbox.sys_subsystem.shci_c2_ble_init(Default::default()).await;
+    let _ = sys.shci_c2_ble_init(Default::default()).await;
 
     info!("resetting BLE...");
-    mbox.ble_subsystem.reset().await;
-    let response = mbox.ble_subsystem.read().await;
+    ble.reset().await;
+    let response = ble.read().await;
     defmt::debug!("{}", response);
 
     info!("config public address...");
-    mbox.ble_subsystem
-        .write_config_data(&ConfigData::public_address(get_bd_addr()).build())
+    ble.write_config_data(&ConfigData::public_address(get_bd_addr()).build())
         .await;
-    let response = mbox.ble_subsystem.read().await;
+    let response = ble.read().await;
     defmt::debug!("{}", response);
 
     info!("config random address...");
-    mbox.ble_subsystem
-        .write_config_data(&ConfigData::random_address(get_random_addr()).build())
+    ble.write_config_data(&ConfigData::random_address(get_random_addr()).build())
         .await;
-    let response = mbox.ble_subsystem.read().await;
+    let response = ble.read().await;
     defmt::debug!("{}", response);
 
     info!("config identity root...");
-    mbox.ble_subsystem
-        .write_config_data(&ConfigData::identity_root(&get_irk()).build())
+    ble.write_config_data(&ConfigData::identity_root(&get_irk()).build())
         .await;
-    let response = mbox.ble_subsystem.read().await;
+    let response = ble.read().await;
     defmt::debug!("{}", response);
 
     info!("config encryption root...");
-    mbox.ble_subsystem
-        .write_config_data(&ConfigData::encryption_root(&get_erk()).build())
+    ble.write_config_data(&ConfigData::encryption_root(&get_erk()).build())
         .await;
-    let response = mbox.ble_subsystem.read().await;
+    let response = ble.read().await;
     defmt::debug!("{}", response);
 
     info!("config tx power level...");
-    mbox.ble_subsystem.set_tx_power_level(PowerLevel::ZerodBm).await;
-    let response = mbox.ble_subsystem.read().await;
+    ble.set_tx_power_level(PowerLevel::ZerodBm).await;
+    let response = ble.read().await;
     defmt::debug!("{}", response);
 
     info!("GATT init...");
-    mbox.ble_subsystem.init_gatt().await;
-    let response = mbox.ble_subsystem.read().await;
+    ble.init_gatt().await;
+    let response = ble.read().await;
     defmt::debug!("{}", response);
 
     info!("GAP init...");
-    mbox.ble_subsystem
-        .init_gap(Role::PERIPHERAL, false, BLE_GAP_DEVICE_NAME_LENGTH)
-        .await;
-    let response = mbox.ble_subsystem.read().await;
+    ble.init_gap(Role::PERIPHERAL, false, BLE_GAP_DEVICE_NAME_LENGTH).await;
+    let response = ble.read().await;
     defmt::debug!("{}", response);
 
     info!("set IO capabilities...");
-    mbox.ble_subsystem.set_io_capability(IoCapability::DisplayConfirm).await;
-    let response = mbox.ble_subsystem.read().await;
+    ble.set_io_capability(IoCapability::DisplayConfirm).await;
+    let response = ble.read().await;
     defmt::debug!("{}", response);
 
     info!("set authentication requirements...");
-    mbox.ble_subsystem
-        .set_authentication_requirement(&AuthenticationRequirements {
-            bonding_required: false,
-            keypress_notification_support: false,
-            mitm_protection_required: false,
-            encryption_key_size_range: (8, 16),
-            fixed_pin: Pin::Requested,
-            identity_address_type: AddressType::Public,
-            secure_connection_support: SecureConnectionSupport::Optional,
-        })
-        .await
-        .unwrap();
-    let response = mbox.ble_subsystem.read().await;
+    ble.set_authentication_requirement(&AuthenticationRequirements {
+        bonding_required: false,
+        keypress_notification_support: false,
+        mitm_protection_required: false,
+        encryption_key_size_range: (8, 16),
+        fixed_pin: Pin::Requested,
+        identity_address_type: AddressType::Public,
+        secure_connection_support: SecureConnectionSupport::Optional,
+    })
+    .await
+    .unwrap();
+    let response = ble.read().await;
     defmt::debug!("{}", response);
 
     info!("set scan response data...");
-    mbox.ble_subsystem.le_set_scan_response_data(b"TXTX").await.unwrap();
-    let response = mbox.ble_subsystem.read().await;
+    ble.le_set_scan_response_data(b"TXTX").await.unwrap();
+    let response = ble.read().await;
     defmt::debug!("{}", response);
 
     defmt::info!("initializing services and characteristics...");
-    let mut ble_context = init_gatt_services(&mut mbox.ble_subsystem).await.unwrap();
+    let mut ble_context = init_gatt_services(&mut ble).await.unwrap();
     defmt::info!("{}", ble_context);
 
     let discovery_params = DiscoverableParameters {
@@ -168,12 +161,12 @@ async fn main(spawner: Spawner) {
     };
 
     info!("set discoverable...");
-    mbox.ble_subsystem.set_discoverable(&discovery_params).await.unwrap();
-    let response = mbox.ble_subsystem.read().await;
+    ble.set_discoverable(&discovery_params).await.unwrap();
+    let response = ble.read().await;
     defmt::debug!("{}", response);
 
     loop {
-        let response = mbox.ble_subsystem.read().await;
+        let response = ble.read().await;
         defmt::debug!("{}", response);
 
         if let Ok(Packet::Event(event)) = response {
@@ -184,24 +177,23 @@ async fn main(spawner: Spawner) {
                 Event::DisconnectionComplete(_) => {
                     defmt::info!("disconnected");
                     ble_context.is_subscribed = false;
-                    mbox.ble_subsystem.set_discoverable(&discovery_params).await.unwrap();
+                    ble.set_discoverable(&discovery_params).await.unwrap();
                 }
                 Event::Vendor(vendor_event) => match vendor_event {
                     VendorEvent::AttReadPermitRequest(read_req) => {
                         defmt::info!("read request received {}, allowing", read_req);
-                        mbox.ble_subsystem.allow_read(read_req.conn_handle).await
+                        ble.allow_read(read_req.conn_handle).await
                     }
                     VendorEvent::AttWritePermitRequest(write_req) => {
                         defmt::info!("write request received {}, allowing", write_req);
-                        mbox.ble_subsystem
-                            .write_response(&WriteResponseParameters {
-                                conn_handle: write_req.conn_handle,
-                                attribute_handle: write_req.attribute_handle,
-                                status: Ok(()),
-                                value: write_req.value(),
-                            })
-                            .await
-                            .unwrap()
+                        ble.write_response(&WriteResponseParameters {
+                            conn_handle: write_req.conn_handle,
+                            attribute_handle: write_req.attribute_handle,
+                            status: Ok(()),
+                            value: write_req.value(),
+                        })
+                        .await
+                        .unwrap()
                     }
                     VendorEvent::GattAttributeModified(attribute) => {
                         defmt::info!("{}", ble_context);
@@ -224,7 +216,7 @@ async fn main(spawner: Spawner) {
 }
 
 #[embassy_executor::task]
-async fn run_mm_queue(memory_manager: mm::MemoryManager) {
+async fn run_mm_queue(mut memory_manager: mm::MemoryManager<'static>) {
     memory_manager.run_queue().await;
 }
 
@@ -285,7 +277,7 @@ pub struct CharHandles {
     pub notify: AttributeHandle,
 }
 
-pub async fn init_gatt_services(ble_subsystem: &mut Ble) -> Result<BleContext, ()> {
+pub async fn init_gatt_services<'a>(ble_subsystem: &mut Ble<'a>) -> Result<BleContext, ()> {
     let service_handle = gatt_add_service(ble_subsystem, Uuid::Uuid16(0x500)).await?;
 
     let read = gatt_add_char(
@@ -322,7 +314,7 @@ pub async fn init_gatt_services(ble_subsystem: &mut Ble) -> Result<BleContext, (
     })
 }
 
-async fn gatt_add_service(ble_subsystem: &mut Ble, uuid: Uuid) -> Result<AttributeHandle, ()> {
+async fn gatt_add_service<'a>(ble_subsystem: &mut Ble<'a>, uuid: Uuid) -> Result<AttributeHandle, ()> {
     ble_subsystem
         .add_service(&AddServiceParameters {
             uuid,
@@ -348,8 +340,8 @@ async fn gatt_add_service(ble_subsystem: &mut Ble, uuid: Uuid) -> Result<Attribu
     }
 }
 
-async fn gatt_add_char(
-    ble_subsystem: &mut Ble,
+async fn gatt_add_char<'a>(
+    ble_subsystem: &mut Ble<'a>,
     service_handle: AttributeHandle,
     characteristic_uuid: Uuid,
     characteristic_properties: CharacteristicProperty,
diff --git a/examples/stm32wb/src/bin/mac_ffd.rs b/examples/stm32wb/src/bin/mac_ffd.rs
index 18a52e162..4bab6ea9f 100644
--- a/examples/stm32wb/src/bin/mac_ffd.rs
+++ b/examples/stm32wb/src/bin/mac_ffd.rs
@@ -19,7 +19,7 @@ bind_interrupts!(struct Irqs{
 });
 
 #[embassy_executor::task]
-async fn run_mm_queue(memory_manager: mm::MemoryManager) {
+async fn run_mm_queue(mut memory_manager: mm::MemoryManager<'static>) {
     memory_manager.run_queue().await;
 }
 
@@ -54,74 +54,72 @@ async fn main(spawner: Spawner) {
     info!("Hello World!");
 
     let config = Config::default();
-    let mbox = TlMbox::init(p.IPCC, Irqs, config);
+    let mbox = TlMbox::init(p.IPCC, Irqs, config).await;
+    let mut sys = mbox.sys_subsystem;
 
     spawner.spawn(run_mm_queue(mbox.mm_subsystem).unwrap());
 
-    let sys_event = mbox.sys_subsystem.read().await;
-    info!("sys event: {}", sys_event.payload());
-
-    core::mem::drop(sys_event);
-
-    let result = mbox.sys_subsystem.shci_c2_mac_802_15_4_init().await;
+    let result = sys.shci_c2_mac_802_15_4_init().await;
     info!("initialized mac: {}", result);
 
+    let (mut mac_rx, mut mac_tx) = mbox.mac_subsystem.split();
+
     info!("resetting");
-    mbox.mac_subsystem
+    mac_tx
         .send_command(&ResetRequest {
             set_default_pib: true,
             ..Default::default()
         })
         .await
         .unwrap();
-    defmt::info!("{:#x}", mbox.mac_subsystem.read().await.unwrap());
+    defmt::info!("{:#x}", mac_rx.read().await.unwrap());
 
     info!("setting extended address");
     let extended_address: u64 = 0xACDE480000000001;
-    mbox.mac_subsystem
+    mac_tx
         .send_command(&SetRequest {
             pib_attribute_ptr: &extended_address as *const _ as *const u8,
             pib_attribute: PibId::ExtendedAddress,
         })
         .await
         .unwrap();
-    defmt::info!("{:#x}", mbox.mac_subsystem.read().await.unwrap());
+    defmt::info!("{:#x}", mac_rx.read().await.unwrap());
 
     info!("setting short address");
     let short_address: u16 = 0x1122;
-    mbox.mac_subsystem
+    mac_tx
         .send_command(&SetRequest {
             pib_attribute_ptr: &short_address as *const _ as *const u8,
             pib_attribute: PibId::ShortAddress,
         })
         .await
         .unwrap();
-    defmt::info!("{:#x}", mbox.mac_subsystem.read().await.unwrap());
+    defmt::info!("{:#x}", mac_rx.read().await.unwrap());
 
     info!("setting association permit");
     let association_permit: bool = true;
-    mbox.mac_subsystem
+    mac_tx
         .send_command(&SetRequest {
             pib_attribute_ptr: &association_permit as *const _ as *const u8,
             pib_attribute: PibId::AssociationPermit,
         })
         .await
         .unwrap();
-    defmt::info!("{:#x}", mbox.mac_subsystem.read().await.unwrap());
+    defmt::info!("{:#x}", mac_rx.read().await.unwrap());
 
     info!("setting TX power");
     let transmit_power: i8 = 2;
-    mbox.mac_subsystem
+    mac_tx
         .send_command(&SetRequest {
             pib_attribute_ptr: &transmit_power as *const _ as *const u8,
             pib_attribute: PibId::TransmitPower,
         })
         .await
         .unwrap();
-    defmt::info!("{:#x}", mbox.mac_subsystem.read().await.unwrap());
+    defmt::info!("{:#x}", mac_rx.read().await.unwrap());
 
     info!("starting FFD device");
-    mbox.mac_subsystem
+    mac_tx
         .send_command(&StartRequest {
             pan_id: PanId([0x1A, 0xAA]),
             channel_number: MacChannel::Channel16,
@@ -133,28 +131,27 @@ async fn main(spawner: Spawner) {
         })
         .await
         .unwrap();
-    defmt::info!("{:#x}", mbox.mac_subsystem.read().await.unwrap());
+    defmt::info!("{:#x}", mac_rx.read().await.unwrap());
 
     info!("setting RX on when idle");
     let rx_on_while_idle: bool = true;
-    mbox.mac_subsystem
+    mac_tx
         .send_command(&SetRequest {
             pib_attribute_ptr: &rx_on_while_idle as *const _ as *const u8,
             pib_attribute: PibId::RxOnWhenIdle,
         })
         .await
         .unwrap();
-    defmt::info!("{:#x}", mbox.mac_subsystem.read().await.unwrap());
+    defmt::info!("{:#x}", mac_rx.read().await.unwrap());
 
     loop {
-        let evt = mbox.mac_subsystem.read().await;
+        let evt = mac_rx.read().await;
         if let Ok(evt) = evt {
             defmt::info!("parsed mac event");
             defmt::info!("{:#x}", evt);
 
             match evt {
-                MacEvent::MlmeAssociateInd(association) => mbox
-                    .mac_subsystem
+                MacEvent::MlmeAssociateInd(association) => mac_tx
                     .send_command(&AssociateResponse {
                         device_address: association.device_address,
                         assoc_short_address: [0x33, 0x44],
diff --git a/examples/stm32wb/src/bin/mac_ffd_net.rs b/examples/stm32wb/src/bin/mac_ffd_net.rs
index 5296943a1..b4789e3ee 100644
--- a/examples/stm32wb/src/bin/mac_ffd_net.rs
+++ b/examples/stm32wb/src/bin/mac_ffd_net.rs
@@ -1,32 +1,44 @@
 #![no_std]
 #![no_main]
 
+use core::net::Ipv6Addr;
+
 use defmt::*;
 use embassy_executor::Spawner;
+use embassy_net::udp::{PacketMetadata, UdpSocket};
+use embassy_net::{Ipv6Cidr, StackResources, StaticConfigV6};
 use embassy_stm32::bind_interrupts;
 use embassy_stm32::ipcc::{Config, ReceiveInterruptHandler, TransmitInterruptHandler};
+use embassy_stm32::peripherals::RNG;
 use embassy_stm32::rcc::WPAN_DEFAULT;
+use embassy_stm32::rng::InterruptHandler as RngInterruptHandler;
 use embassy_stm32_wpan::TlMbox;
-use embassy_stm32_wpan::mac::commands::{ResetRequest, SetRequest, StartRequest};
-use embassy_stm32_wpan::mac::typedefs::{MacChannel, PanId, PibId};
-use embassy_stm32_wpan::mac::{self, Runner};
+use embassy_stm32_wpan::mac::{Driver, DriverState, Runner};
 use embassy_stm32_wpan::sub::mm;
+use embassy_time::{Duration, Timer};
+use heapless::Vec;
 use static_cell::StaticCell;
 use {defmt_rtt as _, panic_probe as _};
 
 bind_interrupts!(struct Irqs{
     IPCC_C1_RX => ReceiveInterruptHandler;
     IPCC_C1_TX => TransmitInterruptHandler;
+    RNG => RngInterruptHandler<RNG>;
 });
 
 #[embassy_executor::task]
-async fn run_mm_queue(memory_manager: mm::MemoryManager) {
-    memory_manager.run_queue().await;
+async fn run_mm_queue(mut memory_manager: mm::MemoryManager<'static>) -> ! {
+    memory_manager.run_queue().await
+}
+
+#[embassy_executor::task]
+async fn run_mac(runner: &'static Runner<'static>) -> ! {
+    runner.run().await
 }
 
 #[embassy_executor::task]
-async fn run_mac(runner: &'static Runner<'static>) {
-    runner.run().await;
+async fn run_net(mut runner: embassy_net::Runner<'static, Driver<'static>>) -> ! {
+    runner.run().await
 }
 
 #[embassy_executor::main]
@@ -60,118 +72,76 @@ async fn main(spawner: Spawner) {
     info!("Hello World!");
 
     let config = Config::default();
-    let mbox = TlMbox::init(p.IPCC, Irqs, config);
+    let mut mbox = TlMbox::init(p.IPCC, Irqs, config).await;
 
     spawner.spawn(run_mm_queue(mbox.mm_subsystem).unwrap());
 
-    let sys_event = mbox.sys_subsystem.read().await;
-    info!("sys event: {}", sys_event.payload());
-
-    core::mem::drop(sys_event);
-
     let result = mbox.sys_subsystem.shci_c2_mac_802_15_4_init().await;
     info!("initialized mac: {}", result);
 
-    info!("resetting");
-    mbox.mac_subsystem
-        .send_command(&ResetRequest {
-            set_default_pib: true,
-            ..Default::default()
-        })
-        .await
-        .unwrap();
-    defmt::info!("{:#x}", mbox.mac_subsystem.read().await.unwrap());
-
-    info!("setting extended address");
-    let extended_address: u64 = 0xACDE480000000001;
-    mbox.mac_subsystem
-        .send_command(&SetRequest {
-            pib_attribute_ptr: &extended_address as *const _ as *const u8,
-            pib_attribute: PibId::ExtendedAddress,
-        })
-        .await
-        .unwrap();
-    defmt::info!("{:#x}", mbox.mac_subsystem.read().await.unwrap());
-
-    info!("setting short address");
-    let short_address: u16 = 0x1122;
-    mbox.mac_subsystem
-        .send_command(&SetRequest {
-            pib_attribute_ptr: &short_address as *const _ as *const u8,
-            pib_attribute: PibId::ShortAddress,
-        })
-        .await
-        .unwrap();
-    defmt::info!("{:#x}", mbox.mac_subsystem.read().await.unwrap());
-
-    info!("setting association permit");
-    let association_permit: bool = true;
-    mbox.mac_subsystem
-        .send_command(&SetRequest {
-            pib_attribute_ptr: &association_permit as *const _ as *const u8,
-            pib_attribute: PibId::AssociationPermit,
-        })
-        .await
-        .unwrap();
-    defmt::info!("{:#x}", mbox.mac_subsystem.read().await.unwrap());
-
-    info!("setting TX power");
-    let transmit_power: i8 = 2;
-    mbox.mac_subsystem
-        .send_command(&SetRequest {
-            pib_attribute_ptr: &transmit_power as *const _ as *const u8,
-            pib_attribute: PibId::TransmitPower,
-        })
-        .await
-        .unwrap();
-    defmt::info!("{:#x}", mbox.mac_subsystem.read().await.unwrap());
-
-    info!("starting FFD device");
-    mbox.mac_subsystem
-        .send_command(&StartRequest {
-            pan_id: PanId([0x1A, 0xAA]),
-            channel_number: MacChannel::Channel16,
-            beacon_order: 0x0F,
-            superframe_order: 0x0F,
-            pan_coordinator: true,
-            battery_life_extension: false,
-            ..Default::default()
-        })
-        .await
-        .unwrap();
-    defmt::info!("{:#x}", mbox.mac_subsystem.read().await.unwrap());
-
-    info!("setting RX on when idle");
-    let rx_on_while_idle: bool = true;
-    mbox.mac_subsystem
-        .send_command(&SetRequest {
-            pib_attribute_ptr: &rx_on_while_idle as *const _ as *const u8,
-            pib_attribute: PibId::RxOnWhenIdle,
-        })
-        .await
-        .unwrap();
-    defmt::info!("{:#x}", mbox.mac_subsystem.read().await.unwrap());
-
-    static TX1: StaticCell<[u8; 127]> = StaticCell::new();
-    static TX2: StaticCell<[u8; 127]> = StaticCell::new();
-    static TX3: StaticCell<[u8; 127]> = StaticCell::new();
-    static TX4: StaticCell<[u8; 127]> = StaticCell::new();
-    static TX5: StaticCell<[u8; 127]> = StaticCell::new();
-    let tx_queue = [
-        TX1.init([0u8; 127]),
-        TX2.init([0u8; 127]),
-        TX3.init([0u8; 127]),
-        TX4.init([0u8; 127]),
-        TX5.init([0u8; 127]),
-    ];
-
+    static DRIVER_STATE: StaticCell<DriverState> = StaticCell::new();
     static RUNNER: StaticCell<Runner> = StaticCell::new();
-    let runner = RUNNER.init(Runner::new(mbox.mac_subsystem, tx_queue));
+    static RESOURCES: StaticCell<StackResources<3>> = StaticCell::new();
+
+    let driver_state = DRIVER_STATE.init(DriverState::new(mbox.mac_subsystem));
+
+    let (driver, mac_runner, mut control) = Driver::new(
+        driver_state,
+        0x1122u16.to_be_bytes().try_into().unwrap(),
+        0xACDE480000000001u64.to_be_bytes().try_into().unwrap(),
+    );
+
+    // TODO: rng does not work for some reason
+    // Generate random seed.
+    // let mut rng = Rng::new(p.RNG, Irqs);
+    let seed = [0; 8];
+    // let _ = rng.async_fill_bytes(&mut seed).await;
+    let seed = u64::from_le_bytes(seed);
+
+    info!("seed generated");
+
+    // Init network stack
+    let ipv6_addr = Ipv6Addr::new(0, 0, 0, 0, 0, 0xffff, 0xc00a, 0x2ff);
+
+    let config = embassy_net::Config::ipv6_static(StaticConfigV6 {
+        address: Ipv6Cidr::new(ipv6_addr, 104),
+        gateway: None,
+        dns_servers: Vec::new(),
+    });
+
+    let (stack, eth_runner) = embassy_net::new(driver, config, RESOURCES.init(StackResources::new()), seed);
+
+    // wpan runner
+    spawner.spawn(run_mac(RUNNER.init(mac_runner)).unwrap());
+
+    // Launch network task
+    spawner.spawn(unwrap!(run_net(eth_runner)));
+
+    info!("Network task initialized");
+
+    control.init_link([0x1A, 0xAA]).await;
+
+    // Ensure DHCP configuration is up before trying connect
+    stack.wait_config_up().await;
+
+    info!("Network up");
+
+    // Then we can use it!
+    let mut rx_meta = [PacketMetadata::EMPTY];
+    let mut rx_buffer = [0; 4096];
+    let mut tx_meta = [PacketMetadata::EMPTY];
+    let mut tx_buffer = [0; 4096];
+
+    let mut socket = UdpSocket::new(stack, &mut rx_meta, &mut rx_buffer, &mut tx_meta, &mut tx_buffer);
+
+    let remote_endpoint = (Ipv6Addr::new(0, 0, 0, 0, 0, 0xffff, 0xc00a, 0x2fb), 8000);
+
+    let send_buf = [0u8; 20];
 
-    spawner.spawn(run_mac(runner).unwrap());
+    socket.bind((ipv6_addr, 8000)).unwrap();
+    socket.send_to(&send_buf, remote_endpoint).await.unwrap();
 
-    let (driver, control) = mac::new(runner).await;
+    Timer::after(Duration::from_secs(2)).await;
 
-    let _ = driver;
-    let _ = control;
+    cortex_m::asm::bkpt();
 }
diff --git a/examples/stm32wb/src/bin/mac_rfd.rs b/examples/stm32wb/src/bin/mac_rfd.rs
index 883179023..dae3c5200 100644
--- a/examples/stm32wb/src/bin/mac_rfd.rs
+++ b/examples/stm32wb/src/bin/mac_rfd.rs
@@ -21,7 +21,7 @@ bind_interrupts!(struct Irqs{
 });
 
 #[embassy_executor::task]
-async fn run_mm_queue(memory_manager: mm::MemoryManager) {
+async fn run_mm_queue(mut memory_manager: mm::MemoryManager<'static>) {
     memory_manager.run_queue().await;
 }
 
@@ -56,41 +56,39 @@ async fn main(spawner: Spawner) {
     info!("Hello World!");
 
     let config = Config::default();
-    let mbox = TlMbox::init(p.IPCC, Irqs, config);
+    let mbox = TlMbox::init(p.IPCC, Irqs, config).await;
+    let mut sys = mbox.sys_subsystem;
 
     spawner.spawn(run_mm_queue(mbox.mm_subsystem).unwrap());
 
-    let sys_event = mbox.sys_subsystem.read().await;
-    info!("sys event: {}", sys_event.payload());
-
-    core::mem::drop(sys_event);
-
-    let result = mbox.sys_subsystem.shci_c2_mac_802_15_4_init().await;
+    let result = sys.shci_c2_mac_802_15_4_init().await;
     info!("initialized mac: {}", result);
 
+    let (mut mac_rx, mut mac_tx) = mbox.mac_subsystem.split();
+
     info!("resetting");
-    mbox.mac_subsystem
+    mac_tx
         .send_command(&ResetRequest {
             set_default_pib: true,
             ..Default::default()
         })
         .await
         .unwrap();
-    defmt::info!("{:#x}", mbox.mac_subsystem.read().await.unwrap());
+    defmt::info!("{:#x}", mac_rx.read().await.unwrap());
 
     info!("setting extended address");
     let extended_address: u64 = 0xACDE480000000002;
-    mbox.mac_subsystem
+    mac_tx
         .send_command(&SetRequest {
             pib_attribute_ptr: &extended_address as *const _ as *const u8,
             pib_attribute: PibId::ExtendedAddress,
         })
         .await
         .unwrap();
-    defmt::info!("{:#x}", mbox.mac_subsystem.read().await.unwrap());
+    defmt::info!("{:#x}", mac_rx.read().await.unwrap());
 
     info!("getting extended address");
-    mbox.mac_subsystem
+    mac_tx
         .send_command(&GetRequest {
             pib_attribute: PibId::ExtendedAddress,
             ..Default::default()
@@ -99,7 +97,7 @@ async fn main(spawner: Spawner) {
         .unwrap();
 
     {
-        let evt = mbox.mac_subsystem.read().await.unwrap();
+        let evt = mac_rx.read().await.unwrap();
         info!("{:#x}", evt);
 
         if let MacEvent::MlmeGetCnf(evt) = evt {
@@ -125,9 +123,9 @@ async fn main(spawner: Spawner) {
         key_index: 152,
     };
     info!("{}", a);
-    mbox.mac_subsystem.send_command(&a).await.unwrap();
+    mac_tx.send_command(&a).await.unwrap();
     let short_addr = {
-        let evt = mbox.mac_subsystem.read().await.unwrap();
+        let evt = mac_rx.read().await.unwrap();
         info!("{:#x}", evt);
 
         if let MacEvent::MlmeAssociateCnf(conf) = evt {
@@ -138,7 +136,7 @@ async fn main(spawner: Spawner) {
     };
 
     info!("setting short address");
-    mbox.mac_subsystem
+    mac_tx
         .send_command(&SetRequest {
             pib_attribute_ptr: &short_addr as *const _ as *const u8,
             pib_attribute: PibId::ShortAddress,
@@ -146,13 +144,13 @@ async fn main(spawner: Spawner) {
         .await
         .unwrap();
     {
-        let evt = mbox.mac_subsystem.read().await.unwrap();
+        let evt = mac_rx.read().await.unwrap();
         info!("{:#x}", evt);
     }
 
     info!("sending data");
     let data = b"Hello from embassy!";
-    mbox.mac_subsystem
+    mac_tx
         .send_command(
             DataRequest {
                 src_addr_mode: AddressMode::Short,
@@ -170,12 +168,12 @@ async fn main(spawner: Spawner) {
         .await
         .unwrap();
     {
-        let evt = mbox.mac_subsystem.read().await.unwrap();
+        let evt = mac_rx.read().await.unwrap();
         info!("{:#x}", evt);
     }
 
     loop {
-        match mbox.mac_subsystem.read().await {
+        match mac_rx.read().await {
             Ok(evt) => info!("{:#x}", evt),
             _ => continue,
         };
diff --git a/examples/stm32wb/src/bin/tl_mbox.rs b/examples/stm32wb/src/bin/tl_mbox.rs
index 4e7f2304d..0902e28e8 100644
--- a/examples/stm32wb/src/bin/tl_mbox.rs
+++ b/examples/stm32wb/src/bin/tl_mbox.rs
@@ -46,7 +46,7 @@ async fn main(_spawner: Spawner) {
     info!("Hello World!");
 
     let config = Config::default();
-    let mbox = TlMbox::init(p.IPCC, Irqs, config);
+    let mbox = TlMbox::init(p.IPCC, Irqs, config).await;
 
     loop {
         let wireless_fw_info = mbox.sys_subsystem.wireless_fw_info();
diff --git a/examples/stm32wb/src/bin/tl_mbox_ble.rs b/examples/stm32wb/src/bin/tl_mbox_ble.rs
index 72a4c18e6..763dc32cd 100644
--- a/examples/stm32wb/src/bin/tl_mbox_ble.rs
+++ b/examples/stm32wb/src/bin/tl_mbox_ble.rs
@@ -7,6 +7,7 @@ use embassy_stm32::bind_interrupts;
 use embassy_stm32::ipcc::{Config, ReceiveInterruptHandler, TransmitInterruptHandler};
 use embassy_stm32::rcc::WPAN_DEFAULT;
 use embassy_stm32_wpan::TlMbox;
+use embassy_stm32_wpan::sub::mm;
 use {defmt_rtt as _, panic_probe as _};
 
 bind_interrupts!(struct Irqs{
@@ -14,8 +15,13 @@ bind_interrupts!(struct Irqs{
     IPCC_C1_TX => TransmitInterruptHandler;
 });
 
+#[embassy_executor::task]
+async fn run_mm_queue(mut memory_manager: mm::MemoryManager<'static>) {
+    memory_manager.run_queue().await;
+}
+
 #[embassy_executor::main]
-async fn main(_spawner: Spawner) {
+async fn main(spawner: Spawner) {
     /*
         How to make this work:
 
@@ -45,18 +51,19 @@ async fn main(_spawner: Spawner) {
     info!("Hello World!");
 
     let config = Config::default();
-    let mbox = TlMbox::init(p.IPCC, Irqs, config);
+    let mbox = TlMbox::init(p.IPCC, Irqs, config).await;
+    let mut sys = mbox.sys_subsystem;
+    let mut ble = mbox.ble_subsystem;
 
-    let sys_event = mbox.sys_subsystem.read().await;
-    info!("sys event: {}", sys_event.payload());
+    spawner.spawn(run_mm_queue(mbox.mm_subsystem).unwrap());
 
-    let _ = mbox.sys_subsystem.shci_c2_ble_init(Default::default()).await;
+    let _ = sys.shci_c2_ble_init(Default::default()).await;
 
     info!("starting ble...");
-    mbox.ble_subsystem.tl_write(0x0c, &[]).await;
+    ble.tl_write(0x0c, &[]).await;
 
     info!("waiting for ble...");
-    let ble_event = mbox.ble_subsystem.tl_read().await;
+    let ble_event = ble.tl_read().await;
 
     info!("ble event: {}", ble_event.payload());
 
diff --git a/examples/stm32wb/src/bin/tl_mbox_mac.rs b/examples/stm32wb/src/bin/tl_mbox_mac.rs
index 16d0a1527..235a48241 100644
--- a/examples/stm32wb/src/bin/tl_mbox_mac.rs
+++ b/examples/stm32wb/src/bin/tl_mbox_mac.rs
@@ -16,7 +16,7 @@ bind_interrupts!(struct Irqs{
 });
 
 #[embassy_executor::task]
-async fn run_mm_queue(memory_manager: mm::MemoryManager) {
+async fn run_mm_queue(mut memory_manager: mm::MemoryManager<'static>) {
     memory_manager.run_queue().await;
 }
 
@@ -51,16 +51,12 @@ async fn main(spawner: Spawner) {
     info!("Hello World!");
 
     let config = Config::default();
-    let mbox = TlMbox::init(p.IPCC, Irqs, config);
+    let mbox = TlMbox::init(p.IPCC, Irqs, config).await;
+    let mut sys = mbox.sys_subsystem;
 
     spawner.spawn(run_mm_queue(mbox.mm_subsystem).unwrap());
 
-    let sys_event = mbox.sys_subsystem.read().await;
-    info!("sys event: {}", sys_event.payload());
-
-    core::mem::drop(sys_event);
-
-    let result = mbox.sys_subsystem.shci_c2_mac_802_15_4_init().await;
+    let result = sys.shci_c2_mac_802_15_4_init().await;
     info!("initialized mac: {}", result);
 
     //
diff --git a/examples/stm32wba/src/bin/adc.rs b/examples/stm32wba/src/bin/adc.rs
index 177aab3f3..ade3f5d6a 100644
--- a/examples/stm32wba/src/bin/adc.rs
+++ b/examples/stm32wba/src/bin/adc.rs
@@ -2,7 +2,7 @@
 #![no_main]
 
 use defmt::*;
-use embassy_stm32::adc::{AdcChannel, adc4};
+use embassy_stm32::adc::{Adc, AdcChannel, SampleTime, adc4};
 use {defmt_rtt as _, panic_probe as _};
 
 #[embassy_executor::main]
@@ -12,11 +12,11 @@ async fn main(_spawner: embassy_executor::Spawner) {
     let mut p = embassy_stm32::init(config);
 
     // **** ADC4 init ****
-    let mut adc4 = adc4::Adc4::new(p.ADC4);
+    let mut adc4 = Adc::new_adc4(p.ADC4);
     let mut adc4_pin1 = p.PA0; // A4
     let mut adc4_pin2 = p.PA1; // A5
-    adc4.set_resolution(adc4::Resolution::BITS12);
-    adc4.set_averaging(adc4::Averaging::Samples256);
+    adc4.set_resolution_adc4(adc4::Resolution::BITS12);
+    adc4.set_averaging_adc4(adc4::Averaging::Samples256);
 
     let max4 = adc4::resolution_to_max_count(adc4::Resolution::BITS12);
 
@@ -37,11 +37,14 @@ async fn main(_spawner: embassy_executor::Spawner) {
     // The channels must be in ascending order and can't repeat for ADC4
     adc4.read(
         p.GPDMA1_CH1.reborrow(),
-        [&mut degraded42, &mut degraded41].into_iter(),
+        [
+            (&mut degraded42, SampleTime::CYCLES12_5),
+            (&mut degraded41, SampleTime::CYCLES12_5),
+        ]
+        .into_iter(),
         &mut measurements,
     )
-    .await
-    .unwrap();
+    .await;
     let volt2: f32 = 3.3 * measurements[0] as f32 / max4 as f32;
     let volt1: f32 = 3.0 * measurements[1] as f32 / max4 as f32;
     info!("Async read 4 pin 1 {}", volt1);
diff --git a/examples/stm32wba/src/bin/button_exti.rs b/examples/stm32wba/src/bin/button_exti.rs
index 34a08bbc6..d63290d42 100644
--- a/examples/stm32wba/src/bin/button_exti.rs
+++ b/examples/stm32wba/src/bin/button_exti.rs
@@ -3,16 +3,22 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::gpio::Pull;
+use embassy_stm32::{bind_interrupts, interrupt};
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI13 => exti::InterruptHandler<interrupt::typelevel::EXTI13>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Hello World!");
 
-    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up);
+    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up, Irqs);
 
     info!("Press the USER button...");
 
diff --git a/examples/stm32wba6/src/bin/adc.rs b/examples/stm32wba6/src/bin/adc.rs
index 0887e124c..51dcff57a 100644
--- a/examples/stm32wba6/src/bin/adc.rs
+++ b/examples/stm32wba6/src/bin/adc.rs
@@ -2,21 +2,47 @@
 #![no_main]
 
 use defmt::*;
-use embassy_stm32::adc::{AdcChannel, adc4};
+use embassy_stm32::Config;
+use embassy_stm32::adc::{Adc, AdcChannel, SampleTime, adc4};
+use embassy_stm32::rcc::{
+    AHB5Prescaler, AHBPrescaler, APBPrescaler, PllDiv, PllMul, PllPreDiv, PllSource, Sysclk, VoltageScale,
+};
 use {defmt_rtt as _, panic_probe as _};
 
 #[embassy_executor::main]
 async fn main(_spawner: embassy_executor::Spawner) {
-    let config = embassy_stm32::Config::default();
+    let mut config = Config::default();
+    // Fine-tune PLL1 dividers/multipliers
+    config.rcc.pll1 = Some(embassy_stm32::rcc::Pll {
+        source: PllSource::HSI,
+        prediv: PllPreDiv::DIV1,  // PLLM = 1 → HSI / 1 = 16 MHz
+        mul: PllMul::MUL30,       // PLLN = 30 → 16 MHz * 30 = 480 MHz VCO
+        divr: Some(PllDiv::DIV5), // PLLR = 5 → 96 MHz (Sysclk)
+        // divq: Some(PllDiv::DIV10), // PLLQ = 10 → 48 MHz (NOT USED)
+        divq: None,
+        divp: Some(PllDiv::DIV30), // PLLP = 30 → 16 MHz (USBOTG)
+        frac: Some(0),             // Fractional part (enabled)
+    });
+
+    config.rcc.ahb_pre = AHBPrescaler::DIV1;
+    config.rcc.apb1_pre = APBPrescaler::DIV1;
+    config.rcc.apb2_pre = APBPrescaler::DIV1;
+    config.rcc.apb7_pre = APBPrescaler::DIV1;
+    config.rcc.ahb5_pre = AHB5Prescaler::DIV4;
+
+    // voltage scale for max performance
+    config.rcc.voltage_scale = VoltageScale::RANGE1;
+    // route PLL1_P into the USB‐OTG‐HS block
+    config.rcc.sys = Sysclk::PLL1_R;
 
     let mut p = embassy_stm32::init(config);
 
     // **** ADC4 init ****
-    let mut adc4 = adc4::Adc4::new(p.ADC4);
+    let mut adc4 = Adc::new_adc4(p.ADC4);
     let mut adc4_pin1 = p.PA0; // A4
     let mut adc4_pin2 = p.PA1; // A5
-    adc4.set_resolution(adc4::Resolution::BITS12);
-    adc4.set_averaging(adc4::Averaging::Samples256);
+    adc4.set_resolution_adc4(adc4::Resolution::BITS12);
+    adc4.set_averaging_adc4(adc4::Averaging::Samples256);
     let max4 = adc4::resolution_to_max_count(adc4::Resolution::BITS12);
 
     // **** ADC4 blocking read ****
@@ -36,11 +62,14 @@ async fn main(_spawner: embassy_executor::Spawner) {
     // The channels must be in ascending order and can't repeat for ADC4
     adc4.read(
         p.GPDMA1_CH1.reborrow(),
-        [&mut degraded42, &mut degraded41].into_iter(),
+        [
+            (&mut degraded42, SampleTime::CYCLES12_5),
+            (&mut degraded41, SampleTime::CYCLES12_5),
+        ]
+        .into_iter(),
         &mut measurements,
     )
-    .await
-    .unwrap();
+    .await;
     let volt2: f32 = 3.3 * measurements[0] as f32 / max4 as f32;
     let volt1: f32 = 3.0 * measurements[1] as f32 / max4 as f32;
     info!("Async read 4 pin 1 {}", volt1);
diff --git a/examples/stm32wba6/src/bin/button_exti.rs b/examples/stm32wba6/src/bin/button_exti.rs
index 34a08bbc6..d63290d42 100644
--- a/examples/stm32wba6/src/bin/button_exti.rs
+++ b/examples/stm32wba6/src/bin/button_exti.rs
@@ -3,16 +3,22 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::gpio::Pull;
+use embassy_stm32::{bind_interrupts, interrupt};
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI13 => exti::InterruptHandler<interrupt::typelevel::EXTI13>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Hello World!");
 
-    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up);
+    let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up, Irqs);
 
     info!("Press the USER button...");
 
diff --git a/examples/stm32wl/src/bin/button_exti.rs b/examples/stm32wl/src/bin/button_exti.rs
index 953b13bac..2bb39c709 100644
--- a/examples/stm32wl/src/bin/button_exti.rs
+++ b/examples/stm32wl/src/bin/button_exti.rs
@@ -5,11 +5,16 @@ use core::mem::MaybeUninit;
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::SharedData;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::gpio::Pull;
+use embassy_stm32::{SharedData, bind_interrupts, interrupt};
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI0 => exti::InterruptHandler<interrupt::typelevel::EXTI0>;
+});
+
 #[unsafe(link_section = ".shared_data")]
 static SHARED_DATA: MaybeUninit<SharedData> = MaybeUninit::uninit();
 
@@ -18,7 +23,7 @@ async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init_primary(Default::default(), &SHARED_DATA);
     info!("Hello World!");
 
-    let mut button = ExtiInput::new(p.PA0, p.EXTI0, Pull::Up);
+    let mut button = ExtiInput::new(p.PA0, p.EXTI0, Pull::Up, Irqs);
 
     info!("Press the USER button...");
 
diff --git a/examples/stm32wle5/src/bin/adc.rs b/examples/stm32wle5/src/bin/adc.rs
index 4e0574d97..ea91fb063 100644
--- a/examples/stm32wle5/src/bin/adc.rs
+++ b/examples/stm32wle5/src/bin/adc.rs
@@ -6,20 +6,12 @@ use defmt::*;
 use defmt_rtt as _;
 use embassy_executor::Spawner;
 use embassy_stm32::adc::{Adc, SampleTime};
-use embassy_stm32::low_power::Executor;
+use embassy_stm32::low_power;
 use embassy_time::Timer;
 use panic_probe as _;
 use static_cell::StaticCell;
 
-#[cortex_m_rt::entry]
-fn main() -> ! {
-    info!("main: Starting!");
-    Executor::take().run(|spawner| {
-        spawner.spawn(unwrap!(async_main(spawner)));
-    });
-}
-
-#[embassy_executor::task]
+#[embassy_executor::main(executor = "low_power::Executor")]
 async fn async_main(_spawner: Spawner) {
     let mut config = embassy_stm32::Config::default();
     // enable HSI clock
diff --git a/examples/stm32wle5/src/bin/blinky.rs b/examples/stm32wle5/src/bin/blinky.rs
index b2745fdaf..9f0c04672 100644
--- a/examples/stm32wle5/src/bin/blinky.rs
+++ b/examples/stm32wle5/src/bin/blinky.rs
@@ -6,20 +6,12 @@ use defmt::*;
 use defmt_rtt as _;
 use embassy_executor::Spawner;
 use embassy_stm32::gpio::{Level, Output, Speed};
-use embassy_stm32::low_power::Executor;
+use embassy_stm32::low_power;
 use embassy_time::Timer;
 use panic_probe as _;
 use static_cell::StaticCell;
 
-#[cortex_m_rt::entry]
-fn main() -> ! {
-    info!("main: Starting!");
-    Executor::take().run(|spawner| {
-        spawner.spawn(unwrap!(async_main(spawner)));
-    });
-}
-
-#[embassy_executor::task]
+#[embassy_executor::main(executor = "low_power::Executor")]
 async fn async_main(_spawner: Spawner) {
     let mut config = embassy_stm32::Config::default();
     // enable HSI clock
diff --git a/examples/stm32wle5/src/bin/button_exti.rs b/examples/stm32wle5/src/bin/button_exti.rs
index db1bff0be..f248b6147 100644
--- a/examples/stm32wle5/src/bin/button_exti.rs
+++ b/examples/stm32wle5/src/bin/button_exti.rs
@@ -5,21 +5,18 @@ use defmt::*;
 #[cfg(feature = "defmt-rtt")]
 use defmt_rtt as _;
 use embassy_executor::Spawner;
-use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::exti::{self, ExtiInput};
 use embassy_stm32::gpio::Pull;
-use embassy_stm32::low_power::Executor;
+use embassy_stm32::{bind_interrupts, interrupt, low_power};
 use panic_probe as _;
 use static_cell::StaticCell;
 
-#[cortex_m_rt::entry]
-fn main() -> ! {
-    info!("main: Starting!");
-    Executor::take().run(|spawner| {
-        spawner.spawn(unwrap!(async_main(spawner)));
-    });
-}
+bind_interrupts!(
+    pub struct Irqs{
+        EXTI0 => exti::InterruptHandler<interrupt::typelevel::EXTI0>;
+});
 
-#[embassy_executor::task]
+#[embassy_executor::main(executor = "low_power::Executor")]
 async fn async_main(_spawner: Spawner) {
     let mut config = embassy_stm32::Config::default();
     // enable HSI clock
@@ -72,7 +69,7 @@ async fn async_main(_spawner: Spawner) {
 
     info!("Hello World!");
 
-    let mut button = ExtiInput::new(p.PA0, p.EXTI0, Pull::Up);
+    let mut button = ExtiInput::new(p.PA0, p.EXTI0, Pull::Up, Irqs);
 
     info!("Press the USER button...");
 
diff --git a/examples/stm32wle5/src/bin/i2c.rs b/examples/stm32wle5/src/bin/i2c.rs
index c31c673c9..68c17a672 100644
--- a/examples/stm32wle5/src/bin/i2c.rs
+++ b/examples/stm32wle5/src/bin/i2c.rs
@@ -6,9 +6,8 @@ use defmt::*;
 use defmt_rtt as _;
 use embassy_executor::Spawner;
 use embassy_stm32::i2c::I2c;
-use embassy_stm32::low_power::Executor;
 use embassy_stm32::time::Hertz;
-use embassy_stm32::{bind_interrupts, i2c, peripherals};
+use embassy_stm32::{bind_interrupts, i2c, low_power, peripherals};
 use embassy_time::{Duration, Timer};
 use panic_probe as _;
 use static_cell::StaticCell;
@@ -18,15 +17,7 @@ bind_interrupts!(struct IrqsI2C{
     I2C2_ER => i2c::ErrorInterruptHandler<peripherals::I2C2>;
 });
 
-#[cortex_m_rt::entry]
-fn main() -> ! {
-    info!("main: Starting!");
-    Executor::take().run(|spawner| {
-        spawner.spawn(unwrap!(async_main(spawner)));
-    });
-}
-
-#[embassy_executor::task]
+#[embassy_executor::main(executor = "low_power::Executor")]
 async fn async_main(_spawner: Spawner) {
     let mut config = embassy_stm32::Config::default();
     // enable HSI clock
diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml
index b92b47be2..496a9de18 100644
--- a/tests/stm32/Cargo.toml
+++ b/tests/stm32/Cargo.toml
@@ -31,9 +31,9 @@ stm32l4r5zi = ["embassy-stm32/stm32l4r5zi", "chrono", "not-gpdma", "rng", "dual-
 stm32l552ze = ["embassy-stm32/stm32l552ze", "not-gpdma", "rng", "hash", "dual-bank"]
 stm32u585ai = ["embassy-stm32/stm32u585ai", "spi-v345", "chrono", "rng", "hash", "cordic"]
 stm32u5a5zj = ["embassy-stm32/stm32u5a5zj", "spi-v345", "chrono", "rng", "hash"] # FIXME: cordic test cause it crash
-stm32wb55rg = ["embassy-stm32/stm32wb55rg", "chrono", "not-gpdma", "ble", "mac" , "rng"]
-stm32wba52cg = ["embassy-stm32/stm32wba52cg", "spi-v345", "chrono", "rng", "hash"]
-stm32wl55jc = ["embassy-stm32/stm32wl55jc-cm4", "not-gpdma", "rng", "chrono"]
+stm32wb55rg = ["embassy-stm32/stm32wb55rg", "chrono", "not-gpdma", "ble", "mac" , "rng", "hsem", "stop"]
+stm32wba52cg = ["embassy-stm32/stm32wba52cg", "spi-v345", "chrono", "rng", "hash", "adc"]
+stm32wl55jc = ["embassy-stm32/stm32wl55jc-cm4", "not-gpdma", "rng", "chrono", "hsem"]
 stm32f091rc = ["embassy-stm32/stm32f091rc", "cm0", "not-gpdma", "chrono"]
 stm32h503rb = ["embassy-stm32/stm32h503rb", "spi-v345", "rng", "stop"]
 stm32h7s3l8 = ["embassy-stm32/stm32h7s3l8", "spi-v345", "rng", "cordic", "hash-v34"] # TODO: fdcan crashes, cryp dma hangs.
@@ -56,8 +56,10 @@ mac = ["dep:embassy-stm32-wpan", "embassy-stm32-wpan/mac"]
 embassy-stm32-wpan = []
 not-gpdma = []
 dac = []
+adc = []
 ucpd = []
 cordic = ["dep:num-traits"]
+hsem = []
 dual-bank = ["embassy-stm32/dual-bank"]
 single-bank = ["embassy-stm32/single-bank"]
 eeprom = []
@@ -110,6 +112,11 @@ path = "src/bin/afio.rs"
 required-features = [ "afio",]
 
 [[bin]]
+name = "adc"
+path = "src/bin/adc.rs"
+required-features = [ "adc",]
+
+[[bin]]
 name = "can"
 path = "src/bin/can.rs"
 required-features = [ "can",]
@@ -224,6 +231,11 @@ name = "wpan_mac"
 path = "src/bin/wpan_mac.rs"
 required-features = [ "mac",]
 
+[[bin]]
+name = "hsem"
+path = "src/bin/hsem.rs"
+required-features = [ "hsem",]
+
 # END TESTS
 
 [profile.dev]
diff --git a/tests/stm32/src/bin/adc.rs b/tests/stm32/src/bin/adc.rs
new file mode 100644
index 000000000..6cedc6498
--- /dev/null
+++ b/tests/stm32/src/bin/adc.rs
@@ -0,0 +1,39 @@
+#![no_std]
+#![no_main]
+
+// required-features: dac
+
+#[path = "../common.rs"]
+mod common;
+
+use common::*;
+use embassy_executor::Spawner;
+use embassy_stm32::adc::{Adc, SampleTime};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    // Initialize the board and obtain a Peripherals instance
+    let p: embassy_stm32::Peripherals = init();
+
+    let adc = peri!(p, ADC);
+    let mut adc_pin = peri!(p, DAC_PIN);
+
+    let mut adc = Adc::new_adc4(adc);
+
+    // Now wait a little to obtain a stable value
+    Timer::after_millis(30).await;
+    let _ = adc.blocking_read(&mut adc_pin, SampleTime::from_bits(0));
+
+    for _ in 0..=255 {
+        // Now wait a little to obtain a stable value
+        Timer::after_millis(30).await;
+
+        // Need to steal the peripherals here because PA4 is obviously in use already
+        let _ = adc.blocking_read(&mut adc_pin, SampleTime::from_bits(0));
+    }
+
+    info!("Test OK");
+    cortex_m::asm::bkpt();
+}
diff --git a/tests/stm32/src/bin/eth.rs b/tests/stm32/src/bin/eth.rs
index a65682a02..ffc76b96f 100644
--- a/tests/stm32/src/bin/eth.rs
+++ b/tests/stm32/src/bin/eth.rs
@@ -7,8 +7,8 @@ mod common;
 use common::*;
 use embassy_executor::Spawner;
 use embassy_net::StackResources;
-use embassy_stm32::eth::{Ethernet, GenericPhy, PacketQueue};
-use embassy_stm32::peripherals::ETH;
+use embassy_stm32::eth::{Ethernet, GenericPhy, PacketQueue, Sma};
+use embassy_stm32::peripherals::{ETH, ETH_SMA};
 use embassy_stm32::rng::Rng;
 use embassy_stm32::{bind_interrupts, eth, peripherals, rng};
 use static_cell::StaticCell;
@@ -27,7 +27,7 @@ bind_interrupts!(struct Irqs {
     RNG => rng::InterruptHandler<peripherals::RNG>;
 });
 
-type Device = Ethernet<'static, ETH, GenericPhy>;
+type Device = Ethernet<'static, ETH, GenericPhy<Sma<'static, ETH_SMA>>>;
 
 #[embassy_executor::task]
 async fn net_task(mut runner: embassy_net::Runner<'static, Device>) -> ! {
@@ -69,13 +69,12 @@ async fn main(spawner: Spawner) {
     const PACKET_QUEUE_SIZE: usize = 4;
 
     static PACKETS: StaticCell<PacketQueue<PACKET_QUEUE_SIZE, PACKET_QUEUE_SIZE>> = StaticCell::new();
+
     let device = Ethernet::new(
         PACKETS.init(PacketQueue::<PACKET_QUEUE_SIZE, PACKET_QUEUE_SIZE>::new()),
         p.ETH,
         Irqs,
         p.PA1,
-        p.PA2,
-        p.PC1,
         p.PA7,
         p.PC4,
         p.PC5,
@@ -85,8 +84,10 @@ async fn main(spawner: Spawner) {
         #[cfg(feature = "stm32h563zi")]
         p.PB15,
         p.PG11,
-        GenericPhy::new_auto(),
         mac_addr,
+        p.ETH_SMA,
+        p.PA2,
+        p.PC1,
     );
 
     let config = embassy_net::Config::dhcpv4(Default::default());
diff --git a/tests/stm32/src/bin/hsem.rs b/tests/stm32/src/bin/hsem.rs
new file mode 100644
index 000000000..fa69f22b2
--- /dev/null
+++ b/tests/stm32/src/bin/hsem.rs
@@ -0,0 +1,50 @@
+// required-features: hsem
+#![no_std]
+#![no_main]
+
+#[path = "../common.rs"]
+mod common;
+
+use common::*;
+use embassy_executor::Spawner;
+use embassy_stm32::bind_interrupts;
+use embassy_stm32::hsem::{HardwareSemaphore, HardwareSemaphoreInterruptHandler};
+use embassy_stm32::peripherals::HSEM;
+
+bind_interrupts!(struct Irqs{
+    HSEM => HardwareSemaphoreInterruptHandler<HSEM>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p: embassy_stm32::Peripherals = init();
+
+    let hsem = HardwareSemaphore::new(p.HSEM, Irqs);
+
+    //    if hsem.channel_for(SemaphoreNumber::Channel5).is_semaphore_locked() {
+    //        defmt::panic!("Semaphore 5 already locked!")
+    //    }
+    //
+    //    hsem.channel_for(SemaphoreNumber::Channel5).one_step_lock().unwrap();
+    //    hsem.channel_for(SemaphoreNumber::Channel1).two_step_lock(0).unwrap();
+    //
+    //    hsem.channel_for(SemaphoreNumber::Channel5).unlock(0);
+
+    #[cfg(feature = "stm32wb55rg")]
+    let [_channel1, _channel2, mut channel5, _channel6] = hsem.split();
+    #[cfg(not(feature = "stm32wb55rg"))]
+    let [_channel1, _channel2, _channel3, _channel4, mut channel5, _channel6] = hsem.split();
+
+    info!("Locking channel 5");
+
+    let mutex = channel5.lock(0).await;
+
+    info!("Locked channel 5");
+
+    drop(mutex);
+
+    info!("Unlocked channel 5");
+
+    info!("Test OK");
+    cortex_m::asm::bkpt();
+}
diff --git a/tests/stm32/src/bin/stop.rs b/tests/stm32/src/bin/stop.rs
index 1fe65d867..83c375bc5 100644
--- a/tests/stm32/src/bin/stop.rs
+++ b/tests/stm32/src/bin/stop.rs
@@ -7,21 +7,13 @@ mod common;
 
 use chrono::NaiveDate;
 use common::*;
-use cortex_m_rt::entry;
 use embassy_executor::Spawner;
-use embassy_stm32::Config;
-use embassy_stm32::low_power::{Executor, StopMode, stop_ready};
+use embassy_stm32::low_power::{StopMode, stop_ready};
 use embassy_stm32::rcc::LsConfig;
 use embassy_stm32::rtc::Rtc;
+use embassy_stm32::{Config, low_power};
 use embassy_time::Timer;
 
-#[entry]
-fn main() -> ! {
-    Executor::take().run(|spawner| {
-        spawner.spawn(unwrap!(async_main(spawner)));
-    });
-}
-
 #[embassy_executor::task]
 async fn task_1() {
     for _ in 0..9 {
@@ -43,7 +35,7 @@ async fn task_2() {
     cortex_m::asm::bkpt();
 }
 
-#[embassy_executor::task]
+#[embassy_executor::main(executor = "low_power::Executor")]
 async fn async_main(spawner: Spawner) {
     let _ = config();
 
diff --git a/tests/stm32/src/bin/wpan_ble.rs b/tests/stm32/src/bin/wpan_ble.rs
index 0f396b848..b4c0cbf56 100644
--- a/tests/stm32/src/bin/wpan_ble.rs
+++ b/tests/stm32/src/bin/wpan_ble.rs
@@ -32,7 +32,7 @@ bind_interrupts!(struct Irqs{
 const BLE_GAP_DEVICE_NAME_LENGTH: u8 = 7;
 
 #[embassy_executor::task]
-async fn run_mm_queue(memory_manager: mm::MemoryManager) {
+async fn run_mm_queue(mut memory_manager: mm::MemoryManager<'static>) {
     memory_manager.run_queue().await;
 }
 
@@ -45,14 +45,13 @@ async fn main(spawner: Spawner) {
     info!("Hello World!");
 
     let config = Config::default();
-    let mut mbox = TlMbox::init(p.IPCC, Irqs, config);
+    let mbox = TlMbox::init(p.IPCC, Irqs, config).await;
+    let mut sys = mbox.sys_subsystem;
+    let mut ble = mbox.ble_subsystem;
 
     spawner.spawn(run_mm_queue(mbox.mm_subsystem).unwrap());
 
-    let sys_event = mbox.sys_subsystem.read().await;
-    info!("sys event: {}", sys_event.payload());
-
-    let fw_info = mbox.sys_subsystem.wireless_fw_info().unwrap();
+    let fw_info = sys.wireless_fw_info().unwrap();
     let version_major = fw_info.version_major();
     let version_minor = fw_info.version_minor();
     let subversion = fw_info.subversion();
@@ -65,121 +64,108 @@ async fn main(spawner: Spawner) {
         version_major, version_minor, subversion, sram2a_size, sram2b_size
     );
 
-    let _ = mbox.sys_subsystem.shci_c2_ble_init(Default::default()).await;
+    let _ = sys.shci_c2_ble_init(Default::default()).await;
 
     info!("resetting BLE...");
-    mbox.ble_subsystem.reset().await;
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    ble.reset().await;
+    let response = ble.read().await.unwrap();
     info!("{}", response);
 
     info!("config public address...");
-    mbox.ble_subsystem
-        .write_config_data(&ConfigData::public_address(get_bd_addr()).build())
+    ble.write_config_data(&ConfigData::public_address(get_bd_addr()).build())
         .await;
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    let response = ble.read().await.unwrap();
     info!("{}", response);
 
     info!("config random address...");
-    mbox.ble_subsystem
-        .write_config_data(&ConfigData::random_address(get_random_addr()).build())
+    ble.write_config_data(&ConfigData::random_address(get_random_addr()).build())
         .await;
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    let response = ble.read().await.unwrap();
     info!("{}", response);
 
     info!("config identity root...");
-    mbox.ble_subsystem
-        .write_config_data(&ConfigData::identity_root(&get_irk()).build())
+    ble.write_config_data(&ConfigData::identity_root(&get_irk()).build())
         .await;
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    let response = ble.read().await.unwrap();
     info!("{}", response);
 
     info!("config encryption root...");
-    mbox.ble_subsystem
-        .write_config_data(&ConfigData::encryption_root(&get_erk()).build())
+    ble.write_config_data(&ConfigData::encryption_root(&get_erk()).build())
         .await;
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    let response = ble.read().await.unwrap();
     info!("{}", response);
 
     info!("config tx power level...");
-    mbox.ble_subsystem.set_tx_power_level(PowerLevel::ZerodBm).await;
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    ble.set_tx_power_level(PowerLevel::ZerodBm).await;
+    let response = ble.read().await.unwrap();
     info!("{}", response);
 
     info!("GATT init...");
-    mbox.ble_subsystem.init_gatt().await;
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    ble.init_gatt().await;
+    let response = ble.read().await.unwrap();
     info!("{}", response);
 
     info!("GAP init...");
-    mbox.ble_subsystem
-        .init_gap(Role::PERIPHERAL, false, BLE_GAP_DEVICE_NAME_LENGTH)
-        .await;
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    ble.init_gap(Role::PERIPHERAL, false, BLE_GAP_DEVICE_NAME_LENGTH).await;
+    let response = ble.read().await.unwrap();
     info!("{}", response);
 
     // info!("set scan response...");
-    // mbox.ble_subsystem.le_set_scan_response_data(&[]).await.unwrap();
-    // let response = mbox.ble_subsystem.read().await.unwrap();
+    // ble.le_set_scan_response_data(&[]).await.unwrap();
+    // let response = ble.read().await.unwrap();
     // info!("{}", response);
 
     info!("set discoverable...");
-    mbox.ble_subsystem
-        .set_discoverable(&DiscoverableParameters {
-            advertising_type: AdvertisingType::NonConnectableUndirected,
-            advertising_interval: Some((Duration::from_millis(250), Duration::from_millis(250))),
-            address_type: OwnAddressType::Public,
-            filter_policy: AdvertisingFilterPolicy::AllowConnectionAndScan,
-            local_name: None,
-            advertising_data: &[],
-            conn_interval: (None, None),
-        })
-        .await
-        .unwrap();
-
-    let response = mbox.ble_subsystem.read().await;
+    ble.set_discoverable(&DiscoverableParameters {
+        advertising_type: AdvertisingType::NonConnectableUndirected,
+        advertising_interval: Some((Duration::from_millis(250), Duration::from_millis(250))),
+        address_type: OwnAddressType::Public,
+        filter_policy: AdvertisingFilterPolicy::AllowConnectionAndScan,
+        local_name: None,
+        advertising_data: &[],
+        conn_interval: (None, None),
+    })
+    .await
+    .unwrap();
+
+    let response = ble.read().await;
     info!("{}", response);
 
     // remove some advertisement to decrease the packet size
     info!("delete tx power ad type...");
-    mbox.ble_subsystem
-        .delete_ad_type(AdvertisingDataType::TxPowerLevel)
-        .await;
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    ble.delete_ad_type(AdvertisingDataType::TxPowerLevel).await;
+    let response = ble.read().await.unwrap();
     info!("{}", response);
 
     info!("delete conn interval ad type...");
-    mbox.ble_subsystem
-        .delete_ad_type(AdvertisingDataType::PeripheralConnectionInterval)
+    ble.delete_ad_type(AdvertisingDataType::PeripheralConnectionInterval)
         .await;
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    let response = ble.read().await.unwrap();
     info!("{}", response);
 
     info!("update advertising data...");
-    mbox.ble_subsystem
-        .update_advertising_data(&eddystone_advertising_data())
+    ble.update_advertising_data(&eddystone_advertising_data())
         .await
         .unwrap();
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    let response = ble.read().await.unwrap();
     info!("{}", response);
 
     info!("update advertising data type...");
-    mbox.ble_subsystem
-        .update_advertising_data(&[3, AdvertisingDataType::UuidCompleteList16 as u8, 0xaa, 0xfe])
+    ble.update_advertising_data(&[3, AdvertisingDataType::UuidCompleteList16 as u8, 0xaa, 0xfe])
         .await
         .unwrap();
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    let response = ble.read().await.unwrap();
     info!("{}", response);
 
     info!("update advertising data flags...");
-    mbox.ble_subsystem
-        .update_advertising_data(&[
-            2,
-            AdvertisingDataType::Flags as u8,
-            (0x02 | 0x04) as u8, // BLE general discoverable, without BR/EDR support
-        ])
-        .await
-        .unwrap();
-    let response = mbox.ble_subsystem.read().await.unwrap();
+    ble.update_advertising_data(&[
+        2,
+        AdvertisingDataType::Flags as u8,
+        (0x02 | 0x04) as u8, // BLE general discoverable, without BR/EDR support
+    ])
+    .await
+    .unwrap();
+    let response = ble.read().await.unwrap();
     info!("{}", response);
 
     info!("Test OK");
diff --git a/tests/stm32/src/bin/wpan_mac.rs b/tests/stm32/src/bin/wpan_mac.rs
index f27146c44..42db39e7e 100644
--- a/tests/stm32/src/bin/wpan_mac.rs
+++ b/tests/stm32/src/bin/wpan_mac.rs
@@ -25,7 +25,7 @@ bind_interrupts!(struct Irqs{
 });
 
 #[embassy_executor::task]
-async fn run_mm_queue(memory_manager: mm::MemoryManager) {
+async fn run_mm_queue(mut memory_manager: mm::MemoryManager<'static>) {
     memory_manager.run_queue().await;
 }
 
@@ -38,20 +38,17 @@ async fn main(spawner: Spawner) {
     info!("Hello World!");
 
     let config = Config::default();
-    let mbox = TlMbox::init(p.IPCC, Irqs, config);
+    let mbox = TlMbox::init(p.IPCC, Irqs, config).await;
+    let mut sys = mbox.sys_subsystem;
+    let (mut mac_rx, mut mac_tx) = mbox.mac_subsystem.split();
 
     spawner.spawn(run_mm_queue(mbox.mm_subsystem).unwrap());
 
-    let sys_event = mbox.sys_subsystem.read().await;
-    info!("sys event: {}", sys_event.payload());
-
-    core::mem::drop(sys_event);
-
-    let result = mbox.sys_subsystem.shci_c2_mac_802_15_4_init().await;
+    let result = sys.shci_c2_mac_802_15_4_init().await;
     info!("initialized mac: {}", result);
 
     info!("resetting");
-    mbox.mac_subsystem
+    mac_tx
         .send_command(&ResetRequest {
             set_default_pib: true,
             ..Default::default()
@@ -59,13 +56,13 @@ async fn main(spawner: Spawner) {
         .await
         .unwrap();
     {
-        let evt = mbox.mac_subsystem.read().await.unwrap();
+        let evt = mac_rx.read().await.unwrap();
         info!("{:#x}", evt);
     }
 
     info!("setting extended address");
     let extended_address: u64 = 0xACDE480000000002;
-    mbox.mac_subsystem
+    mac_tx
         .send_command(&SetRequest {
             pib_attribute_ptr: &extended_address as *const _ as *const u8,
             pib_attribute: PibId::ExtendedAddress,
@@ -73,12 +70,12 @@ async fn main(spawner: Spawner) {
         .await
         .unwrap();
     {
-        let evt = mbox.mac_subsystem.read().await.unwrap();
+        let evt = mac_rx.read().await.unwrap();
         info!("{:#x}", evt);
     }
 
     info!("getting extended address");
-    mbox.mac_subsystem
+    mac_tx
         .send_command(&GetRequest {
             pib_attribute: PibId::ExtendedAddress,
             ..Default::default()
@@ -87,7 +84,7 @@ async fn main(spawner: Spawner) {
         .unwrap();
 
     {
-        let evt = mbox.mac_subsystem.read().await.unwrap();
+        let evt = mac_rx.read().await.unwrap();
         info!("{:#x}", evt);
 
         if let MacEvent::MlmeGetCnf(evt) = evt {
@@ -113,8 +110,8 @@ async fn main(spawner: Spawner) {
         key_index: 152,
     };
     info!("{}", a);
-    mbox.mac_subsystem.send_command(&a).await.unwrap();
-    let short_addr = if let MacEvent::MlmeAssociateCnf(conf) = mbox.mac_subsystem.read().await.unwrap() {
+    mac_tx.send_command(&a).await.unwrap();
+    let short_addr = if let MacEvent::MlmeAssociateCnf(conf) = mac_rx.read().await.unwrap() {
         conf.assoc_short_address
     } else {
         defmt::panic!()
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 096cce947..9f88b182a 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -259,6 +259,7 @@ define_peris!(
 define_peris!(
     UART = LPUART1, UART_TX = PB5, UART_RX = PA10, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
     SPI = SPI1, SPI_SCK = PB4, SPI_MOSI = PA15, SPI_MISO = PB3, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
+    ADC = ADC4, DAC_PIN = PA0,
     @irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
 );
 #[cfg(feature = "stm32h7s3l8")]