aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--embassy-nrf/src/spim.rs24
1 files changed, 17 insertions, 7 deletions
diff --git a/embassy-nrf/src/spim.rs b/embassy-nrf/src/spim.rs
index c84861f30..5d55a3cce 100644
--- a/embassy-nrf/src/spim.rs
+++ b/embassy-nrf/src/spim.rs
@@ -9,7 +9,8 @@ use embassy_extras::unborrow;
9use futures::future::poll_fn; 9use futures::future::poll_fn;
10use traits::spi::FullDuplex; 10use traits::spi::FullDuplex;
11 11
12use crate::gpio::Pin as GpioPin; 12use crate::gpio::sealed::Pin as _;
13use crate::gpio::{OptionalPin, Pin as GpioPin};
13use crate::interrupt::{self, Interrupt}; 14use crate::interrupt::{self, Interrupt};
14use crate::{pac, peripherals, slice_in_ram_or}; 15use crate::{pac, peripherals, slice_in_ram_or};
15 16
@@ -43,8 +44,8 @@ impl<'d, T: Instance> Spim<'d, T> {
43 spim: impl PeripheralBorrow<Target = T> + 'd, 44 spim: impl PeripheralBorrow<Target = T> + 'd,
44 irq: impl PeripheralBorrow<Target = T::Interrupt> + 'd, 45 irq: impl PeripheralBorrow<Target = T::Interrupt> + 'd,
45 sck: impl PeripheralBorrow<Target = impl GpioPin> + 'd, 46 sck: impl PeripheralBorrow<Target = impl GpioPin> + 'd,
46 miso: impl PeripheralBorrow<Target = impl GpioPin> + 'd, 47 miso: impl PeripheralBorrow<Target = impl OptionalPin> + 'd,
47 mosi: impl PeripheralBorrow<Target = impl GpioPin> + 'd, 48 mosi: impl PeripheralBorrow<Target = impl OptionalPin> + 'd,
48 config: Config, 49 config: Config,
49 ) -> Self { 50 ) -> Self {
50 unborrow!(spim, irq, sck, miso, mosi); 51 unborrow!(spim, irq, sck, miso, mosi);
@@ -53,21 +54,30 @@ impl<'d, T: Instance> Spim<'d, T> {
53 54
54 // Configure pins 55 // Configure pins
55 sck.conf().write(|w| w.dir().output().drive().h0h1()); 56 sck.conf().write(|w| w.dir().output().drive().h0h1());
56 mosi.conf().write(|w| w.dir().output().drive().h0h1()); 57 if let Some(mosi) = mosi.pin_mut() {
57 miso.conf().write(|w| w.input().connect().drive().h0h1()); 58 mosi.conf().write(|w| w.dir().output().drive().h0h1());
59 }
60 if let Some(miso) = miso.pin_mut() {
61 miso.conf().write(|w| w.input().connect().drive().h0h1());
62 }
58 63
59 match config.mode.polarity { 64 match config.mode.polarity {
60 Polarity::IdleHigh => { 65 Polarity::IdleHigh => {
61 sck.set_high(); 66 sck.set_high();
62 mosi.set_high(); 67 if let Some(mosi) = mosi.pin_mut() {
68 mosi.set_high();
69 }
63 } 70 }
64 Polarity::IdleLow => { 71 Polarity::IdleLow => {
65 sck.set_low(); 72 sck.set_low();
66 mosi.set_low(); 73 if let Some(mosi) = mosi.pin_mut() {
74 mosi.set_low();
75 }
67 } 76 }
68 } 77 }
69 78
70 // Select pins. 79 // Select pins.
80 // Note: OptionalPin reports 'disabled' for psel_bits when no pin was selected.
71 r.psel.sck.write(|w| unsafe { w.bits(sck.psel_bits()) }); 81 r.psel.sck.write(|w| unsafe { w.bits(sck.psel_bits()) });
72 r.psel.mosi.write(|w| unsafe { w.bits(mosi.psel_bits()) }); 82 r.psel.mosi.write(|w| unsafe { w.bits(mosi.psel_bits()) });
73 r.psel.miso.write(|w| unsafe { w.bits(miso.psel_bits()) }); 83 r.psel.miso.write(|w| unsafe { w.bits(miso.psel_bits()) });