16 files changed, 703 insertions, 24 deletions

diff --git a/docs/pages/embassy_in_the_wild.adoc b/docs/pages/embassy_in_the_wild.adoc
index b0a16fc4c..0792130eb 100644
--- a/docs/pages/embassy_in_the_wild.adoc
+++ b/docs/pages/embassy_in_the_wild.adoc
@@ -6,6 +6,8 @@ _newer entries at the top_
 
 * link:https://github.com/thataquarel/protovolt[ProtoV MINI: A USB-C mini lab power supply]
 ** A dual-channel USB PD powered breadboard power supply based on the RP2040, running embedded graphics. Open-source schematics and firmware.
+* link:https://github.com/Dawson-HEP/opentrig/[Opentrig: A particle physics trigger and data acquisition system]
+** Digital event trigger with threshold, data acquisition system designed to interface with AIDA-2020 TLU systems, tested at the DESY II Test Beam Facility. Based on the RP2040, and Embassy's async event handling.
 * link:https://github.com/1-rafael-1/air-quality-monitor[Air Quality Monitor]
 ** Air Quality Monitor based on rp2350 board, ens160 and aht21 sensors and ssd1306 display. Code and 3D printable enclosure included.
 * link:https://github.com/CarlKCarlK/clock[Embassy Clock: Layered, modular bare-metal clock with emulation]
diff --git a/embassy-stm32/CHANGELOG.md b/embassy-stm32/CHANGELOG.md
index df1d909b7..91785143f 100644
--- a/embassy-stm32/CHANGELOG.md
+++ b/embassy-stm32/CHANGELOG.md
@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ## Unreleased - ReleaseDate
 
+- feat: Add support for injected ADC measurements for g4 ([#4840](https://github.com/embassy-rs/embassy/pull/4840))
+- feat: Implement into_ring_buffered for g4 ([#4840](https://github.com/embassy-rs/embassy/pull/4840))
 - feat: stm32/hrtim add new_chx_with_config to provide pin configuration
 - fix flash erase on L4 & L5
 - fix: Fixed STM32H5 builds requiring time feature
@@ -37,6 +39,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - feat: timer: add ability to set master mode
 - fix: sdmmc: don't wait for DBCKEND flag on sdmmc_v2 devices as it never fires (Fixes #4723)
 - fix: usart: fix race condition in ringbuffered usart
+- feat: Add backup_sram::init() for H5 devices to access BKPSRAM
 - feat: Add I2C MultiMaster (Slave) support for I2C v1
 - feat: stm32/fdcan: add ability to control automatic recovery from bus off ([#4821](https://github.com/embassy-rs/embassy/pull/4821))
 - low-power: update rtc api to allow reconfig
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index eea1acf68..2800c73ac 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -114,6 +114,8 @@ fn main() {
         }
     };
 
+    let has_bkpsram = memory.iter().any(|m| m.name == "BKPSRAM");
+
     // ========
     // Generate singletons
 
@@ -124,6 +126,13 @@ fn main() {
         singletons.push(p.name.to_string());
     }
 
+    cfgs.declare("backup_sram");
+
+    if has_bkpsram {
+        singletons.push("BKPSRAM".to_string());
+        cfgs.enable("backup_sram")
+    }
+
     // generate one singleton per peripheral (with many exceptions...)
     for p in METADATA.peripherals {
         if let Some(r) = &p.registers {
@@ -1985,6 +1994,18 @@ fn main() {
     ));
 
     // ========
+    // Generate backup sram constants
+    if let Some(m) = memory.iter().find(|m| m.name == "BKPSRAM") {
+        let bkpsram_base = m.address as usize;
+        let bkpsram_size = m.size as usize;
+
+        g.extend(quote!(
+            pub const BKPSRAM_BASE: usize = #bkpsram_base;
+            pub const BKPSRAM_SIZE: usize = #bkpsram_size;
+        ));
+    }
+
+    // ========
     // Generate flash constants
 
     let flash_regions: Vec<&MemoryRegion> = memory
diff --git a/embassy-stm32/src/adc/g4.rs b/embassy-stm32/src/adc/g4.rs
index 5098aadd8..3767820cf 100644
--- a/embassy-stm32/src/adc/g4.rs
+++ b/embassy-stm32/src/adc/g4.rs
@@ -1,11 +1,14 @@
+use core::mem;
+
 #[allow(unused)]
 #[cfg(stm32h7)]
 use pac::adc::vals::{Adcaldif, Difsel, Exten};
 #[allow(unused)]
 #[cfg(stm32g4)]
-use pac::adc::vals::{Adcaldif, Difsel, Exten, Rovsm, Trovs};
-use pac::adccommon::vals::Presc;
-use stm32_metapac::adc::vals::{Adstp, Dmacfg, Dmaen};
+pub use pac::adc::vals::{Adcaldif, Difsel, Exten, Rovsm, Trovs};
+pub use pac::adccommon::vals::Presc;
+pub use stm32_metapac::adc::vals::{Adstp, Dmacfg, Dmaen};
+pub use stm32_metapac::adccommon::vals::Dual;
 
 use super::{Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, blocking_delay_us};
 use crate::adc::SealedAdcChannel;
@@ -13,11 +16,19 @@ use crate::dma::Transfer;
 use crate::time::Hertz;
 use crate::{Peri, pac, rcc};
 
+mod ringbuffered;
+pub use ringbuffered::RingBufferedAdc;
+
+mod injected;
+pub use injected::InjectedAdc;
+
 /// Default VREF voltage used for sample conversion to millivolts.
 pub const VREF_DEFAULT_MV: u32 = 3300;
 /// VREF voltage used for factory calibration of VREFINTCAL register.
 pub const VREF_CALIB_MV: u32 = 3300;
 
+const NR_INJECTED_RANKS: usize = 4;
+
 /// Max single ADC operation clock frequency
 #[cfg(stm32g4)]
 const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(60);
@@ -120,6 +131,24 @@ impl Prescaler {
     }
 }
 
+// Trigger source for ADC conversions¨
+#[derive(Copy, Clone)]
+pub struct ConversionTrigger {
+    // See Table 166 and 167 in RM0440 Rev 9 for ADC1/2 External triggers
+    // Note that Injected and Regular channels uses different mappings
+    pub channel: u8,
+    pub edge: Exten,
+}
+
+// Conversion mode for regular ADC channels
+#[derive(Copy, Clone)]
+pub enum RegularConversionMode {
+    // Samples as fast as possible
+    Continuous,
+    // Sample at rate determined by external trigger
+    Triggered(ConversionTrigger),
+}
+
 impl<'d, T: Instance> Adc<'d, T> {
     /// Create a new ADC driver.
     pub fn new(adc: Peri<'d, T>) -> Self {
@@ -357,7 +386,29 @@ impl<'d, T: Instance> Adc<'d, T> {
         self.read_channel(channel)
     }
 
-    /// Read one or multiple ADC channels using DMA.
+    /// Start regular adc conversion
+    pub(super) fn start() {
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
+    }
+
+    /// Stop regular conversions
+    pub(super) fn stop() {
+        Self::stop_regular_conversions();
+    }
+
+    /// Teardown method for stopping regular ADC conversions
+    pub(super) fn teardown_adc() {
+        Self::stop_regular_conversions();
+
+        // Disable dma control
+        T::regs().cfgr().modify(|reg| {
+            reg.set_dmaen(Dmaen::DISABLE);
+        });
+    }
+
+    /// Read one or multiple ADC regular channels using DMA.
     ///
     /// `sequence` iterator and `readings` must have the same length.
     ///
@@ -382,6 +433,9 @@ impl<'d, T: Instance> Adc<'d, T> {
     /// .await;
     /// defmt::info!("measurements: {}", measurements);
     /// ```
+    ///
+    /// Note: This is not very efficient as the ADC needs to be reconfigured for each read. Use
+    /// `into_ring_buffered`, `into_ring_buffered_and_injected`
     pub async fn read(
         &mut self,
         rx_dma: Peri<'_, impl RxDma<T>>,
@@ -399,18 +453,16 @@ impl<'d, T: Instance> Adc<'d, T> {
         );
 
         // Ensure no conversions are ongoing and ADC is enabled.
-        Self::cancel_conversions();
+        Self::stop_regular_conversions();
         self.enable();
 
         // Set sequence length
         T::regs().sqr1().modify(|w| {
             w.set_l(sequence.len() as u8 - 1);
         });
-
         // Configure channels and ranks
         for (_i, (channel, sample_time)) in sequence.enumerate() {
             Self::configure_channel(channel, sample_time);
-
             match _i {
                 0..=3 => {
                     T::regs().sqr1().modify(|w| {
@@ -469,7 +521,7 @@ impl<'d, T: Instance> Adc<'d, T> {
         transfer.await;
 
         // Ensure conversions are finished.
-        Self::cancel_conversions();
+        Self::stop_regular_conversions();
 
         // Reset configuration.
         T::regs().cfgr().modify(|reg| {
@@ -477,6 +529,277 @@ impl<'d, T: Instance> Adc<'d, T> {
         });
     }
 
+    /// Set external trigger for regular conversion sequence
+    fn set_regular_conversion_trigger(&mut self, trigger: ConversionTrigger) {
+        T::regs().cfgr().modify(|r| {
+            r.set_extsel(trigger.channel);
+            r.set_exten(trigger.edge);
+        });
+        // Regular conversions uses DMA so no need to generate interrupt
+        T::regs().ier().modify(|r| r.set_eosie(false));
+    }
+
+    // Dual ADC mode selection
+    pub fn configure_dual_mode(&mut self, val: Dual) {
+        T::common_regs().ccr().modify(|reg| {
+            reg.set_dual(val);
+        })
+    }
+
+    /// Configures the ADC to use a DMA ring buffer for continuous data acquisition.
+    ///
+    /// Use the [`read`] method to retrieve measurements from the DMA ring buffer. The read buffer
+    /// should be exactly half the size of `dma_buf`. When using triggered mode, it is recommended
+    /// to configure `dma_buf` as a double buffer so that one half can be read while the other half
+    /// is being filled by the DMA, preventing data loss. The trigger period of the ADC effectively
+    /// defines the period at which the buffer should be read.
+    ///
+    /// If continous conversion mode is selected, the provided `dma_buf` must be large enough to prevent
+    /// DMA buffer overruns. Its length should be a multiple of the number of ADC channels being measured.
+    /// For example, if 3 channels are measured and you want to store 40 samples per channel,
+    /// the buffer length should be `3 * 40 = 120`.
+    ///
+    /// # Parameters
+    /// - `dma`: The DMA peripheral used to transfer ADC data into the buffer.
+    /// - `dma_buf`: The buffer where DMA stores ADC samples.
+    /// - `regular_sequence`: Sequence of channels and sample times for regular ADC conversions.
+    /// - `regular_conversion_mode`: Mode for regular conversions (continuous or triggered).
+    ///
+    /// # Returns
+    /// A `RingBufferedAdc<'a, T>` instance configured for continuous DMA-based sampling.
+    pub fn into_ring_buffered<'a>(
+        mut self,
+        dma: Peri<'a, impl RxDma<T>>,
+        dma_buf: &'a mut [u16],
+        sequence: impl ExactSizeIterator<Item = (AnyAdcChannel<T>, SampleTime)>,
+        mode: RegularConversionMode,
+    ) -> RingBufferedAdc<'a, T> {
+        assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
+        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
+        assert!(
+            sequence.len() <= 16,
+            "Asynchronous read sequence cannot be more than 16 in length"
+        );
+        // reset conversions and enable the adc
+        Self::stop_regular_conversions();
+        self.enable();
+
+        //adc side setup
+
+        // Set sequence length
+        T::regs().sqr1().modify(|w| {
+            w.set_l(sequence.len() as u8 - 1);
+        });
+
+        // Configure channels and ranks
+        for (_i, (mut channel, sample_time)) in sequence.enumerate() {
+            Self::configure_channel(&mut channel, sample_time);
+
+            match _i {
+                0..=3 => {
+                    T::regs().sqr1().modify(|w| {
+                        w.set_sq(_i, channel.channel());
+                    });
+                }
+                4..=8 => {
+                    T::regs().sqr2().modify(|w| {
+                        w.set_sq(_i - 4, channel.channel());
+                    });
+                }
+                9..=13 => {
+                    T::regs().sqr3().modify(|w| {
+                        w.set_sq(_i - 9, channel.channel());
+                    });
+                }
+                14..=15 => {
+                    T::regs().sqr4().modify(|w| {
+                        w.set_sq(_i - 14, channel.channel());
+                    });
+                }
+                _ => unreachable!(),
+            }
+        }
+
+        // Clear overrun flag before starting transfer.
+        T::regs().isr().modify(|reg| {
+            reg.set_ovr(true);
+        });
+
+        T::regs().cfgr().modify(|reg| {
+            reg.set_discen(false); // Convert all channels for each trigger
+            reg.set_dmacfg(Dmacfg::CIRCULAR);
+            reg.set_dmaen(Dmaen::ENABLE);
+        });
+
+        match mode {
+            RegularConversionMode::Continuous => {
+                T::regs().cfgr().modify(|reg| {
+                    reg.set_cont(true);
+                });
+            }
+            RegularConversionMode::Triggered(trigger) => {
+                T::regs().cfgr().modify(|r| {
+                    r.set_cont(false); // New trigger is neede for each sample to be read
+                });
+                self.set_regular_conversion_trigger(trigger);
+            }
+        }
+
+        mem::forget(self);
+
+        RingBufferedAdc::new(dma, dma_buf)
+    }
+
+    /// Configures the ADC for injected conversions.
+    ///
+    /// Injected conversions are separate from the regular conversion sequence and are typically
+    /// triggered by software or an external event. This method sets up a fixed-length sequence of
+    /// injected channels with specified sample times, the trigger source, and whether the end-of-sequence
+    /// interrupt should be enabled.
+    ///
+    /// # Parameters
+    /// - `sequence`: An array of tuples containing the ADC channels and their sample times. The length
+    ///   `N` determines the number of injected ranks to configure (maximum 4 for STM32).
+    /// - `trigger`: The trigger source that starts the injected conversion sequence.
+    /// - `interrupt`: If `true`, enables the end-of-sequence (JEOS) interrupt for injected conversions.
+    ///
+    /// # Returns
+    /// An `InjectedAdc<T, N>` instance that represents the configured injected sequence. The returned
+    /// type encodes the sequence length `N` in its type, ensuring that reads return exactly `N` samples.
+    ///
+    /// # Panics
+    /// This function will panic if:
+    /// - `sequence` is empty.
+    /// - `sequence` length exceeds the maximum number of injected ranks (`NR_INJECTED_RANKS`).
+    ///
+    /// # Notes
+    /// - Injected conversions can run independently of regular ADC conversions.
+    /// - The order of channels in `sequence` determines the rank order in the injected sequence.
+    /// - Accessing samples beyond `N` will result in a panic; use the returned type
+    ///   `InjectedAdc<T, N>` to enforce bounds at compile time.
+    pub fn setup_injected_conversions<'a, const N: usize>(
+        mut self,
+        sequence: [(AnyAdcChannel<T>, SampleTime); N],
+        trigger: ConversionTrigger,
+        interrupt: bool,
+    ) -> InjectedAdc<T, N> {
+        assert!(N != 0, "Read sequence cannot be empty");
+        assert!(
+            N <= NR_INJECTED_RANKS,
+            "Read sequence cannot be more than {} in length",
+            NR_INJECTED_RANKS
+        );
+
+        Self::stop_regular_conversions();
+        self.enable();
+
+        T::regs().jsqr().modify(|w| w.set_jl(N as u8 - 1));
+
+        for (n, (mut channel, sample_time)) in sequence.into_iter().enumerate() {
+            Self::configure_channel(&mut channel, sample_time);
+
+            let idx = match n {
+                0..=3 => n,
+                4..=8 => n - 4,
+                9..=13 => n - 9,
+                14..=15 => n - 14,
+                _ => unreachable!(),
+            };
+
+            T::regs().jsqr().modify(|w| w.set_jsq(idx, channel.channel()));
+        }
+
+        T::regs().cfgr().modify(|reg| reg.set_jdiscen(false));
+
+        self.set_injected_conversion_trigger(trigger);
+        self.enable_injected_eos_interrupt(interrupt);
+        Self::start_injected_conversions();
+
+        InjectedAdc::new(sequence) // InjectedAdc<'a, T, N> now borrows the channels
+    }
+
+    /// Configures ADC for both regular conversions with a ring-buffered DMA and injected conversions.
+    ///
+    /// # Parameters
+    /// - `dma`: The DMA peripheral to use for the ring-buffered ADC transfers.
+    /// - `dma_buf`: The buffer to store DMA-transferred samples for regular conversions.
+    /// - `regular_sequence`: The sequence of channels and their sample times for regular conversions.
+    /// - `regular_conversion_mode`: The mode for regular conversions (e.g., continuous or triggered).
+    /// - `injected_sequence`: An array of channels and sample times for injected conversions (length `N`).
+    /// - `injected_trigger`: The trigger source for injected conversions.
+    /// - `injected_interrupt`: Whether to enable the end-of-sequence interrupt for injected conversions.
+    ///
+    /// Injected conversions are typically used with interrupts. If ADC1 and ADC2 are used in dual mode,
+    /// it is recommended to enable interrupts only for the ADC whose sequence takes the longest to complete.
+    ///
+    /// # Returns
+    /// A tuple containing:
+    /// 1. `RingBufferedAdc<'a, T>` — the configured ADC for regular conversions using DMA.
+    /// 2. `InjectedAdc<T, N>` — the configured ADC for injected conversions.
+    ///
+    /// # Safety
+    /// This function is `unsafe` because it clones the ADC peripheral handle unchecked. Both the
+    /// `RingBufferedAdc` and `InjectedAdc` take ownership of the handle and drop it independently.
+    /// Ensure no other code concurrently accesses the same ADC instance in a conflicting way.
+    pub fn into_ring_buffered_and_injected<'a, const N: usize>(
+        self,
+        dma: Peri<'a, impl RxDma<T>>,
+        dma_buf: &'a mut [u16],
+        regular_sequence: impl ExactSizeIterator<Item = (AnyAdcChannel<T>, SampleTime)>,
+        regular_conversion_mode: RegularConversionMode,
+        injected_sequence: [(AnyAdcChannel<T>, SampleTime); N],
+        injected_trigger: ConversionTrigger,
+        injected_interrupt: bool,
+    ) -> (RingBufferedAdc<'a, T>, InjectedAdc<T, N>) {
+        unsafe {
+            (
+                Self {
+                    adc: self.adc.clone_unchecked(),
+                    sample_time: self.sample_time,
+                }
+                .into_ring_buffered(dma, dma_buf, regular_sequence, regular_conversion_mode),
+                Self {
+                    adc: self.adc.clone_unchecked(),
+                    sample_time: self.sample_time,
+                }
+                .setup_injected_conversions(injected_sequence, injected_trigger, injected_interrupt),
+            )
+        }
+    }
+
+    /// Stop injected conversions
+    pub(super) fn stop_injected_conversions() {
+        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
+            T::regs().cr().modify(|reg| {
+                reg.set_jadstp(Adstp::STOP);
+            });
+            // The software must poll JADSTART until the bit is reset before assuming the
+            // ADC is completely stopped
+            while T::regs().cr().read().jadstart() {}
+        }
+    }
+
+    /// Start injected ADC conversion
+    pub(super) fn start_injected_conversions() {
+        T::regs().cr().modify(|reg| {
+            reg.set_jadstart(true);
+        });
+    }
+
+    /// Set external trigger for injected conversion sequence
+    /// Possible trigger values are seen in Table 167 in RM0440 Rev 9
+    fn set_injected_conversion_trigger(&mut self, trigger: ConversionTrigger) {
+        T::regs().jsqr().modify(|r| {
+            r.set_jextsel(trigger.channel);
+            r.set_jexten(trigger.edge);
+        });
+    }
+
+    /// Enable end of injected sequence interrupt
+    fn enable_injected_eos_interrupt(&mut self, enable: bool) {
+        T::regs().ier().modify(|r| r.set_jeosie(enable));
+    }
+
     fn configure_channel(channel: &mut impl AdcChannel<T>, sample_time: SampleTime) {
         // Configure channel
         Self::set_channel_sample_time(channel.channel(), sample_time);
@@ -509,16 +832,34 @@ impl<'d, T: Instance> Adc<'d, T> {
         }
     }
 
-    fn cancel_conversions() {
+    // Stop regular conversions
+    fn stop_regular_conversions() {
         if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
             T::regs().cr().modify(|reg| {
                 reg.set_adstp(Adstp::STOP);
             });
+            // The software must poll ADSTART until the bit is reset before assuming the
+            // ADC is completely stopped
             while T::regs().cr().read().adstart() {}
         }
     }
 }
 
+impl<T: Instance, const N: usize> InjectedAdc<T, N> {
+    /// Read sampled data from all injected ADC injected ranks
+    /// Clear the JEOS flag to allow a new injected sequence
+    pub(super) fn read_injected_data() -> [u16; N] {
+        let mut data = [0u16; N];
+        for i in 0..N {
+            data[i] = T::regs().jdr(i).read().jdata();
+        }
+
+        // Clear JEOS by writing 1
+        T::regs().isr().modify(|r| r.set_jeos(true));
+        data
+    }
+}
+
 /// Implemented for ADCs that have a Temperature channel
 pub trait TemperatureChannel {
     const CHANNEL: u8;
diff --git a/embassy-stm32/src/adc/injected.rs b/embassy-stm32/src/adc/injected.rs
new file mode 100644
index 000000000..0e4fe5847
--- /dev/null
+++ b/embassy-stm32/src/adc/injected.rs
@@ -0,0 +1,44 @@
+use core::marker::PhantomData;
+use core::sync::atomic::{Ordering, compiler_fence};
+
+#[allow(unused_imports)]
+use embassy_hal_internal::Peri;
+
+use super::{AnyAdcChannel, SampleTime};
+use crate::adc::Adc;
+#[allow(unused_imports)]
+use crate::adc::Instance;
+
+/// Injected ADC sequence with owned channels.
+pub struct InjectedAdc<T: Instance, const N: usize> {
+    _channels: [(AnyAdcChannel<T>, SampleTime); N],
+    _phantom: PhantomData<T>,
+}
+
+impl<T: Instance, const N: usize> InjectedAdc<T, N> {
+    pub(crate) fn new(channels: [(AnyAdcChannel<T>, SampleTime); N]) -> Self {
+        Self {
+            _channels: channels,
+            _phantom: PhantomData,
+        }
+    }
+
+    pub fn stop_injected_conversions(&mut self) {
+        Adc::<T>::stop_injected_conversions()
+    }
+
+    pub fn start_injected_conversions(&mut self) {
+        Adc::<T>::start_injected_conversions()
+    }
+
+    pub fn read_injected_samples(&mut self) -> [u16; N] {
+        InjectedAdc::<T, N>::read_injected_data()
+    }
+}
+
+impl<T: Instance, const N: usize> Drop for InjectedAdc<T, N> {
+    fn drop(&mut self) {
+        Adc::<T>::teardown_adc();
+        compiler_fence(Ordering::SeqCst);
+    }
+}
diff --git a/embassy-stm32/src/adc/ringbuffered.rs b/embassy-stm32/src/adc/ringbuffered.rs
index 1f384efb5..971c8195c 100644
--- a/embassy-stm32/src/adc/ringbuffered.rs
+++ b/embassy-stm32/src/adc/ringbuffered.rs
@@ -63,14 +63,17 @@ impl<'d, T: Instance> RingBufferedAdc<'d, T> {
     /// Reads measurements from the DMA ring buffer.
     ///
     /// This method fills the provided `measurements` array with ADC readings from the DMA buffer.
-    /// The length of the `measurements` array should be exactly half of the DMA buffer length. Because interrupts are only generated if half or full DMA transfer completes.
+    /// The length of the `measurements` array should be exactly half of the DMA buffer length.
+    /// Because interrupts are only generated if half or full DMA transfer completes.
     ///
-    /// Each call to `read` will populate the `measurements` array in the same order as the channels defined with `sequence`.
-    /// There will be many sequences worth of measurements in this array because it only returns if at least half of the DMA buffer is filled.
-    /// For example if 2 channels are sampled `measurements` contain: `[sq0 sq1 sq0 sq1 sq0 sq1 ..]`.
+    /// Each call to `read` will populate the `measurements` array in the same order as the channels
+    /// defined with `sequence`. There will be many sequences worth of measurements in this array
+    /// because it only returns if at least half of the DMA buffer is filled. For example if 2
+    /// channels are sampled `measurements` contain: `[sq0 sq1 sq0 sq1 sq0 sq1 ..]`.
     ///
-    /// Note that the ADC Datarate can be very fast, it is suggested to use DMA mode inside tightly running tasks
-    /// Otherwise, you'll see constant Overrun errors occuring, this means that you're sampling too quickly for the task to handle, and you may need to increase the buffer size.
+    /// Note that the ADC Datarate can be very fast, it is suggested to use DMA mode inside tightly
+    /// running tasks. Otherwise, you'll see constant Overrun errors occurring, this means that
+    /// you're sampling too quickly for the task to handle, and you may need to increase the buffer size.
     /// Example:
     /// ```rust,ignore
     /// const DMA_BUF_LEN: usize = 120;
diff --git a/embassy-stm32/src/backup_sram.rs b/embassy-stm32/src/backup_sram.rs
new file mode 100644
index 000000000..31b373c6c
--- /dev/null
+++ b/embassy-stm32/src/backup_sram.rs
@@ -0,0 +1,28 @@
+//! Battary backed SRAM
+
+use core::slice;
+
+use embassy_hal_internal::Peri;
+
+use crate::_generated::{BKPSRAM_BASE, BKPSRAM_SIZE};
+use crate::peripherals::BKPSRAM;
+
+/// Struct used to initilize backup sram
+pub struct BackupMemory {}
+
+impl BackupMemory {
+    /// Setup battery backed sram
+    ///
+    /// Returns slice to sram and whether the sram was retained
+    pub fn new(_backup_sram: Peri<'static, BKPSRAM>) -> (&'static mut [u8], bool) {
+        // Assert bksram has been enabled in rcc
+        assert!(crate::pac::PWR.bdcr().read().bren() == crate::pac::pwr::vals::Retention::PRESERVED);
+
+        unsafe {
+            (
+                slice::from_raw_parts_mut(BKPSRAM_BASE as *mut u8, BKPSRAM_SIZE),
+                critical_section::with(|_| crate::rcc::BKSRAM_RETAINED),
+            )
+        }
+    }
+}
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs
index 85606e7de..e08ab30e6 100644
--- a/embassy-stm32/src/lib.rs
+++ b/embassy-stm32/src/lib.rs
@@ -54,6 +54,8 @@ pub mod timer;
 
 #[cfg(adc)]
 pub mod adc;
+#[cfg(backup_sram)]
+pub mod backup_sram;
 #[cfg(can)]
 pub mod can;
 // FIXME: Cordic driver cause stm32u5a5zj crash
diff --git a/embassy-stm32/src/rcc/bd.rs b/embassy-stm32/src/rcc/bd.rs
index 3b2a10581..5b367c043 100644
--- a/embassy-stm32/src/rcc/bd.rs
+++ b/embassy-stm32/src/rcc/bd.rs
@@ -1,6 +1,8 @@
 use core::sync::atomic::{Ordering, compiler_fence};
 
 use crate::pac::common::{RW, Reg};
+#[cfg(backup_sram)]
+use crate::pac::pwr::vals::Retention;
 pub use crate::pac::rcc::vals::Rtcsel as RtcClockSource;
 use crate::time::Hertz;
 
@@ -89,6 +91,8 @@ pub struct LsConfig {
     pub rtc: RtcClockSource,
     pub lsi: bool,
     pub lse: Option<LseConfig>,
+    #[cfg(backup_sram)]
+    pub enable_backup_sram: bool,
 }
 
 impl LsConfig {
@@ -113,6 +117,8 @@ impl LsConfig {
                 peripherals_clocked: false,
             }),
             lsi: false,
+            #[cfg(backup_sram)]
+            enable_backup_sram: false,
         }
     }
 
@@ -121,6 +127,8 @@ impl LsConfig {
             rtc: RtcClockSource::LSI,
             lsi: true,
             lse: None,
+            #[cfg(backup_sram)]
+            enable_backup_sram: false,
         }
     }
 
@@ -129,6 +137,8 @@ impl LsConfig {
             rtc: RtcClockSource::DISABLE,
             lsi: false,
             lse: None,
+            #[cfg(backup_sram)]
+            enable_backup_sram: false,
         }
     }
 }
@@ -193,6 +203,22 @@ impl LsConfig {
             while !csr.read().lsi1rdy() {}
         }
 
+        // Enable backup regulator for peristent battery backed sram
+        #[cfg(backup_sram)]
+        {
+            unsafe { super::BKSRAM_RETAINED = crate::pac::PWR.bdcr().read().bren() == Retention::PRESERVED };
+
+            crate::pac::PWR.bdcr().modify(|w| {
+                w.set_bren(match self.enable_backup_sram {
+                    true => Retention::PRESERVED,
+                    false => Retention::LOST,
+                });
+            });
+
+            // Wait for backup regulator voltage to stabilize
+            while self.enable_backup_sram && !crate::pac::PWR.bdsr().read().brrdy() {}
+        }
+
         // backup domain configuration (LSEON, RTCEN, RTCSEL) is kept across resets.
         // once set, changing it requires a backup domain reset.
         // first check if the configuration matches what we want.
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index c817dd4b7..01fa3a475 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -48,6 +48,9 @@ pub(crate) static mut REFCOUNT_STOP1: u32 = 0;
 /// May be read without a critical section
 pub(crate) static mut REFCOUNT_STOP2: u32 = 0;
 
+#[cfg(backup_sram)]
+pub(crate) static mut BKSRAM_RETAINED: bool = false;
+
 #[cfg(not(feature = "_dual-core"))]
 /// Frozen clock frequencies
 ///
diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs
index 75a83629c..9a56a41fb 100644
--- a/embassy-stm32/src/timer/complementary_pwm.rs
+++ b/embassy-stm32/src/timer/complementary_pwm.rs
@@ -2,7 +2,7 @@
 
 use core::marker::PhantomData;
 
-pub use stm32_metapac::timer::vals::{Ckd, Ossi, Ossr};
+pub use stm32_metapac::timer::vals::{Ckd, Mms2, Ossi, Ossr};
 
 use super::low_level::{CountingMode, OutputPolarity, Timer};
 use super::simple_pwm::PwmPin;
@@ -136,6 +136,16 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
         self.inner.get_moe()
     }
 
+    /// Set Master Slave Mode 2
+    pub fn set_mms2(&mut self, mms2: Mms2) {
+        self.inner.set_mms2_selection(mms2);
+    }
+
+    /// Set Repetition Counter
+    pub fn set_repetition_counter(&mut self, val: u16) {
+        self.inner.set_repetition_counter(val);
+    }
+
     /// Enable the given channel.
     pub fn enable(&mut self, channel: Channel) {
         self.inner.enable_channel(channel, true);
diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs
index 82645887e..0122fe4f7 100644
--- a/embassy-stm32/src/timer/low_level.rs
+++ b/embassy-stm32/src/timer/low_level.rs
@@ -814,6 +814,16 @@ impl<'d, T: AdvancedInstance4Channel> Timer<'d, T> {
         self.regs_advanced().cr2().modify(|w| w.set_oisn(channel.index(), val));
     }
 
+    /// Set master mode selection 2
+    pub fn set_mms2_selection(&self, mms2: vals::Mms2) {
+        self.regs_advanced().cr2().modify(|w| w.set_mms2(mms2));
+    }
+
+    /// Set repetition counter
+    pub fn set_repetition_counter(&self, val: u16) {
+        self.regs_advanced().rcr().modify(|w| w.set_rep(val));
+    }
+
     /// Trigger software break 1 or 2
     /// Setting this bit generates a break event. This bit is automatically cleared by the hardware.
     pub fn trigger_software_break(&self, n: usize) {
diff --git a/examples/stm32g4/Cargo.toml b/examples/stm32g4/Cargo.toml
index 6fd282d6d..8bbeb594c 100644
--- a/examples/stm32g4/Cargo.toml
+++ b/examples/stm32g4/Cargo.toml
@@ -7,12 +7,12 @@ publish = false
 
 [dependencies]
 # Change stm32g491re to your chip name, if necessary.
-embassy-stm32 = { version = "0.4.0", path = "../../embassy-stm32", features = [ "defmt", "time-driver-any", "stm32g491re", "memory-x", "unstable-pac", "exti"]  }
-embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt"] }
-embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
-embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
-embassy-usb = { version = "0.5.1", path = "../../embassy-usb", features = ["defmt"] }
-embassy-futures = { version = "0.1.2", path = "../../embassy-futures" }
+embassy-stm32 = { path = "../../embassy-stm32", features = [ "defmt", "time-driver-any", "stm32g491re", "memory-x", "unstable-pac", "exti"]  }
+embassy-sync = { path = "../../embassy-sync", features = ["defmt"] }
+embassy-executor = { path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
+embassy-time = { path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
+embassy-usb = { path = "../../embassy-usb", features = ["defmt"] }
+embassy-futures = { path = "../../embassy-futures" }
 usbd-hid = "0.8.1"
 
 defmt = "1.0.1"
@@ -25,6 +25,7 @@ embedded-can = { version = "0.4" }
 panic-probe = { version = "1.0.0", features = ["print-defmt"] }
 heapless = { version = "0.8", default-features = false }
 static_cell = "2.0.0"
+critical-section = "1.1"
 
 [profile.release]
 debug = 2
diff --git a/examples/stm32g4/src/bin/adc_dma.rs b/examples/stm32g4/src/bin/adc_dma.rs
index a82067049..ef8b0c3c2 100644
--- a/examples/stm32g4/src/bin/adc_dma.rs
+++ b/examples/stm32g4/src/bin/adc_dma.rs
@@ -12,7 +12,7 @@ static mut DMA_BUF: [u16; 2] = [0; 2];
 
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
-    let mut read_buffer = unsafe { &mut DMA_BUF[..] };
+    let read_buffer = unsafe { &mut DMA_BUF[..] };
 
     let mut config = Config::default();
     {
@@ -47,7 +47,7 @@ async fn main(_spawner: Spawner) {
                 (&mut pa0, SampleTime::CYCLES247_5),
             ]
             .into_iter(),
-            &mut read_buffer,
+            read_buffer,
         )
         .await;
 
diff --git a/examples/stm32g4/src/bin/adc_injected_and_regular.rs b/examples/stm32g4/src/bin/adc_injected_and_regular.rs
new file mode 100644
index 000000000..3ae2ff064
--- /dev/null
+++ b/examples/stm32g4/src/bin/adc_injected_and_regular.rs
@@ -0,0 +1,154 @@
+//! adc injected and regular conversions
+//!
+//! This example both regular and injected ADC conversions at the same time
+//! p:pa0 n:pa2
+
+#![no_std]
+#![no_main]
+
+use core::cell::RefCell;
+
+use defmt::info;
+use embassy_stm32::adc::{
+    Adc, AdcChannel as _, ConversionTrigger, Exten, InjectedAdc, RegularConversionMode, SampleTime,
+};
+use embassy_stm32::interrupt::typelevel::{ADC1_2, Interrupt};
+use embassy_stm32::peripherals::ADC1;
+use embassy_stm32::time::Hertz;
+use embassy_stm32::timer::complementary_pwm::{ComplementaryPwm, Mms2};
+use embassy_stm32::timer::low_level::CountingMode;
+use embassy_stm32::{Config, interrupt};
+use embassy_sync::blocking_mutex::CriticalSectionMutex;
+use {defmt_rtt as _, panic_probe as _};
+
+static ADC1_HANDLE: CriticalSectionMutex<RefCell<Option<InjectedAdc<ADC1, 1>>>> =
+    CriticalSectionMutex::new(RefCell::new(None));
+
+/// This example showcases how to use both regular ADC conversions with DMA and injected ADC
+/// conversions with ADC interrupt simultaneously. Both conversion types can be configured with
+/// different triggers and thanks to DMA it is possible to use the measurements in different task
+/// without needing to access the ADC peripheral.
+///
+/// If you don't need both regular and injected conversions the example code can easily be reworked
+/// to only include one of the ADC conversion types.
+#[embassy_executor::main]
+async fn main(_spawner: embassy_executor::Spawner) {
+    // See Table 166 and 167 in RM0440 Rev 9 for ADC1/2 External triggers
+    // Note: Regular and Injected channels use different tables!!
+    const ADC1_INJECTED_TRIGGER_TIM1_TRGO2: u8 = 8;
+    const ADC1_REGULAR_TRIGGER_TIM1_TRGO2: u8 = 10;
+
+    // --- RCC config ---
+    let mut config = Config::default();
+    {
+        use embassy_stm32::rcc::*;
+        config.rcc.pll = Some(Pll {
+            source: PllSource::HSI,
+            prediv: PllPreDiv::DIV4,
+            mul: PllMul::MUL85,
+            divp: None,
+            divq: None,
+            divr: Some(PllRDiv::DIV2),
+        });
+        config.rcc.mux.adc12sel = mux::Adcsel::SYS;
+        config.rcc.sys = Sysclk::PLL1_R;
+    }
+    let p = embassy_stm32::init(config);
+
+    // In this example we use tim1_trgo2 event to trigger the ADC conversions
+    let tim1 = p.TIM1;
+    let pwm_freq = 1;
+    let mut pwm = ComplementaryPwm::new(
+        tim1,
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        Hertz::hz(pwm_freq),
+        CountingMode::EdgeAlignedUp,
+    );
+    pwm.set_master_output_enable(false);
+    // Mms2 is used to configure which timer event that is connected to tim1_trgo2.
+    // In this case we use the update event of the timer.
+    pwm.set_mms2(Mms2::UPDATE);
+
+    // Configure regular conversions with DMA
+    let adc1 = Adc::new(p.ADC1);
+
+    let vrefint_channel = adc1.enable_vrefint().degrade_adc();
+    let pa0 = p.PC1.degrade_adc();
+    let regular_sequence = [
+        (vrefint_channel, SampleTime::CYCLES247_5),
+        (pa0, SampleTime::CYCLES247_5),
+    ]
+    .into_iter();
+
+    // Configurations of Injected ADC measurements
+    let pa2 = p.PA2.degrade_adc();
+    let injected_sequence = [(pa2, SampleTime::CYCLES247_5)];
+
+    // Configure DMA for retrieving regular ADC measurements
+    let dma1_ch1 = p.DMA1_CH1;
+    // Using buffer of double size means the half-full interrupts will generate at the expected rate
+    let mut readings = [0u16; 4];
+
+    let injected_trigger = ConversionTrigger {
+        channel: ADC1_INJECTED_TRIGGER_TIM1_TRGO2,
+        edge: Exten::RISING_EDGE,
+    };
+    let regular_trigger = ConversionTrigger {
+        channel: ADC1_REGULAR_TRIGGER_TIM1_TRGO2,
+        edge: Exten::RISING_EDGE,
+    };
+
+    let (mut ring_buffered_adc, injected_adc) = adc1.into_ring_buffered_and_injected(
+        dma1_ch1,
+        &mut readings,
+        regular_sequence,
+        RegularConversionMode::Triggered(regular_trigger),
+        injected_sequence,
+        injected_trigger,
+        true,
+    );
+
+    // Store ADC globally to allow access from ADC interrupt
+    critical_section::with(|cs| {
+        ADC1_HANDLE.borrow(cs).replace(Some(injected_adc));
+    });
+    // Enable interrupt for ADC1_2
+    unsafe { ADC1_2::enable() };
+
+    // Main loop for reading regular ADC measurements periodically
+    let mut data = [0u16; 2];
+    loop {
+        {
+            match ring_buffered_adc.read(&mut data).await {
+                Ok(n) => {
+                    defmt::info!("Regular ADC reading, VrefInt: {}, PA0: {}", data[0], data[1]);
+                    defmt::info!("Remaining samples: {}", n,);
+                }
+                Err(e) => {
+                    defmt::error!("DMA error: {:?}", e);
+                    ring_buffered_adc.clear();
+                }
+            }
+        }
+    }
+}
+
+/// Use ADC1_2 interrupt to retrieve injected ADC measurements
+/// Interrupt must be unsafe as hardware can invoke it any-time. Critical sections ensure safety
+/// within the interrupt.
+#[interrupt]
+unsafe fn ADC1_2() {
+    critical_section::with(|cs| {
+        if let Some(injected_adc) = ADC1_HANDLE.borrow(cs).borrow_mut().as_mut() {
+            let injected_data = injected_adc.read_injected_samples();
+            info!("Injected reading of PA2: {}", injected_data[0]);
+        }
+    });
+}
diff --git a/examples/stm32h5/src/bin/backup_sram.rs b/examples/stm32h5/src/bin/backup_sram.rs
new file mode 100644
index 000000000..f8db1853e
--- /dev/null
+++ b/examples/stm32h5/src/bin/backup_sram.rs
@@ -0,0 +1,31 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::Config;
+use embassy_stm32::backup_sram::BackupMemory;
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut config = Config::default();
+    config.rcc.ls.enable_backup_sram = true;
+
+    let p = embassy_stm32::init(config);
+    info!("Started!");
+
+    let (bytes, status) = BackupMemory::new(p.BKPSRAM);
+
+    match status {
+        false => info!("BKPSRAM just enabled"),
+        true => info!("BKPSRAM already enabled"),
+    }
+
+    loop {
+        info!("byte0: {}", bytes[0]);
+        bytes[0] = bytes[0].wrapping_add(1);
+        Timer::after_millis(500).await;
+    }
+}