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-rw-r--r--embassy-stm32/src/rcc/c0.rs55
-rw-r--r--embassy-stm32/src/rcc/common.rs174
-rw-r--r--embassy-stm32/src/rcc/f2.rs118
-rw-r--r--embassy-stm32/src/rcc/g0.rs74
-rw-r--r--embassy-stm32/src/rcc/g4.rs25
-rw-r--r--embassy-stm32/src/rcc/h5.rs104
-rw-r--r--embassy-stm32/src/rcc/h7.rs16
-rw-r--r--embassy-stm32/src/rcc/l0.rs53
-rw-r--r--embassy-stm32/src/rcc/l1.rs53
-rw-r--r--embassy-stm32/src/rcc/l4.rs53
-rw-r--r--embassy-stm32/src/rcc/l5.rs53
-rw-r--r--embassy-stm32/src/rcc/mod.rs2
-rw-r--r--embassy-stm32/src/rcc/u5.rs79
-rw-r--r--embassy-stm32/src/rcc/wb.rs63
-rw-r--r--embassy-stm32/src/rcc/wl.rs85
15 files changed, 222 insertions, 785 deletions
diff --git a/embassy-stm32/src/rcc/c0.rs b/embassy-stm32/src/rcc/c0.rs
index df6e9047c..6a9326347 100644
--- a/embassy-stm32/src/rcc/c0.rs
+++ b/embassy-stm32/src/rcc/c0.rs
@@ -1,5 +1,6 @@
1pub use super::common::{AHBPrescaler, APBPrescaler};
1use crate::pac::flash::vals::Latency; 2use crate::pac::flash::vals::Latency;
2use crate::pac::rcc::vals::{Hpre, Hsidiv, Ppre, Sw}; 3use crate::pac::rcc::vals::{Hsidiv, Ppre, Sw};
3use crate::pac::{FLASH, RCC}; 4use crate::pac::{FLASH, RCC};
4use crate::rcc::{set_freqs, Clocks}; 5use crate::rcc::{set_freqs, Clocks};
5use crate::time::Hertz; 6use crate::time::Hertz;
@@ -45,58 +46,6 @@ impl Into<Hsidiv> for HSIPrescaler {
45 } 46 }
46} 47}
47 48
48/// AHB prescaler
49#[derive(Clone, Copy, PartialEq)]
50pub enum AHBPrescaler {
51 NotDivided,
52 Div2,
53 Div4,
54 Div8,
55 Div16,
56 Div64,
57 Div128,
58 Div256,
59 Div512,
60}
61
62/// APB prescaler
63#[derive(Clone, Copy)]
64pub enum APBPrescaler {
65 NotDivided,
66 Div2,
67 Div4,
68 Div8,
69 Div16,
70}
71
72impl Into<Ppre> for APBPrescaler {
73 fn into(self) -> Ppre {
74 match self {
75 APBPrescaler::NotDivided => Ppre::DIV1,
76 APBPrescaler::Div2 => Ppre::DIV2,
77 APBPrescaler::Div4 => Ppre::DIV4,
78 APBPrescaler::Div8 => Ppre::DIV8,
79 APBPrescaler::Div16 => Ppre::DIV16,
80 }
81 }
82}
83
84impl Into<Hpre> for AHBPrescaler {
85 fn into(self) -> Hpre {
86 match self {
87 AHBPrescaler::NotDivided => Hpre::DIV1,
88 AHBPrescaler::Div2 => Hpre::DIV2,
89 AHBPrescaler::Div4 => Hpre::DIV4,
90 AHBPrescaler::Div8 => Hpre::DIV8,
91 AHBPrescaler::Div16 => Hpre::DIV16,
92 AHBPrescaler::Div64 => Hpre::DIV64,
93 AHBPrescaler::Div128 => Hpre::DIV128,
94 AHBPrescaler::Div256 => Hpre::DIV256,
95 AHBPrescaler::Div512 => Hpre::DIV512,
96 }
97 }
98}
99
100/// Clocks configutation 49/// Clocks configutation
101pub struct Config { 50pub struct Config {
102 pub mux: ClockSrc, 51 pub mux: ClockSrc,
diff --git a/embassy-stm32/src/rcc/common.rs b/embassy-stm32/src/rcc/common.rs
new file mode 100644
index 000000000..62736a43a
--- /dev/null
+++ b/embassy-stm32/src/rcc/common.rs
@@ -0,0 +1,174 @@
1use core::ops::Div;
2
3#[allow(unused_imports)]
4use crate::pac::rcc;
5use crate::time::Hertz;
6
7/// Voltage Scale
8///
9/// Represents the voltage range feeding the CPU core. The maximum core
10/// clock frequency depends on this value.
11///
12/// Scale0 represents the highest voltage range
13#[derive(Copy, Clone, PartialEq)]
14pub enum VoltageScale {
15 Scale0,
16 Scale1,
17 #[cfg(not(any(rcc_wl5, rcc_wle)))]
18 Scale2,
19 #[cfg(not(any(rcc_wl5, rcc_wle)))]
20 Scale3,
21}
22
23/// AHB prescaler
24#[derive(Clone, Copy, PartialEq)]
25pub enum AHBPrescaler {
26 NotDivided,
27 Div2,
28 #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
29 Div3,
30 Div4,
31 #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
32 Div5,
33 #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
34 Div6,
35 Div8,
36 #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
37 Div10,
38 Div16,
39 #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
40 Div32,
41 Div64,
42 Div128,
43 Div256,
44 Div512,
45}
46
47impl Div<AHBPrescaler> for Hertz {
48 type Output = Hertz;
49
50 fn div(self, rhs: AHBPrescaler) -> Self::Output {
51 let divisor = match rhs {
52 AHBPrescaler::NotDivided => 1,
53 AHBPrescaler::Div2 => 2,
54 #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
55 AHBPrescaler::Div3 => 3,
56 AHBPrescaler::Div4 => 4,
57 #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
58 AHBPrescaler::Div5 => 5,
59 #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
60 AHBPrescaler::Div6 => 6,
61 AHBPrescaler::Div8 => 8,
62 #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
63 AHBPrescaler::Div10 => 10,
64 AHBPrescaler::Div16 => 16,
65 #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
66 AHBPrescaler::Div32 => 32,
67 AHBPrescaler::Div64 => 64,
68 AHBPrescaler::Div128 => 128,
69 AHBPrescaler::Div256 => 256,
70 AHBPrescaler::Div512 => 512,
71 };
72 Hertz(self.0 / divisor)
73 }
74}
75
76#[cfg(not(any(rcc_g4, rcc_wb, rcc_wl5, rcc_wle)))]
77impl From<AHBPrescaler> for rcc::vals::Hpre {
78 fn from(val: AHBPrescaler) -> rcc::vals::Hpre {
79 use rcc::vals::Hpre;
80
81 match val {
82 #[cfg(not(rcc_u5))]
83 AHBPrescaler::NotDivided => Hpre::DIV1,
84 #[cfg(rcc_u5)]
85 AHBPrescaler::NotDivided => Hpre::NONE,
86 AHBPrescaler::Div2 => Hpre::DIV2,
87 AHBPrescaler::Div4 => Hpre::DIV4,
88 AHBPrescaler::Div8 => Hpre::DIV8,
89 AHBPrescaler::Div16 => Hpre::DIV16,
90 AHBPrescaler::Div64 => Hpre::DIV64,
91 AHBPrescaler::Div128 => Hpre::DIV128,
92 AHBPrescaler::Div256 => Hpre::DIV256,
93 AHBPrescaler::Div512 => Hpre::DIV512,
94 }
95 }
96}
97
98#[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
99impl From<AHBPrescaler> for u8 {
100 fn from(val: AHBPrescaler) -> u8 {
101 match val {
102 AHBPrescaler::NotDivided => 0x0,
103 AHBPrescaler::Div2 => 0x08,
104 AHBPrescaler::Div3 => 0x01,
105 AHBPrescaler::Div4 => 0x09,
106 AHBPrescaler::Div5 => 0x02,
107 AHBPrescaler::Div6 => 0x05,
108 AHBPrescaler::Div8 => 0x0a,
109 AHBPrescaler::Div10 => 0x06,
110 AHBPrescaler::Div16 => 0x0b,
111 AHBPrescaler::Div32 => 0x07,
112 AHBPrescaler::Div64 => 0x0c,
113 AHBPrescaler::Div128 => 0x0d,
114 AHBPrescaler::Div256 => 0x0e,
115 AHBPrescaler::Div512 => 0x0f,
116 }
117 }
118}
119
120/// APB prescaler
121#[derive(Clone, Copy)]
122pub enum APBPrescaler {
123 NotDivided,
124 Div2,
125 Div4,
126 Div8,
127 Div16,
128}
129
130impl Div<APBPrescaler> for Hertz {
131 type Output = Hertz;
132
133 fn div(self, rhs: APBPrescaler) -> Self::Output {
134 let divisor = match rhs {
135 APBPrescaler::NotDivided => 1,
136 APBPrescaler::Div2 => 2,
137 APBPrescaler::Div4 => 4,
138 APBPrescaler::Div8 => 8,
139 APBPrescaler::Div16 => 16,
140 };
141 Hertz(self.0 / divisor)
142 }
143}
144
145#[cfg(not(any(rcc_f1, rcc_f100, rcc_f1cl, rcc_g4, rcc_h7, rcc_h7ab, rcc_wb, rcc_wl5, rcc_wle)))]
146impl From<APBPrescaler> for rcc::vals::Ppre {
147 fn from(val: APBPrescaler) -> rcc::vals::Ppre {
148 use rcc::vals::Ppre;
149
150 match val {
151 #[cfg(not(rcc_u5))]
152 APBPrescaler::NotDivided => Ppre::DIV1,
153 #[cfg(rcc_u5)]
154 APBPrescaler::NotDivided => Ppre::NONE,
155 APBPrescaler::Div2 => Ppre::DIV2,
156 APBPrescaler::Div4 => Ppre::DIV4,
157 APBPrescaler::Div8 => Ppre::DIV8,
158 APBPrescaler::Div16 => Ppre::DIV16,
159 }
160 }
161}
162
163#[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
164impl From<APBPrescaler> for u8 {
165 fn from(val: APBPrescaler) -> u8 {
166 match val {
167 APBPrescaler::NotDivided => 1,
168 APBPrescaler::Div2 => 0x04,
169 APBPrescaler::Div4 => 0x05,
170 APBPrescaler::Div8 => 0x06,
171 APBPrescaler::Div16 => 0x07,
172 }
173 }
174}
diff --git a/embassy-stm32/src/rcc/f2.rs b/embassy-stm32/src/rcc/f2.rs
index bc240fcb1..d016d1dea 100644
--- a/embassy-stm32/src/rcc/f2.rs
+++ b/embassy-stm32/src/rcc/f2.rs
@@ -1,8 +1,9 @@
1use core::convert::TryFrom; 1use core::convert::TryFrom;
2use core::ops::{Div, Mul}; 2use core::ops::{Div, Mul};
3 3
4pub use super::common::{AHBPrescaler, APBPrescaler};
4use crate::pac::flash::vals::Latency; 5use crate::pac::flash::vals::Latency;
5use crate::pac::rcc::vals::{Hpre, Pllp, Pllsrc, Ppre, Sw}; 6use crate::pac::rcc::vals::{Pllp, Pllsrc, Sw};
6use crate::pac::{FLASH, RCC}; 7use crate::pac::{FLASH, RCC};
7use crate::rcc::{set_freqs, Clocks}; 8use crate::rcc::{set_freqs, Clocks};
8use crate::time::Hertz; 9use crate::time::Hertz;
@@ -200,114 +201,15 @@ pub struct PLLClocks {
200 pub pll48_freq: Hertz, 201 pub pll48_freq: Hertz,
201} 202}
202 203
203/// AHB prescaler 204pub use super::common::VoltageScale;
204#[derive(Clone, Copy, PartialEq)]
205pub enum AHBPrescaler {
206 NotDivided,
207 Div2,
208 Div4,
209 Div8,
210 Div16,
211 Div64,
212 Div128,
213 Div256,
214 Div512,
215}
216
217impl Div<AHBPrescaler> for Hertz {
218 type Output = Hertz;
219
220 fn div(self, rhs: AHBPrescaler) -> Self::Output {
221 let divisor = match rhs {
222 AHBPrescaler::NotDivided => 1,
223 AHBPrescaler::Div2 => 2,
224 AHBPrescaler::Div4 => 4,
225 AHBPrescaler::Div8 => 8,
226 AHBPrescaler::Div16 => 16,
227 AHBPrescaler::Div64 => 64,
228 AHBPrescaler::Div128 => 128,
229 AHBPrescaler::Div256 => 256,
230 AHBPrescaler::Div512 => 512,
231 };
232 Hertz(self.0 / divisor)
233 }
234}
235
236/// APB prescaler
237#[derive(Clone, Copy)]
238pub enum APBPrescaler {
239 NotDivided,
240 Div2,
241 Div4,
242 Div8,
243 Div16,
244}
245
246impl Div<APBPrescaler> for Hertz {
247 type Output = Hertz;
248
249 fn div(self, rhs: APBPrescaler) -> Self::Output {
250 let divisor = match rhs {
251 APBPrescaler::NotDivided => 1,
252 APBPrescaler::Div2 => 2,
253 APBPrescaler::Div4 => 4,
254 APBPrescaler::Div8 => 8,
255 APBPrescaler::Div16 => 16,
256 };
257 Hertz(self.0 / divisor)
258 }
259}
260
261impl Into<Ppre> for APBPrescaler {
262 fn into(self) -> Ppre {
263 match self {
264 APBPrescaler::NotDivided => Ppre::DIV1,
265 APBPrescaler::Div2 => Ppre::DIV2,
266 APBPrescaler::Div4 => Ppre::DIV4,
267 APBPrescaler::Div8 => Ppre::DIV8,
268 APBPrescaler::Div16 => Ppre::DIV16,
269 }
270 }
271}
272
273impl Into<Hpre> for AHBPrescaler {
274 fn into(self) -> Hpre {
275 match self {
276 AHBPrescaler::NotDivided => Hpre::DIV1,
277 AHBPrescaler::Div2 => Hpre::DIV2,
278 AHBPrescaler::Div4 => Hpre::DIV4,
279 AHBPrescaler::Div8 => Hpre::DIV8,
280 AHBPrescaler::Div16 => Hpre::DIV16,
281 AHBPrescaler::Div64 => Hpre::DIV64,
282 AHBPrescaler::Div128 => Hpre::DIV128,
283 AHBPrescaler::Div256 => Hpre::DIV256,
284 AHBPrescaler::Div512 => Hpre::DIV512,
285 }
286 }
287}
288
289/// Voltage Range
290///
291/// Represents the system supply voltage range
292#[derive(Copy, Clone, PartialEq)]
293pub enum VoltageRange {
294 /// 1.8 to 3.6 V
295 Min1V8,
296 /// 2.1 to 3.6 V
297 Min2V1,
298 /// 2.4 to 3.6 V
299 Min2V4,
300 /// 2.7 to 3.6 V
301 Min2V7,
302}
303 205
304impl VoltageRange { 206impl VoltageScale {
305 const fn wait_states(&self, ahb_freq: Hertz) -> Option<Latency> { 207 const fn wait_states(&self, ahb_freq: Hertz) -> Option<Latency> {
306 let ahb_freq = ahb_freq.0; 208 let ahb_freq = ahb_freq.0;
307 // Reference: RM0033 - Table 3. Number of wait states according to Cortex®-M3 clock 209 // Reference: RM0033 - Table 3. Number of wait states according to Cortex®-M3 clock
308 // frequency 210 // frequency
309 match self { 211 match self {
310 VoltageRange::Min1V8 => { 212 VoltageScale::Scale3 => {
311 if ahb_freq <= 16_000_000 { 213 if ahb_freq <= 16_000_000 {
312 Some(Latency::WS0) 214 Some(Latency::WS0)
313 } else if ahb_freq <= 32_000_000 { 215 } else if ahb_freq <= 32_000_000 {
@@ -328,7 +230,7 @@ impl VoltageRange {
328 None 230 None
329 } 231 }
330 } 232 }
331 VoltageRange::Min2V1 => { 233 VoltageScale::Scale2 => {
332 if ahb_freq <= 18_000_000 { 234 if ahb_freq <= 18_000_000 {
333 Some(Latency::WS0) 235 Some(Latency::WS0)
334 } else if ahb_freq <= 36_000_000 { 236 } else if ahb_freq <= 36_000_000 {
@@ -347,7 +249,7 @@ impl VoltageRange {
347 None 249 None
348 } 250 }
349 } 251 }
350 VoltageRange::Min2V4 => { 252 VoltageScale::Scale1 => {
351 if ahb_freq <= 24_000_000 { 253 if ahb_freq <= 24_000_000 {
352 Some(Latency::WS0) 254 Some(Latency::WS0)
353 } else if ahb_freq <= 48_000_000 { 255 } else if ahb_freq <= 48_000_000 {
@@ -362,7 +264,7 @@ impl VoltageRange {
362 None 264 None
363 } 265 }
364 } 266 }
365 VoltageRange::Min2V7 => { 267 VoltageScale::Scale0 => {
366 if ahb_freq <= 30_000_000 { 268 if ahb_freq <= 30_000_000 {
367 Some(Latency::WS0) 269 Some(Latency::WS0)
368 } else if ahb_freq <= 60_000_000 { 270 } else if ahb_freq <= 60_000_000 {
@@ -386,7 +288,7 @@ pub struct Config {
386 pub pll_mux: PLLSrc, 288 pub pll_mux: PLLSrc,
387 pub pll: PLLConfig, 289 pub pll: PLLConfig,
388 pub mux: ClockSrc, 290 pub mux: ClockSrc,
389 pub voltage: VoltageRange, 291 pub voltage: VoltageScale,
390 pub ahb_pre: AHBPrescaler, 292 pub ahb_pre: AHBPrescaler,
391 pub apb1_pre: APBPrescaler, 293 pub apb1_pre: APBPrescaler,
392 pub apb2_pre: APBPrescaler, 294 pub apb2_pre: APBPrescaler,
@@ -400,7 +302,7 @@ impl Default for Config {
400 hsi: true, 302 hsi: true,
401 pll_mux: PLLSrc::HSI, 303 pll_mux: PLLSrc::HSI,
402 pll: PLLConfig::default(), 304 pll: PLLConfig::default(),
403 voltage: VoltageRange::Min1V8, 305 voltage: VoltageScale::Scale3,
404 mux: ClockSrc::HSI, 306 mux: ClockSrc::HSI,
405 ahb_pre: AHBPrescaler::NotDivided, 307 ahb_pre: AHBPrescaler::NotDivided,
406 apb1_pre: APBPrescaler::NotDivided, 308 apb1_pre: APBPrescaler::NotDivided,
diff --git a/embassy-stm32/src/rcc/g0.rs b/embassy-stm32/src/rcc/g0.rs
index 5e3a7911a..bf2d5199e 100644
--- a/embassy-stm32/src/rcc/g0.rs
+++ b/embassy-stm32/src/rcc/g0.rs
@@ -1,5 +1,6 @@
1pub use super::common::{AHBPrescaler, APBPrescaler};
1use crate::pac::flash::vals::Latency; 2use crate::pac::flash::vals::Latency;
2use crate::pac::rcc::vals::{self, Hpre, Hsidiv, Ppre, Sw}; 3use crate::pac::rcc::vals::{self, Hsidiv, Ppre, Sw};
3use crate::pac::{FLASH, PWR, RCC}; 4use crate::pac::{FLASH, PWR, RCC};
4use crate::rcc::{set_freqs, Clocks}; 5use crate::rcc::{set_freqs, Clocks};
5use crate::time::Hertz; 6use crate::time::Hertz;
@@ -172,58 +173,6 @@ impl From<Pllr> for u32 {
172 } 173 }
173} 174}
174 175
175/// AHB prescaler
176#[derive(Clone, Copy, PartialEq)]
177pub enum AHBPrescaler {
178 NotDivided,
179 Div2,
180 Div4,
181 Div8,
182 Div16,
183 Div64,
184 Div128,
185 Div256,
186 Div512,
187}
188
189/// APB prescaler
190#[derive(Clone, Copy)]
191pub enum APBPrescaler {
192 NotDivided,
193 Div2,
194 Div4,
195 Div8,
196 Div16,
197}
198
199impl Into<Ppre> for APBPrescaler {
200 fn into(self) -> Ppre {
201 match self {
202 APBPrescaler::NotDivided => Ppre::DIV1,
203 APBPrescaler::Div2 => Ppre::DIV2,
204 APBPrescaler::Div4 => Ppre::DIV4,
205 APBPrescaler::Div8 => Ppre::DIV8,
206 APBPrescaler::Div16 => Ppre::DIV16,
207 }
208 }
209}
210
211impl Into<Hpre> for AHBPrescaler {
212 fn into(self) -> Hpre {
213 match self {
214 AHBPrescaler::NotDivided => Hpre::DIV1,
215 AHBPrescaler::Div2 => Hpre::DIV2,
216 AHBPrescaler::Div4 => Hpre::DIV4,
217 AHBPrescaler::Div8 => Hpre::DIV8,
218 AHBPrescaler::Div16 => Hpre::DIV16,
219 AHBPrescaler::Div64 => Hpre::DIV64,
220 AHBPrescaler::Div128 => Hpre::DIV128,
221 AHBPrescaler::Div256 => Hpre::DIV256,
222 AHBPrescaler::Div512 => Hpre::DIV512,
223 }
224 }
225}
226
227/// Clocks configutation 176/// Clocks configutation
228pub struct Config { 177pub struct Config {
229 pub mux: ClockSrc, 178 pub mux: ClockSrc,
@@ -425,25 +374,14 @@ pub(crate) unsafe fn init(config: Config) {
425 FLASH.acr().modify(|w| w.set_latency(target_flash_latency)); 374 FLASH.acr().modify(|w| w.set_latency(target_flash_latency));
426 } 375 }
427 376
428 let ahb_div = match config.ahb_pre { 377 let ahb_freq = Hertz(sys_clk) / config.ahb_pre;
429 AHBPrescaler::NotDivided => 1,
430 AHBPrescaler::Div2 => 2,
431 AHBPrescaler::Div4 => 4,
432 AHBPrescaler::Div8 => 8,
433 AHBPrescaler::Div16 => 16,
434 AHBPrescaler::Div64 => 64,
435 AHBPrescaler::Div128 => 128,
436 AHBPrescaler::Div256 => 256,
437 AHBPrescaler::Div512 => 512,
438 };
439 let ahb_freq = sys_clk / ahb_div;
440 378
441 let (apb_freq, apb_tim_freq) = match config.apb_pre { 379 let (apb_freq, apb_tim_freq) = match config.apb_pre {
442 APBPrescaler::NotDivided => (ahb_freq, ahb_freq), 380 APBPrescaler::NotDivided => (ahb_freq.0, ahb_freq.0),
443 pre => { 381 pre => {
444 let pre: Ppre = pre.into(); 382 let pre: Ppre = pre.into();
445 let pre: u8 = 1 << (pre.to_bits() - 3); 383 let pre: u8 = 1 << (pre.to_bits() - 3);
446 let freq = ahb_freq / pre as u32; 384 let freq = ahb_freq.0 / pre as u32;
447 (freq, freq * 2) 385 (freq, freq * 2)
448 } 386 }
449 }; 387 };
@@ -455,7 +393,7 @@ pub(crate) unsafe fn init(config: Config) {
455 393
456 set_freqs(Clocks { 394 set_freqs(Clocks {
457 sys: Hertz(sys_clk), 395 sys: Hertz(sys_clk),
458 ahb1: Hertz(ahb_freq), 396 ahb1: ahb_freq,
459 apb1: Hertz(apb_freq), 397 apb1: Hertz(apb_freq),
460 apb1_tim: Hertz(apb_tim_freq), 398 apb1_tim: Hertz(apb_tim_freq),
461 }); 399 });
diff --git a/embassy-stm32/src/rcc/g4.rs b/embassy-stm32/src/rcc/g4.rs
index ff8f97541..dff04023e 100644
--- a/embassy-stm32/src/rcc/g4.rs
+++ b/embassy-stm32/src/rcc/g4.rs
@@ -2,6 +2,7 @@ use stm32_metapac::flash::vals::Latency;
2use stm32_metapac::rcc::vals::{Hpre, Pllsrc, Ppre, Sw}; 2use stm32_metapac::rcc::vals::{Hpre, Pllsrc, Ppre, Sw};
3use stm32_metapac::FLASH; 3use stm32_metapac::FLASH;
4 4
5pub use super::common::{AHBPrescaler, APBPrescaler};
5use crate::pac::{PWR, RCC}; 6use crate::pac::{PWR, RCC};
6use crate::rcc::sealed::RccPeripheral; 7use crate::rcc::sealed::RccPeripheral;
7use crate::rcc::{set_freqs, Clocks}; 8use crate::rcc::{set_freqs, Clocks};
@@ -21,30 +22,6 @@ pub enum ClockSrc {
21 PLL, 22 PLL,
22} 23}
23 24
24/// AHB prescaler
25#[derive(Clone, Copy, PartialEq)]
26pub enum AHBPrescaler {
27 NotDivided,
28 Div2,
29 Div4,
30 Div8,
31 Div16,
32 Div64,
33 Div128,
34 Div256,
35 Div512,
36}
37
38/// APB prescaler
39#[derive(Clone, Copy)]
40pub enum APBPrescaler {
41 NotDivided,
42 Div2,
43 Div4,
44 Div8,
45 Div16,
46}
47
48/// PLL clock input source 25/// PLL clock input source
49#[derive(Clone, Copy, Debug)] 26#[derive(Clone, Copy, Debug)]
50pub enum PllSrc { 27pub enum PllSrc {
diff --git a/embassy-stm32/src/rcc/h5.rs b/embassy-stm32/src/rcc/h5.rs
index 7e2f75ab7..2e72b1931 100644
--- a/embassy-stm32/src/rcc/h5.rs
+++ b/embassy-stm32/src/rcc/h5.rs
@@ -1,6 +1,6 @@
1use core::marker::PhantomData; 1use core::marker::PhantomData;
2 2
3use stm32_metapac::rcc::vals::{Hpre, Ppre, Timpre}; 3use stm32_metapac::rcc::vals::Timpre;
4 4
5use crate::pac::pwr::vals::Vos; 5use crate::pac::pwr::vals::Vos;
6use crate::pac::rcc::vals::{Hseext, Hsidiv, Mco1, Mco2, Pllrge, Pllsrc, Pllvcosel, Sw}; 6use crate::pac::rcc::vals::{Hseext, Hsidiv, Mco1, Mco2, Pllrge, Pllsrc, Pllvcosel, Sw};
@@ -26,21 +26,7 @@ const VCO_MAX: u32 = 420_000_000;
26const VCO_WIDE_MIN: u32 = 128_000_000; 26const VCO_WIDE_MIN: u32 = 128_000_000;
27const VCO_WIDE_MAX: u32 = 560_000_000; 27const VCO_WIDE_MAX: u32 = 560_000_000;
28 28
29/// Voltage Scale 29pub use super::common::{AHBPrescaler, APBPrescaler, VoltageScale};
30///
31/// Represents the voltage range feeding the CPU core. The maximum core
32/// clock frequency depends on this value.
33#[derive(Copy, Clone, PartialEq)]
34pub enum VoltageScale {
35 /// VOS 0 range VCORE 1.30V - 1.40V
36 Scale0,
37 /// VOS 1 range VCORE 1.15V - 1.26V
38 Scale1,
39 /// VOS 2 range VCORE 1.05V - 1.15V
40 Scale2,
41 /// VOS 3 range VCORE 0.95V - 1.05V
42 Scale3,
43}
44 30
45pub enum HseMode { 31pub enum HseMode {
46 /// crystal/ceramic oscillator (HSEBYP=0) 32 /// crystal/ceramic oscillator (HSEBYP=0)
@@ -105,57 +91,7 @@ pub struct Pll {
105 pub divr: Option<u16>, 91 pub divr: Option<u16>,
106} 92}
107 93
108/// AHB prescaler
109#[derive(Clone, Copy, PartialEq)]
110pub enum AHBPrescaler {
111 NotDivided,
112 Div2,
113 Div4,
114 Div8,
115 Div16,
116 Div64,
117 Div128,
118 Div256,
119 Div512,
120}
121
122impl AHBPrescaler {
123 fn div(&self, clk: Hertz) -> Hertz {
124 match self {
125 Self::NotDivided => clk,
126 Self::Div2 => clk / 2u32,
127 Self::Div4 => clk / 4u32,
128 Self::Div8 => clk / 8u32,
129 Self::Div16 => clk / 16u32,
130 Self::Div64 => clk / 64u32,
131 Self::Div128 => clk / 128u32,
132 Self::Div256 => clk / 256u32,
133 Self::Div512 => clk / 512u32,
134 }
135 }
136}
137
138/// APB prescaler
139#[derive(Clone, Copy)]
140pub enum APBPrescaler {
141 NotDivided,
142 Div2,
143 Div4,
144 Div8,
145 Div16,
146}
147
148impl APBPrescaler { 94impl APBPrescaler {
149 fn div(&self, clk: Hertz) -> Hertz {
150 match self {
151 Self::NotDivided => clk,
152 Self::Div2 => clk / 2u32,
153 Self::Div4 => clk / 4u32,
154 Self::Div8 => clk / 8u32,
155 Self::Div16 => clk / 16u32,
156 }
157 }
158
159 fn div_tim(&self, clk: Hertz, tim: TimerPrescaler) -> Hertz { 95 fn div_tim(&self, clk: Hertz, tim: TimerPrescaler) -> Hertz {
160 match (tim, self) { 96 match (tim, self) {
161 // The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a 97 // The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a
@@ -193,34 +129,6 @@ impl From<TimerPrescaler> for Timpre {
193 } 129 }
194} 130}
195 131
196impl From<APBPrescaler> for Ppre {
197 fn from(val: APBPrescaler) -> Ppre {
198 match val {
199 APBPrescaler::NotDivided => Ppre::DIV1,
200 APBPrescaler::Div2 => Ppre::DIV2,
201 APBPrescaler::Div4 => Ppre::DIV4,
202 APBPrescaler::Div8 => Ppre::DIV8,
203 APBPrescaler::Div16 => Ppre::DIV16,
204 }
205 }
206}
207
208impl From<AHBPrescaler> for Hpre {
209 fn from(val: AHBPrescaler) -> Hpre {
210 match val {
211 AHBPrescaler::NotDivided => Hpre::DIV1,
212 AHBPrescaler::Div2 => Hpre::DIV2,
213 AHBPrescaler::Div4 => Hpre::DIV4,
214 AHBPrescaler::Div8 => Hpre::DIV8,
215 AHBPrescaler::Div16 => Hpre::DIV16,
216 AHBPrescaler::Div64 => Hpre::DIV64,
217 AHBPrescaler::Div128 => Hpre::DIV128,
218 AHBPrescaler::Div256 => Hpre::DIV256,
219 AHBPrescaler::Div512 => Hpre::DIV512,
220 }
221 }
222}
223
224/// Configuration of the core clocks 132/// Configuration of the core clocks
225#[non_exhaustive] 133#[non_exhaustive]
226pub struct Config { 134pub struct Config {
@@ -406,13 +314,13 @@ pub(crate) unsafe fn init(config: Config) {
406 }; 314 };
407 assert!(sys <= max_clk); 315 assert!(sys <= max_clk);
408 316
409 let hclk = config.ahb_pre.div(sys); 317 let hclk = sys / config.ahb_pre;
410 318
411 let apb1 = config.apb1_pre.div(hclk); 319 let apb1 = hclk / config.apb1_pre;
412 let apb1_tim = config.apb1_pre.div_tim(hclk, config.timer_prescaler); 320 let apb1_tim = config.apb1_pre.div_tim(hclk, config.timer_prescaler);
413 let apb2 = config.apb2_pre.div(hclk); 321 let apb2 = hclk / config.apb2_pre;
414 let apb2_tim = config.apb2_pre.div_tim(hclk, config.timer_prescaler); 322 let apb2_tim = config.apb2_pre.div_tim(hclk, config.timer_prescaler);
415 let apb3 = config.apb3_pre.div(hclk); 323 let apb3 = hclk / config.apb3_pre;
416 324
417 flash_setup(hclk, config.voltage_scale); 325 flash_setup(hclk, config.voltage_scale);
418 326
diff --git a/embassy-stm32/src/rcc/h7.rs b/embassy-stm32/src/rcc/h7.rs
index bbc0e0831..0788b0640 100644
--- a/embassy-stm32/src/rcc/h7.rs
+++ b/embassy-stm32/src/rcc/h7.rs
@@ -24,21 +24,7 @@ pub const HSI48_FREQ: Hertz = Hertz(48_000_000);
24/// LSI speed 24/// LSI speed
25pub const LSI_FREQ: Hertz = Hertz(32_000); 25pub const LSI_FREQ: Hertz = Hertz(32_000);
26 26
27/// Voltage Scale 27pub use super::common::VoltageScale;
28///
29/// Represents the voltage range feeding the CPU core. The maximum core
30/// clock frequency depends on this value.
31#[derive(Copy, Clone, PartialEq)]
32pub enum VoltageScale {
33 /// VOS 0 range VCORE 1.26V - 1.40V
34 Scale0,
35 /// VOS 1 range VCORE 1.15V - 1.26V
36 Scale1,
37 /// VOS 2 range VCORE 1.05V - 1.15V
38 Scale2,
39 /// VOS 3 range VCORE 0.95V - 1.05V
40 Scale3,
41}
42 28
43#[derive(Clone, Copy)] 29#[derive(Clone, Copy)]
44pub enum AdcClockSource { 30pub enum AdcClockSource {
diff --git a/embassy-stm32/src/rcc/l0.rs b/embassy-stm32/src/rcc/l0.rs
index 46a528e31..46b58ca7c 100644
--- a/embassy-stm32/src/rcc/l0.rs
+++ b/embassy-stm32/src/rcc/l0.rs
@@ -1,3 +1,4 @@
1pub use super::common::{AHBPrescaler, APBPrescaler};
1use crate::pac::rcc::vals::{Hpre, Msirange, Plldiv, Pllmul, Pllsrc, Ppre, Sw}; 2use crate::pac::rcc::vals::{Hpre, Msirange, Plldiv, Pllmul, Pllsrc, Ppre, Sw};
2use crate::pac::RCC; 3use crate::pac::RCC;
3#[cfg(crs)] 4#[cfg(crs)]
@@ -70,30 +71,6 @@ pub enum PLLMul {
70 Mul48, 71 Mul48,
71} 72}
72 73
73/// AHB prescaler
74#[derive(Clone, Copy, PartialEq)]
75pub enum AHBPrescaler {
76 NotDivided,
77 Div2,
78 Div4,
79 Div8,
80 Div16,
81 Div64,
82 Div128,
83 Div256,
84 Div512,
85}
86
87/// APB prescaler
88#[derive(Clone, Copy)]
89pub enum APBPrescaler {
90 NotDivided,
91 Div2,
92 Div4,
93 Div8,
94 Div16,
95}
96
97/// PLL clock input source 74/// PLL clock input source
98#[derive(Clone, Copy)] 75#[derive(Clone, Copy)]
99pub enum PLLSource { 76pub enum PLLSource {
@@ -136,34 +113,6 @@ impl From<PLLSource> for Pllsrc {
136 } 113 }
137} 114}
138 115
139impl From<APBPrescaler> for Ppre {
140 fn from(val: APBPrescaler) -> Ppre {
141 match val {
142 APBPrescaler::NotDivided => Ppre::DIV1,
143 APBPrescaler::Div2 => Ppre::DIV2,
144 APBPrescaler::Div4 => Ppre::DIV4,
145 APBPrescaler::Div8 => Ppre::DIV8,
146 APBPrescaler::Div16 => Ppre::DIV16,
147 }
148 }
149}
150
151impl From<AHBPrescaler> for Hpre {
152 fn from(val: AHBPrescaler) -> Hpre {
153 match val {
154 AHBPrescaler::NotDivided => Hpre::DIV1,
155 AHBPrescaler::Div2 => Hpre::DIV2,
156 AHBPrescaler::Div4 => Hpre::DIV4,
157 AHBPrescaler::Div8 => Hpre::DIV8,
158 AHBPrescaler::Div16 => Hpre::DIV16,
159 AHBPrescaler::Div64 => Hpre::DIV64,
160 AHBPrescaler::Div128 => Hpre::DIV128,
161 AHBPrescaler::Div256 => Hpre::DIV256,
162 AHBPrescaler::Div512 => Hpre::DIV512,
163 }
164 }
165}
166
167impl From<MSIRange> for Msirange { 116impl From<MSIRange> for Msirange {
168 fn from(val: MSIRange) -> Msirange { 117 fn from(val: MSIRange) -> Msirange {
169 match val { 118 match val {
diff --git a/embassy-stm32/src/rcc/l1.rs b/embassy-stm32/src/rcc/l1.rs
index 59a6eac8f..bdfc5b87a 100644
--- a/embassy-stm32/src/rcc/l1.rs
+++ b/embassy-stm32/src/rcc/l1.rs
@@ -1,3 +1,4 @@
1pub use super::common::{AHBPrescaler, APBPrescaler};
1use crate::pac::rcc::vals::{Hpre, Msirange, Plldiv, Pllmul, Pllsrc, Ppre, Sw}; 2use crate::pac::rcc::vals::{Hpre, Msirange, Plldiv, Pllmul, Pllsrc, Ppre, Sw};
2use crate::pac::{FLASH, RCC}; 3use crate::pac::{FLASH, RCC};
3use crate::rcc::{set_freqs, Clocks}; 4use crate::rcc::{set_freqs, Clocks};
@@ -68,30 +69,6 @@ pub enum PLLMul {
68 Mul48, 69 Mul48,
69} 70}
70 71
71/// AHB prescaler
72#[derive(Clone, Copy, PartialEq)]
73pub enum AHBPrescaler {
74 NotDivided,
75 Div2,
76 Div4,
77 Div8,
78 Div16,
79 Div64,
80 Div128,
81 Div256,
82 Div512,
83}
84
85/// APB prescaler
86#[derive(Clone, Copy)]
87pub enum APBPrescaler {
88 NotDivided,
89 Div2,
90 Div4,
91 Div8,
92 Div16,
93}
94
95/// PLL clock input source 72/// PLL clock input source
96#[derive(Clone, Copy)] 73#[derive(Clone, Copy)]
97pub enum PLLSource { 74pub enum PLLSource {
@@ -134,34 +111,6 @@ impl From<PLLSource> for Pllsrc {
134 } 111 }
135} 112}
136 113
137impl From<APBPrescaler> for Ppre {
138 fn from(val: APBPrescaler) -> Ppre {
139 match val {
140 APBPrescaler::NotDivided => Ppre::DIV1,
141 APBPrescaler::Div2 => Ppre::DIV2,
142 APBPrescaler::Div4 => Ppre::DIV4,
143 APBPrescaler::Div8 => Ppre::DIV8,
144 APBPrescaler::Div16 => Ppre::DIV16,
145 }
146 }
147}
148
149impl From<AHBPrescaler> for Hpre {
150 fn from(val: AHBPrescaler) -> Hpre {
151 match val {
152 AHBPrescaler::NotDivided => Hpre::DIV1,
153 AHBPrescaler::Div2 => Hpre::DIV2,
154 AHBPrescaler::Div4 => Hpre::DIV4,
155 AHBPrescaler::Div8 => Hpre::DIV8,
156 AHBPrescaler::Div16 => Hpre::DIV16,
157 AHBPrescaler::Div64 => Hpre::DIV64,
158 AHBPrescaler::Div128 => Hpre::DIV128,
159 AHBPrescaler::Div256 => Hpre::DIV256,
160 AHBPrescaler::Div512 => Hpre::DIV512,
161 }
162 }
163}
164
165impl From<MSIRange> for Msirange { 114impl From<MSIRange> for Msirange {
166 fn from(val: MSIRange) -> Msirange { 115 fn from(val: MSIRange) -> Msirange {
167 match val { 116 match val {
diff --git a/embassy-stm32/src/rcc/l4.rs b/embassy-stm32/src/rcc/l4.rs
index dc5f55d0c..237b7bc91 100644
--- a/embassy-stm32/src/rcc/l4.rs
+++ b/embassy-stm32/src/rcc/l4.rs
@@ -4,6 +4,7 @@ use embassy_hal_internal::into_ref;
4use stm32_metapac::rcc::regs::Cfgr; 4use stm32_metapac::rcc::regs::Cfgr;
5use stm32_metapac::rcc::vals::{Lsedrv, Mcopre, Mcosel}; 5use stm32_metapac::rcc::vals::{Lsedrv, Mcopre, Mcosel};
6 6
7pub use super::common::{AHBPrescaler, APBPrescaler};
7use crate::gpio::sealed::AFType; 8use crate::gpio::sealed::AFType;
8use crate::gpio::Speed; 9use crate::gpio::Speed;
9use crate::pac::rcc::vals::{Hpre, Msirange, Pllsrc, Ppre, Sw}; 10use crate::pac::rcc::vals::{Hpre, Msirange, Pllsrc, Ppre, Sw};
@@ -78,30 +79,6 @@ pub enum PLLDiv {
78 Div4, 79 Div4,
79} 80}
80 81
81/// AHB prescaler
82#[derive(Clone, Copy, PartialEq)]
83pub enum AHBPrescaler {
84 NotDivided,
85 Div2,
86 Div4,
87 Div8,
88 Div16,
89 Div64,
90 Div128,
91 Div256,
92 Div512,
93}
94
95/// APB prescaler
96#[derive(Clone, Copy)]
97pub enum APBPrescaler {
98 NotDivided,
99 Div2,
100 Div4,
101 Div8,
102 Div16,
103}
104
105/// PLL clock input source 82/// PLL clock input source
106#[derive(Clone, Copy)] 83#[derive(Clone, Copy)]
107pub enum PLLSource { 84pub enum PLLSource {
@@ -209,34 +186,6 @@ impl From<PLLSource> for Pllsrc {
209 } 186 }
210} 187}
211 188
212impl From<APBPrescaler> for Ppre {
213 fn from(val: APBPrescaler) -> Ppre {
214 match val {
215 APBPrescaler::NotDivided => Ppre::DIV1,
216 APBPrescaler::Div2 => Ppre::DIV2,
217 APBPrescaler::Div4 => Ppre::DIV4,
218 APBPrescaler::Div8 => Ppre::DIV8,
219 APBPrescaler::Div16 => Ppre::DIV16,
220 }
221 }
222}
223
224impl From<AHBPrescaler> for Hpre {
225 fn from(val: AHBPrescaler) -> Hpre {
226 match val {
227 AHBPrescaler::NotDivided => Hpre::DIV1,
228 AHBPrescaler::Div2 => Hpre::DIV2,
229 AHBPrescaler::Div4 => Hpre::DIV4,
230 AHBPrescaler::Div8 => Hpre::DIV8,
231 AHBPrescaler::Div16 => Hpre::DIV16,
232 AHBPrescaler::Div64 => Hpre::DIV64,
233 AHBPrescaler::Div128 => Hpre::DIV128,
234 AHBPrescaler::Div256 => Hpre::DIV256,
235 AHBPrescaler::Div512 => Hpre::DIV512,
236 }
237 }
238}
239
240impl From<MSIRange> for Msirange { 189impl From<MSIRange> for Msirange {
241 fn from(val: MSIRange) -> Msirange { 190 fn from(val: MSIRange) -> Msirange {
242 match val { 191 match val {
diff --git a/embassy-stm32/src/rcc/l5.rs b/embassy-stm32/src/rcc/l5.rs
index 16da65d5e..a85e14889 100644
--- a/embassy-stm32/src/rcc/l5.rs
+++ b/embassy-stm32/src/rcc/l5.rs
@@ -1,5 +1,6 @@
1use stm32_metapac::PWR; 1use stm32_metapac::PWR;
2 2
3pub use super::common::{AHBPrescaler, APBPrescaler};
3use crate::pac::rcc::vals::{Hpre, Msirange, Pllsrc, Ppre, Sw}; 4use crate::pac::rcc::vals::{Hpre, Msirange, Pllsrc, Ppre, Sw};
4use crate::pac::{FLASH, RCC}; 5use crate::pac::{FLASH, RCC};
5use crate::rcc::{set_freqs, Clocks}; 6use crate::rcc::{set_freqs, Clocks};
@@ -71,30 +72,6 @@ pub enum PLLDiv {
71 Div4, 72 Div4,
72} 73}
73 74
74/// AHB prescaler
75#[derive(Clone, Copy, PartialEq)]
76pub enum AHBPrescaler {
77 NotDivided,
78 Div2,
79 Div4,
80 Div8,
81 Div16,
82 Div64,
83 Div128,
84 Div256,
85 Div512,
86}
87
88/// APB prescaler
89#[derive(Clone, Copy)]
90pub enum APBPrescaler {
91 NotDivided,
92 Div2,
93 Div4,
94 Div8,
95 Div16,
96}
97
98/// PLL clock input source 75/// PLL clock input source
99#[derive(Clone, Copy)] 76#[derive(Clone, Copy)]
100pub enum PLLSource { 77pub enum PLLSource {
@@ -202,34 +179,6 @@ impl From<PLLSource> for Pllsrc {
202 } 179 }
203} 180}
204 181
205impl From<APBPrescaler> for Ppre {
206 fn from(val: APBPrescaler) -> Ppre {
207 match val {
208 APBPrescaler::NotDivided => Ppre::DIV1,
209 APBPrescaler::Div2 => Ppre::DIV2,
210 APBPrescaler::Div4 => Ppre::DIV4,
211 APBPrescaler::Div8 => Ppre::DIV8,
212 APBPrescaler::Div16 => Ppre::DIV16,
213 }
214 }
215}
216
217impl From<AHBPrescaler> for Hpre {
218 fn from(val: AHBPrescaler) -> Hpre {
219 match val {
220 AHBPrescaler::NotDivided => Hpre::DIV1,
221 AHBPrescaler::Div2 => Hpre::DIV2,
222 AHBPrescaler::Div4 => Hpre::DIV4,
223 AHBPrescaler::Div8 => Hpre::DIV8,
224 AHBPrescaler::Div16 => Hpre::DIV16,
225 AHBPrescaler::Div64 => Hpre::DIV64,
226 AHBPrescaler::Div128 => Hpre::DIV128,
227 AHBPrescaler::Div256 => Hpre::DIV256,
228 AHBPrescaler::Div512 => Hpre::DIV512,
229 }
230 }
231}
232
233impl From<MSIRange> for Msirange { 182impl From<MSIRange> for Msirange {
234 fn from(val: MSIRange) -> Msirange { 183 fn from(val: MSIRange) -> Msirange {
235 match val { 184 match val {
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index 4ae65d3e6..5c69037ed 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -1,5 +1,7 @@
1#![macro_use] 1#![macro_use]
2 2
3pub mod common;
4
3use core::mem::MaybeUninit; 5use core::mem::MaybeUninit;
4 6
5use crate::time::Hertz; 7use crate::time::Hertz;
diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs
index cfc07f069..b5feeb0c4 100644
--- a/embassy-stm32/src/rcc/u5.rs
+++ b/embassy-stm32/src/rcc/u5.rs
@@ -1,5 +1,6 @@
1use stm32_metapac::rcc::vals::{Hpre, Msirange, Msirgsel, Pllm, Pllsrc, Ppre, Sw}; 1use stm32_metapac::rcc::vals::{Msirange, Msirgsel, Pllm, Pllsrc, Sw};
2 2
3pub use super::common::{AHBPrescaler, APBPrescaler};
3use crate::pac::{FLASH, RCC}; 4use crate::pac::{FLASH, RCC};
4use crate::rcc::{set_freqs, Clocks}; 5use crate::rcc::{set_freqs, Clocks};
5use crate::time::Hertz; 6use crate::time::Hertz;
@@ -10,19 +11,7 @@ pub const HSI_FREQ: Hertz = Hertz(16_000_000);
10/// LSI speed 11/// LSI speed
11pub const LSI_FREQ: Hertz = Hertz(32_000); 12pub const LSI_FREQ: Hertz = Hertz(32_000);
12 13
13/// Voltage Scale 14pub use super::common::VoltageScale;
14///
15/// Represents the voltage range feeding the CPU core. The maximum core
16/// clock frequency depends on this value.
17#[derive(Copy, Clone, PartialEq)]
18pub enum VoltageScale {
19 // Highest frequency
20 Range1,
21 Range2,
22 Range3,
23 // Lowest power
24 Range4,
25}
26 15
27#[derive(Copy, Clone)] 16#[derive(Copy, Clone)]
28pub enum ClockSrc { 17pub enum ClockSrc {
@@ -130,36 +119,6 @@ impl Into<Pllm> for PllM {
130 } 119 }
131} 120}
132 121
133/// AHB prescaler
134#[derive(Clone, Copy, PartialEq)]
135pub enum AHBPrescaler {
136 NotDivided,
137 Div2,
138 Div4,
139 Div8,
140 Div16,
141 Div64,
142 Div128,
143 Div256,
144 Div512,
145}
146
147impl Into<Hpre> for AHBPrescaler {
148 fn into(self) -> Hpre {
149 match self {
150 AHBPrescaler::NotDivided => Hpre::NONE,
151 AHBPrescaler::Div2 => Hpre::DIV2,
152 AHBPrescaler::Div4 => Hpre::DIV4,
153 AHBPrescaler::Div8 => Hpre::DIV8,
154 AHBPrescaler::Div16 => Hpre::DIV16,
155 AHBPrescaler::Div64 => Hpre::DIV64,
156 AHBPrescaler::Div128 => Hpre::DIV128,
157 AHBPrescaler::Div256 => Hpre::DIV256,
158 AHBPrescaler::Div512 => Hpre::DIV512,
159 }
160 }
161}
162
163impl Into<u8> for AHBPrescaler { 122impl Into<u8> for AHBPrescaler {
164 fn into(self) -> u8 { 123 fn into(self) -> u8 {
165 match self { 124 match self {
@@ -182,28 +141,6 @@ impl Default for AHBPrescaler {
182 } 141 }
183} 142}
184 143
185/// APB prescaler
186#[derive(Clone, Copy)]
187pub enum APBPrescaler {
188 NotDivided,
189 Div2,
190 Div4,
191 Div8,
192 Div16,
193}
194
195impl Into<Ppre> for APBPrescaler {
196 fn into(self) -> Ppre {
197 match self {
198 APBPrescaler::NotDivided => Ppre::NONE,
199 APBPrescaler::Div2 => Ppre::DIV2,
200 APBPrescaler::Div4 => Ppre::DIV4,
201 APBPrescaler::Div8 => Ppre::DIV8,
202 APBPrescaler::Div16 => Ppre::DIV16,
203 }
204 }
205}
206
207impl Default for APBPrescaler { 144impl Default for APBPrescaler {
208 fn default() -> Self { 145 fn default() -> Self {
209 APBPrescaler::NotDivided 146 APBPrescaler::NotDivided
@@ -389,12 +326,12 @@ pub(crate) unsafe fn init(config: Config) {
389 } 326 }
390 327
391 // TODO make configurable 328 // TODO make configurable
392 let power_vos = VoltageScale::Range4; 329 let power_vos = VoltageScale::Scale3;
393 330
394 // states and programming delay 331 // states and programming delay
395 let wait_states = match power_vos { 332 let wait_states = match power_vos {
396 // VOS 0 range VCORE 1.26V - 1.40V 333 // VOS 0 range VCORE 1.26V - 1.40V
397 VoltageScale::Range1 => { 334 VoltageScale::Scale0 => {
398 if sys_clk < 32_000_000 { 335 if sys_clk < 32_000_000 {
399 0 336 0
400 } else if sys_clk < 64_000_000 { 337 } else if sys_clk < 64_000_000 {
@@ -408,7 +345,7 @@ pub(crate) unsafe fn init(config: Config) {
408 } 345 }
409 } 346 }
410 // VOS 1 range VCORE 1.15V - 1.26V 347 // VOS 1 range VCORE 1.15V - 1.26V
411 VoltageScale::Range2 => { 348 VoltageScale::Scale1 => {
412 if sys_clk < 30_000_000 { 349 if sys_clk < 30_000_000 {
413 0 350 0
414 } else if sys_clk < 60_000_000 { 351 } else if sys_clk < 60_000_000 {
@@ -420,7 +357,7 @@ pub(crate) unsafe fn init(config: Config) {
420 } 357 }
421 } 358 }
422 // VOS 2 range VCORE 1.05V - 1.15V 359 // VOS 2 range VCORE 1.05V - 1.15V
423 VoltageScale::Range3 => { 360 VoltageScale::Scale2 => {
424 if sys_clk < 24_000_000 { 361 if sys_clk < 24_000_000 {
425 0 362 0
426 } else if sys_clk < 48_000_000 { 363 } else if sys_clk < 48_000_000 {
@@ -430,7 +367,7 @@ pub(crate) unsafe fn init(config: Config) {
430 } 367 }
431 } 368 }
432 // VOS 3 range VCORE 0.95V - 1.05V 369 // VOS 3 range VCORE 0.95V - 1.05V
433 VoltageScale::Range4 => { 370 VoltageScale::Scale3 => {
434 if sys_clk < 12_000_000 { 371 if sys_clk < 12_000_000 {
435 0 372 0
436 } else { 373 } else {
diff --git a/embassy-stm32/src/rcc/wb.rs b/embassy-stm32/src/rcc/wb.rs
index 4322b950a..21aacec58 100644
--- a/embassy-stm32/src/rcc/wb.rs
+++ b/embassy-stm32/src/rcc/wb.rs
@@ -1,3 +1,4 @@
1pub use super::common::{AHBPrescaler, APBPrescaler};
1use crate::rcc::Clocks; 2use crate::rcc::Clocks;
2use crate::time::{khz, mhz, Hertz}; 3use crate::time::{khz, mhz, Hertz};
3 4
@@ -102,68 +103,6 @@ pub struct Pll {
102 pub divr: Option<u16>, 103 pub divr: Option<u16>,
103} 104}
104 105
105/// AHB prescaler
106#[derive(Clone, Copy, PartialEq)]
107pub enum AHBPrescaler {
108 NotDivided,
109 Div2,
110 Div3,
111 Div4,
112 Div5,
113 Div6,
114 Div8,
115 Div10,
116 Div16,
117 Div32,
118 Div64,
119 Div128,
120 Div256,
121 Div512,
122}
123
124/// APB prescaler
125#[derive(Clone, Copy)]
126pub enum APBPrescaler {
127 NotDivided,
128 Div2,
129 Div4,
130 Div8,
131 Div16,
132}
133
134impl Into<u8> for APBPrescaler {
135 fn into(self) -> u8 {
136 match self {
137 APBPrescaler::NotDivided => 1,
138 APBPrescaler::Div2 => 0x04,
139 APBPrescaler::Div4 => 0x05,
140 APBPrescaler::Div8 => 0x06,
141 APBPrescaler::Div16 => 0x07,
142 }
143 }
144}
145
146impl Into<u8> for AHBPrescaler {
147 fn into(self) -> u8 {
148 match self {
149 AHBPrescaler::NotDivided => 0x0,
150 AHBPrescaler::Div2 => 0x08,
151 AHBPrescaler::Div3 => 0x01,
152 AHBPrescaler::Div4 => 0x09,
153 AHBPrescaler::Div5 => 0x02,
154 AHBPrescaler::Div6 => 0x05,
155 AHBPrescaler::Div8 => 0x0a,
156 AHBPrescaler::Div10 => 0x06,
157 AHBPrescaler::Div16 => 0x0b,
158 AHBPrescaler::Div32 => 0x07,
159 AHBPrescaler::Div64 => 0x0c,
160 AHBPrescaler::Div128 => 0x0d,
161 AHBPrescaler::Div256 => 0x0e,
162 AHBPrescaler::Div512 => 0x0f,
163 }
164 }
165}
166
167/// Clocks configutation 106/// Clocks configutation
168pub struct Config { 107pub struct Config {
169 pub hse: Option<Hse>, 108 pub hse: Option<Hse>,
diff --git a/embassy-stm32/src/rcc/wl.rs b/embassy-stm32/src/rcc/wl.rs
index 6b69bb1cb..ea6e8dde6 100644
--- a/embassy-stm32/src/rcc/wl.rs
+++ b/embassy-stm32/src/rcc/wl.rs
@@ -1,3 +1,4 @@
1pub use super::common::{AHBPrescaler, APBPrescaler, VoltageScale};
1use crate::pac::pwr::vals::Dbp; 2use crate::pac::pwr::vals::Dbp;
2use crate::pac::{FLASH, PWR, RCC}; 3use crate::pac::{FLASH, PWR, RCC};
3use crate::rcc::{set_freqs, Clocks}; 4use crate::rcc::{set_freqs, Clocks};
@@ -73,9 +74,9 @@ impl MSIRange {
73 74
74 fn vos(&self) -> VoltageScale { 75 fn vos(&self) -> VoltageScale {
75 if self > &MSIRange::Range8 { 76 if self > &MSIRange::Range8 {
76 VoltageScale::Range1 77 VoltageScale::Scale0
77 } else { 78 } else {
78 VoltageScale::Range2 79 VoltageScale::Scale1
79 } 80 }
80 } 81 }
81} 82}
@@ -105,78 +106,6 @@ impl Into<u8> for MSIRange {
105 } 106 }
106} 107}
107 108
108/// Voltage Scale
109///
110/// Represents the voltage range feeding the CPU core. The maximum core
111/// clock frequency depends on this value.
112#[derive(Copy, Clone, PartialEq)]
113pub enum VoltageScale {
114 Range1,
115 Range2,
116}
117
118/// AHB prescaler
119#[derive(Clone, Copy, PartialEq)]
120pub enum AHBPrescaler {
121 NotDivided,
122 Div2,
123 Div3,
124 Div4,
125 Div5,
126 Div6,
127 Div8,
128 Div10,
129 Div16,
130 Div32,
131 Div64,
132 Div128,
133 Div256,
134 Div512,
135}
136
137/// APB prescaler
138#[derive(Clone, Copy)]
139pub enum APBPrescaler {
140 NotDivided,
141 Div2,
142 Div4,
143 Div8,
144 Div16,
145}
146
147impl Into<u8> for APBPrescaler {
148 fn into(self) -> u8 {
149 match self {
150 APBPrescaler::NotDivided => 1,
151 APBPrescaler::Div2 => 0x04,
152 APBPrescaler::Div4 => 0x05,
153 APBPrescaler::Div8 => 0x06,
154 APBPrescaler::Div16 => 0x07,
155 }
156 }
157}
158
159impl Into<u8> for AHBPrescaler {
160 fn into(self) -> u8 {
161 match self {
162 AHBPrescaler::NotDivided => 0x0,
163 AHBPrescaler::Div2 => 0x08,
164 AHBPrescaler::Div3 => 0x01,
165 AHBPrescaler::Div4 => 0x09,
166 AHBPrescaler::Div5 => 0x02,
167 AHBPrescaler::Div6 => 0x05,
168 AHBPrescaler::Div8 => 0x0a,
169 AHBPrescaler::Div10 => 0x06,
170 AHBPrescaler::Div16 => 0x0b,
171 AHBPrescaler::Div32 => 0x07,
172 AHBPrescaler::Div64 => 0x0c,
173 AHBPrescaler::Div128 => 0x0d,
174 AHBPrescaler::Div256 => 0x0e,
175 AHBPrescaler::Div512 => 0x0f,
176 }
177 }
178}
179
180/// Clocks configutation 109/// Clocks configutation
181pub struct Config { 110pub struct Config {
182 pub mux: ClockSrc, 111 pub mux: ClockSrc,
@@ -220,8 +149,8 @@ pub enum Lsedrv {
220 149
221pub(crate) unsafe fn init(config: Config) { 150pub(crate) unsafe fn init(config: Config) {
222 let (sys_clk, sw, vos) = match config.mux { 151 let (sys_clk, sw, vos) = match config.mux {
223 ClockSrc::HSI16 => (HSI_FREQ.0, 0x01, VoltageScale::Range2), 152 ClockSrc::HSI16 => (HSI_FREQ.0, 0x01, VoltageScale::Scale1),
224 ClockSrc::HSE32 => (HSE32_FREQ.0, 0x02, VoltageScale::Range1), 153 ClockSrc::HSE32 => (HSE32_FREQ.0, 0x02, VoltageScale::Scale0),
225 ClockSrc::MSI(range) => (range.freq(), 0x00, range.vos()), 154 ClockSrc::MSI(range) => (range.freq(), 0x00, range.vos()),
226 }; 155 };
227 156
@@ -266,12 +195,12 @@ pub(crate) unsafe fn init(config: Config) {
266 // Adjust flash latency 195 // Adjust flash latency
267 let flash_clk_src_freq: u32 = shd_ahb_freq; 196 let flash_clk_src_freq: u32 = shd_ahb_freq;
268 let ws = match vos { 197 let ws = match vos {
269 VoltageScale::Range1 => match flash_clk_src_freq { 198 VoltageScale::Scale0 => match flash_clk_src_freq {
270 0..=18_000_000 => 0b000, 199 0..=18_000_000 => 0b000,
271 18_000_001..=36_000_000 => 0b001, 200 18_000_001..=36_000_000 => 0b001,
272 _ => 0b010, 201 _ => 0b010,
273 }, 202 },
274 VoltageScale::Range2 => match flash_clk_src_freq { 203 VoltageScale::Scale1 => match flash_clk_src_freq {
275 0..=6_000_000 => 0b000, 204 0..=6_000_000 => 0b000,
276 6_000_001..=12_000_000 => 0b001, 205 6_000_001..=12_000_000 => 0b001,
277 _ => 0b010, 206 _ => 0b010,
generated by cgit (git 2.34.1) at 2026-04-06 19:30:51 +0000