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-rw-r--r--embassy-stm32/Cargo.toml4
-rw-r--r--embassy-stm32/src/rcc/bus.rs144
-rw-r--r--embassy-stm32/src/rcc/c0.rs25
-rw-r--r--embassy-stm32/src/rcc/f1.rs4
-rw-r--r--embassy-stm32/src/rcc/f2.rs10
-rw-r--r--embassy-stm32/src/rcc/g0.rs6
-rw-r--r--embassy-stm32/src/rcc/g4.rs90
-rw-r--r--embassy-stm32/src/rcc/h5.rs50
-rw-r--r--embassy-stm32/src/rcc/h7.rs10
-rw-r--r--embassy-stm32/src/rcc/l0.rs12
-rw-r--r--embassy-stm32/src/rcc/l1.rs12
-rw-r--r--embassy-stm32/src/rcc/l4.rs12
-rw-r--r--embassy-stm32/src/rcc/l5.rs12
-rw-r--r--embassy-stm32/src/rcc/u5.rs56
-rw-r--r--embassy-stm32/src/rcc/wb.rs30
-rw-r--r--embassy-stm32/src/rcc/wl.rs24
-rw-r--r--examples/stm32f2/src/bin/pll.rs4
-rw-r--r--examples/stm32h5/src/bin/eth.rs8
-rw-r--r--examples/stm32h5/src/bin/usb_serial.rs8
19 files changed, 174 insertions, 347 deletions
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 699995bc5..0cae981c7 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -59,7 +59,7 @@ sdio-host = "0.5.0"
59embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true } 59embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
60critical-section = "1.1" 60critical-section = "1.1"
61atomic-polyfill = "1.0.1" 61atomic-polyfill = "1.0.1"
62stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-546aead07086342605102d66dec49c5e2d459a0c" } 62stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-907dd82c848bc912252c61509944e85c2a48c919" }
63vcell = "0.1.3" 63vcell = "0.1.3"
64bxcan = "0.7.0" 64bxcan = "0.7.0"
65nb = "1.0.0" 65nb = "1.0.0"
@@ -78,7 +78,7 @@ critical-section = { version = "1.1", features = ["std"] }
78[build-dependencies] 78[build-dependencies]
79proc-macro2 = "1.0.36" 79proc-macro2 = "1.0.36"
80quote = "1.0.15" 80quote = "1.0.15"
81stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-546aead07086342605102d66dec49c5e2d459a0c", default-features = false, features = ["metadata"]} 81stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-907dd82c848bc912252c61509944e85c2a48c919", default-features = false, features = ["metadata"]}
82 82
83[features] 83[features]
84default = ["rt"] 84default = ["rt"]
diff --git a/embassy-stm32/src/rcc/bus.rs b/embassy-stm32/src/rcc/bus.rs
index 32e10b7ec..fb6dcb01d 100644
--- a/embassy-stm32/src/rcc/bus.rs
+++ b/embassy-stm32/src/rcc/bus.rs
@@ -2,6 +2,7 @@ use core::ops::Div;
2 2
3#[allow(unused_imports)] 3#[allow(unused_imports)]
4use crate::pac::rcc; 4use crate::pac::rcc;
5pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Ppre as APBPrescaler};
5use crate::time::Hertz; 6use crate::time::Hertz;
6 7
7/// Voltage Scale 8/// Voltage Scale
@@ -20,149 +21,48 @@ pub enum VoltageScale {
20 Scale3, 21 Scale3,
21} 22}
22 23
23/// AHB prescaler
24#[derive(Clone, Copy, PartialEq)]
25pub enum AHBPrescaler {
26 NotDivided,
27 Div2,
28 #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
29 Div3,
30 Div4,
31 #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
32 Div5,
33 #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
34 Div6,
35 Div8,
36 #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
37 Div10,
38 Div16,
39 #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
40 Div32,
41 Div64,
42 Div128,
43 Div256,
44 Div512,
45}
46
47impl Div<AHBPrescaler> for Hertz { 24impl Div<AHBPrescaler> for Hertz {
48 type Output = Hertz; 25 type Output = Hertz;
49 26
50 fn div(self, rhs: AHBPrescaler) -> Self::Output { 27 fn div(self, rhs: AHBPrescaler) -> Self::Output {
51 let divisor = match rhs { 28 let divisor = match rhs {
52 AHBPrescaler::NotDivided => 1, 29 AHBPrescaler::DIV1 => 1,
53 AHBPrescaler::Div2 => 2, 30 AHBPrescaler::DIV2 => 2,
54 #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))] 31 #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
55 AHBPrescaler::Div3 => 3, 32 AHBPrescaler::DIV3 => 3,
56 AHBPrescaler::Div4 => 4, 33 AHBPrescaler::DIV4 => 4,
57 #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))] 34 #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
58 AHBPrescaler::Div5 => 5, 35 AHBPrescaler::DIV5 => 5,
59 #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))] 36 #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
60 AHBPrescaler::Div6 => 6, 37 AHBPrescaler::DIV6 => 6,
61 AHBPrescaler::Div8 => 8, 38 AHBPrescaler::DIV8 => 8,
62 #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))] 39 #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
63 AHBPrescaler::Div10 => 10, 40 AHBPrescaler::DIV10 => 10,
64 AHBPrescaler::Div16 => 16, 41 AHBPrescaler::DIV16 => 16,
65 #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))] 42 #[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
66 AHBPrescaler::Div32 => 32, 43 AHBPrescaler::DIV32 => 32,
67 AHBPrescaler::Div64 => 64, 44 AHBPrescaler::DIV64 => 64,
68 AHBPrescaler::Div128 => 128, 45 AHBPrescaler::DIV128 => 128,
69 AHBPrescaler::Div256 => 256, 46 AHBPrescaler::DIV256 => 256,
70 AHBPrescaler::Div512 => 512, 47 AHBPrescaler::DIV512 => 512,
48 _ => unreachable!(),
71 }; 49 };
72 Hertz(self.0 / divisor) 50 Hertz(self.0 / divisor)
73 } 51 }
74} 52}
75 53
76#[cfg(not(any(rcc_g4, rcc_wb, rcc_wl5, rcc_wle)))]
77impl From<AHBPrescaler> for rcc::vals::Hpre {
78 fn from(val: AHBPrescaler) -> rcc::vals::Hpre {
79 use rcc::vals::Hpre;
80
81 match val {
82 AHBPrescaler::NotDivided => Hpre::DIV1,
83 AHBPrescaler::Div2 => Hpre::DIV2,
84 AHBPrescaler::Div4 => Hpre::DIV4,
85 AHBPrescaler::Div8 => Hpre::DIV8,
86 AHBPrescaler::Div16 => Hpre::DIV16,
87 AHBPrescaler::Div64 => Hpre::DIV64,
88 AHBPrescaler::Div128 => Hpre::DIV128,
89 AHBPrescaler::Div256 => Hpre::DIV256,
90 AHBPrescaler::Div512 => Hpre::DIV512,
91 }
92 }
93}
94
95#[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
96impl From<AHBPrescaler> for u8 {
97 fn from(val: AHBPrescaler) -> u8 {
98 match val {
99 AHBPrescaler::NotDivided => 0x0,
100 AHBPrescaler::Div2 => 0x08,
101 AHBPrescaler::Div3 => 0x01,
102 AHBPrescaler::Div4 => 0x09,
103 AHBPrescaler::Div5 => 0x02,
104 AHBPrescaler::Div6 => 0x05,
105 AHBPrescaler::Div8 => 0x0a,
106 AHBPrescaler::Div10 => 0x06,
107 AHBPrescaler::Div16 => 0x0b,
108 AHBPrescaler::Div32 => 0x07,
109 AHBPrescaler::Div64 => 0x0c,
110 AHBPrescaler::Div128 => 0x0d,
111 AHBPrescaler::Div256 => 0x0e,
112 AHBPrescaler::Div512 => 0x0f,
113 }
114 }
115}
116
117/// APB prescaler
118#[derive(Clone, Copy)]
119pub enum APBPrescaler {
120 NotDivided,
121 Div2,
122 Div4,
123 Div8,
124 Div16,
125}
126
127impl Div<APBPrescaler> for Hertz { 54impl Div<APBPrescaler> for Hertz {
128 type Output = Hertz; 55 type Output = Hertz;
129 56
130 fn div(self, rhs: APBPrescaler) -> Self::Output { 57 fn div(self, rhs: APBPrescaler) -> Self::Output {
131 let divisor = match rhs { 58 let divisor = match rhs {
132 APBPrescaler::NotDivided => 1, 59 APBPrescaler::DIV1 => 1,
133 APBPrescaler::Div2 => 2, 60 APBPrescaler::DIV2 => 2,
134 APBPrescaler::Div4 => 4, 61 APBPrescaler::DIV4 => 4,
135 APBPrescaler::Div8 => 8, 62 APBPrescaler::DIV8 => 8,
136 APBPrescaler::Div16 => 16, 63 APBPrescaler::DIV16 => 16,
64 _ => unreachable!(),
137 }; 65 };
138 Hertz(self.0 / divisor) 66 Hertz(self.0 / divisor)
139 } 67 }
140} 68}
141
142#[cfg(not(any(rcc_f1, rcc_f100, rcc_f1cl, rcc_g4, rcc_h7, rcc_h7ab, rcc_wb, rcc_wl5, rcc_wle)))]
143impl From<APBPrescaler> for rcc::vals::Ppre {
144 fn from(val: APBPrescaler) -> rcc::vals::Ppre {
145 use rcc::vals::Ppre;
146
147 match val {
148 APBPrescaler::NotDivided => Ppre::DIV1,
149 APBPrescaler::Div2 => Ppre::DIV2,
150 APBPrescaler::Div4 => Ppre::DIV4,
151 APBPrescaler::Div8 => Ppre::DIV8,
152 APBPrescaler::Div16 => Ppre::DIV16,
153 }
154 }
155}
156
157#[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
158impl From<APBPrescaler> for u8 {
159 fn from(val: APBPrescaler) -> u8 {
160 match val {
161 APBPrescaler::NotDivided => 1,
162 APBPrescaler::Div2 => 0x04,
163 APBPrescaler::Div4 => 0x05,
164 APBPrescaler::Div8 => 0x06,
165 APBPrescaler::Div16 => 0x07,
166 }
167 }
168}
diff --git a/embassy-stm32/src/rcc/c0.rs b/embassy-stm32/src/rcc/c0.rs
index d85790797..8f45e7c0f 100644
--- a/embassy-stm32/src/rcc/c0.rs
+++ b/embassy-stm32/src/rcc/c0.rs
@@ -58,8 +58,8 @@ impl Default for Config {
58 fn default() -> Config { 58 fn default() -> Config {
59 Config { 59 Config {
60 mux: ClockSrc::HSI(HSIPrescaler::NotDivided), 60 mux: ClockSrc::HSI(HSIPrescaler::NotDivided),
61 ahb_pre: AHBPrescaler::NotDivided, 61 ahb_pre: AHBPrescaler::DIV1,
62 apb_pre: APBPrescaler::NotDivided, 62 apb_pre: APBPrescaler::DIV1,
63 } 63 }
64 } 64 }
65} 65}
@@ -151,20 +151,21 @@ pub(crate) unsafe fn init(config: Config) {
151 } 151 }
152 152
153 let ahb_div = match config.ahb_pre { 153 let ahb_div = match config.ahb_pre {
154 AHBPrescaler::NotDivided => 1, 154 AHBPrescaler::DIV1 => 1,
155 AHBPrescaler::Div2 => 2, 155 AHBPrescaler::DIV2 => 2,
156 AHBPrescaler::Div4 => 4, 156 AHBPrescaler::DIV4 => 4,
157 AHBPrescaler::Div8 => 8, 157 AHBPrescaler::DIV8 => 8,
158 AHBPrescaler::Div16 => 16, 158 AHBPrescaler::DIV16 => 16,
159 AHBPrescaler::Div64 => 64, 159 AHBPrescaler::DIV64 => 64,
160 AHBPrescaler::Div128 => 128, 160 AHBPrescaler::DIV128 => 128,
161 AHBPrescaler::Div256 => 256, 161 AHBPrescaler::DIV256 => 256,
162 AHBPrescaler::Div512 => 512, 162 AHBPrescaler::DIV512 => 512,
163 _ => unreachable!(),
163 }; 164 };
164 let ahb_freq = sys_clk / ahb_div; 165 let ahb_freq = sys_clk / ahb_div;
165 166
166 let (apb_freq, apb_tim_freq) = match config.apb_pre { 167 let (apb_freq, apb_tim_freq) = match config.apb_pre {
167 APBPrescaler::NotDivided => (ahb_freq, ahb_freq), 168 APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
168 pre => { 169 pre => {
169 let pre: Ppre = pre.into(); 170 let pre: Ppre = pre.into();
170 let pre: u8 = 1 << (pre.to_bits() - 3); 171 let pre: u8 = 1 << (pre.to_bits() - 3);
diff --git a/embassy-stm32/src/rcc/f1.rs b/embassy-stm32/src/rcc/f1.rs
index 304d8f504..081c0c767 100644
--- a/embassy-stm32/src/rcc/f1.rs
+++ b/embassy-stm32/src/rcc/f1.rs
@@ -163,8 +163,8 @@ pub(crate) unsafe fn init(config: Config) {
163 // Only needed for stm32f103? 163 // Only needed for stm32f103?
164 RCC.cfgr().modify(|w| { 164 RCC.cfgr().modify(|w| {
165 w.set_adcpre(Adcpre::from_bits(apre_bits)); 165 w.set_adcpre(Adcpre::from_bits(apre_bits));
166 w.set_ppre2(Ppre1::from_bits(ppre2_bits)); 166 w.set_ppre2(Ppre::from_bits(ppre2_bits));
167 w.set_ppre1(Ppre1::from_bits(ppre1_bits)); 167 w.set_ppre1(Ppre::from_bits(ppre1_bits));
168 w.set_hpre(Hpre::from_bits(hpre_bits)); 168 w.set_hpre(Hpre::from_bits(hpre_bits));
169 #[cfg(not(rcc_f100))] 169 #[cfg(not(rcc_f100))]
170 w.set_usbpre(Usbpre::from_bits(usbpre as u8)); 170 w.set_usbpre(Usbpre::from_bits(usbpre as u8));
diff --git a/embassy-stm32/src/rcc/f2.rs b/embassy-stm32/src/rcc/f2.rs
index b821f9585..da88e44dc 100644
--- a/embassy-stm32/src/rcc/f2.rs
+++ b/embassy-stm32/src/rcc/f2.rs
@@ -308,9 +308,9 @@ impl Default for Config {
308 voltage: VoltageScale::Scale3, 308 voltage: VoltageScale::Scale3,
309 mux: ClockSrc::HSI, 309 mux: ClockSrc::HSI,
310 rtc: None, 310 rtc: None,
311 ahb_pre: AHBPrescaler::NotDivided, 311 ahb_pre: AHBPrescaler::DIV1,
312 apb1_pre: APBPrescaler::NotDivided, 312 apb1_pre: APBPrescaler::DIV1,
313 apb2_pre: APBPrescaler::NotDivided, 313 apb2_pre: APBPrescaler::DIV1,
314 } 314 }
315 } 315 }
316} 316}
@@ -383,7 +383,7 @@ pub(crate) unsafe fn init(config: Config) {
383 assert!(ahb_freq <= Hertz(120_000_000)); 383 assert!(ahb_freq <= Hertz(120_000_000));
384 384
385 let (apb1_freq, apb1_tim_freq) = match config.apb1_pre { 385 let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
386 APBPrescaler::NotDivided => (ahb_freq, ahb_freq), 386 APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
387 pre => { 387 pre => {
388 let freq = ahb_freq / pre; 388 let freq = ahb_freq / pre;
389 (freq, Hertz(freq.0 * 2)) 389 (freq, Hertz(freq.0 * 2))
@@ -393,7 +393,7 @@ pub(crate) unsafe fn init(config: Config) {
393 assert!(apb1_freq <= Hertz(30_000_000)); 393 assert!(apb1_freq <= Hertz(30_000_000));
394 394
395 let (apb2_freq, apb2_tim_freq) = match config.apb2_pre { 395 let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
396 APBPrescaler::NotDivided => (ahb_freq, ahb_freq), 396 APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
397 pre => { 397 pre => {
398 let freq = ahb_freq / pre; 398 let freq = ahb_freq / pre;
399 (freq, Hertz(freq.0 * 2)) 399 (freq, Hertz(freq.0 * 2))
diff --git a/embassy-stm32/src/rcc/g0.rs b/embassy-stm32/src/rcc/g0.rs
index 7fdbcb00c..7f0a2c7fb 100644
--- a/embassy-stm32/src/rcc/g0.rs
+++ b/embassy-stm32/src/rcc/g0.rs
@@ -186,8 +186,8 @@ impl Default for Config {
186 fn default() -> Config { 186 fn default() -> Config {
187 Config { 187 Config {
188 mux: ClockSrc::HSI16(HSI16Prescaler::NotDivided), 188 mux: ClockSrc::HSI16(HSI16Prescaler::NotDivided),
189 ahb_pre: AHBPrescaler::NotDivided, 189 ahb_pre: AHBPrescaler::DIV1,
190 apb_pre: APBPrescaler::NotDivided, 190 apb_pre: APBPrescaler::DIV1,
191 low_power_run: false, 191 low_power_run: false,
192 } 192 }
193 } 193 }
@@ -377,7 +377,7 @@ pub(crate) unsafe fn init(config: Config) {
377 let ahb_freq = Hertz(sys_clk) / config.ahb_pre; 377 let ahb_freq = Hertz(sys_clk) / config.ahb_pre;
378 378
379 let (apb_freq, apb_tim_freq) = match config.apb_pre { 379 let (apb_freq, apb_tim_freq) = match config.apb_pre {
380 APBPrescaler::NotDivided => (ahb_freq.0, ahb_freq.0), 380 APBPrescaler::DIV1 => (ahb_freq.0, ahb_freq.0),
381 pre => { 381 pre => {
382 let pre: Ppre = pre.into(); 382 let pre: Ppre = pre.into();
383 let pre: u8 = 1 << (pre.to_bits() - 3); 383 let pre: u8 = 1 << (pre.to_bits() - 3);
diff --git a/embassy-stm32/src/rcc/g4.rs b/embassy-stm32/src/rcc/g4.rs
index 2359f39c1..41bebc918 100644
--- a/embassy-stm32/src/rcc/g4.rs
+++ b/embassy-stm32/src/rcc/g4.rs
@@ -1,5 +1,5 @@
1use stm32_metapac::flash::vals::Latency; 1use stm32_metapac::flash::vals::Latency;
2use stm32_metapac::rcc::vals::{Adcsel, Hpre, Pllsrc, Ppre, Sw}; 2use stm32_metapac::rcc::vals::{Adcsel, Pllsrc, Sw};
3use stm32_metapac::FLASH; 3use stm32_metapac::FLASH;
4 4
5pub use super::bus::{AHBPrescaler, APBPrescaler}; 5pub use super::bus::{AHBPrescaler, APBPrescaler};
@@ -261,59 +261,29 @@ pub struct Pll {
261 pub div_r: Option<PllR>, 261 pub div_r: Option<PllR>,
262} 262}
263 263
264impl AHBPrescaler { 264fn ahb_div(ahb: AHBPrescaler) -> u32 {
265 const fn div(self) -> u32 { 265 match ahb {
266 match self { 266 AHBPrescaler::DIV1 => 1,
267 AHBPrescaler::NotDivided => 1, 267 AHBPrescaler::DIV2 => 2,
268 AHBPrescaler::Div2 => 2, 268 AHBPrescaler::DIV4 => 4,
269 AHBPrescaler::Div4 => 4, 269 AHBPrescaler::DIV8 => 8,
270 AHBPrescaler::Div8 => 8, 270 AHBPrescaler::DIV16 => 16,
271 AHBPrescaler::Div16 => 16, 271 AHBPrescaler::DIV64 => 64,
272 AHBPrescaler::Div64 => 64, 272 AHBPrescaler::DIV128 => 128,
273 AHBPrescaler::Div128 => 128, 273 AHBPrescaler::DIV256 => 256,
274 AHBPrescaler::Div256 => 256, 274 AHBPrescaler::DIV512 => 512,
275 AHBPrescaler::Div512 => 512, 275 _ => unreachable!(),
276 }
277 }
278}
279
280impl APBPrescaler {
281 const fn div(self) -> u32 {
282 match self {
283 APBPrescaler::NotDivided => 1,
284 APBPrescaler::Div2 => 2,
285 APBPrescaler::Div4 => 4,
286 APBPrescaler::Div8 => 8,
287 APBPrescaler::Div16 => 16,
288 }
289 } 276 }
290} 277}
291 278
292impl Into<Ppre> for APBPrescaler { 279fn apb_div(apb: APBPrescaler) -> u32 {
293 fn into(self) -> Ppre { 280 match apb {
294 match self { 281 APBPrescaler::DIV1 => 1,
295 APBPrescaler::NotDivided => Ppre::DIV1, 282 APBPrescaler::DIV2 => 2,
296 APBPrescaler::Div2 => Ppre::DIV2, 283 APBPrescaler::DIV4 => 4,
297 APBPrescaler::Div4 => Ppre::DIV4, 284 APBPrescaler::DIV8 => 8,
298 APBPrescaler::Div8 => Ppre::DIV8, 285 APBPrescaler::DIV16 => 16,
299 APBPrescaler::Div16 => Ppre::DIV16, 286 _ => unreachable!(),
300 }
301 }
302}
303
304impl Into<Hpre> for AHBPrescaler {
305 fn into(self) -> Hpre {
306 match self {
307 AHBPrescaler::NotDivided => Hpre::DIV1,
308 AHBPrescaler::Div2 => Hpre::DIV2,
309 AHBPrescaler::Div4 => Hpre::DIV4,
310 AHBPrescaler::Div8 => Hpre::DIV8,
311 AHBPrescaler::Div16 => Hpre::DIV16,
312 AHBPrescaler::Div64 => Hpre::DIV64,
313 AHBPrescaler::Div128 => Hpre::DIV128,
314 AHBPrescaler::Div256 => Hpre::DIV256,
315 AHBPrescaler::Div512 => Hpre::DIV512,
316 }
317 } 287 }
318} 288}
319 289
@@ -365,9 +335,9 @@ impl Default for Config {
365 fn default() -> Config { 335 fn default() -> Config {
366 Config { 336 Config {
367 mux: ClockSrc::HSI16, 337 mux: ClockSrc::HSI16,
368 ahb_pre: AHBPrescaler::NotDivided, 338 ahb_pre: AHBPrescaler::DIV1,
369 apb1_pre: APBPrescaler::NotDivided, 339 apb1_pre: APBPrescaler::DIV1,
370 apb2_pre: APBPrescaler::NotDivided, 340 apb2_pre: APBPrescaler::DIV1,
371 low_power_run: false, 341 low_power_run: false,
372 pll: None, 342 pll: None,
373 clock_48mhz_src: None, 343 clock_48mhz_src: None,
@@ -512,22 +482,22 @@ pub(crate) unsafe fn init(config: Config) {
512 }); 482 });
513 483
514 let ahb_freq: u32 = match config.ahb_pre { 484 let ahb_freq: u32 = match config.ahb_pre {
515 AHBPrescaler::NotDivided => sys_clk, 485 AHBPrescaler::DIV1 => sys_clk,
516 pre => sys_clk / pre.div(), 486 pre => sys_clk / ahb_div(pre),
517 }; 487 };
518 488
519 let (apb1_freq, apb1_tim_freq) = match config.apb1_pre { 489 let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
520 APBPrescaler::NotDivided => (ahb_freq, ahb_freq), 490 APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
521 pre => { 491 pre => {
522 let freq = ahb_freq / pre.div(); 492 let freq = ahb_freq / apb_div(pre);
523 (freq, freq * 2) 493 (freq, freq * 2)
524 } 494 }
525 }; 495 };
526 496
527 let (apb2_freq, apb2_tim_freq) = match config.apb2_pre { 497 let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
528 APBPrescaler::NotDivided => (ahb_freq, ahb_freq), 498 APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
529 pre => { 499 pre => {
530 let freq = ahb_freq / pre.div(); 500 let freq = ahb_freq / apb_div(pre);
531 (freq, freq * 2) 501 (freq, freq * 2)
532 } 502 }
533 }; 503 };
diff --git a/embassy-stm32/src/rcc/h5.rs b/embassy-stm32/src/rcc/h5.rs
index 5741cdf92..ac45605f7 100644
--- a/embassy-stm32/src/rcc/h5.rs
+++ b/embassy-stm32/src/rcc/h5.rs
@@ -91,25 +91,25 @@ pub struct Pll {
91 pub divr: Option<u16>, 91 pub divr: Option<u16>,
92} 92}
93 93
94impl APBPrescaler { 94fn apb_div_tim(apb: &APBPrescaler, clk: Hertz, tim: TimerPrescaler) -> Hertz {
95 fn div_tim(&self, clk: Hertz, tim: TimerPrescaler) -> Hertz { 95 match (tim, apb) {
96 match (tim, self) { 96 // The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a
97 // The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a 97 // division by 1 or 2, else it is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2
98 // division by 1 or 2, else it is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 98 (TimerPrescaler::DefaultX2, APBPrescaler::DIV1) => clk,
99 (TimerPrescaler::DefaultX2, Self::NotDivided) => clk, 99 (TimerPrescaler::DefaultX2, APBPrescaler::DIV2) => clk,
100 (TimerPrescaler::DefaultX2, Self::Div2) => clk, 100 (TimerPrescaler::DefaultX2, APBPrescaler::DIV4) => clk / 2u32,
101 (TimerPrescaler::DefaultX2, Self::Div4) => clk / 2u32, 101 (TimerPrescaler::DefaultX2, APBPrescaler::DIV8) => clk / 4u32,
102 (TimerPrescaler::DefaultX2, Self::Div8) => clk / 4u32, 102 (TimerPrescaler::DefaultX2, APBPrescaler::DIV16) => clk / 8u32,
103 (TimerPrescaler::DefaultX2, Self::Div16) => clk / 8u32, 103 // The timers kernel clock is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 if PPRE1 or PPRE2
104 // The timers kernel clock is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 if PPRE1 or PPRE2 104 // corresponds to a division by 1, 2 or 4, else it is equal to 4 x Frcc_pclk1 or 4 x Frcc_pclk2
105 // corresponds to a division by 1, 2 or 4, else it is equal to 4 x Frcc_pclk1 or 4 x Frcc_pclk2 105 // this makes NO SENSE and is different than in the H7. Mistake in the RM??
106 // this makes NO SENSE and is different than in the H7. Mistake in the RM?? 106 (TimerPrescaler::DefaultX4, APBPrescaler::DIV1) => clk * 2u32,
107 (TimerPrescaler::DefaultX4, Self::NotDivided) => clk * 2u32, 107 (TimerPrescaler::DefaultX4, APBPrescaler::DIV2) => clk,
108 (TimerPrescaler::DefaultX4, Self::Div2) => clk, 108 (TimerPrescaler::DefaultX4, APBPrescaler::DIV4) => clk / 2u32,
109 (TimerPrescaler::DefaultX4, Self::Div4) => clk / 2u32, 109 (TimerPrescaler::DefaultX4, APBPrescaler::DIV8) => clk / 2u32,
110 (TimerPrescaler::DefaultX4, Self::Div8) => clk / 2u32, 110 (TimerPrescaler::DefaultX4, APBPrescaler::DIV16) => clk / 4u32,
111 (TimerPrescaler::DefaultX4, Self::Div16) => clk / 4u32, 111
112 } 112 _ => unreachable!(),
113 } 113 }
114} 114}
115 115
@@ -165,10 +165,10 @@ impl Default for Config {
165 #[cfg(rcc_h5)] 165 #[cfg(rcc_h5)]
166 pll3: None, 166 pll3: None,
167 167
168 ahb_pre: AHBPrescaler::NotDivided, 168 ahb_pre: AHBPrescaler::DIV1,
169 apb1_pre: APBPrescaler::NotDivided, 169 apb1_pre: APBPrescaler::DIV1,
170 apb2_pre: APBPrescaler::NotDivided, 170 apb2_pre: APBPrescaler::DIV1,
171 apb3_pre: APBPrescaler::NotDivided, 171 apb3_pre: APBPrescaler::DIV1,
172 timer_prescaler: TimerPrescaler::DefaultX2, 172 timer_prescaler: TimerPrescaler::DefaultX2,
173 173
174 voltage_scale: VoltageScale::Scale3, 174 voltage_scale: VoltageScale::Scale3,
@@ -317,9 +317,9 @@ pub(crate) unsafe fn init(config: Config) {
317 let hclk = sys / config.ahb_pre; 317 let hclk = sys / config.ahb_pre;
318 318
319 let apb1 = hclk / config.apb1_pre; 319 let apb1 = hclk / config.apb1_pre;
320 let apb1_tim = config.apb1_pre.div_tim(hclk, config.timer_prescaler); 320 let apb1_tim = apb_div_tim(&config.apb1_pre, hclk, config.timer_prescaler);
321 let apb2 = hclk / config.apb2_pre; 321 let apb2 = hclk / config.apb2_pre;
322 let apb2_tim = config.apb2_pre.div_tim(hclk, config.timer_prescaler); 322 let apb2_tim = apb_div_tim(&config.apb2_pre, hclk, config.timer_prescaler);
323 let apb3 = hclk / config.apb3_pre; 323 let apb3 = hclk / config.apb3_pre;
324 324
325 flash_setup(hclk, config.voltage_scale); 325 flash_setup(hclk, config.voltage_scale);
diff --git a/embassy-stm32/src/rcc/h7.rs b/embassy-stm32/src/rcc/h7.rs
index a6e694618..23e186943 100644
--- a/embassy-stm32/src/rcc/h7.rs
+++ b/embassy-stm32/src/rcc/h7.rs
@@ -6,7 +6,7 @@ use stm32_metapac::rcc::vals::{Mco1, Mco2};
6 6
7use crate::gpio::sealed::AFType; 7use crate::gpio::sealed::AFType;
8use crate::gpio::Speed; 8use crate::gpio::Speed;
9use crate::pac::rcc::vals::{Adcsel, Ckpersel, Dppre, Hpre, Hsidiv, Pllsrc, Sw, Timpre}; 9use crate::pac::rcc::vals::{Adcsel, Ckpersel, Hpre, Hsidiv, Pllsrc, Ppre, Sw, Timpre};
10use crate::pac::{PWR, RCC, SYSCFG}; 10use crate::pac::{PWR, RCC, SYSCFG};
11use crate::rcc::{set_freqs, Clocks}; 11use crate::rcc::{set_freqs, Clocks};
12use crate::time::Hertz; 12use crate::time::Hertz;
@@ -631,7 +631,7 @@ pub(crate) unsafe fn init(mut config: Config) {
631 // Core Prescaler / AHB Prescaler / APB3 Prescaler 631 // Core Prescaler / AHB Prescaler / APB3 Prescaler
632 RCC.d1cfgr().modify(|w| { 632 RCC.d1cfgr().modify(|w| {
633 w.set_d1cpre(Hpre::from_bits(d1cpre_bits)); 633 w.set_d1cpre(Hpre::from_bits(d1cpre_bits));
634 w.set_d1ppre(Dppre::from_bits(ppre3_bits)); 634 w.set_d1ppre(Ppre::from_bits(ppre3_bits));
635 w.set_hpre(hpre_bits) 635 w.set_hpre(hpre_bits)
636 }); 636 });
637 // Ensure core prescaler value is valid before future lower 637 // Ensure core prescaler value is valid before future lower
@@ -642,12 +642,12 @@ pub(crate) unsafe fn init(mut config: Config) {
642 642
643 // APB1 / APB2 Prescaler 643 // APB1 / APB2 Prescaler
644 RCC.d2cfgr().modify(|w| { 644 RCC.d2cfgr().modify(|w| {
645 w.set_d2ppre1(Dppre::from_bits(ppre1_bits)); 645 w.set_d2ppre1(Ppre::from_bits(ppre1_bits));
646 w.set_d2ppre2(Dppre::from_bits(ppre2_bits)); 646 w.set_d2ppre2(Ppre::from_bits(ppre2_bits));
647 }); 647 });
648 648
649 // APB4 Prescaler 649 // APB4 Prescaler
650 RCC.d3cfgr().modify(|w| w.set_d3ppre(Dppre::from_bits(ppre4_bits))); 650 RCC.d3cfgr().modify(|w| w.set_d3ppre(Ppre::from_bits(ppre4_bits)));
651 651
652 // Peripheral Clock (per_ck) 652 // Peripheral Clock (per_ck)
653 RCC.d1ccipr().modify(|w| w.set_ckpersel(ckpersel)); 653 RCC.d1ccipr().modify(|w| w.set_ckpersel(ckpersel));
diff --git a/embassy-stm32/src/rcc/l0.rs b/embassy-stm32/src/rcc/l0.rs
index 3c8511ffd..2dfd0232c 100644
--- a/embassy-stm32/src/rcc/l0.rs
+++ b/embassy-stm32/src/rcc/l0.rs
@@ -145,9 +145,9 @@ impl Default for Config {
145 fn default() -> Config { 145 fn default() -> Config {
146 Config { 146 Config {
147 mux: ClockSrc::MSI(MSIRange::default()), 147 mux: ClockSrc::MSI(MSIRange::default()),
148 ahb_pre: AHBPrescaler::NotDivided, 148 ahb_pre: AHBPrescaler::DIV1,
149 apb1_pre: APBPrescaler::NotDivided, 149 apb1_pre: APBPrescaler::DIV1,
150 apb2_pre: APBPrescaler::NotDivided, 150 apb2_pre: APBPrescaler::DIV1,
151 #[cfg(crs)] 151 #[cfg(crs)]
152 enable_hsi48: false, 152 enable_hsi48: false,
153 rtc: None, 153 rtc: None,
@@ -247,7 +247,7 @@ pub(crate) unsafe fn init(config: Config) {
247 }); 247 });
248 248
249 let ahb_freq: u32 = match config.ahb_pre { 249 let ahb_freq: u32 = match config.ahb_pre {
250 AHBPrescaler::NotDivided => sys_clk, 250 AHBPrescaler::DIV1 => sys_clk,
251 pre => { 251 pre => {
252 let pre: Hpre = pre.into(); 252 let pre: Hpre = pre.into();
253 let pre = 1 << (pre.to_bits() as u32 - 7); 253 let pre = 1 << (pre.to_bits() as u32 - 7);
@@ -256,7 +256,7 @@ pub(crate) unsafe fn init(config: Config) {
256 }; 256 };
257 257
258 let (apb1_freq, apb1_tim_freq) = match config.apb1_pre { 258 let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
259 APBPrescaler::NotDivided => (ahb_freq, ahb_freq), 259 APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
260 pre => { 260 pre => {
261 let pre: Ppre = pre.into(); 261 let pre: Ppre = pre.into();
262 let pre: u8 = 1 << (pre.to_bits() - 3); 262 let pre: u8 = 1 << (pre.to_bits() - 3);
@@ -266,7 +266,7 @@ pub(crate) unsafe fn init(config: Config) {
266 }; 266 };
267 267
268 let (apb2_freq, apb2_tim_freq) = match config.apb2_pre { 268 let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
269 APBPrescaler::NotDivided => (ahb_freq, ahb_freq), 269 APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
270 pre => { 270 pre => {
271 let pre: Ppre = pre.into(); 271 let pre: Ppre = pre.into();
272 let pre: u8 = 1 << (pre.to_bits() - 3); 272 let pre: u8 = 1 << (pre.to_bits() - 3);
diff --git a/embassy-stm32/src/rcc/l1.rs b/embassy-stm32/src/rcc/l1.rs
index ed949ea6f..90524fb37 100644
--- a/embassy-stm32/src/rcc/l1.rs
+++ b/embassy-stm32/src/rcc/l1.rs
@@ -138,9 +138,9 @@ impl Default for Config {
138 fn default() -> Config { 138 fn default() -> Config {
139 Config { 139 Config {
140 mux: ClockSrc::MSI(MSIRange::default()), 140 mux: ClockSrc::MSI(MSIRange::default()),
141 ahb_pre: AHBPrescaler::NotDivided, 141 ahb_pre: AHBPrescaler::DIV1,
142 apb1_pre: APBPrescaler::NotDivided, 142 apb1_pre: APBPrescaler::DIV1,
143 apb2_pre: APBPrescaler::NotDivided, 143 apb2_pre: APBPrescaler::DIV1,
144 } 144 }
145 } 145 }
146} 146}
@@ -240,7 +240,7 @@ pub(crate) unsafe fn init(config: Config) {
240 }); 240 });
241 241
242 let ahb_freq: u32 = match config.ahb_pre { 242 let ahb_freq: u32 = match config.ahb_pre {
243 AHBPrescaler::NotDivided => sys_clk, 243 AHBPrescaler::DIV1 => sys_clk,
244 pre => { 244 pre => {
245 let pre: Hpre = pre.into(); 245 let pre: Hpre = pre.into();
246 let pre = 1 << (pre.to_bits() as u32 - 7); 246 let pre = 1 << (pre.to_bits() as u32 - 7);
@@ -249,7 +249,7 @@ pub(crate) unsafe fn init(config: Config) {
249 }; 249 };
250 250
251 let (apb1_freq, apb1_tim_freq) = match config.apb1_pre { 251 let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
252 APBPrescaler::NotDivided => (ahb_freq, ahb_freq), 252 APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
253 pre => { 253 pre => {
254 let pre: Ppre = pre.into(); 254 let pre: Ppre = pre.into();
255 let pre: u8 = 1 << (pre.to_bits() - 3); 255 let pre: u8 = 1 << (pre.to_bits() - 3);
@@ -259,7 +259,7 @@ pub(crate) unsafe fn init(config: Config) {
259 }; 259 };
260 260
261 let (apb2_freq, apb2_tim_freq) = match config.apb2_pre { 261 let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
262 APBPrescaler::NotDivided => (ahb_freq, ahb_freq), 262 APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
263 pre => { 263 pre => {
264 let pre: Ppre = pre.into(); 264 let pre: Ppre = pre.into();
265 let pre: u8 = 1 << (pre.to_bits() - 3); 265 let pre: u8 = 1 << (pre.to_bits() - 3);
diff --git a/embassy-stm32/src/rcc/l4.rs b/embassy-stm32/src/rcc/l4.rs
index 41dbff01e..447a57b2c 100644
--- a/embassy-stm32/src/rcc/l4.rs
+++ b/embassy-stm32/src/rcc/l4.rs
@@ -248,9 +248,9 @@ impl Default for Config {
248 fn default() -> Config { 248 fn default() -> Config {
249 Config { 249 Config {
250 mux: ClockSrc::MSI(MSIRange::Range6), 250 mux: ClockSrc::MSI(MSIRange::Range6),
251 ahb_pre: AHBPrescaler::NotDivided, 251 ahb_pre: AHBPrescaler::DIV1,
252 apb1_pre: APBPrescaler::NotDivided, 252 apb1_pre: APBPrescaler::DIV1,
253 apb2_pre: APBPrescaler::NotDivided, 253 apb2_pre: APBPrescaler::DIV1,
254 pllsai1: None, 254 pllsai1: None,
255 #[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))] 255 #[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))]
256 hsi48: false, 256 hsi48: false,
@@ -576,7 +576,7 @@ pub(crate) unsafe fn init(config: Config) {
576 }); 576 });
577 577
578 let ahb_freq: u32 = match config.ahb_pre { 578 let ahb_freq: u32 = match config.ahb_pre {
579 AHBPrescaler::NotDivided => sys_clk, 579 AHBPrescaler::DIV1 => sys_clk,
580 pre => { 580 pre => {
581 let pre: Hpre = pre.into(); 581 let pre: Hpre = pre.into();
582 let pre = 1 << (pre.to_bits() as u32 - 7); 582 let pre = 1 << (pre.to_bits() as u32 - 7);
@@ -585,7 +585,7 @@ pub(crate) unsafe fn init(config: Config) {
585 }; 585 };
586 586
587 let (apb1_freq, apb1_tim_freq) = match config.apb1_pre { 587 let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
588 APBPrescaler::NotDivided => (ahb_freq, ahb_freq), 588 APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
589 pre => { 589 pre => {
590 let pre: Ppre = pre.into(); 590 let pre: Ppre = pre.into();
591 let pre: u8 = 1 << (pre.to_bits() - 3); 591 let pre: u8 = 1 << (pre.to_bits() - 3);
@@ -595,7 +595,7 @@ pub(crate) unsafe fn init(config: Config) {
595 }; 595 };
596 596
597 let (apb2_freq, apb2_tim_freq) = match config.apb2_pre { 597 let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
598 APBPrescaler::NotDivided => (ahb_freq, ahb_freq), 598 APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
599 pre => { 599 pre => {
600 let pre: Ppre = pre.into(); 600 let pre: Ppre = pre.into();
601 let pre: u8 = 1 << (pre.to_bits() - 3); 601 let pre: u8 = 1 << (pre.to_bits() - 3);
diff --git a/embassy-stm32/src/rcc/l5.rs b/embassy-stm32/src/rcc/l5.rs
index 9e4e0fc75..553b1619e 100644
--- a/embassy-stm32/src/rcc/l5.rs
+++ b/embassy-stm32/src/rcc/l5.rs
@@ -238,9 +238,9 @@ impl Default for Config {
238 fn default() -> Config { 238 fn default() -> Config {
239 Config { 239 Config {
240 mux: ClockSrc::MSI(MSIRange::Range6), 240 mux: ClockSrc::MSI(MSIRange::Range6),
241 ahb_pre: AHBPrescaler::NotDivided, 241 ahb_pre: AHBPrescaler::DIV1,
242 apb1_pre: APBPrescaler::NotDivided, 242 apb1_pre: APBPrescaler::DIV1,
243 apb2_pre: APBPrescaler::NotDivided, 243 apb2_pre: APBPrescaler::DIV1,
244 pllsai1: None, 244 pllsai1: None,
245 hsi48: false, 245 hsi48: false,
246 } 246 }
@@ -407,7 +407,7 @@ pub(crate) unsafe fn init(config: Config) {
407 }); 407 });
408 408
409 let ahb_freq: u32 = match config.ahb_pre { 409 let ahb_freq: u32 = match config.ahb_pre {
410 AHBPrescaler::NotDivided => sys_clk, 410 AHBPrescaler::DIV1 => sys_clk,
411 pre => { 411 pre => {
412 let pre: Hpre = pre.into(); 412 let pre: Hpre = pre.into();
413 let pre = 1 << (pre.to_bits() as u32 - 7); 413 let pre = 1 << (pre.to_bits() as u32 - 7);
@@ -416,7 +416,7 @@ pub(crate) unsafe fn init(config: Config) {
416 }; 416 };
417 417
418 let (apb1_freq, apb1_tim_freq) = match config.apb1_pre { 418 let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
419 APBPrescaler::NotDivided => (ahb_freq, ahb_freq), 419 APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
420 pre => { 420 pre => {
421 let pre: Ppre = pre.into(); 421 let pre: Ppre = pre.into();
422 let pre: u8 = 1 << (pre.to_bits() - 3); 422 let pre: u8 = 1 << (pre.to_bits() - 3);
@@ -426,7 +426,7 @@ pub(crate) unsafe fn init(config: Config) {
426 }; 426 };
427 427
428 let (apb2_freq, apb2_tim_freq) = match config.apb2_pre { 428 let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
429 APBPrescaler::NotDivided => (ahb_freq, ahb_freq), 429 APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
430 pre => { 430 pre => {
431 let pre: Ppre = pre.into(); 431 let pre: Ppre = pre.into();
432 let pre: u8 = 1 << (pre.to_bits() - 3); 432 let pre: u8 = 1 << (pre.to_bits() - 3);
diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs
index 6540b1f5c..ff43c5eb7 100644
--- a/embassy-stm32/src/rcc/u5.rs
+++ b/embassy-stm32/src/rcc/u5.rs
@@ -119,46 +119,6 @@ impl Into<Pllm> for PllM {
119 } 119 }
120} 120}
121 121
122impl Into<u8> for AHBPrescaler {
123 fn into(self) -> u8 {
124 match self {
125 AHBPrescaler::NotDivided => 1,
126 AHBPrescaler::Div2 => 0x08,
127 AHBPrescaler::Div4 => 0x09,
128 AHBPrescaler::Div8 => 0x0a,
129 AHBPrescaler::Div16 => 0x0b,
130 AHBPrescaler::Div64 => 0x0c,
131 AHBPrescaler::Div128 => 0x0d,
132 AHBPrescaler::Div256 => 0x0e,
133 AHBPrescaler::Div512 => 0x0f,
134 }
135 }
136}
137
138impl Default for AHBPrescaler {
139 fn default() -> Self {
140 AHBPrescaler::NotDivided
141 }
142}
143
144impl Default for APBPrescaler {
145 fn default() -> Self {
146 APBPrescaler::NotDivided
147 }
148}
149
150impl Into<u8> for APBPrescaler {
151 fn into(self) -> u8 {
152 match self {
153 APBPrescaler::NotDivided => 1,
154 APBPrescaler::Div2 => 0x04,
155 APBPrescaler::Div4 => 0x05,
156 APBPrescaler::Div8 => 0x06,
157 APBPrescaler::Div16 => 0x07,
158 }
159 }
160}
161
162impl Into<Sw> for ClockSrc { 122impl Into<Sw> for ClockSrc {
163 fn into(self) -> Sw { 123 fn into(self) -> Sw {
164 match self { 124 match self {
@@ -239,10 +199,10 @@ impl Default for Config {
239 fn default() -> Self { 199 fn default() -> Self {
240 Self { 200 Self {
241 mux: ClockSrc::MSI(MSIRange::default()), 201 mux: ClockSrc::MSI(MSIRange::default()),
242 ahb_pre: Default::default(), 202 ahb_pre: AHBPrescaler::DIV1,
243 apb1_pre: Default::default(), 203 apb1_pre: APBPrescaler::DIV1,
244 apb2_pre: Default::default(), 204 apb2_pre: APBPrescaler::DIV1,
245 apb3_pre: Default::default(), 205 apb3_pre: APBPrescaler::DIV1,
246 hsi48: false, 206 hsi48: false,
247 } 207 }
248 } 208 }
@@ -395,7 +355,7 @@ pub(crate) unsafe fn init(config: Config) {
395 }); 355 });
396 356
397 let ahb_freq: u32 = match config.ahb_pre { 357 let ahb_freq: u32 = match config.ahb_pre {
398 AHBPrescaler::NotDivided => sys_clk, 358 AHBPrescaler::DIV1 => sys_clk,
399 pre => { 359 pre => {
400 let pre: u8 = pre.into(); 360 let pre: u8 = pre.into();
401 let pre = 1 << (pre as u32 - 7); 361 let pre = 1 << (pre as u32 - 7);
@@ -404,7 +364,7 @@ pub(crate) unsafe fn init(config: Config) {
404 }; 364 };
405 365
406 let (apb1_freq, apb1_tim_freq) = match config.apb1_pre { 366 let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
407 APBPrescaler::NotDivided => (ahb_freq, ahb_freq), 367 APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
408 pre => { 368 pre => {
409 let pre: u8 = pre.into(); 369 let pre: u8 = pre.into();
410 let pre: u8 = 1 << (pre - 3); 370 let pre: u8 = 1 << (pre - 3);
@@ -414,7 +374,7 @@ pub(crate) unsafe fn init(config: Config) {
414 }; 374 };
415 375
416 let (apb2_freq, apb2_tim_freq) = match config.apb2_pre { 376 let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
417 APBPrescaler::NotDivided => (ahb_freq, ahb_freq), 377 APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
418 pre => { 378 pre => {
419 let pre: u8 = pre.into(); 379 let pre: u8 = pre.into();
420 let pre: u8 = 1 << (pre - 3); 380 let pre: u8 = 1 << (pre - 3);
@@ -424,7 +384,7 @@ pub(crate) unsafe fn init(config: Config) {
424 }; 384 };
425 385
426 let (apb3_freq, _apb3_tim_freq) = match config.apb3_pre { 386 let (apb3_freq, _apb3_tim_freq) = match config.apb3_pre {
427 APBPrescaler::NotDivided => (ahb_freq, ahb_freq), 387 APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
428 pre => { 388 pre => {
429 let pre: u8 = pre.into(); 389 let pre: u8 = pre.into();
430 let pre: u8 = 1 << (pre - 3); 390 let pre: u8 = 1 << (pre - 3);
diff --git a/embassy-stm32/src/rcc/wb.rs b/embassy-stm32/src/rcc/wb.rs
index f003f6d7d..3f4c37429 100644
--- a/embassy-stm32/src/rcc/wb.rs
+++ b/embassy-stm32/src/rcc/wb.rs
@@ -145,11 +145,11 @@ pub const WPAN_DEFAULT: Config = Config {
145 }), 145 }),
146 pllsai: None, 146 pllsai: None,
147 147
148 ahb1_pre: AHBPrescaler::NotDivided, 148 ahb1_pre: AHBPrescaler::DIV1,
149 ahb2_pre: AHBPrescaler::Div2, 149 ahb2_pre: AHBPrescaler::DIV2,
150 ahb3_pre: AHBPrescaler::NotDivided, 150 ahb3_pre: AHBPrescaler::DIV1,
151 apb1_pre: APBPrescaler::NotDivided, 151 apb1_pre: APBPrescaler::DIV1,
152 apb2_pre: APBPrescaler::NotDivided, 152 apb2_pre: APBPrescaler::DIV1,
153}; 153};
154 154
155impl Default for Config { 155impl Default for Config {
@@ -165,11 +165,11 @@ impl Default for Config {
165 pllsai: None, 165 pllsai: None,
166 rtc: None, 166 rtc: None,
167 167
168 ahb1_pre: AHBPrescaler::NotDivided, 168 ahb1_pre: AHBPrescaler::DIV1,
169 ahb2_pre: AHBPrescaler::NotDivided, 169 ahb2_pre: AHBPrescaler::DIV1,
170 ahb3_pre: AHBPrescaler::NotDivided, 170 ahb3_pre: AHBPrescaler::DIV1,
171 apb1_pre: APBPrescaler::NotDivided, 171 apb1_pre: APBPrescaler::DIV1,
172 apb2_pre: APBPrescaler::NotDivided, 172 apb2_pre: APBPrescaler::DIV1,
173 } 173 }
174 } 174 }
175} 175}
@@ -209,7 +209,7 @@ pub(crate) fn compute_clocks(config: &Config) -> Clocks {
209 }; 209 };
210 210
211 let ahb1_clk = match config.ahb1_pre { 211 let ahb1_clk = match config.ahb1_pre {
212 AHBPrescaler::NotDivided => sys_clk, 212 AHBPrescaler::DIV1 => sys_clk,
213 pre => { 213 pre => {
214 let pre: u8 = pre.into(); 214 let pre: u8 = pre.into();
215 let pre = 1u32 << (pre as u32 - 7); 215 let pre = 1u32 << (pre as u32 - 7);
@@ -218,7 +218,7 @@ pub(crate) fn compute_clocks(config: &Config) -> Clocks {
218 }; 218 };
219 219
220 let ahb2_clk = match config.ahb2_pre { 220 let ahb2_clk = match config.ahb2_pre {
221 AHBPrescaler::NotDivided => sys_clk, 221 AHBPrescaler::DIV1 => sys_clk,
222 pre => { 222 pre => {
223 let pre: u8 = pre.into(); 223 let pre: u8 = pre.into();
224 let pre = 1u32 << (pre as u32 - 7); 224 let pre = 1u32 << (pre as u32 - 7);
@@ -227,7 +227,7 @@ pub(crate) fn compute_clocks(config: &Config) -> Clocks {
227 }; 227 };
228 228
229 let ahb3_clk = match config.ahb3_pre { 229 let ahb3_clk = match config.ahb3_pre {
230 AHBPrescaler::NotDivided => sys_clk, 230 AHBPrescaler::DIV1 => sys_clk,
231 pre => { 231 pre => {
232 let pre: u8 = pre.into(); 232 let pre: u8 = pre.into();
233 let pre = 1u32 << (pre as u32 - 7); 233 let pre = 1u32 << (pre as u32 - 7);
@@ -236,7 +236,7 @@ pub(crate) fn compute_clocks(config: &Config) -> Clocks {
236 }; 236 };
237 237
238 let (apb1_clk, apb1_tim_clk) = match config.apb1_pre { 238 let (apb1_clk, apb1_tim_clk) = match config.apb1_pre {
239 APBPrescaler::NotDivided => (ahb1_clk, ahb1_clk), 239 APBPrescaler::DIV1 => (ahb1_clk, ahb1_clk),
240 pre => { 240 pre => {
241 let pre: u8 = pre.into(); 241 let pre: u8 = pre.into();
242 let pre: u8 = 1 << (pre - 3); 242 let pre: u8 = 1 << (pre - 3);
@@ -246,7 +246,7 @@ pub(crate) fn compute_clocks(config: &Config) -> Clocks {
246 }; 246 };
247 247
248 let (apb2_clk, apb2_tim_clk) = match config.apb2_pre { 248 let (apb2_clk, apb2_tim_clk) = match config.apb2_pre {
249 APBPrescaler::NotDivided => (ahb1_clk, ahb1_clk), 249 APBPrescaler::DIV1 => (ahb1_clk, ahb1_clk),
250 pre => { 250 pre => {
251 let pre: u8 = pre.into(); 251 let pre: u8 = pre.into();
252 let pre: u8 = 1 << (pre - 3); 252 let pre: u8 = 1 << (pre - 3);
diff --git a/embassy-stm32/src/rcc/wl.rs b/embassy-stm32/src/rcc/wl.rs
index 6035f50b0..07856a28c 100644
--- a/embassy-stm32/src/rcc/wl.rs
+++ b/embassy-stm32/src/rcc/wl.rs
@@ -146,10 +146,10 @@ impl Default for Config {
146 fn default() -> Config { 146 fn default() -> Config {
147 Config { 147 Config {
148 mux: ClockSrc::MSI(MSIRange::default()), 148 mux: ClockSrc::MSI(MSIRange::default()),
149 ahb_pre: AHBPrescaler::NotDivided, 149 ahb_pre: AHBPrescaler::DIV1,
150 shd_ahb_pre: AHBPrescaler::NotDivided, 150 shd_ahb_pre: AHBPrescaler::DIV1,
151 apb1_pre: APBPrescaler::NotDivided, 151 apb1_pre: APBPrescaler::DIV1,
152 apb2_pre: APBPrescaler::NotDivided, 152 apb2_pre: APBPrescaler::DIV1,
153 rtc_mux: RtcClockSource::LSI, 153 rtc_mux: RtcClockSource::LSI,
154 adc_clock_source: AdcClockSource::default(), 154 adc_clock_source: AdcClockSource::default(),
155 } 155 }
@@ -172,7 +172,7 @@ pub(crate) unsafe fn init(config: Config) {
172 }; 172 };
173 173
174 let ahb_freq: u32 = match config.ahb_pre { 174 let ahb_freq: u32 = match config.ahb_pre {
175 AHBPrescaler::NotDivided => sys_clk, 175 AHBPrescaler::DIV1 => sys_clk,
176 pre => { 176 pre => {
177 let pre: u8 = pre.into(); 177 let pre: u8 = pre.into();
178 let pre = 1 << (pre as u32 - 7); 178 let pre = 1 << (pre as u32 - 7);
@@ -181,7 +181,7 @@ pub(crate) unsafe fn init(config: Config) {
181 }; 181 };
182 182
183 let shd_ahb_freq: u32 = match config.shd_ahb_pre { 183 let shd_ahb_freq: u32 = match config.shd_ahb_pre {
184 AHBPrescaler::NotDivided => sys_clk, 184 AHBPrescaler::DIV1 => sys_clk,
185 pre => { 185 pre => {
186 let pre: u8 = pre.into(); 186 let pre: u8 = pre.into();
187 let pre = 1 << (pre as u32 - 7); 187 let pre = 1 << (pre as u32 - 7);
@@ -190,7 +190,7 @@ pub(crate) unsafe fn init(config: Config) {
190 }; 190 };
191 191
192 let (apb1_freq, apb1_tim_freq) = match config.apb1_pre { 192 let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
193 APBPrescaler::NotDivided => (ahb_freq, ahb_freq), 193 APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
194 pre => { 194 pre => {
195 let pre: u8 = pre.into(); 195 let pre: u8 = pre.into();
196 let pre: u8 = 1 << (pre - 3); 196 let pre: u8 = 1 << (pre - 3);
@@ -200,7 +200,7 @@ pub(crate) unsafe fn init(config: Config) {
200 }; 200 };
201 201
202 let (apb2_freq, apb2_tim_freq) = match config.apb2_pre { 202 let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
203 APBPrescaler::NotDivided => (ahb_freq, ahb_freq), 203 APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
204 pre => { 204 pre => {
205 let pre: u8 = pre.into(); 205 let pre: u8 = pre.into();
206 let pre: u8 = 1 << (pre - 3); 206 let pre: u8 = 1 << (pre - 3);
@@ -267,7 +267,7 @@ pub(crate) unsafe fn init(config: Config) {
267 } 267 }
268 268
269 RCC.extcfgr().modify(|w| { 269 RCC.extcfgr().modify(|w| {
270 if config.shd_ahb_pre == AHBPrescaler::NotDivided { 270 if config.shd_ahb_pre == AHBPrescaler::DIV1 {
271 w.set_shdhpre(0); 271 w.set_shdhpre(0);
272 } else { 272 } else {
273 w.set_shdhpre(config.shd_ahb_pre.into()); 273 w.set_shdhpre(config.shd_ahb_pre.into());
@@ -276,11 +276,7 @@ pub(crate) unsafe fn init(config: Config) {
276 276
277 RCC.cfgr().modify(|w| { 277 RCC.cfgr().modify(|w| {
278 w.set_sw(sw.into()); 278 w.set_sw(sw.into());
279 if config.ahb_pre == AHBPrescaler::NotDivided { 279 w.set_hpre(config.ahb_pre);
280 w.set_hpre(0);
281 } else {
282 w.set_hpre(config.ahb_pre.into());
283 }
284 w.set_ppre1(config.apb1_pre.into()); 280 w.set_ppre1(config.apb1_pre.into());
285 w.set_ppre2(config.apb2_pre.into()); 281 w.set_ppre2(config.apb2_pre.into());
286 }); 282 });
diff --git a/examples/stm32f2/src/bin/pll.rs b/examples/stm32f2/src/bin/pll.rs
index 17f09538c..894937614 100644
--- a/examples/stm32f2/src/bin/pll.rs
+++ b/examples/stm32f2/src/bin/pll.rs
@@ -39,9 +39,9 @@ async fn main(_spawner: Spawner) {
39 // System clock comes from PLL (= the 120 MHz main PLL output) 39 // System clock comes from PLL (= the 120 MHz main PLL output)
40 config.rcc.mux = ClockSrc::PLL; 40 config.rcc.mux = ClockSrc::PLL;
41 // 120 MHz / 4 = 30 MHz APB1 frequency 41 // 120 MHz / 4 = 30 MHz APB1 frequency
42 config.rcc.apb1_pre = APBPrescaler::Div4; 42 config.rcc.apb1_pre = APBPrescaler::DIV4;
43 // 120 MHz / 2 = 60 MHz APB2 frequency 43 // 120 MHz / 2 = 60 MHz APB2 frequency
44 config.rcc.apb2_pre = APBPrescaler::Div2; 44 config.rcc.apb2_pre = APBPrescaler::DIV2;
45 45
46 let _p = embassy_stm32::init(config); 46 let _p = embassy_stm32::init(config);
47 47
diff --git a/examples/stm32h5/src/bin/eth.rs b/examples/stm32h5/src/bin/eth.rs
index c32e0fdb5..fdba6cd5c 100644
--- a/examples/stm32h5/src/bin/eth.rs
+++ b/examples/stm32h5/src/bin/eth.rs
@@ -48,10 +48,10 @@ async fn main(spawner: Spawner) -> ! {
48 divq: Some(2), 48 divq: Some(2),
49 divr: None, 49 divr: None,
50 }); 50 });
51 config.rcc.ahb_pre = AHBPrescaler::NotDivided; 51 config.rcc.ahb_pre = AHBPrescaler::DIV1;
52 config.rcc.apb1_pre = APBPrescaler::NotDivided; 52 config.rcc.apb1_pre = APBPrescaler::DIV1;
53 config.rcc.apb2_pre = APBPrescaler::NotDivided; 53 config.rcc.apb2_pre = APBPrescaler::DIV1;
54 config.rcc.apb3_pre = APBPrescaler::NotDivided; 54 config.rcc.apb3_pre = APBPrescaler::DIV1;
55 config.rcc.sys = Sysclk::Pll1P; 55 config.rcc.sys = Sysclk::Pll1P;
56 config.rcc.voltage_scale = VoltageScale::Scale0; 56 config.rcc.voltage_scale = VoltageScale::Scale0;
57 let p = embassy_stm32::init(config); 57 let p = embassy_stm32::init(config);
diff --git a/examples/stm32h5/src/bin/usb_serial.rs b/examples/stm32h5/src/bin/usb_serial.rs
index 336eed644..cbe540a06 100644
--- a/examples/stm32h5/src/bin/usb_serial.rs
+++ b/examples/stm32h5/src/bin/usb_serial.rs
@@ -35,10 +35,10 @@ async fn main(_spawner: Spawner) {
35 divq: None, 35 divq: None,
36 divr: None, 36 divr: None,
37 }); 37 });
38 config.rcc.ahb_pre = AHBPrescaler::Div2; 38 config.rcc.ahb_pre = AHBPrescaler::DIV2;
39 config.rcc.apb1_pre = APBPrescaler::Div4; 39 config.rcc.apb1_pre = APBPrescaler::DIV4;
40 config.rcc.apb2_pre = APBPrescaler::Div2; 40 config.rcc.apb2_pre = APBPrescaler::DIV2;
41 config.rcc.apb3_pre = APBPrescaler::Div4; 41 config.rcc.apb3_pre = APBPrescaler::DIV4;
42 config.rcc.sys = Sysclk::Pll1P; 42 config.rcc.sys = Sysclk::Pll1P;
43 config.rcc.voltage_scale = VoltageScale::Scale0; 43 config.rcc.voltage_scale = VoltageScale::Scale0;
44 let p = embassy_stm32::init(config); 44 let p = embassy_stm32::init(config);
generated by cgit (git 2.34.1) at 2026-04-05 23:46:43 +0000