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-rw-r--r--embassy-cortex-m/src/interrupt.rs160
-rw-r--r--embassy-lora/src/iv.rs6
-rw-r--r--embassy-macros/src/lib.rs11
-rw-r--r--embassy-macros/src/macros/cortex_m_interrupt_declare.rs21
-rw-r--r--embassy-macros/src/macros/cortex_m_interrupt_take.rs57
-rw-r--r--embassy-macros/src/macros/mod.rs1
-rw-r--r--embassy-nrf/src/buffered_uarte.rs8
-rw-r--r--embassy-nrf/src/gpiote.rs56
-rw-r--r--embassy-nrf/src/i2s.rs5
-rw-r--r--embassy-nrf/src/lib.rs2
-rw-r--r--embassy-nrf/src/pdm.rs6
-rw-r--r--embassy-nrf/src/qdec.rs7
-rw-r--r--embassy-nrf/src/qspi.rs6
-rw-r--r--embassy-nrf/src/rng.rs7
-rw-r--r--embassy-nrf/src/saadc.rs6
-rw-r--r--embassy-nrf/src/spim.rs6
-rw-r--r--embassy-nrf/src/spis.rs6
-rw-r--r--embassy-nrf/src/temp.rs7
-rw-r--r--embassy-nrf/src/time_driver.rs7
-rw-r--r--embassy-nrf/src/twim.rs6
-rw-r--r--embassy-nrf/src/twis.rs6
-rw-r--r--embassy-nrf/src/uarte.rs14
-rw-r--r--embassy-nrf/src/usb/mod.rs6
-rw-r--r--embassy-nrf/src/usb/vbus_detect.rs6
-rw-r--r--embassy-rp/src/adc.rs6
-rw-r--r--embassy-rp/src/dma.rs9
-rw-r--r--embassy-rp/src/gpio.rs9
-rw-r--r--embassy-rp/src/i2c.rs14
-rw-r--r--embassy-rp/src/interrupt.rs2
-rw-r--r--embassy-rp/src/multicore.rs5
-rw-r--r--embassy-rp/src/pio.rs16
-rw-r--r--embassy-rp/src/timer.rs10
-rw-r--r--embassy-rp/src/uart/buffered.rs14
-rw-r--r--embassy-rp/src/uart/mod.rs14
-rw-r--r--embassy-rp/src/usb.rs8
-rw-r--r--embassy-stm32/src/dcmi.rs6
-rw-r--r--embassy-stm32/src/dma/bdma.rs7
-rw-r--r--embassy-stm32/src/dma/dma.rs7
-rw-r--r--embassy-stm32/src/dma/gpdma.rs7
-rw-r--r--embassy-stm32/src/eth/v1/mod.rs6
-rw-r--r--embassy-stm32/src/eth/v2/mod.rs6
-rw-r--r--embassy-stm32/src/exti.rs4
-rw-r--r--embassy-stm32/src/flash/asynch.rs7
-rw-r--r--embassy-stm32/src/i2c/v2.rs6
-rw-r--r--embassy-stm32/src/lib.rs2
-rw-r--r--embassy-stm32/src/sdmmc/mod.rs8
-rw-r--r--embassy-stm32/src/time_driver.rs7
-rw-r--r--embassy-stm32/src/tl_mbox/mod.rs10
-rw-r--r--embassy-stm32/src/usart/buffered.rs18
-rw-r--r--embassy-stm32/src/usart/mod.rs10
-rw-r--r--embassy-stm32/src/usb/usb.rs6
-rw-r--r--embassy-stm32/src/usb_otg/usb.rs8
-rw-r--r--examples/boot/bootloader/rp/Cargo.toml1
-rw-r--r--examples/std/src/bin/tcp_accept.rs2
54 files changed, 229 insertions, 429 deletions
diff --git a/embassy-cortex-m/src/interrupt.rs b/embassy-cortex-m/src/interrupt.rs
index 3a82726df..0e790eaaf 100644
--- a/embassy-cortex-m/src/interrupt.rs
+++ b/embassy-cortex-m/src/interrupt.rs
@@ -1,10 +1,8 @@
1//! Interrupt handling for cortex-m devices. 1//! Interrupt handling for cortex-m devices.
2use core::{mem, ptr}; 2use core::mem;
3use core::sync::atomic::{compiler_fence, Ordering};
3 4
4use atomic_polyfill::{compiler_fence, AtomicPtr, Ordering};
5use cortex_m::peripheral::NVIC; 5use cortex_m::peripheral::NVIC;
6use embassy_hal_common::Peripheral;
7pub use embassy_macros::cortex_m_interrupt_take as take;
8 6
9/// Do not use. Used for macros and HALs only. Not covered by semver guarantees. 7/// Do not use. Used for macros and HALs only. Not covered by semver guarantees.
10#[doc(hidden)] 8#[doc(hidden)]
@@ -43,22 +41,6 @@ pub trait Handler<I: Interrupt> {
43/// This allows drivers to check bindings at compile-time. 41/// This allows drivers to check bindings at compile-time.
44pub unsafe trait Binding<I: Interrupt, H: Handler<I>> {} 42pub unsafe trait Binding<I: Interrupt, H: Handler<I>> {}
45 43
46/// Implementation detail, do not use outside embassy crates.
47#[doc(hidden)]
48pub struct DynHandler {
49 pub func: AtomicPtr<()>,
50 pub ctx: AtomicPtr<()>,
51}
52
53impl DynHandler {
54 pub const fn new() -> Self {
55 Self {
56 func: AtomicPtr::new(ptr::null_mut()),
57 ctx: AtomicPtr::new(ptr::null_mut()),
58 }
59 }
60}
61
62#[derive(Clone, Copy)] 44#[derive(Clone, Copy)]
63pub(crate) struct NrWrap(pub(crate) u16); 45pub(crate) struct NrWrap(pub(crate) u16);
64unsafe impl cortex_m::interrupt::InterruptNumber for NrWrap { 46unsafe impl cortex_m::interrupt::InterruptNumber for NrWrap {
@@ -69,144 +51,68 @@ unsafe impl cortex_m::interrupt::InterruptNumber for NrWrap {
69 51
70/// Represents an interrupt type that can be configured by embassy to handle 52/// Represents an interrupt type that can be configured by embassy to handle
71/// interrupts. 53/// interrupts.
72pub unsafe trait Interrupt: Peripheral<P = Self> { 54pub unsafe trait Interrupt {
73 /// Return the NVIC interrupt number for this interrupt. 55 /// Return the NVIC interrupt number for this interrupt.
74 fn number(&self) -> u16; 56 fn number() -> u16;
75 /// Steal an instance of this interrupt
76 ///
77 /// # Safety
78 ///
79 /// This may panic if the interrupt has already been stolen and configured.
80 unsafe fn steal() -> Self;
81
82 /// Implementation detail, do not use outside embassy crates.
83 #[doc(hidden)]
84 unsafe fn __handler(&self) -> &'static DynHandler;
85}
86
87/// Represents additional behavior for all interrupts.
88pub trait InterruptExt: Interrupt {
89 /// Configure the interrupt handler for this interrupt.
90 ///
91 /// # Safety
92 ///
93 /// It is the responsibility of the caller to ensure the handler
94 /// points to a valid handler as long as interrupts are enabled.
95 fn set_handler(&self, func: unsafe fn(*mut ()));
96
97 /// Remove the interrupt handler for this interrupt.
98 fn remove_handler(&self);
99
100 /// Set point to a context that is passed to the interrupt handler when
101 /// an interrupt is pending.
102 ///
103 /// # Safety
104 ///
105 /// It is the responsibility of the caller to ensure the context
106 /// points to a valid handler as long as interrupts are enabled.
107 fn set_handler_context(&self, ctx: *mut ());
108
109 /// Enable the interrupt. Once enabled, the interrupt handler may
110 /// be called "any time".
111 fn enable(&self);
112
113 /// Disable the interrupt.
114 fn disable(&self);
115
116 /// Check if interrupt is being handled.
117 #[cfg(not(armv6m))]
118 fn is_active(&self) -> bool;
119
120 /// Check if interrupt is enabled.
121 fn is_enabled(&self) -> bool;
122
123 /// Check if interrupt is pending.
124 fn is_pending(&self) -> bool;
125
126 /// Set interrupt pending.
127 fn pend(&self);
128
129 /// Unset interrupt pending.
130 fn unpend(&self);
131
132 /// Get the priority of the interrupt.
133 fn get_priority(&self) -> Priority;
134
135 /// Set the interrupt priority.
136 fn set_priority(&self, prio: Priority);
137}
138
139impl<T: Interrupt + ?Sized> InterruptExt for T {
140 fn set_handler(&self, func: unsafe fn(*mut ())) {
141 compiler_fence(Ordering::SeqCst);
142 let handler = unsafe { self.__handler() };
143 handler.func.store(func as *mut (), Ordering::Relaxed);
144 compiler_fence(Ordering::SeqCst);
145 }
146
147 fn remove_handler(&self) {
148 compiler_fence(Ordering::SeqCst);
149 let handler = unsafe { self.__handler() };
150 handler.func.store(ptr::null_mut(), Ordering::Relaxed);
151 compiler_fence(Ordering::SeqCst);
152 }
153
154 fn set_handler_context(&self, ctx: *mut ()) {
155 let handler = unsafe { self.__handler() };
156 handler.ctx.store(ctx, Ordering::Relaxed);
157 }
158 57
58 /// Enable the interrupt.
159 #[inline] 59 #[inline]
160 fn enable(&self) { 60 unsafe fn enable() {
161 compiler_fence(Ordering::SeqCst); 61 compiler_fence(Ordering::SeqCst);
162 unsafe { 62 NVIC::unmask(NrWrap(Self::number()))
163 NVIC::unmask(NrWrap(self.number()));
164 }
165 } 63 }
166 64
65 /// Disable the interrupt.
167 #[inline] 66 #[inline]
168 fn disable(&self) { 67 fn disable() {
169 NVIC::mask(NrWrap(self.number())); 68 NVIC::mask(NrWrap(Self::number()));
170 compiler_fence(Ordering::SeqCst); 69 compiler_fence(Ordering::SeqCst);
171 } 70 }
172 71
72 /// Check if interrupt is being handled.
173 #[inline] 73 #[inline]
174 #[cfg(not(armv6m))] 74 #[cfg(not(armv6m))]
175 fn is_active(&self) -> bool { 75 fn is_active() -> bool {
176 NVIC::is_active(NrWrap(self.number())) 76 NVIC::is_active(NrWrap(Self::number()))
177 } 77 }
178 78
79 /// Check if interrupt is enabled.
179 #[inline] 80 #[inline]
180 fn is_enabled(&self) -> bool { 81 fn is_enabled() -> bool {
181 NVIC::is_enabled(NrWrap(self.number())) 82 NVIC::is_enabled(NrWrap(Self::number()))
182 } 83 }
183 84
85 /// Check if interrupt is pending.
184 #[inline] 86 #[inline]
185 fn is_pending(&self) -> bool { 87 fn is_pending() -> bool {
186 NVIC::is_pending(NrWrap(self.number())) 88 NVIC::is_pending(NrWrap(Self::number()))
187 } 89 }
188 90
91 /// Set interrupt pending.
189 #[inline] 92 #[inline]
190 fn pend(&self) { 93 fn pend() {
191 NVIC::pend(NrWrap(self.number())) 94 NVIC::pend(NrWrap(Self::number()))
192 } 95 }
193 96
97 /// Unset interrupt pending.
194 #[inline] 98 #[inline]
195 fn unpend(&self) { 99 fn unpend() {
196 NVIC::unpend(NrWrap(self.number())) 100 NVIC::unpend(NrWrap(Self::number()))
197 } 101 }
198 102
103 /// Get the priority of the interrupt.
199 #[inline] 104 #[inline]
200 fn get_priority(&self) -> Priority { 105 fn get_priority() -> Priority {
201 Priority::from(NVIC::get_priority(NrWrap(self.number()))) 106 Priority::from(NVIC::get_priority(NrWrap(Self::number())))
202 } 107 }
203 108
109 /// Set the interrupt priority.
204 #[inline] 110 #[inline]
205 fn set_priority(&self, prio: Priority) { 111 fn set_priority(prio: Priority) {
206 unsafe { 112 critical_section::with(|_| unsafe {
207 let mut nvic: cortex_m::peripheral::NVIC = mem::transmute(()); 113 let mut nvic: cortex_m::peripheral::NVIC = mem::transmute(());
208 nvic.set_priority(NrWrap(self.number()), prio.into()) 114 nvic.set_priority(NrWrap(Self::number()), prio.into())
209 } 115 })
210 } 116 }
211} 117}
212 118
diff --git a/embassy-lora/src/iv.rs b/embassy-lora/src/iv.rs
index d515bc365..8d521040f 100644
--- a/embassy-lora/src/iv.rs
+++ b/embassy-lora/src/iv.rs
@@ -22,7 +22,7 @@ pub struct InterruptHandler {}
22#[cfg(feature = "stm32wl")] 22#[cfg(feature = "stm32wl")]
23impl interrupt::Handler<interrupt::SUBGHZ_RADIO> for InterruptHandler { 23impl interrupt::Handler<interrupt::SUBGHZ_RADIO> for InterruptHandler {
24 unsafe fn on_interrupt() { 24 unsafe fn on_interrupt() {
25 unsafe { SUBGHZ_RADIO::steal() }.disable(); 25 interrupt::SUBGHZ_RADIO::disable();
26 IRQ_SIGNAL.signal(()); 26 IRQ_SIGNAL.signal(());
27 } 27 }
28} 28}
@@ -49,7 +49,7 @@ where
49 rf_switch_rx: Option<CTRL>, 49 rf_switch_rx: Option<CTRL>,
50 rf_switch_tx: Option<CTRL>, 50 rf_switch_tx: Option<CTRL>,
51 ) -> Result<Self, RadioError> { 51 ) -> Result<Self, RadioError> {
52 unsafe { interrupt::SUBGHZ_RADIO::steal() }.disable(); 52 interrupt::SUBGHZ_RADIO::disable();
53 Ok(Self { 53 Ok(Self {
54 board_type: BoardType::Stm32wlSx1262, // updated when associated with a specific LoRa board 54 board_type: BoardType::Stm32wlSx1262, // updated when associated with a specific LoRa board
55 rf_switch_rx, 55 rf_switch_rx,
@@ -95,7 +95,7 @@ where
95 } 95 }
96 96
97 async fn await_irq(&mut self) -> Result<(), RadioError> { 97 async fn await_irq(&mut self) -> Result<(), RadioError> {
98 unsafe { interrupt::SUBGHZ_RADIO::steal() }.enable(); 98 unsafe { interrupt::SUBGHZ_RADIO::enable() };
99 IRQ_SIGNAL.wait().await; 99 IRQ_SIGNAL.wait().await;
100 Ok(()) 100 Ok(())
101 } 101 }
diff --git a/embassy-macros/src/lib.rs b/embassy-macros/src/lib.rs
index dc5b519ff..d7ca1f69c 100644
--- a/embassy-macros/src/lib.rs
+++ b/embassy-macros/src/lib.rs
@@ -169,14 +169,3 @@ pub fn cortex_m_interrupt_declare(item: TokenStream) -> TokenStream {
169 let name = syn::parse_macro_input!(item as syn::Ident); 169 let name = syn::parse_macro_input!(item as syn::Ident);
170 cortex_m_interrupt_declare::run(name).unwrap_or_else(|x| x).into() 170 cortex_m_interrupt_declare::run(name).unwrap_or_else(|x| x).into()
171} 171}
172
173/// # interrupt_take procedural macro
174///
175/// core::panic! is used as a default way to panic in this macro as there is no sensible way of enabling/disabling defmt for macro generation.
176/// We are aware that this brings bloat in the form of core::fmt, but the bloat is already included with e.g. array indexing panics.
177/// To get rid of this bloat, use the compiler flags `-Zbuild-std=core -Zbuild-std-features=panic_immediate_abort`.
178#[proc_macro]
179pub fn cortex_m_interrupt_take(item: TokenStream) -> TokenStream {
180 let name = syn::parse_macro_input!(item as syn::Ident);
181 cortex_m_interrupt_take::run(name).unwrap_or_else(|x| x).into()
182}
diff --git a/embassy-macros/src/macros/cortex_m_interrupt_declare.rs b/embassy-macros/src/macros/cortex_m_interrupt_declare.rs
index 699883efa..b317482f5 100644
--- a/embassy-macros/src/macros/cortex_m_interrupt_declare.rs
+++ b/embassy-macros/src/macros/cortex_m_interrupt_declare.rs
@@ -3,32 +3,19 @@ use quote::{format_ident, quote};
3 3
4pub fn run(name: syn::Ident) -> Result<TokenStream, TokenStream> { 4pub fn run(name: syn::Ident) -> Result<TokenStream, TokenStream> {
5 let name = format_ident!("{}", name); 5 let name = format_ident!("{}", name);
6 let name_interrupt = format_ident!("{}", name); 6 let doc = format!("{} interrupt.", name);
7 let name_handler = format!("__EMBASSY_{}_HANDLER", name);
8
9 let doc = format!("{} interrupt singleton.", name);
10 7
11 let result = quote! { 8 let result = quote! {
12 #[doc = #doc] 9 #[doc = #doc]
13 #[allow(non_camel_case_types)] 10 #[allow(non_camel_case_types)]
14 pub struct #name_interrupt(()); 11 pub enum #name{}
15 unsafe impl ::embassy_cortex_m::interrupt::Interrupt for #name_interrupt { 12 unsafe impl ::embassy_cortex_m::interrupt::Interrupt for #name {
16 fn number(&self) -> u16 { 13 fn number() -> u16 {
17 use cortex_m::interrupt::InterruptNumber; 14 use cortex_m::interrupt::InterruptNumber;
18 let irq = InterruptEnum::#name; 15 let irq = InterruptEnum::#name;
19 irq.number() as u16 16 irq.number() as u16
20 } 17 }
21 unsafe fn steal() -> Self {
22 Self(())
23 }
24 unsafe fn __handler(&self) -> &'static ::embassy_cortex_m::interrupt::DynHandler {
25 #[export_name = #name_handler]
26 static HANDLER: ::embassy_cortex_m::interrupt::DynHandler = ::embassy_cortex_m::interrupt::DynHandler::new();
27 &HANDLER
28 }
29 } 18 }
30
31 ::embassy_hal_common::impl_peripheral!(#name_interrupt);
32 }; 19 };
33 Ok(result) 20 Ok(result)
34} 21}
diff --git a/embassy-macros/src/macros/cortex_m_interrupt_take.rs b/embassy-macros/src/macros/cortex_m_interrupt_take.rs
deleted file mode 100644
index 4806d1c12..000000000
--- a/embassy-macros/src/macros/cortex_m_interrupt_take.rs
+++ /dev/null
@@ -1,57 +0,0 @@
1use proc_macro2::TokenStream;
2use quote::{format_ident, quote};
3
4pub fn run(name: syn::Ident) -> Result<TokenStream, TokenStream> {
5 let name = format!("{}", name);
6 let name_interrupt = format_ident!("{}", name);
7 let name_handler = format!("__EMBASSY_{}_HANDLER", name);
8
9 #[cfg(feature = "rtos-trace-interrupt")]
10 let (isr_enter, isr_exit) = (
11 quote! {
12 ::embassy_executor::rtos_trace_interrupt! {
13 ::embassy_executor::_export::trace::isr_enter();
14 }
15 },
16 quote! {
17 ::embassy_executor::rtos_trace_interrupt! {
18 ::embassy_executor::_export::trace::isr_exit();
19 }
20 },
21 );
22
23 #[cfg(not(feature = "rtos-trace-interrupt"))]
24 let (isr_enter, isr_exit) = (quote! {}, quote! {});
25
26 let result = quote! {
27 {
28 #[allow(non_snake_case)]
29 #[export_name = #name]
30 pub unsafe extern "C" fn trampoline() {
31 extern "C" {
32 #[link_name = #name_handler]
33 static HANDLER: interrupt::DynHandler;
34 }
35
36 let func = HANDLER.func.load(interrupt::_export::atomic::Ordering::Relaxed);
37 let ctx = HANDLER.ctx.load(interrupt::_export::atomic::Ordering::Relaxed);
38 let func: fn(*mut ()) = ::core::mem::transmute(func);
39 #isr_enter
40
41 func(ctx);
42 #isr_exit
43
44 }
45
46 static TAKEN: interrupt::_export::atomic::AtomicBool = interrupt::_export::atomic::AtomicBool::new(false);
47
48 if TAKEN.compare_exchange(false, true, interrupt::_export::atomic::Ordering::AcqRel, interrupt::_export::atomic::Ordering::Acquire).is_err() {
49 core::panic!("IRQ Already taken");
50 }
51
52 let irq: interrupt::#name_interrupt = unsafe { ::core::mem::transmute(()) };
53 irq
54 }
55 };
56 Ok(result)
57}
diff --git a/embassy-macros/src/macros/mod.rs b/embassy-macros/src/macros/mod.rs
index e547736fc..a5e7a50e6 100644
--- a/embassy-macros/src/macros/mod.rs
+++ b/embassy-macros/src/macros/mod.rs
@@ -1,5 +1,4 @@
1pub mod cortex_m_interrupt; 1pub mod cortex_m_interrupt;
2pub mod cortex_m_interrupt_declare; 2pub mod cortex_m_interrupt_declare;
3pub mod cortex_m_interrupt_take;
4pub mod main; 3pub mod main;
5pub mod task; 4pub mod task;
diff --git a/embassy-nrf/src/buffered_uarte.rs b/embassy-nrf/src/buffered_uarte.rs
index 4d053c023..b4fe2d874 100644
--- a/embassy-nrf/src/buffered_uarte.rs
+++ b/embassy-nrf/src/buffered_uarte.rs
@@ -24,7 +24,7 @@ pub use pac::uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Pari
24 24
25use crate::gpio::sealed::Pin; 25use crate::gpio::sealed::Pin;
26use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits}; 26use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits};
27use crate::interrupt::{self, InterruptExt}; 27use crate::interrupt::{self};
28use crate::ppi::{ 28use crate::ppi::{
29 self, AnyConfigurableChannel, AnyGroup, Channel, ConfigurableChannel, Event, Group, Ppi, PpiGroup, Task, 29 self, AnyConfigurableChannel, AnyGroup, Channel, ConfigurableChannel, Event, Group, Ppi, PpiGroup, Task,
30}; 30};
@@ -362,8 +362,8 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
362 ppi_ch2.disable(); 362 ppi_ch2.disable();
363 ppi_group.add_channel(&ppi_ch2); 363 ppi_group.add_channel(&ppi_ch2);
364 364
365 unsafe { U::Interrupt::steal() }.pend(); 365 U::Interrupt::pend();
366 unsafe { U::Interrupt::steal() }.enable(); 366 unsafe { U::Interrupt::enable() };
367 367
368 Self { 368 Self {
369 _peri: peri, 369 _peri: peri,
@@ -375,7 +375,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
375 } 375 }
376 376
377 fn pend_irq() { 377 fn pend_irq() {
378 unsafe { <U::Interrupt as Interrupt>::steal() }.pend() 378 U::Interrupt::pend()
379 } 379 }
380 380
381 /// Adjust the baud rate to the provided value. 381 /// Adjust the baud rate to the provided value.
diff --git a/embassy-nrf/src/gpiote.rs b/embassy-nrf/src/gpiote.rs
index 66c682b43..2ec5220a7 100644
--- a/embassy-nrf/src/gpiote.rs
+++ b/embassy-nrf/src/gpiote.rs
@@ -9,7 +9,7 @@ use embassy_sync::waitqueue::AtomicWaker;
9 9
10use crate::gpio::sealed::Pin as _; 10use crate::gpio::sealed::Pin as _;
11use crate::gpio::{AnyPin, Flex, Input, Output, Pin as GpioPin}; 11use crate::gpio::{AnyPin, Flex, Input, Output, Pin as GpioPin};
12use crate::interrupt::{Interrupt, InterruptExt}; 12use crate::interrupt::Interrupt;
13use crate::ppi::{Event, Task}; 13use crate::ppi::{Event, Task};
14use crate::{interrupt, pac, peripherals}; 14use crate::{interrupt, pac, peripherals};
15 15
@@ -74,42 +74,38 @@ pub(crate) fn init(irq_prio: crate::interrupt::Priority) {
74 } 74 }
75 75
76 // Enable interrupts 76 // Enable interrupts
77 cfg_if::cfg_if! { 77 #[cfg(any(feature = "nrf5340-app-s", feature = "nrf9160-s"))]
78 if #[cfg(any(feature="nrf5340-app-s", feature="nrf9160-s"))] { 78 type Irq = interrupt::GPIOTE0;
79 let irq = unsafe { interrupt::GPIOTE0::steal() }; 79 #[cfg(any(feature = "nrf5340-app-ns", feature = "nrf9160-ns"))]
80 } else if #[cfg(any(feature="nrf5340-app-ns", feature="nrf9160-ns"))] { 80 type Irq = interrupt::GPIOTE1;
81 let irq = unsafe { interrupt::GPIOTE1::steal() }; 81 #[cfg(any(feature = "_nrf52", feature = "nrf5340-net"))]
82 } else { 82 type Irq = interrupt::GPIOTE;
83 let irq = unsafe { interrupt::GPIOTE::steal() };
84 }
85 }
86 83
87 irq.unpend(); 84 Irq::unpend();
88 irq.set_priority(irq_prio); 85 Irq::set_priority(irq_prio);
89 irq.enable(); 86 unsafe { Irq::enable() };
90 87
91 let g = regs(); 88 let g = regs();
92 g.events_port.write(|w| w); 89 g.events_port.write(|w| w);
93 g.intenset.write(|w| w.port().set()); 90 g.intenset.write(|w| w.port().set());
94} 91}
95 92
96cfg_if::cfg_if! { 93#[cfg(any(feature = "nrf5340-app-s", feature = "nrf9160-s"))]
97 if #[cfg(any(feature="nrf5340-app-s", feature="nrf9160-s"))] { 94#[interrupt]
98 #[interrupt] 95fn GPIOTE0() {
99 fn GPIOTE0() { 96 unsafe { handle_gpiote_interrupt() };
100 unsafe { handle_gpiote_interrupt() }; 97}
101 } 98
102 } else if #[cfg(any(feature="nrf5340-app-ns", feature="nrf9160-ns"))] { 99#[cfg(any(feature = "nrf5340-app-ns", feature = "nrf9160-ns"))]
103 #[interrupt] 100#[interrupt]
104 fn GPIOTE1() { 101fn GPIOTE1() {
105 unsafe { handle_gpiote_interrupt() }; 102 unsafe { handle_gpiote_interrupt() };
106 } 103}
107 } else { 104
108 #[interrupt] 105#[cfg(any(feature = "_nrf52", feature = "nrf5340-net"))]
109 fn GPIOTE() { 106#[interrupt]
110 unsafe { handle_gpiote_interrupt() }; 107fn GPIOTE() {
111 } 108 unsafe { handle_gpiote_interrupt() };
112 }
113} 109}
114 110
115unsafe fn handle_gpiote_interrupt() { 111unsafe fn handle_gpiote_interrupt() {
diff --git a/embassy-nrf/src/i2s.rs b/embassy-nrf/src/i2s.rs
index 8a1188ce4..13db77d3b 100644
--- a/embassy-nrf/src/i2s.rs
+++ b/embassy-nrf/src/i2s.rs
@@ -9,7 +9,6 @@ use core::ops::{Deref, DerefMut};
9use core::sync::atomic::{compiler_fence, Ordering}; 9use core::sync::atomic::{compiler_fence, Ordering};
10use core::task::Poll; 10use core::task::Poll;
11 11
12use embassy_cortex_m::interrupt::InterruptExt;
13use embassy_hal_common::drop::OnDrop; 12use embassy_hal_common::drop::OnDrop;
14use embassy_hal_common::{into_ref, PeripheralRef}; 13use embassy_hal_common::{into_ref, PeripheralRef};
15 14
@@ -564,8 +563,8 @@ impl<'d, T: Instance> I2S<'d, T> {
564 } 563 }
565 564
566 fn setup_interrupt(&self) { 565 fn setup_interrupt(&self) {
567 unsafe { T::Interrupt::steal() }.unpend(); 566 T::Interrupt::unpend();
568 unsafe { T::Interrupt::steal() }.enable(); 567 unsafe { T::Interrupt::enable() };
569 568
570 let device = Device::<T>::new(); 569 let device = Device::<T>::new();
571 device.disable_tx_ptr_interrupt(); 570 device.disable_tx_ptr_interrupt();
diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index d4d7a1cad..6b57c2545 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -96,7 +96,7 @@ mod chip;
96pub mod interrupt { 96pub mod interrupt {
97 //! Interrupt definitions and macros to bind them. 97 //! Interrupt definitions and macros to bind them.
98 pub use cortex_m::interrupt::{CriticalSection, Mutex}; 98 pub use cortex_m::interrupt::{CriticalSection, Mutex};
99 pub use embassy_cortex_m::interrupt::{Binding, Handler, Interrupt, InterruptExt, Priority}; 99 pub use embassy_cortex_m::interrupt::{Binding, Handler, Interrupt, Priority};
100 100
101 pub use crate::chip::irqs::*; 101 pub use crate::chip::irqs::*;
102 102
diff --git a/embassy-nrf/src/pdm.rs b/embassy-nrf/src/pdm.rs
index 8815bb316..9df685a26 100644
--- a/embassy-nrf/src/pdm.rs
+++ b/embassy-nrf/src/pdm.rs
@@ -14,7 +14,7 @@ use futures::future::poll_fn;
14use crate::chip::EASY_DMA_SIZE; 14use crate::chip::EASY_DMA_SIZE;
15use crate::gpio::sealed::Pin; 15use crate::gpio::sealed::Pin;
16use crate::gpio::{AnyPin, Pin as GpioPin}; 16use crate::gpio::{AnyPin, Pin as GpioPin};
17use crate::interrupt::{self, InterruptExt}; 17use crate::interrupt::{self};
18use crate::Peripheral; 18use crate::Peripheral;
19 19
20/// Interrupt handler. 20/// Interrupt handler.
@@ -94,8 +94,8 @@ impl<'d, T: Instance> Pdm<'d, T> {
94 r.gainr.write(|w| w.gainr().default_gain()); 94 r.gainr.write(|w| w.gainr().default_gain());
95 95
96 // IRQ 96 // IRQ
97 unsafe { T::Interrupt::steal() }.unpend(); 97 T::Interrupt::unpend();
98 unsafe { T::Interrupt::steal() }.enable(); 98 unsafe { T::Interrupt::enable() };
99 99
100 r.enable.write(|w| w.enable().set_bit()); 100 r.enable.write(|w| w.enable().set_bit());
101 101
diff --git a/embassy-nrf/src/qdec.rs b/embassy-nrf/src/qdec.rs
index c845492fc..5761d04e1 100644
--- a/embassy-nrf/src/qdec.rs
+++ b/embassy-nrf/src/qdec.rs
@@ -6,12 +6,11 @@ use core::future::poll_fn;
6use core::marker::PhantomData; 6use core::marker::PhantomData;
7use core::task::Poll; 7use core::task::Poll;
8 8
9use embassy_cortex_m::interrupt::Interrupt;
10use embassy_hal_common::{into_ref, PeripheralRef}; 9use embassy_hal_common::{into_ref, PeripheralRef};
11 10
12use crate::gpio::sealed::Pin as _; 11use crate::gpio::sealed::Pin as _;
13use crate::gpio::{AnyPin, Pin as GpioPin}; 12use crate::gpio::{AnyPin, Pin as GpioPin};
14use crate::interrupt::InterruptExt; 13use crate::interrupt::Interrupt;
15use crate::{interrupt, Peripheral}; 14use crate::{interrupt, Peripheral};
16 15
17/// Quadrature decoder driver. 16/// Quadrature decoder driver.
@@ -134,8 +133,8 @@ impl<'d, T: Instance> Qdec<'d, T> {
134 SamplePeriod::_131ms => w.sampleper()._131ms(), 133 SamplePeriod::_131ms => w.sampleper()._131ms(),
135 }); 134 });
136 135
137 unsafe { T::Interrupt::steal() }.unpend(); 136 T::Interrupt::unpend();
138 unsafe { T::Interrupt::steal() }.enable(); 137 unsafe { T::Interrupt::enable() };
139 138
140 // Enable peripheral 139 // Enable peripheral
141 r.enable.write(|w| w.enable().set_bit()); 140 r.enable.write(|w| w.enable().set_bit());
diff --git a/embassy-nrf/src/qspi.rs b/embassy-nrf/src/qspi.rs
index 2e16c2ff5..3f48568b3 100644
--- a/embassy-nrf/src/qspi.rs
+++ b/embassy-nrf/src/qspi.rs
@@ -12,7 +12,7 @@ use embassy_hal_common::{into_ref, PeripheralRef};
12use embedded_storage::nor_flash::{ErrorType, NorFlash, NorFlashError, NorFlashErrorKind, ReadNorFlash}; 12use embedded_storage::nor_flash::{ErrorType, NorFlash, NorFlashError, NorFlashErrorKind, ReadNorFlash};
13 13
14use crate::gpio::{self, Pin as GpioPin}; 14use crate::gpio::{self, Pin as GpioPin};
15use crate::interrupt::{self, Interrupt, InterruptExt}; 15use crate::interrupt::{self, Interrupt};
16pub use crate::pac::qspi::ifconfig0::{ 16pub use crate::pac::qspi::ifconfig0::{
17 ADDRMODE_A as AddressMode, PPSIZE_A as WritePageSize, READOC_A as ReadOpcode, WRITEOC_A as WriteOpcode, 17 ADDRMODE_A as AddressMode, PPSIZE_A as WritePageSize, READOC_A as ReadOpcode, WRITEOC_A as WriteOpcode,
18}; 18};
@@ -207,8 +207,8 @@ impl<'d, T: Instance> Qspi<'d, T> {
207 w 207 w
208 }); 208 });
209 209
210 unsafe { T::Interrupt::steal() }.unpend(); 210 T::Interrupt::unpend();
211 unsafe { T::Interrupt::steal() }.enable(); 211 unsafe { T::Interrupt::enable() };
212 212
213 // Enable it 213 // Enable it
214 r.enable.write(|w| w.enable().enabled()); 214 r.enable.write(|w| w.enable().enabled());
diff --git a/embassy-nrf/src/rng.rs b/embassy-nrf/src/rng.rs
index a5602248d..7e9b35481 100644
--- a/embassy-nrf/src/rng.rs
+++ b/embassy-nrf/src/rng.rs
@@ -8,12 +8,11 @@ use core::ptr;
8use core::sync::atomic::{AtomicPtr, Ordering}; 8use core::sync::atomic::{AtomicPtr, Ordering};
9use core::task::Poll; 9use core::task::Poll;
10 10
11use embassy_cortex_m::interrupt::Interrupt;
12use embassy_hal_common::drop::OnDrop; 11use embassy_hal_common::drop::OnDrop;
13use embassy_hal_common::{into_ref, PeripheralRef}; 12use embassy_hal_common::{into_ref, PeripheralRef};
14use embassy_sync::waitqueue::AtomicWaker; 13use embassy_sync::waitqueue::AtomicWaker;
15 14
16use crate::interrupt::InterruptExt; 15use crate::interrupt::Interrupt;
17use crate::{interrupt, Peripheral}; 16use crate::{interrupt, Peripheral};
18 17
19/// Interrupt handler. 18/// Interrupt handler.
@@ -99,8 +98,8 @@ impl<'d, T: Instance> Rng<'d, T> {
99 this.stop(); 98 this.stop();
100 this.disable_irq(); 99 this.disable_irq();
101 100
102 unsafe { T::Interrupt::steal() }.unpend(); 101 T::Interrupt::unpend();
103 unsafe { T::Interrupt::steal() }.enable(); 102 unsafe { T::Interrupt::enable() };
104 103
105 this 104 this
106 } 105 }
diff --git a/embassy-nrf/src/saadc.rs b/embassy-nrf/src/saadc.rs
index 8aff7df16..39764e380 100644
--- a/embassy-nrf/src/saadc.rs
+++ b/embassy-nrf/src/saadc.rs
@@ -6,7 +6,7 @@ use core::future::poll_fn;
6use core::sync::atomic::{compiler_fence, Ordering}; 6use core::sync::atomic::{compiler_fence, Ordering};
7use core::task::Poll; 7use core::task::Poll;
8 8
9use embassy_cortex_m::interrupt::{Interrupt, InterruptExt}; 9use embassy_cortex_m::interrupt::Interrupt;
10use embassy_hal_common::drop::OnDrop; 10use embassy_hal_common::drop::OnDrop;
11use embassy_hal_common::{impl_peripheral, into_ref, PeripheralRef}; 11use embassy_hal_common::{impl_peripheral, into_ref, PeripheralRef};
12use embassy_sync::waitqueue::AtomicWaker; 12use embassy_sync::waitqueue::AtomicWaker;
@@ -189,8 +189,8 @@ impl<'d, const N: usize> Saadc<'d, N> {
189 // Disable all events interrupts 189 // Disable all events interrupts
190 r.intenclr.write(|w| unsafe { w.bits(0x003F_FFFF) }); 190 r.intenclr.write(|w| unsafe { w.bits(0x003F_FFFF) });
191 191
192 unsafe { interrupt::SAADC::steal() }.unpend(); 192 interrupt::SAADC::unpend();
193 unsafe { interrupt::SAADC::steal() }.enable(); 193 unsafe { interrupt::SAADC::enable() };
194 194
195 Self { _p: saadc } 195 Self { _p: saadc }
196 } 196 }
diff --git a/embassy-nrf/src/spim.rs b/embassy-nrf/src/spim.rs
index 89cbdfee9..bb9cda323 100644
--- a/embassy-nrf/src/spim.rs
+++ b/embassy-nrf/src/spim.rs
@@ -15,7 +15,7 @@ pub use pac::spim0::frequency::FREQUENCY_A as Frequency;
15use crate::chip::FORCE_COPY_BUFFER_SIZE; 15use crate::chip::FORCE_COPY_BUFFER_SIZE;
16use crate::gpio::sealed::Pin as _; 16use crate::gpio::sealed::Pin as _;
17use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits}; 17use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits};
18use crate::interrupt::{self, Interrupt, InterruptExt}; 18use crate::interrupt::{self, Interrupt};
19use crate::util::{slice_in_ram_or, slice_ptr_parts, slice_ptr_parts_mut}; 19use crate::util::{slice_in_ram_or, slice_ptr_parts, slice_ptr_parts_mut};
20use crate::{pac, Peripheral}; 20use crate::{pac, Peripheral};
21 21
@@ -207,8 +207,8 @@ impl<'d, T: Instance> Spim<'d, T> {
207 // Disable all events interrupts 207 // Disable all events interrupts
208 r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) }); 208 r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
209 209
210 unsafe { T::Interrupt::steal() }.unpend(); 210 T::Interrupt::unpend();
211 unsafe { T::Interrupt::steal() }.enable(); 211 unsafe { T::Interrupt::enable() };
212 212
213 Self { _p: spim } 213 Self { _p: spim }
214 } 214 }
diff --git a/embassy-nrf/src/spis.rs b/embassy-nrf/src/spis.rs
index 55b5e060e..a1d6803ed 100644
--- a/embassy-nrf/src/spis.rs
+++ b/embassy-nrf/src/spis.rs
@@ -13,7 +13,7 @@ pub use embedded_hal_02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MO
13use crate::chip::FORCE_COPY_BUFFER_SIZE; 13use crate::chip::FORCE_COPY_BUFFER_SIZE;
14use crate::gpio::sealed::Pin as _; 14use crate::gpio::sealed::Pin as _;
15use crate::gpio::{self, AnyPin, Pin as GpioPin}; 15use crate::gpio::{self, AnyPin, Pin as GpioPin};
16use crate::interrupt::{self, Interrupt, InterruptExt}; 16use crate::interrupt::{self, Interrupt};
17use crate::util::{slice_in_ram_or, slice_ptr_parts, slice_ptr_parts_mut}; 17use crate::util::{slice_in_ram_or, slice_ptr_parts, slice_ptr_parts_mut};
18use crate::{pac, Peripheral}; 18use crate::{pac, Peripheral};
19 19
@@ -214,8 +214,8 @@ impl<'d, T: Instance> Spis<'d, T> {
214 // Disable all events interrupts. 214 // Disable all events interrupts.
215 r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) }); 215 r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
216 216
217 unsafe { T::Interrupt::steal() }.unpend(); 217 T::Interrupt::unpend();
218 unsafe { T::Interrupt::steal() }.enable(); 218 unsafe { T::Interrupt::enable() };
219 219
220 Self { _p: spis } 220 Self { _p: spis }
221 } 221 }
diff --git a/embassy-nrf/src/temp.rs b/embassy-nrf/src/temp.rs
index 0653710af..8a127efc5 100644
--- a/embassy-nrf/src/temp.rs
+++ b/embassy-nrf/src/temp.rs
@@ -3,13 +3,12 @@
3use core::future::poll_fn; 3use core::future::poll_fn;
4use core::task::Poll; 4use core::task::Poll;
5 5
6use embassy_cortex_m::interrupt::Interrupt;
7use embassy_hal_common::drop::OnDrop; 6use embassy_hal_common::drop::OnDrop;
8use embassy_hal_common::{into_ref, PeripheralRef}; 7use embassy_hal_common::{into_ref, PeripheralRef};
9use embassy_sync::waitqueue::AtomicWaker; 8use embassy_sync::waitqueue::AtomicWaker;
10use fixed::types::I30F2; 9use fixed::types::I30F2;
11 10
12use crate::interrupt::InterruptExt; 11use crate::interrupt::Interrupt;
13use crate::peripherals::TEMP; 12use crate::peripherals::TEMP;
14use crate::{interrupt, pac, Peripheral}; 13use crate::{interrupt, pac, Peripheral};
15 14
@@ -42,8 +41,8 @@ impl<'d> Temp<'d> {
42 into_ref!(_peri); 41 into_ref!(_peri);
43 42
44 // Enable interrupt that signals temperature values 43 // Enable interrupt that signals temperature values
45 unsafe { interrupt::TEMP::steal() }.unpend(); 44 interrupt::TEMP::unpend();
46 unsafe { interrupt::TEMP::steal() }.enable(); 45 unsafe { interrupt::TEMP::enable() };
47 46
48 Self { _peri } 47 Self { _peri }
49 } 48 }
diff --git a/embassy-nrf/src/time_driver.rs b/embassy-nrf/src/time_driver.rs
index c82c238cc..4feff8a75 100644
--- a/embassy-nrf/src/time_driver.rs
+++ b/embassy-nrf/src/time_driver.rs
@@ -7,7 +7,7 @@ use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
7use embassy_sync::blocking_mutex::CriticalSectionMutex as Mutex; 7use embassy_sync::blocking_mutex::CriticalSectionMutex as Mutex;
8use embassy_time::driver::{AlarmHandle, Driver}; 8use embassy_time::driver::{AlarmHandle, Driver};
9 9
10use crate::interrupt::{Interrupt, InterruptExt}; 10use crate::interrupt::Interrupt;
11use crate::{interrupt, pac}; 11use crate::{interrupt, pac};
12 12
13fn rtc() -> &'static pac::rtc0::RegisterBlock { 13fn rtc() -> &'static pac::rtc0::RegisterBlock {
@@ -142,9 +142,8 @@ impl RtcDriver {
142 // Wait for clear 142 // Wait for clear
143 while r.counter.read().bits() != 0 {} 143 while r.counter.read().bits() != 0 {}
144 144
145 let irq = unsafe { interrupt::RTC1::steal() }; 145 interrupt::RTC1::set_priority(irq_prio);
146 irq.set_priority(irq_prio); 146 unsafe { interrupt::RTC1::enable() };
147 irq.enable();
148 } 147 }
149 148
150 fn on_interrupt(&self) { 149 fn on_interrupt(&self) {
diff --git a/embassy-nrf/src/twim.rs b/embassy-nrf/src/twim.rs
index cab36884f..dea398a67 100644
--- a/embassy-nrf/src/twim.rs
+++ b/embassy-nrf/src/twim.rs
@@ -16,7 +16,7 @@ use embassy_time::{Duration, Instant};
16 16
17use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE}; 17use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE};
18use crate::gpio::Pin as GpioPin; 18use crate::gpio::Pin as GpioPin;
19use crate::interrupt::{self, Interrupt, InterruptExt}; 19use crate::interrupt::{self, Interrupt};
20use crate::util::{slice_in_ram, slice_in_ram_or}; 20use crate::util::{slice_in_ram, slice_in_ram_or};
21use crate::{gpio, pac, Peripheral}; 21use crate::{gpio, pac, Peripheral};
22 22
@@ -174,8 +174,8 @@ impl<'d, T: Instance> Twim<'d, T> {
174 // Disable all events interrupts 174 // Disable all events interrupts
175 r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) }); 175 r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
176 176
177 unsafe { T::Interrupt::steal() }.unpend(); 177 T::Interrupt::unpend();
178 unsafe { T::Interrupt::steal() }.enable(); 178 unsafe { T::Interrupt::enable() };
179 179
180 Self { _p: twim } 180 Self { _p: twim }
181 } 181 }
diff --git a/embassy-nrf/src/twis.rs b/embassy-nrf/src/twis.rs
index f68a9940a..752a8c046 100644
--- a/embassy-nrf/src/twis.rs
+++ b/embassy-nrf/src/twis.rs
@@ -15,7 +15,7 @@ use embassy_time::{Duration, Instant};
15 15
16use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE}; 16use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE};
17use crate::gpio::Pin as GpioPin; 17use crate::gpio::Pin as GpioPin;
18use crate::interrupt::{self, Interrupt, InterruptExt}; 18use crate::interrupt::{self, Interrupt};
19use crate::util::slice_in_ram_or; 19use crate::util::slice_in_ram_or;
20use crate::{gpio, pac, Peripheral}; 20use crate::{gpio, pac, Peripheral};
21 21
@@ -204,8 +204,8 @@ impl<'d, T: Instance> Twis<'d, T> {
204 // Generate suspend on read event 204 // Generate suspend on read event
205 r.shorts.write(|w| w.read_suspend().enabled()); 205 r.shorts.write(|w| w.read_suspend().enabled());
206 206
207 unsafe { T::Interrupt::steal() }.unpend(); 207 T::Interrupt::unpend();
208 unsafe { T::Interrupt::steal() }.enable(); 208 unsafe { T::Interrupt::enable() };
209 209
210 Self { _p: twis } 210 Self { _p: twis }
211 } 211 }
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs
index 032089635..6c6941ee8 100644
--- a/embassy-nrf/src/uarte.rs
+++ b/embassy-nrf/src/uarte.rs
@@ -27,7 +27,7 @@ pub use pac::uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Pari
27use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE}; 27use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE};
28use crate::gpio::sealed::Pin as _; 28use crate::gpio::sealed::Pin as _;
29use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits}; 29use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits};
30use crate::interrupt::{self, Interrupt, InterruptExt}; 30use crate::interrupt::{self, Interrupt};
31use crate::ppi::{AnyConfigurableChannel, ConfigurableChannel, Event, Ppi, Task}; 31use crate::ppi::{AnyConfigurableChannel, ConfigurableChannel, Event, Ppi, Task};
32use crate::timer::{Frequency, Instance as TimerInstance, Timer}; 32use crate::timer::{Frequency, Instance as TimerInstance, Timer};
33use crate::util::slice_in_ram_or; 33use crate::util::slice_in_ram_or;
@@ -168,8 +168,8 @@ impl<'d, T: Instance> Uarte<'d, T> {
168 } 168 }
169 r.psel.rts.write(|w| unsafe { w.bits(rts.psel_bits()) }); 169 r.psel.rts.write(|w| unsafe { w.bits(rts.psel_bits()) });
170 170
171 unsafe { T::Interrupt::steal() }.unpend(); 171 T::Interrupt::unpend();
172 unsafe { T::Interrupt::steal() }.enable(); 172 unsafe { T::Interrupt::enable() };
173 173
174 let hardware_flow_control = match (rts.is_some(), cts.is_some()) { 174 let hardware_flow_control = match (rts.is_some(), cts.is_some()) {
175 (false, false) => false, 175 (false, false) => false,
@@ -358,8 +358,8 @@ impl<'d, T: Instance> UarteTx<'d, T> {
358 let hardware_flow_control = cts.is_some(); 358 let hardware_flow_control = cts.is_some();
359 configure(r, config, hardware_flow_control); 359 configure(r, config, hardware_flow_control);
360 360
361 unsafe { T::Interrupt::steal() }.unpend(); 361 T::Interrupt::unpend();
362 unsafe { T::Interrupt::steal() }.enable(); 362 unsafe { T::Interrupt::enable() };
363 363
364 let s = T::state(); 364 let s = T::state();
365 s.tx_rx_refcount.store(1, Ordering::Relaxed); 365 s.tx_rx_refcount.store(1, Ordering::Relaxed);
@@ -551,8 +551,8 @@ impl<'d, T: Instance> UarteRx<'d, T> {
551 r.psel.txd.write(|w| w.connect().disconnected()); 551 r.psel.txd.write(|w| w.connect().disconnected());
552 r.psel.cts.write(|w| w.connect().disconnected()); 552 r.psel.cts.write(|w| w.connect().disconnected());
553 553
554 unsafe { T::Interrupt::steal() }.unpend(); 554 T::Interrupt::unpend();
555 unsafe { T::Interrupt::steal() }.enable(); 555 unsafe { T::Interrupt::enable() };
556 556
557 let hardware_flow_control = rts.is_some(); 557 let hardware_flow_control = rts.is_some();
558 configure(r, config, hardware_flow_control); 558 configure(r, config, hardware_flow_control);
diff --git a/embassy-nrf/src/usb/mod.rs b/embassy-nrf/src/usb/mod.rs
index c1f3f48cb..3c62b4452 100644
--- a/embassy-nrf/src/usb/mod.rs
+++ b/embassy-nrf/src/usb/mod.rs
@@ -18,7 +18,7 @@ use embassy_usb_driver::{Direction, EndpointAddress, EndpointError, EndpointInfo
18use pac::usbd::RegisterBlock; 18use pac::usbd::RegisterBlock;
19 19
20use self::vbus_detect::VbusDetect; 20use self::vbus_detect::VbusDetect;
21use crate::interrupt::{self, Interrupt, InterruptExt}; 21use crate::interrupt::{self, Interrupt};
22use crate::util::slice_in_ram; 22use crate::util::slice_in_ram;
23use crate::{pac, Peripheral}; 23use crate::{pac, Peripheral};
24 24
@@ -103,8 +103,8 @@ impl<'d, T: Instance, V: VbusDetect> Driver<'d, T, V> {
103 ) -> Self { 103 ) -> Self {
104 into_ref!(usb); 104 into_ref!(usb);
105 105
106 unsafe { T::Interrupt::steal() }.unpend(); 106 T::Interrupt::unpend();
107 unsafe { T::Interrupt::steal() }.enable(); 107 unsafe { T::Interrupt::enable() };
108 108
109 Self { 109 Self {
110 _p: usb, 110 _p: usb,
diff --git a/embassy-nrf/src/usb/vbus_detect.rs b/embassy-nrf/src/usb/vbus_detect.rs
index cecd4c595..a6a959905 100644
--- a/embassy-nrf/src/usb/vbus_detect.rs
+++ b/embassy-nrf/src/usb/vbus_detect.rs
@@ -7,7 +7,7 @@ use core::task::Poll;
7use embassy_sync::waitqueue::AtomicWaker; 7use embassy_sync::waitqueue::AtomicWaker;
8 8
9use super::BUS_WAKER; 9use super::BUS_WAKER;
10use crate::interrupt::{self, Interrupt, InterruptExt}; 10use crate::interrupt::{self, Interrupt};
11use crate::pac; 11use crate::pac;
12 12
13/// Trait for detecting USB VBUS power. 13/// Trait for detecting USB VBUS power.
@@ -80,8 +80,8 @@ impl HardwareVbusDetect {
80 pub fn new(_irq: impl interrupt::Binding<UsbRegIrq, InterruptHandler> + 'static) -> Self { 80 pub fn new(_irq: impl interrupt::Binding<UsbRegIrq, InterruptHandler> + 'static) -> Self {
81 let regs = unsafe { &*UsbRegPeri::ptr() }; 81 let regs = unsafe { &*UsbRegPeri::ptr() };
82 82
83 unsafe { UsbRegIrq::steal() }.unpend(); 83 UsbRegIrq::unpend();
84 unsafe { UsbRegIrq::steal() }.enable(); 84 unsafe { UsbRegIrq::enable() };
85 85
86 regs.intenset 86 regs.intenset
87 .write(|w| w.usbdetected().set().usbremoved().set().usbpwrrdy().set()); 87 .write(|w| w.usbdetected().set().usbremoved().set().usbpwrrdy().set());
diff --git a/embassy-rp/src/adc.rs b/embassy-rp/src/adc.rs
index 59c7a47ce..86a353670 100644
--- a/embassy-rp/src/adc.rs
+++ b/embassy-rp/src/adc.rs
@@ -8,7 +8,7 @@ use embassy_sync::waitqueue::AtomicWaker;
8use embedded_hal_02::adc::{Channel, OneShot}; 8use embedded_hal_02::adc::{Channel, OneShot};
9 9
10use crate::gpio::Pin; 10use crate::gpio::Pin;
11use crate::interrupt::{self, InterruptExt, ADC_IRQ_FIFO}; 11use crate::interrupt::{self, ADC_IRQ_FIFO};
12use crate::peripherals::ADC; 12use crate::peripherals::ADC;
13use crate::{pac, peripherals, Peripheral}; 13use crate::{pac, peripherals, Peripheral};
14static WAKER: AtomicWaker = AtomicWaker::new(); 14static WAKER: AtomicWaker = AtomicWaker::new();
@@ -63,8 +63,8 @@ impl<'d> Adc<'d> {
63 63
64 // Setup IRQ 64 // Setup IRQ
65 unsafe { 65 unsafe {
66 ADC_IRQ_FIFO::steal().unpend(); 66 ADC_IRQ_FIFO::unpend();
67 ADC_IRQ_FIFO::steal().enable(); 67 ADC_IRQ_FIFO::enable();
68 }; 68 };
69 69
70 Self { phantom: PhantomData } 70 Self { phantom: PhantomData }
diff --git a/embassy-rp/src/dma.rs b/embassy-rp/src/dma.rs
index ba07a88df..74f4e6998 100644
--- a/embassy-rp/src/dma.rs
+++ b/embassy-rp/src/dma.rs
@@ -4,7 +4,7 @@ use core::pin::Pin;
4use core::sync::atomic::{compiler_fence, Ordering}; 4use core::sync::atomic::{compiler_fence, Ordering};
5use core::task::{Context, Poll}; 5use core::task::{Context, Poll};
6 6
7use embassy_cortex_m::interrupt::{Interrupt, InterruptExt}; 7use embassy_cortex_m::interrupt::Interrupt;
8use embassy_hal_common::{impl_peripheral, into_ref, Peripheral, PeripheralRef}; 8use embassy_hal_common::{impl_peripheral, into_ref, Peripheral, PeripheralRef};
9use embassy_sync::waitqueue::AtomicWaker; 9use embassy_sync::waitqueue::AtomicWaker;
10use pac::dma::vals::DataSize; 10use pac::dma::vals::DataSize;
@@ -29,13 +29,12 @@ unsafe fn DMA_IRQ_0() {
29} 29}
30 30
31pub(crate) unsafe fn init() { 31pub(crate) unsafe fn init() {
32 let irq = interrupt::DMA_IRQ_0::steal(); 32 interrupt::DMA_IRQ_0::disable();
33 irq.disable(); 33 interrupt::DMA_IRQ_0::set_priority(interrupt::Priority::P3);
34 irq.set_priority(interrupt::Priority::P3);
35 34
36 pac::DMA.inte0().write(|w| w.set_inte0(0xFFFF)); 35 pac::DMA.inte0().write(|w| w.set_inte0(0xFFFF));
37 36
38 irq.enable(); 37 interrupt::DMA_IRQ_0::enable();
39} 38}
40 39
41pub unsafe fn read<'a, C: Channel, W: Word>( 40pub unsafe fn read<'a, C: Channel, W: Word>(
diff --git a/embassy-rp/src/gpio.rs b/embassy-rp/src/gpio.rs
index da8efba91..f213bfeab 100644
--- a/embassy-rp/src/gpio.rs
+++ b/embassy-rp/src/gpio.rs
@@ -3,7 +3,7 @@ use core::future::Future;
3use core::pin::Pin as FuturePin; 3use core::pin::Pin as FuturePin;
4use core::task::{Context, Poll}; 4use core::task::{Context, Poll};
5 5
6use embassy_cortex_m::interrupt::{Interrupt, InterruptExt}; 6use embassy_cortex_m::interrupt::Interrupt;
7use embassy_hal_common::{impl_peripheral, into_ref, PeripheralRef}; 7use embassy_hal_common::{impl_peripheral, into_ref, PeripheralRef};
8use embassy_sync::waitqueue::AtomicWaker; 8use embassy_sync::waitqueue::AtomicWaker;
9 9
@@ -137,10 +137,9 @@ pub enum InterruptTrigger {
137} 137}
138 138
139pub(crate) unsafe fn init() { 139pub(crate) unsafe fn init() {
140 let irq = interrupt::IO_IRQ_BANK0::steal(); 140 interrupt::IO_IRQ_BANK0::disable();
141 irq.disable(); 141 interrupt::IO_IRQ_BANK0::set_priority(interrupt::Priority::P3);
142 irq.set_priority(interrupt::Priority::P3); 142 interrupt::IO_IRQ_BANK0::enable();
143 irq.enable();
144} 143}
145 144
146#[interrupt] 145#[interrupt]
diff --git a/embassy-rp/src/i2c.rs b/embassy-rp/src/i2c.rs
index 6ce77f073..124f1c00a 100644
--- a/embassy-rp/src/i2c.rs
+++ b/embassy-rp/src/i2c.rs
@@ -2,7 +2,7 @@ use core::future;
2use core::marker::PhantomData; 2use core::marker::PhantomData;
3use core::task::Poll; 3use core::task::Poll;
4 4
5use embassy_cortex_m::interrupt::{self, Binding, Interrupt, InterruptExt}; 5use embassy_cortex_m::interrupt::{self, Binding, Interrupt};
6use embassy_hal_common::{into_ref, PeripheralRef}; 6use embassy_hal_common::{into_ref, PeripheralRef};
7use embassy_sync::waitqueue::AtomicWaker; 7use embassy_sync::waitqueue::AtomicWaker;
8use pac::i2c; 8use pac::i2c;
@@ -82,14 +82,12 @@ impl<'d, T: Instance> I2c<'d, T, Async> {
82 82
83 let i2c = Self::new_inner(peri, scl.map_into(), sda.map_into(), config); 83 let i2c = Self::new_inner(peri, scl.map_into(), sda.map_into(), config);
84 84
85 unsafe { 85 let r = T::regs();
86 let i2c = T::regs();
87 86
88 // mask everything initially 87 // mask everything initially
89 i2c.ic_intr_mask().write_value(i2c::regs::IcIntrMask(0)); 88 unsafe { r.ic_intr_mask().write_value(i2c::regs::IcIntrMask(0)) }
90 T::Interrupt::steal().unpend(); 89 T::Interrupt::unpend();
91 T::Interrupt::steal().enable(); 90 unsafe { T::Interrupt::enable() };
92 }
93 91
94 i2c 92 i2c
95 } 93 }
diff --git a/embassy-rp/src/interrupt.rs b/embassy-rp/src/interrupt.rs
index 1db13deef..c9298644d 100644
--- a/embassy-rp/src/interrupt.rs
+++ b/embassy-rp/src/interrupt.rs
@@ -1,7 +1,7 @@
1//! Interrupt definitions and macros to bind them. 1//! Interrupt definitions and macros to bind them.
2pub use cortex_m::interrupt::{CriticalSection, Mutex}; 2pub use cortex_m::interrupt::{CriticalSection, Mutex};
3use embassy_cortex_m::interrupt::_export::declare; 3use embassy_cortex_m::interrupt::_export::declare;
4pub use embassy_cortex_m::interrupt::{Binding, Handler, Interrupt, InterruptExt, Priority}; 4pub use embassy_cortex_m::interrupt::{Binding, Handler, Interrupt, Priority};
5 5
6use crate::pac::Interrupt as InterruptEnum; 6use crate::pac::Interrupt as InterruptEnum;
7declare!(TIMER_IRQ_0); 7declare!(TIMER_IRQ_0);
diff --git a/embassy-rp/src/multicore.rs b/embassy-rp/src/multicore.rs
index a13209f74..807fda57b 100644
--- a/embassy-rp/src/multicore.rs
+++ b/embassy-rp/src/multicore.rs
@@ -50,7 +50,7 @@
50use core::mem::ManuallyDrop; 50use core::mem::ManuallyDrop;
51use core::sync::atomic::{compiler_fence, AtomicBool, Ordering}; 51use core::sync::atomic::{compiler_fence, AtomicBool, Ordering};
52 52
53use crate::interrupt::{Interrupt, InterruptExt}; 53use crate::interrupt::Interrupt;
54use crate::peripherals::CORE1; 54use crate::peripherals::CORE1;
55use crate::{gpio, interrupt, pac}; 55use crate::{gpio, interrupt, pac};
56 56
@@ -156,8 +156,7 @@ where
156 156
157 IS_CORE1_INIT.store(true, Ordering::Release); 157 IS_CORE1_INIT.store(true, Ordering::Release);
158 // Enable fifo interrupt on CORE1 for `pause` functionality. 158 // Enable fifo interrupt on CORE1 for `pause` functionality.
159 let irq = unsafe { interrupt::SIO_IRQ_PROC1::steal() }; 159 unsafe { interrupt::SIO_IRQ_PROC1::enable() };
160 irq.enable();
161 160
162 entry() 161 entry()
163 } 162 }
diff --git a/embassy-rp/src/pio.rs b/embassy-rp/src/pio.rs
index cbe45334a..93e5bd34b 100644
--- a/embassy-rp/src/pio.rs
+++ b/embassy-rp/src/pio.rs
@@ -5,7 +5,7 @@ use core::sync::atomic::{compiler_fence, Ordering};
5use core::task::{Context, Poll}; 5use core::task::{Context, Poll};
6 6
7use atomic_polyfill::{AtomicU32, AtomicU8}; 7use atomic_polyfill::{AtomicU32, AtomicU8};
8use embassy_cortex_m::interrupt::{Interrupt, InterruptExt}; 8use embassy_cortex_m::interrupt::Interrupt;
9use embassy_hal_common::{into_ref, Peripheral, PeripheralRef}; 9use embassy_hal_common::{into_ref, Peripheral, PeripheralRef};
10use embassy_sync::waitqueue::AtomicWaker; 10use embassy_sync::waitqueue::AtomicWaker;
11use fixed::types::extra::U8; 11use fixed::types::extra::U8;
@@ -110,17 +110,15 @@ unsafe fn PIO1_IRQ_0() {
110} 110}
111 111
112pub(crate) unsafe fn init() { 112pub(crate) unsafe fn init() {
113 let irq = interrupt::PIO0_IRQ_0::steal(); 113 interrupt::PIO0_IRQ_0::disable();
114 irq.disable(); 114 interrupt::PIO0_IRQ_0::set_priority(interrupt::Priority::P3);
115 irq.set_priority(interrupt::Priority::P3);
116 pac::PIO0.irqs(0).inte().write(|m| m.0 = 0); 115 pac::PIO0.irqs(0).inte().write(|m| m.0 = 0);
117 irq.enable(); 116 interrupt::PIO0_IRQ_0::enable();
118 117
119 let irq = interrupt::PIO1_IRQ_0::steal(); 118 interrupt::PIO1_IRQ_0::disable();
120 irq.disable(); 119 interrupt::PIO1_IRQ_0::set_priority(interrupt::Priority::P3);
121 irq.set_priority(interrupt::Priority::P3);
122 pac::PIO1.irqs(0).inte().write(|m| m.0 = 0); 120 pac::PIO1.irqs(0).inte().write(|m| m.0 = 0);
123 irq.enable(); 121 interrupt::PIO1_IRQ_0::enable();
124} 122}
125 123
126/// Future that waits for TX-FIFO to become writable 124/// Future that waits for TX-FIFO to become writable
diff --git a/embassy-rp/src/timer.rs b/embassy-rp/src/timer.rs
index 80efd779f..68793950f 100644
--- a/embassy-rp/src/timer.rs
+++ b/embassy-rp/src/timer.rs
@@ -6,7 +6,7 @@ use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
6use embassy_sync::blocking_mutex::Mutex; 6use embassy_sync::blocking_mutex::Mutex;
7use embassy_time::driver::{AlarmHandle, Driver}; 7use embassy_time::driver::{AlarmHandle, Driver};
8 8
9use crate::interrupt::{Interrupt, InterruptExt}; 9use crate::interrupt::Interrupt;
10use crate::{interrupt, pac}; 10use crate::{interrupt, pac};
11 11
12struct AlarmState { 12struct AlarmState {
@@ -145,10 +145,10 @@ pub unsafe fn init() {
145 w.set_alarm(2, true); 145 w.set_alarm(2, true);
146 w.set_alarm(3, true); 146 w.set_alarm(3, true);
147 }); 147 });
148 interrupt::TIMER_IRQ_0::steal().enable(); 148 interrupt::TIMER_IRQ_0::enable();
149 interrupt::TIMER_IRQ_1::steal().enable(); 149 interrupt::TIMER_IRQ_1::enable();
150 interrupt::TIMER_IRQ_2::steal().enable(); 150 interrupt::TIMER_IRQ_2::enable();
151 interrupt::TIMER_IRQ_3::steal().enable(); 151 interrupt::TIMER_IRQ_3::enable();
152} 152}
153 153
154#[interrupt] 154#[interrupt]
diff --git a/embassy-rp/src/uart/buffered.rs b/embassy-rp/src/uart/buffered.rs
index 12d6b8d91..bb808c467 100644
--- a/embassy-rp/src/uart/buffered.rs
+++ b/embassy-rp/src/uart/buffered.rs
@@ -3,7 +3,7 @@ use core::slice;
3use core::task::Poll; 3use core::task::Poll;
4 4
5use atomic_polyfill::{AtomicU8, Ordering}; 5use atomic_polyfill::{AtomicU8, Ordering};
6use embassy_cortex_m::interrupt::{self, Binding, Interrupt, InterruptExt}; 6use embassy_cortex_m::interrupt::{self, Binding, Interrupt};
7use embassy_hal_common::atomic_ring_buffer::RingBuffer; 7use embassy_hal_common::atomic_ring_buffer::RingBuffer;
8use embassy_sync::waitqueue::AtomicWaker; 8use embassy_sync::waitqueue::AtomicWaker;
9use embassy_time::{Duration, Timer}; 9use embassy_time::{Duration, Timer};
@@ -80,8 +80,8 @@ pub(crate) fn init_buffers<'d, T: Instance + 'd>(
80 w.set_txim(true); 80 w.set_txim(true);
81 }); 81 });
82 82
83 T::Interrupt::steal().unpend(); 83 T::Interrupt::unpend();
84 T::Interrupt::steal().enable(); 84 T::Interrupt::enable();
85 }; 85 };
86} 86}
87 87
@@ -362,7 +362,7 @@ impl<'d, T: Instance> BufferedUartTx<'d, T> {
362 // FIFO and the number of bytes drops below a threshold. When the 362 // FIFO and the number of bytes drops below a threshold. When the
363 // FIFO was empty we have to manually pend the interrupt to shovel 363 // FIFO was empty we have to manually pend the interrupt to shovel
364 // TX data from the buffer into the FIFO. 364 // TX data from the buffer into the FIFO.
365 unsafe { T::Interrupt::steal() }.pend(); 365 T::Interrupt::pend();
366 Poll::Ready(Ok(n)) 366 Poll::Ready(Ok(n))
367 }) 367 })
368 } 368 }
@@ -398,7 +398,7 @@ impl<'d, T: Instance> BufferedUartTx<'d, T> {
398 // FIFO and the number of bytes drops below a threshold. When the 398 // FIFO and the number of bytes drops below a threshold. When the
399 // FIFO was empty we have to manually pend the interrupt to shovel 399 // FIFO was empty we have to manually pend the interrupt to shovel
400 // TX data from the buffer into the FIFO. 400 // TX data from the buffer into the FIFO.
401 unsafe { T::Interrupt::steal() }.pend(); 401 T::Interrupt::pend();
402 return Ok(n); 402 return Ok(n);
403 } 403 }
404 } 404 }
@@ -460,7 +460,7 @@ impl<'d, T: Instance> Drop for BufferedUartRx<'d, T> {
460 // TX is inactive if the the buffer is not available. 460 // TX is inactive if the the buffer is not available.
461 // We can now unregister the interrupt handler 461 // We can now unregister the interrupt handler
462 if state.tx_buf.len() == 0 { 462 if state.tx_buf.len() == 0 {
463 T::Interrupt::steal().disable(); 463 T::Interrupt::disable();
464 } 464 }
465 } 465 }
466 } 466 }
@@ -475,7 +475,7 @@ impl<'d, T: Instance> Drop for BufferedUartTx<'d, T> {
475 // RX is inactive if the the buffer is not available. 475 // RX is inactive if the the buffer is not available.
476 // We can now unregister the interrupt handler 476 // We can now unregister the interrupt handler
477 if state.rx_buf.len() == 0 { 477 if state.rx_buf.len() == 0 {
478 T::Interrupt::steal().disable(); 478 T::Interrupt::disable();
479 } 479 }
480 } 480 }
481 } 481 }
diff --git a/embassy-rp/src/uart/mod.rs b/embassy-rp/src/uart/mod.rs
index 44e0ca0f6..a83d94e49 100644
--- a/embassy-rp/src/uart/mod.rs
+++ b/embassy-rp/src/uart/mod.rs
@@ -3,7 +3,7 @@ use core::marker::PhantomData;
3use core::task::Poll; 3use core::task::Poll;
4 4
5use atomic_polyfill::{AtomicU16, Ordering}; 5use atomic_polyfill::{AtomicU16, Ordering};
6use embassy_cortex_m::interrupt::{self, Binding, Interrupt, InterruptExt}; 6use embassy_cortex_m::interrupt::{self, Binding, Interrupt};
7use embassy_futures::select::{select, Either}; 7use embassy_futures::select::{select, Either};
8use embassy_hal_common::{into_ref, PeripheralRef}; 8use embassy_hal_common::{into_ref, PeripheralRef};
9use embassy_sync::waitqueue::AtomicWaker; 9use embassy_sync::waitqueue::AtomicWaker;
@@ -245,12 +245,10 @@ impl<'d, T: Instance, M: Mode> UartRx<'d, T, M> {
245 fn new_inner(has_irq: bool, rx_dma: Option<PeripheralRef<'d, AnyChannel>>) -> Self { 245 fn new_inner(has_irq: bool, rx_dma: Option<PeripheralRef<'d, AnyChannel>>) -> Self {
246 debug_assert_eq!(has_irq, rx_dma.is_some()); 246 debug_assert_eq!(has_irq, rx_dma.is_some());
247 if has_irq { 247 if has_irq {
248 unsafe { 248 // disable all error interrupts initially
249 // disable all error interrupts initially 249 unsafe { T::regs().uartimsc().write(|w| w.0 = 0) }
250 T::regs().uartimsc().write(|w| w.0 = 0); 250 T::Interrupt::unpend();
251 T::Interrupt::steal().unpend(); 251 unsafe { T::Interrupt::enable() };
252 T::Interrupt::steal().enable();
253 }
254 } 252 }
255 Self { 253 Self {
256 rx_dma, 254 rx_dma,
@@ -295,7 +293,7 @@ impl<'d, T: Instance, M: Mode> Drop for UartRx<'d, T, M> {
295 fn drop(&mut self) { 293 fn drop(&mut self) {
296 if let Some(_) = self.rx_dma { 294 if let Some(_) = self.rx_dma {
297 unsafe { 295 unsafe {
298 T::Interrupt::steal().disable(); 296 T::Interrupt::disable();
299 // clear dma flags. irq handlers use these to disambiguate among themselves. 297 // clear dma flags. irq handlers use these to disambiguate among themselves.
300 T::regs().uartdmacr().write_clear(|reg| { 298 T::regs().uartdmacr().write_clear(|reg| {
301 reg.set_rxdmae(true); 299 reg.set_rxdmae(true);
diff --git a/embassy-rp/src/usb.rs b/embassy-rp/src/usb.rs
index fada2790f..cc88226df 100644
--- a/embassy-rp/src/usb.rs
+++ b/embassy-rp/src/usb.rs
@@ -11,7 +11,7 @@ use embassy_usb_driver::{
11 Direction, EndpointAddress, EndpointAllocError, EndpointError, EndpointInfo, EndpointType, Event, Unsupported, 11 Direction, EndpointAddress, EndpointAllocError, EndpointError, EndpointInfo, EndpointType, Event, Unsupported,
12}; 12};
13 13
14use crate::interrupt::{Interrupt, InterruptExt}; 14use crate::interrupt::Interrupt;
15use crate::{pac, peripherals, Peripheral, RegExt}; 15use crate::{pac, peripherals, Peripheral, RegExt};
16 16
17pub(crate) mod sealed { 17pub(crate) mod sealed {
@@ -106,10 +106,8 @@ pub struct Driver<'d, T: Instance> {
106 106
107impl<'d, T: Instance> Driver<'d, T> { 107impl<'d, T: Instance> Driver<'d, T> {
108 pub fn new(_usb: impl Peripheral<P = T> + 'd, _irq: impl Binding<T::Interrupt, InterruptHandler<T>>) -> Self { 108 pub fn new(_usb: impl Peripheral<P = T> + 'd, _irq: impl Binding<T::Interrupt, InterruptHandler<T>>) -> Self {
109 unsafe { 109 T::Interrupt::unpend();
110 T::Interrupt::steal().unpend(); 110 unsafe { T::Interrupt::enable() };
111 T::Interrupt::steal().enable();
112 }
113 111
114 let regs = T::regs(); 112 let regs = T::regs();
115 unsafe { 113 unsafe {
diff --git a/embassy-stm32/src/dcmi.rs b/embassy-stm32/src/dcmi.rs
index 5f3fc6a93..c13915a1b 100644
--- a/embassy-stm32/src/dcmi.rs
+++ b/embassy-stm32/src/dcmi.rs
@@ -8,7 +8,7 @@ use embassy_sync::waitqueue::AtomicWaker;
8use crate::dma::Transfer; 8use crate::dma::Transfer;
9use crate::gpio::sealed::AFType; 9use crate::gpio::sealed::AFType;
10use crate::gpio::Speed; 10use crate::gpio::Speed;
11use crate::interrupt::{Interrupt, InterruptExt}; 11use crate::interrupt::Interrupt;
12use crate::{interrupt, Peripheral}; 12use crate::{interrupt, Peripheral};
13 13
14/// Interrupt handler. 14/// Interrupt handler.
@@ -346,8 +346,8 @@ where
346 }); 346 });
347 } 347 }
348 348
349 unsafe { T::Interrupt::steal() }.unpend(); 349 T::Interrupt::unpend();
350 unsafe { T::Interrupt::steal() }.enable(); 350 unsafe { T::Interrupt::enable() };
351 351
352 Self { inner: peri, dma } 352 Self { inner: peri, dma }
353 } 353 }
diff --git a/embassy-stm32/src/dma/bdma.rs b/embassy-stm32/src/dma/bdma.rs
index 9dafa26d0..7a1ecda35 100644
--- a/embassy-stm32/src/dma/bdma.rs
+++ b/embassy-stm32/src/dma/bdma.rs
@@ -14,7 +14,7 @@ use super::ringbuffer::{DmaCtrl, DmaRingBuffer, OverrunError};
14use super::word::{Word, WordSize}; 14use super::word::{Word, WordSize};
15use super::Dir; 15use super::Dir;
16use crate::_generated::BDMA_CHANNEL_COUNT; 16use crate::_generated::BDMA_CHANNEL_COUNT;
17use crate::interrupt::{Interrupt, InterruptExt}; 17use crate::interrupt::Interrupt;
18use crate::pac; 18use crate::pac;
19use crate::pac::bdma::{regs, vals}; 19use crate::pac::bdma::{regs, vals};
20 20
@@ -70,9 +70,8 @@ static STATE: State = State::new();
70pub(crate) unsafe fn init(irq_priority: Priority) { 70pub(crate) unsafe fn init(irq_priority: Priority) {
71 foreach_interrupt! { 71 foreach_interrupt! {
72 ($peri:ident, bdma, $block:ident, $signal_name:ident, $irq:ident) => { 72 ($peri:ident, bdma, $block:ident, $signal_name:ident, $irq:ident) => {
73 let irq = crate::interrupt::$irq::steal(); 73 crate::interrupt::$irq::set_priority(irq_priority);
74 irq.set_priority(irq_priority); 74 crate::interrupt::$irq::enable();
75 irq.enable();
76 }; 75 };
77 } 76 }
78 crate::_generated::init_bdma(); 77 crate::_generated::init_bdma();
diff --git a/embassy-stm32/src/dma/dma.rs b/embassy-stm32/src/dma/dma.rs
index 47b749ece..3b602b991 100644
--- a/embassy-stm32/src/dma/dma.rs
+++ b/embassy-stm32/src/dma/dma.rs
@@ -13,7 +13,7 @@ use super::ringbuffer::{DmaCtrl, DmaRingBuffer, OverrunError};
13use super::word::{Word, WordSize}; 13use super::word::{Word, WordSize};
14use super::Dir; 14use super::Dir;
15use crate::_generated::DMA_CHANNEL_COUNT; 15use crate::_generated::DMA_CHANNEL_COUNT;
16use crate::interrupt::{Interrupt, InterruptExt}; 16use crate::interrupt::Interrupt;
17use crate::pac::dma::{regs, vals}; 17use crate::pac::dma::{regs, vals};
18use crate::{interrupt, pac}; 18use crate::{interrupt, pac};
19 19
@@ -149,9 +149,8 @@ static STATE: State = State::new();
149pub(crate) unsafe fn init(irq_priority: Priority) { 149pub(crate) unsafe fn init(irq_priority: Priority) {
150 foreach_interrupt! { 150 foreach_interrupt! {
151 ($peri:ident, dma, $block:ident, $signal_name:ident, $irq:ident) => { 151 ($peri:ident, dma, $block:ident, $signal_name:ident, $irq:ident) => {
152 let irq = interrupt::$irq::steal(); 152 interrupt::$irq::set_priority(irq_priority);
153 irq.set_priority(irq_priority); 153 interrupt::$irq::enable();
154 irq.enable();
155 }; 154 };
156 } 155 }
157 crate::_generated::init_dma(); 156 crate::_generated::init_dma();
diff --git a/embassy-stm32/src/dma/gpdma.rs b/embassy-stm32/src/dma/gpdma.rs
index 5a516ccda..7f8b82b46 100644
--- a/embassy-stm32/src/dma/gpdma.rs
+++ b/embassy-stm32/src/dma/gpdma.rs
@@ -12,7 +12,7 @@ use embassy_sync::waitqueue::AtomicWaker;
12use super::word::{Word, WordSize}; 12use super::word::{Word, WordSize};
13use super::Dir; 13use super::Dir;
14use crate::_generated::GPDMA_CHANNEL_COUNT; 14use crate::_generated::GPDMA_CHANNEL_COUNT;
15use crate::interrupt::{Interrupt, InterruptExt}; 15use crate::interrupt::Interrupt;
16use crate::pac; 16use crate::pac;
17use crate::pac::gpdma::vals; 17use crate::pac::gpdma::vals;
18 18
@@ -56,9 +56,8 @@ static STATE: State = State::new();
56pub(crate) unsafe fn init(irq_priority: Priority) { 56pub(crate) unsafe fn init(irq_priority: Priority) {
57 foreach_interrupt! { 57 foreach_interrupt! {
58 ($peri:ident, gpdma, $block:ident, $signal_name:ident, $irq:ident) => { 58 ($peri:ident, gpdma, $block:ident, $signal_name:ident, $irq:ident) => {
59 let irq = crate::interrupt::$irq::steal(); 59 crate::interrupt::$irq::set_priority(irq_priority);
60 irq.set_priority(irq_priority); 60 crate::interrupt::$irq::enable();
61 irq.enable();
62 }; 61 };
63 } 62 }
64 crate::_generated::init_gpdma(); 63 crate::_generated::init_gpdma();
diff --git a/embassy-stm32/src/eth/v1/mod.rs b/embassy-stm32/src/eth/v1/mod.rs
index 8ef2c3584..a5f1a268d 100644
--- a/embassy-stm32/src/eth/v1/mod.rs
+++ b/embassy-stm32/src/eth/v1/mod.rs
@@ -5,7 +5,7 @@ mod tx_desc;
5 5
6use core::sync::atomic::{fence, Ordering}; 6use core::sync::atomic::{fence, Ordering};
7 7
8use embassy_cortex_m::interrupt::{Interrupt, InterruptExt}; 8use embassy_cortex_m::interrupt::Interrupt;
9use embassy_hal_common::{into_ref, PeripheralRef}; 9use embassy_hal_common::{into_ref, PeripheralRef};
10use stm32_metapac::eth::vals::{Apcs, Cr, Dm, DmaomrSr, Fes, Ftf, Ifg, MbProgress, Mw, Pbl, Rsf, St, Tsf}; 10use stm32_metapac::eth::vals::{Apcs, Cr, Dm, DmaomrSr, Fes, Ftf, Ifg, MbProgress, Mw, Pbl, Rsf, St, Tsf};
11 11
@@ -267,8 +267,8 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
267 P::phy_reset(&mut this); 267 P::phy_reset(&mut this);
268 P::phy_init(&mut this); 268 P::phy_init(&mut this);
269 269
270 interrupt::ETH::steal().unpend(); 270 interrupt::ETH::unpend();
271 interrupt::ETH::steal().enable(); 271 interrupt::ETH::enable();
272 272
273 this 273 this
274 } 274 }
diff --git a/embassy-stm32/src/eth/v2/mod.rs b/embassy-stm32/src/eth/v2/mod.rs
index b56c3e8ab..9efa436ac 100644
--- a/embassy-stm32/src/eth/v2/mod.rs
+++ b/embassy-stm32/src/eth/v2/mod.rs
@@ -2,7 +2,7 @@ mod descriptors;
2 2
3use core::sync::atomic::{fence, Ordering}; 3use core::sync::atomic::{fence, Ordering};
4 4
5use embassy_cortex_m::interrupt::{Interrupt, InterruptExt}; 5use embassy_cortex_m::interrupt::Interrupt;
6use embassy_hal_common::{into_ref, PeripheralRef}; 6use embassy_hal_common::{into_ref, PeripheralRef};
7 7
8pub(crate) use self::descriptors::{RDes, RDesRing, TDes, TDesRing}; 8pub(crate) use self::descriptors::{RDes, RDesRing, TDes, TDesRing};
@@ -238,8 +238,8 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
238 P::phy_reset(&mut this); 238 P::phy_reset(&mut this);
239 P::phy_init(&mut this); 239 P::phy_init(&mut this);
240 240
241 interrupt::ETH::steal().unpend(); 241 interrupt::ETH::unpend();
242 interrupt::ETH::steal().enable(); 242 interrupt::ETH::enable();
243 243
244 this 244 this
245 } 245 }
diff --git a/embassy-stm32/src/exti.rs b/embassy-stm32/src/exti.rs
index 10109e56a..c2fa31b20 100644
--- a/embassy-stm32/src/exti.rs
+++ b/embassy-stm32/src/exti.rs
@@ -354,13 +354,13 @@ impl_exti!(EXTI15, 15);
354 354
355macro_rules! enable_irq { 355macro_rules! enable_irq {
356 ($e:ident) => { 356 ($e:ident) => {
357 crate::interrupt::$e::steal().enable(); 357 crate::interrupt::$e::enable();
358 }; 358 };
359} 359}
360 360
361/// safety: must be called only once 361/// safety: must be called only once
362pub(crate) unsafe fn init() { 362pub(crate) unsafe fn init() {
363 use crate::interrupt::{Interrupt, InterruptExt}; 363 use crate::interrupt::Interrupt;
364 364
365 foreach_exti_irq!(enable_irq); 365 foreach_exti_irq!(enable_irq);
366 366
diff --git a/embassy-stm32/src/flash/asynch.rs b/embassy-stm32/src/flash/asynch.rs
index 3c3ece99a..872614d4e 100644
--- a/embassy-stm32/src/flash/asynch.rs
+++ b/embassy-stm32/src/flash/asynch.rs
@@ -1,7 +1,7 @@
1use core::marker::PhantomData; 1use core::marker::PhantomData;
2 2
3use atomic_polyfill::{fence, Ordering}; 3use atomic_polyfill::{fence, Ordering};
4use embassy_cortex_m::interrupt::{Interrupt, InterruptExt}; 4use embassy_cortex_m::interrupt::Interrupt;
5use embassy_hal_common::drop::OnDrop; 5use embassy_hal_common::drop::OnDrop;
6use embassy_hal_common::into_ref; 6use embassy_hal_common::into_ref;
7use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex; 7use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
@@ -23,9 +23,8 @@ impl<'d> Flash<'d, Async> {
23 ) -> Self { 23 ) -> Self {
24 into_ref!(p); 24 into_ref!(p);
25 25
26 let flash_irq = unsafe { crate::interrupt::FLASH::steal() }; 26 crate::interrupt::FLASH::unpend();
27 flash_irq.unpend(); 27 unsafe { crate::interrupt::FLASH::enable() };
28 flash_irq.enable();
29 28
30 Self { 29 Self {
31 inner: p, 30 inner: p,
diff --git a/embassy-stm32/src/i2c/v2.rs b/embassy-stm32/src/i2c/v2.rs
index 642ddc18c..10f57f700 100644
--- a/embassy-stm32/src/i2c/v2.rs
+++ b/embassy-stm32/src/i2c/v2.rs
@@ -3,7 +3,7 @@ use core::future::poll_fn;
3use core::marker::PhantomData; 3use core::marker::PhantomData;
4use core::task::Poll; 4use core::task::Poll;
5 5
6use embassy_cortex_m::interrupt::{Interrupt, InterruptExt}; 6use embassy_cortex_m::interrupt::Interrupt;
7use embassy_embedded_hal::SetConfig; 7use embassy_embedded_hal::SetConfig;
8use embassy_hal_common::drop::OnDrop; 8use embassy_hal_common::drop::OnDrop;
9use embassy_hal_common::{into_ref, PeripheralRef}; 9use embassy_hal_common::{into_ref, PeripheralRef};
@@ -133,8 +133,8 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
133 }); 133 });
134 } 134 }
135 135
136 unsafe { T::Interrupt::steal() }.unpend(); 136 T::Interrupt::unpend();
137 unsafe { T::Interrupt::steal() }.enable(); 137 unsafe { T::Interrupt::enable() };
138 138
139 Self { 139 Self {
140 _peri: peri, 140 _peri: peri,
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs
index 6533509eb..75d8af3dd 100644
--- a/embassy-stm32/src/lib.rs
+++ b/embassy-stm32/src/lib.rs
@@ -75,7 +75,7 @@ pub(crate) mod _generated {
75pub mod interrupt { 75pub mod interrupt {
76 //! Interrupt definitions and macros to bind them. 76 //! Interrupt definitions and macros to bind them.
77 pub use cortex_m::interrupt::{CriticalSection, Mutex}; 77 pub use cortex_m::interrupt::{CriticalSection, Mutex};
78 pub use embassy_cortex_m::interrupt::{Binding, Handler, Interrupt, InterruptExt, Priority}; 78 pub use embassy_cortex_m::interrupt::{Binding, Handler, Interrupt, Priority};
79 79
80 pub use crate::_generated::interrupt::*; 80 pub use crate::_generated::interrupt::*;
81 81
diff --git a/embassy-stm32/src/sdmmc/mod.rs b/embassy-stm32/src/sdmmc/mod.rs
index be03a1bac..3cc17aa68 100644
--- a/embassy-stm32/src/sdmmc/mod.rs
+++ b/embassy-stm32/src/sdmmc/mod.rs
@@ -14,7 +14,7 @@ use sdio_host::{BusWidth, CardCapacity, CardStatus, CurrentState, SDStatus, CID,
14use crate::dma::NoDma; 14use crate::dma::NoDma;
15use crate::gpio::sealed::{AFType, Pin}; 15use crate::gpio::sealed::{AFType, Pin};
16use crate::gpio::{AnyPin, Pull, Speed}; 16use crate::gpio::{AnyPin, Pull, Speed};
17use crate::interrupt::{Interrupt, InterruptExt}; 17use crate::interrupt::Interrupt;
18use crate::pac::sdmmc::Sdmmc as RegBlock; 18use crate::pac::sdmmc::Sdmmc as RegBlock;
19use crate::rcc::RccPeripheral; 19use crate::rcc::RccPeripheral;
20use crate::time::Hertz; 20use crate::time::Hertz;
@@ -447,8 +447,8 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
447 T::enable(); 447 T::enable();
448 T::reset(); 448 T::reset();
449 449
450 unsafe { T::Interrupt::steal() }.unpend(); 450 T::Interrupt::unpend();
451 unsafe { T::Interrupt::steal() }.enable(); 451 unsafe { T::Interrupt::enable() };
452 452
453 let regs = T::regs(); 453 let regs = T::regs();
454 unsafe { 454 unsafe {
@@ -1288,7 +1288,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
1288 1288
1289impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Drop for Sdmmc<'d, T, Dma> { 1289impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Drop for Sdmmc<'d, T, Dma> {
1290 fn drop(&mut self) { 1290 fn drop(&mut self) {
1291 unsafe { T::Interrupt::steal() }.disable(); 1291 T::Interrupt::disable();
1292 unsafe { Self::on_drop() }; 1292 unsafe { Self::on_drop() };
1293 1293
1294 critical_section::with(|_| unsafe { 1294 critical_section::with(|_| unsafe {
diff --git a/embassy-stm32/src/time_driver.rs b/embassy-stm32/src/time_driver.rs
index 2236fde28..bab700993 100644
--- a/embassy-stm32/src/time_driver.rs
+++ b/embassy-stm32/src/time_driver.rs
@@ -11,7 +11,7 @@ use embassy_time::driver::{AlarmHandle, Driver};
11use embassy_time::TICK_HZ; 11use embassy_time::TICK_HZ;
12use stm32_metapac::timer::regs; 12use stm32_metapac::timer::regs;
13 13
14use crate::interrupt::InterruptExt; 14use crate::interrupt::Interrupt;
15use crate::pac::timer::vals; 15use crate::pac::timer::vals;
16use crate::rcc::sealed::RccPeripheral; 16use crate::rcc::sealed::RccPeripheral;
17use crate::timer::sealed::{Basic16bitInstance as BasicInstance, GeneralPurpose16bitInstance as Instance}; 17use crate::timer::sealed::{Basic16bitInstance as BasicInstance, GeneralPurpose16bitInstance as Instance};
@@ -177,9 +177,8 @@ impl RtcDriver {
177 w.set_ccie(0, true); 177 w.set_ccie(0, true);
178 }); 178 });
179 179
180 let irq: <T as BasicInstance>::Interrupt = core::mem::transmute(()); 180 <T as BasicInstance>::Interrupt::unpend();
181 irq.unpend(); 181 <T as BasicInstance>::Interrupt::enable();
182 irq.enable();
183 182
184 r.cr1().modify(|w| w.set_cen(true)); 183 r.cr1().modify(|w| w.set_cen(true));
185 }) 184 })
diff --git a/embassy-stm32/src/tl_mbox/mod.rs b/embassy-stm32/src/tl_mbox/mod.rs
index 616f7dc56..efbbf2d1d 100644
--- a/embassy-stm32/src/tl_mbox/mod.rs
+++ b/embassy-stm32/src/tl_mbox/mod.rs
@@ -2,7 +2,7 @@ use core::mem::MaybeUninit;
2 2
3use atomic_polyfill::{compiler_fence, Ordering}; 3use atomic_polyfill::{compiler_fence, Ordering};
4use bit_field::BitField; 4use bit_field::BitField;
5use embassy_cortex_m::interrupt::{Interrupt, InterruptExt}; 5use embassy_cortex_m::interrupt::Interrupt;
6use embassy_hal_common::{into_ref, Peripheral, PeripheralRef}; 6use embassy_hal_common::{into_ref, Peripheral, PeripheralRef};
7use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex; 7use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
8use embassy_sync::channel::Channel; 8use embassy_sync::channel::Channel;
@@ -379,11 +379,11 @@ impl<'d> TlMbox<'d> {
379 MemoryManager::enable(); 379 MemoryManager::enable();
380 380
381 // enable interrupts 381 // enable interrupts
382 unsafe { crate::interrupt::IPCC_C1_RX::steal() }.unpend(); 382 crate::interrupt::IPCC_C1_RX::unpend();
383 unsafe { crate::interrupt::IPCC_C1_TX::steal() }.unpend(); 383 crate::interrupt::IPCC_C1_TX::unpend();
384 384
385 unsafe { crate::interrupt::IPCC_C1_RX::steal() }.enable(); 385 unsafe { crate::interrupt::IPCC_C1_RX::enable() };
386 unsafe { crate::interrupt::IPCC_C1_TX::steal() }.enable(); 386 unsafe { crate::interrupt::IPCC_C1_TX::enable() };
387 387
388 Self { _ipcc: ipcc } 388 Self { _ipcc: ipcc }
389 } 389 }
diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs
index 9f1da3583..252e945da 100644
--- a/embassy-stm32/src/usart/buffered.rs
+++ b/embassy-stm32/src/usart/buffered.rs
@@ -216,8 +216,8 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> {
216 }); 216 });
217 } 217 }
218 218
219 unsafe { T::Interrupt::steal() }.unpend(); 219 T::Interrupt::unpend();
220 unsafe { T::Interrupt::steal() }.enable(); 220 unsafe { T::Interrupt::enable() };
221 221
222 Self { 222 Self {
223 rx: BufferedUartRx { phantom: PhantomData }, 223 rx: BufferedUartRx { phantom: PhantomData },
@@ -245,7 +245,7 @@ impl<'d, T: BasicInstance> BufferedUartRx<'d, T> {
245 rx_reader.pop_done(len); 245 rx_reader.pop_done(len);
246 246
247 if do_pend { 247 if do_pend {
248 unsafe { T::Interrupt::steal().pend() }; 248 T::Interrupt::pend();
249 } 249 }
250 250
251 return Poll::Ready(Ok(len)); 251 return Poll::Ready(Ok(len));
@@ -271,7 +271,7 @@ impl<'d, T: BasicInstance> BufferedUartRx<'d, T> {
271 rx_reader.pop_done(len); 271 rx_reader.pop_done(len);
272 272
273 if do_pend { 273 if do_pend {
274 unsafe { T::Interrupt::steal().pend() }; 274 T::Interrupt::pend();
275 } 275 }
276 276
277 return Ok(len); 277 return Ok(len);
@@ -301,7 +301,7 @@ impl<'d, T: BasicInstance> BufferedUartRx<'d, T> {
301 let full = state.rx_buf.is_full(); 301 let full = state.rx_buf.is_full();
302 rx_reader.pop_done(amt); 302 rx_reader.pop_done(amt);
303 if full { 303 if full {
304 unsafe { T::Interrupt::steal().pend() }; 304 T::Interrupt::pend();
305 } 305 }
306 } 306 }
307} 307}
@@ -324,7 +324,7 @@ impl<'d, T: BasicInstance> BufferedUartTx<'d, T> {
324 tx_writer.push_done(n); 324 tx_writer.push_done(n);
325 325
326 if empty { 326 if empty {
327 unsafe { T::Interrupt::steal() }.pend(); 327 T::Interrupt::pend();
328 } 328 }
329 329
330 Poll::Ready(Ok(n)) 330 Poll::Ready(Ok(n))
@@ -358,7 +358,7 @@ impl<'d, T: BasicInstance> BufferedUartTx<'d, T> {
358 tx_writer.push_done(n); 358 tx_writer.push_done(n);
359 359
360 if empty { 360 if empty {
361 unsafe { T::Interrupt::steal() }.pend(); 361 T::Interrupt::pend();
362 } 362 }
363 363
364 return Ok(n); 364 return Ok(n);
@@ -385,7 +385,7 @@ impl<'d, T: BasicInstance> Drop for BufferedUartRx<'d, T> {
385 // TX is inactive if the the buffer is not available. 385 // TX is inactive if the the buffer is not available.
386 // We can now unregister the interrupt handler 386 // We can now unregister the interrupt handler
387 if state.tx_buf.len() == 0 { 387 if state.tx_buf.len() == 0 {
388 T::Interrupt::steal().disable(); 388 T::Interrupt::disable();
389 } 389 }
390 } 390 }
391 } 391 }
@@ -400,7 +400,7 @@ impl<'d, T: BasicInstance> Drop for BufferedUartTx<'d, T> {
400 // RX is inactive if the the buffer is not available. 400 // RX is inactive if the the buffer is not available.
401 // We can now unregister the interrupt handler 401 // We can now unregister the interrupt handler
402 if state.rx_buf.len() == 0 { 402 if state.rx_buf.len() == 0 {
403 T::Interrupt::steal().disable(); 403 T::Interrupt::disable();
404 } 404 }
405 } 405 }
406 } 406 }
diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs
index 05ccb8749..ef1080153 100644
--- a/embassy-stm32/src/usart/mod.rs
+++ b/embassy-stm32/src/usart/mod.rs
@@ -5,7 +5,7 @@ use core::marker::PhantomData;
5use core::sync::atomic::{compiler_fence, Ordering}; 5use core::sync::atomic::{compiler_fence, Ordering};
6use core::task::Poll; 6use core::task::Poll;
7 7
8use embassy_cortex_m::interrupt::{Interrupt, InterruptExt}; 8use embassy_cortex_m::interrupt::Interrupt;
9use embassy_hal_common::drop::OnDrop; 9use embassy_hal_common::drop::OnDrop;
10use embassy_hal_common::{into_ref, PeripheralRef}; 10use embassy_hal_common::{into_ref, PeripheralRef};
11use futures::future::{select, Either}; 11use futures::future::{select, Either};
@@ -331,8 +331,8 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
331 331
332 configure(r, &config, T::frequency(), T::KIND, true, false); 332 configure(r, &config, T::frequency(), T::KIND, true, false);
333 333
334 unsafe { T::Interrupt::steal() }.unpend(); 334 T::Interrupt::unpend();
335 unsafe { T::Interrupt::steal() }.enable(); 335 unsafe { T::Interrupt::enable() };
336 336
337 // create state once! 337 // create state once!
338 let _s = T::state(); 338 let _s = T::state();
@@ -732,8 +732,8 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
732 732
733 configure(r, &config, T::frequency(), T::KIND, true, true); 733 configure(r, &config, T::frequency(), T::KIND, true, true);
734 734
735 unsafe { T::Interrupt::steal() }.unpend(); 735 T::Interrupt::unpend();
736 unsafe { T::Interrupt::steal() }.enable(); 736 unsafe { T::Interrupt::enable() };
737 737
738 // create state once! 738 // create state once!
739 let _s = T::state(); 739 let _s = T::state();
diff --git a/embassy-stm32/src/usb/usb.rs b/embassy-stm32/src/usb/usb.rs
index a9ff284ae..134107978 100644
--- a/embassy-stm32/src/usb/usb.rs
+++ b/embassy-stm32/src/usb/usb.rs
@@ -14,7 +14,7 @@ use embassy_usb_driver::{
14 14
15use super::{DmPin, DpPin, Instance}; 15use super::{DmPin, DpPin, Instance};
16use crate::gpio::sealed::AFType; 16use crate::gpio::sealed::AFType;
17use crate::interrupt::{Interrupt, InterruptExt}; 17use crate::interrupt::Interrupt;
18use crate::pac::usb::regs; 18use crate::pac::usb::regs;
19use crate::pac::usb::vals::{EpType, Stat}; 19use crate::pac::usb::vals::{EpType, Stat};
20use crate::pac::USBRAM; 20use crate::pac::USBRAM;
@@ -260,8 +260,8 @@ impl<'d, T: Instance> Driver<'d, T> {
260 dm: impl Peripheral<P = impl DmPin<T>> + 'd, 260 dm: impl Peripheral<P = impl DmPin<T>> + 'd,
261 ) -> Self { 261 ) -> Self {
262 into_ref!(dp, dm); 262 into_ref!(dp, dm);
263 unsafe { T::Interrupt::steal() }.unpend(); 263 T::Interrupt::unpend();
264 unsafe { T::Interrupt::steal() }.enable(); 264 unsafe { T::Interrupt::enable() };
265 265
266 let regs = T::regs(); 266 let regs = T::regs();
267 267
diff --git a/embassy-stm32/src/usb_otg/usb.rs b/embassy-stm32/src/usb_otg/usb.rs
index 921a73c8b..c7f19f6e9 100644
--- a/embassy-stm32/src/usb_otg/usb.rs
+++ b/embassy-stm32/src/usb_otg/usb.rs
@@ -3,7 +3,7 @@ use core::marker::PhantomData;
3use core::task::Poll; 3use core::task::Poll;
4 4
5use atomic_polyfill::{AtomicBool, AtomicU16, Ordering}; 5use atomic_polyfill::{AtomicBool, AtomicU16, Ordering};
6use embassy_cortex_m::interrupt::InterruptExt; 6use embassy_cortex_m::interrupt::Interrupt;
7use embassy_hal_common::{into_ref, Peripheral}; 7use embassy_hal_common::{into_ref, Peripheral};
8use embassy_sync::waitqueue::AtomicWaker; 8use embassy_sync::waitqueue::AtomicWaker;
9use embassy_usb_driver::{ 9use embassy_usb_driver::{
@@ -629,7 +629,7 @@ impl<'d, T: Instance> Bus<'d, T> {
629 } 629 }
630 630
631 fn disable(&mut self) { 631 fn disable(&mut self) {
632 unsafe { T::Interrupt::steal() }.disable(); 632 T::Interrupt::disable();
633 633
634 <T as RccPeripheral>::disable(); 634 <T as RccPeripheral>::disable();
635 635
@@ -902,8 +902,8 @@ impl<'d, T: Instance> embassy_usb_driver::Bus for Bus<'d, T> {
902 <T as RccPeripheral>::enable(); 902 <T as RccPeripheral>::enable();
903 <T as RccPeripheral>::reset(); 903 <T as RccPeripheral>::reset();
904 904
905 T::Interrupt::steal().unpend(); 905 T::Interrupt::unpend();
906 T::Interrupt::steal().enable(); 906 T::Interrupt::enable();
907 907
908 let r = T::regs(); 908 let r = T::regs();
909 let core_id = r.cid().read().0; 909 let core_id = r.cid().read().0;
diff --git a/examples/boot/bootloader/rp/Cargo.toml b/examples/boot/bootloader/rp/Cargo.toml
index 8d60f18be..c1dc99eec 100644
--- a/examples/boot/bootloader/rp/Cargo.toml
+++ b/examples/boot/bootloader/rp/Cargo.toml
@@ -30,3 +30,4 @@ debug = ["defmt-rtt", "defmt"]
30 30
31[profile.release] 31[profile.release]
32debug = true 32debug = true
33opt-level = 's'
diff --git a/examples/std/src/bin/tcp_accept.rs b/examples/std/src/bin/tcp_accept.rs
index d24e218dc..01695baea 100644
--- a/examples/std/src/bin/tcp_accept.rs
+++ b/examples/std/src/bin/tcp_accept.rs
@@ -108,7 +108,7 @@ async fn main_task(spawner: Spawner) {
108 info!("Closing the connection"); 108 info!("Closing the connection");
109 socket.abort(); 109 socket.abort();
110 info!("Flushing the RST out..."); 110 info!("Flushing the RST out...");
111 socket.flush().await; 111 _ = socket.flush().await;
112 info!("Finished with the socket"); 112 info!("Finished with the socket");
113 } 113 }
114} 114}
generated by cgit (git 2.34.1) at 2026-04-05 22:04:29 +0000