aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--embassy-net-adin1110/src/lib.rs11
-rw-r--r--embassy-net-adin1110/src/mdio.rs175
-rw-r--r--embassy-net-adin1110/src/phy.rs1
3 files changed, 98 insertions, 89 deletions
diff --git a/embassy-net-adin1110/src/lib.rs b/embassy-net-adin1110/src/lib.rs
index e0af7bde9..53f361284 100644
--- a/embassy-net-adin1110/src/lib.rs
+++ b/embassy-net-adin1110/src/lib.rs
@@ -32,6 +32,7 @@ pub use regs::{Config0, Config2, SpiRegisters as sr, Status0, Status1};
32use crate::fmt::Bytes; 32use crate::fmt::Bytes;
33use crate::regs::{LedCntrl, LedFunc, LedPol, LedPolarity, SpiHeader}; 33use crate::regs::{LedCntrl, LedFunc, LedPol, LedPolarity, SpiHeader};
34 34
35/// ADIN1110 intern PHY ID
35pub const PHYID: u32 = 0x0283_BC91; 36pub const PHYID: u32 = 0x0283_BC91;
36 37
37/// Error values ADIN1110 38/// Error values ADIN1110
@@ -53,7 +54,9 @@ pub enum AdinError<E> {
53 MDIO_ACC_TIMEOUT, 54 MDIO_ACC_TIMEOUT,
54} 55}
55 56
57/// Type alias `Result` type with `AdinError` as error type.
56pub type AEResult<T, SPIError> = core::result::Result<T, AdinError<SPIError>>; 58pub type AEResult<T, SPIError> = core::result::Result<T, AdinError<SPIError>>;
59
57/// Internet PHY address 60/// Internet PHY address
58pub const MDIO_PHY_ADDR: u8 = 0x01; 61pub const MDIO_PHY_ADDR: u8 = 0x01;
59 62
@@ -104,6 +107,7 @@ impl<const N_RX: usize, const N_TX: usize> State<N_RX, N_TX> {
104 } 107 }
105} 108}
106 109
110/// ADIN1110 embassy-net driver
107#[derive(Debug)] 111#[derive(Debug)]
108pub struct ADIN1110<SPI> { 112pub struct ADIN1110<SPI> {
109 /// SPI bus 113 /// SPI bus
@@ -116,6 +120,7 @@ pub struct ADIN1110<SPI> {
116} 120}
117 121
118impl<SPI: SpiDevice> ADIN1110<SPI> { 122impl<SPI: SpiDevice> ADIN1110<SPI> {
123 /// Create a new ADIN1110 instance.
119 pub fn new(spi: SPI, spi_crc: bool, append_fcs_on_tx: bool) -> Self { 124 pub fn new(spi: SPI, spi_crc: bool, append_fcs_on_tx: bool) -> Self {
120 Self { 125 Self {
121 spi, 126 spi,
@@ -124,6 +129,7 @@ impl<SPI: SpiDevice> ADIN1110<SPI> {
124 } 129 }
125 } 130 }
126 131
132 /// Read a SPI register
127 pub async fn read_reg(&mut self, reg: sr) -> AEResult<u32, SPI::Error> { 133 pub async fn read_reg(&mut self, reg: sr) -> AEResult<u32, SPI::Error> {
128 let mut tx_buf = Vec::<u8, 16>::new(); 134 let mut tx_buf = Vec::<u8, 16>::new();
129 135
@@ -162,6 +168,7 @@ impl<SPI: SpiDevice> ADIN1110<SPI> {
162 Ok(value) 168 Ok(value)
163 } 169 }
164 170
171 /// Write a SPI register
165 pub async fn write_reg(&mut self, reg: sr, value: u32) -> AEResult<(), SPI::Error> { 172 pub async fn write_reg(&mut self, reg: sr, value: u32) -> AEResult<(), SPI::Error> {
166 let mut tx_buf = Vec::<u8, 16>::new(); 173 let mut tx_buf = Vec::<u8, 16>::new();
167 174
@@ -427,9 +434,9 @@ impl<SPI: SpiDevice> mdio::MdioBus for ADIN1110<SPI> {
427 } 434 }
428} 435}
429 436
430/// Background runner for the ADIN110. 437/// Background runner for the ADIN1110.
431/// 438///
432/// You must call `.run()` in a background task for the ADIN1100 to operate. 439/// You must call `.run()` in a background task for the ADIN1110 to operate.
433pub struct Runner<'d, SPI, INT, RST> { 440pub struct Runner<'d, SPI, INT, RST> {
434 mac: ADIN1110<SPI>, 441 mac: ADIN1110<SPI>,
435 ch: ch::Runner<'d, MTU>, 442 ch: ch::Runner<'d, MTU>,
diff --git a/embassy-net-adin1110/src/mdio.rs b/embassy-net-adin1110/src/mdio.rs
index 68477006a..1ae5f0043 100644
--- a/embassy-net-adin1110/src/mdio.rs
+++ b/embassy-net-adin1110/src/mdio.rs
@@ -32,11 +32,12 @@ enum Reg13Op {
32 PostReadIncAddr = 0b10 << 14, 32 PostReadIncAddr = 0b10 << 14,
33 Read = 0b11 << 14, 33 Read = 0b11 << 14,
34} 34}
35
35/// `MdioBus` trait 36/// `MdioBus` trait
36/// Driver needs to implement the Clause 22 37/// Driver needs to implement the Clause 22
37/// Optional Clause 45 is the device supports this. 38/// Optional Clause 45 is the device supports this.
38/// 39///
39/// Claus 45 methodes are bases on <https://www.ieee802.org/3/efm/public/nov02/oam/pannell_oam_1_1102.pdf> 40/// Clause 45 methodes are bases on <https://www.ieee802.org/3/efm/public/nov02/oam/pannell_oam_1_1102.pdf>
40pub trait MdioBus { 41pub trait MdioBus {
41 type Error; 42 type Error;
42 43
@@ -87,89 +88,89 @@ pub trait MdioBus {
87 } 88 }
88} 89}
89 90
90// #[cfg(test)] 91#[cfg(test)]
91// mod tests { 92mod tests {
92// use core::convert::Infallible; 93 use core::convert::Infallible;
93 94
94// use super::{MdioBus, PhyAddr, RegC22, RegVal}; 95 use super::{MdioBus, PhyAddr, RegC22, RegVal};
95 96
96// #[derive(Debug, PartialEq, Eq)] 97 #[derive(Debug, PartialEq, Eq)]
97// enum A { 98 enum A {
98// Read(PhyAddr, RegC22), 99 Read(PhyAddr, RegC22),
99// Write(PhyAddr, RegC22, RegVal), 100 Write(PhyAddr, RegC22, RegVal),
100// } 101 }
101 102
102// struct MockMdioBus(Vec<A>); 103 struct MockMdioBus(Vec<A>);
103 104
104// impl MockMdioBus { 105 impl MockMdioBus {
105// pub fn clear(&mut self) { 106 pub fn clear(&mut self) {
106// self.0.clear(); 107 self.0.clear();
107// } 108 }
108// } 109 }
109 110
110// impl MdioBus for MockMdioBus { 111 impl MdioBus for MockMdioBus {
111// type Error = Infallible; 112 type Error = Infallible;
112 113
113// fn write_cl22( 114 async fn write_cl22(
114// &mut self, 115 &mut self,
115// phy_id: super::PhyAddr, 116 phy_id: super::PhyAddr,
116// reg: super::RegC22, 117 reg: super::RegC22,
117// reg_val: super::RegVal, 118 reg_val: super::RegVal,
118// ) -> Result<(), Self::Error> { 119 ) -> Result<(), Self::Error> {
119// self.0.push(A::Write(phy_id, reg, reg_val)); 120 self.0.push(A::Write(phy_id, reg, reg_val));
120// Ok(()) 121 Ok(())
121// } 122 }
122 123
123// fn read_cl22( 124 async fn read_cl22(
124// &mut self, 125 &mut self,
125// phy_id: super::PhyAddr, 126 phy_id: super::PhyAddr,
126// reg: super::RegC22, 127 reg: super::RegC22,
127// ) -> Result<super::RegVal, Self::Error> { 128 ) -> Result<super::RegVal, Self::Error> {
128// self.0.push(A::Read(phy_id, reg)); 129 self.0.push(A::Read(phy_id, reg));
129// Ok(0) 130 Ok(0)
130// } 131 }
131// } 132 }
132 133
133// #[test] 134 #[futures_test::test]
134// fn read_test() { 135 async fn read_test() {
135// let mut mdiobus = MockMdioBus(Vec::with_capacity(20)); 136 let mut mdiobus = MockMdioBus(Vec::with_capacity(20));
136 137
137// mdiobus.clear(); 138 mdiobus.clear();
138// mdiobus.read_cl22(0x01, 0x00).unwrap(); 139 mdiobus.read_cl22(0x01, 0x00).await.unwrap();
139// assert_eq!(mdiobus.0, vec![A::Read(0x01, 0x00)]); 140 assert_eq!(mdiobus.0, vec![A::Read(0x01, 0x00)]);
140 141
141// mdiobus.clear(); 142 mdiobus.clear();
142// mdiobus.read_cl45(0x01, (0xBB, 0x1234)).unwrap(); 143 mdiobus.read_cl45(0x01, (0xBB, 0x1234)).await.unwrap();
143// assert_eq!( 144 assert_eq!(
144// mdiobus.0, 145 mdiobus.0,
145// vec![ 146 vec![
146// #[allow(clippy::identity_op)] 147 #[allow(clippy::identity_op)]
147// A::Write(0x01, 13, (0b00 << 14) | 27), 148 A::Write(0x01, 13, (0b00 << 14) | 27),
148// A::Write(0x01, 14, 0x1234), 149 A::Write(0x01, 14, 0x1234),
149// A::Write(0x01, 13, (0b11 << 14) | 27), 150 A::Write(0x01, 13, (0b11 << 14) | 27),
150// A::Read(0x01, 14) 151 A::Read(0x01, 14)
151// ] 152 ]
152// ); 153 );
153// } 154 }
154 155
155// #[test] 156 #[futures_test::test]
156// fn write_test() { 157 async fn write_test() {
157// let mut mdiobus = MockMdioBus(Vec::with_capacity(20)); 158 let mut mdiobus = MockMdioBus(Vec::with_capacity(20));
158 159
159// mdiobus.clear(); 160 mdiobus.clear();
160// mdiobus.write_cl22(0x01, 0x00, 0xABCD).unwrap(); 161 mdiobus.write_cl22(0x01, 0x00, 0xABCD).await.unwrap();
161// assert_eq!(mdiobus.0, vec![A::Write(0x01, 0x00, 0xABCD)]); 162 assert_eq!(mdiobus.0, vec![A::Write(0x01, 0x00, 0xABCD)]);
162 163
163// mdiobus.clear(); 164 mdiobus.clear();
164// mdiobus.write_cl45(0x01, (0xBB, 0x1234), 0xABCD).unwrap(); 165 mdiobus.write_cl45(0x01, (0xBB, 0x1234), 0xABCD).await.unwrap();
165// assert_eq!( 166 assert_eq!(
166// mdiobus.0, 167 mdiobus.0,
167// vec![ 168 vec![
168// A::Write(0x01, 13, 27), 169 A::Write(0x01, 13, 27),
169// A::Write(0x01, 14, 0x1234), 170 A::Write(0x01, 14, 0x1234),
170// A::Write(0x01, 13, (0b01 << 14) | 27), 171 A::Write(0x01, 13, (0b01 << 14) | 27),
171// A::Write(0x01, 14, 0xABCD) 172 A::Write(0x01, 14, 0xABCD)
172// ] 173 ]
173// ); 174 );
174// } 175 }
175// } 176}
diff --git a/embassy-net-adin1110/src/phy.rs b/embassy-net-adin1110/src/phy.rs
index 176ad019b..d54d843d2 100644
--- a/embassy-net-adin1110/src/phy.rs
+++ b/embassy-net-adin1110/src/phy.rs
@@ -111,6 +111,7 @@ pub mod RegsC45 {
111 } 111 }
112} 112}
113 113
114/// 10-BASE-T1x PHY functions.
114pub struct Phy10BaseT1x(u8); 115pub struct Phy10BaseT1x(u8);
115 116
116impl Default for Phy10BaseT1x { 117impl Default for Phy10BaseT1x {
generated by cgit (git 2.34.1) at 2026-04-05 23:44:27 +0000