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-rw-r--r--embassy-stm32/src/dma/dma.rs8
1 files changed, 2 insertions, 6 deletions
diff --git a/embassy-stm32/src/dma/dma.rs b/embassy-stm32/src/dma/dma.rs
index fec60f708..8966214ec 100644
--- a/embassy-stm32/src/dma/dma.rs
+++ b/embassy-stm32/src/dma/dma.rs
@@ -411,12 +411,8 @@ mod low_level_api {
411 } 411 }
412 412
413 if isr.tcif(channel_num % 4) && cr.read().tcie() { 413 if isr.tcif(channel_num % 4) && cr.read().tcie() {
414 if cr.read().dbm() == vals::Dbm::DISABLED { 414 /* acknowledge transfer complete interrupt */
415 cr.write(|_| ()); // Disable channel with the default value. 415 dma.ifcr(channel_num / 4).write(|w| w.set_tcif(channel_num % 4, true));
416 } else {
417 // for double buffered mode, clear TCIF flag but do not stop the transfer
418 dma.ifcr(channel_num / 4).write(|w| w.set_tcif(channel_num % 4, true));
419 }
420 STATE.channels[state_index].waker.wake(); 416 STATE.channels[state_index].waker.wake();
421 } 417 }
422 } 418 }