aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--.github/workflows/rust.yml9
-rw-r--r--embassy-net/src/stack.rs1
-rw-r--r--embassy-nrf/Cargo.toml22
-rw-r--r--embassy-nrf/src/chips/nrf5340_app.rs506
-rw-r--r--embassy-nrf/src/chips/nrf5340_net.rs353
-rw-r--r--embassy-nrf/src/chips/nrf9160.rs32
-rw-r--r--embassy-nrf/src/gpio.rs23
-rw-r--r--embassy-nrf/src/gpiote.rs81
-rw-r--r--embassy-nrf/src/lib.rs27
-rw-r--r--embassy-nrf/src/ppi/dppi.rs22
-rw-r--r--embassy-nrf/src/ppi/mod.rs20
-rw-r--r--embassy-nrf/src/ppi/ppi.rs28
12 files changed, 1038 insertions, 86 deletions
diff --git a/.github/workflows/rust.yml b/.github/workflows/rust.yml
index 759435d8b..de500c3a7 100644
--- a/.github/workflows/rust.yml
+++ b/.github/workflows/rust.yml
@@ -61,6 +61,15 @@ jobs:
61 target: thumbv8m.main-none-eabihf 61 target: thumbv8m.main-none-eabihf
62 features: nrf9160-ns 62 features: nrf9160-ns
63 - package: embassy-nrf 63 - package: embassy-nrf
64 target: thumbv8m.main-none-eabihf
65 features: nrf5340-app-s
66 - package: embassy-nrf
67 target: thumbv8m.main-none-eabihf
68 features: nrf5340-app-ns
69 - package: embassy-nrf
70 target: thumbv8m.main-none-eabihf
71 features: nrf5340-net
72 - package: embassy-nrf
64 target: thumbv7em-none-eabi 73 target: thumbv7em-none-eabi
65 features: nrf52840 74 features: nrf52840
66 - package: embassy-nrf 75 - package: embassy-nrf
diff --git a/embassy-net/src/stack.rs b/embassy-net/src/stack.rs
index 42defdcaf..4faf94953 100644
--- a/embassy-net/src/stack.rs
+++ b/embassy-net/src/stack.rs
@@ -75,6 +75,7 @@ impl Stack {
75 f(stack) 75 f(stack)
76 } 76 }
77 77
78 #[allow(clippy::absurd_extreme_comparisons)]
78 pub fn get_local_port(&mut self) -> u16 { 79 pub fn get_local_port(&mut self) -> u16 {
79 let res = self.next_local_port; 80 let res = self.next_local_port;
80 self.next_local_port = if res >= LOCAL_PORT_MAX { 81 self.next_local_port = if res >= LOCAL_PORT_MAX {
diff --git a/embassy-nrf/Cargo.toml b/embassy-nrf/Cargo.toml
index 17c3e29d5..3ce174372 100644
--- a/embassy-nrf/Cargo.toml
+++ b/embassy-nrf/Cargo.toml
@@ -23,21 +23,30 @@ nrf52810 = ["nrf52810-pac", "_ppi"]
23nrf52811 = ["nrf52811-pac", "_ppi"] 23nrf52811 = ["nrf52811-pac", "_ppi"]
24nrf52820 = ["nrf52820-pac", "_ppi"] 24nrf52820 = ["nrf52820-pac", "_ppi"]
25nrf52832 = ["nrf52832-pac", "_ppi"] 25nrf52832 = ["nrf52832-pac", "_ppi"]
26nrf52833 = ["nrf52833-pac", "_ppi"] 26nrf52833 = ["nrf52833-pac", "_ppi", "_gpio-p1"]
27nrf52840 = ["nrf52840-pac", "_ppi"] 27nrf52840 = ["nrf52840-pac", "_ppi", "_gpio-p1"]
28nrf5340-app-s = ["_nrf5340-app"]
29nrf5340-app-ns = ["_nrf5340-app"]
30nrf5340-net = ["_nrf5340-net"]
28nrf9160-s = ["_nrf9160"] 31nrf9160-s = ["_nrf9160"]
29nrf9160-ns = ["_nrf9160"] 32nrf9160-ns = ["_nrf9160"]
30 33
34gpiote = []
35time-driver-rtc1 = ["_time-driver"]
36
31# Features starting with `_` are for internal use only. They're not intended 37# Features starting with `_` are for internal use only. They're not intended
32# to be enabled by other crates, and are not covered by semver guarantees. 38# to be enabled by other crates, and are not covered by semver guarantees.
33 39
40_nrf5340-app = ["_nrf5340", "nrf5340-app-pac"]
41_nrf5340-net = ["_nrf5340", "nrf5340-net-pac"]
42_nrf5340 = ["_gpio-p1", "_dppi"]
34_nrf9160 = ["nrf9160-pac", "_dppi"] 43_nrf9160 = ["nrf9160-pac", "_dppi"]
44
35_time-driver = ["embassy/time-tick-32768hz"] 45_time-driver = ["embassy/time-tick-32768hz"]
46
36_ppi = [] 47_ppi = []
37_dppi = [] 48_dppi = []
38 49_gpio-p1 = []
39gpiote = []
40time-driver-rtc1 = ["_time-driver"]
41 50
42[dependencies] 51[dependencies]
43embassy = { version = "0.1.0", path = "../embassy" } 52embassy = { version = "0.1.0", path = "../embassy" }
@@ -55,6 +64,7 @@ critical-section = "0.2.5"
55rand_core = "0.6.3" 64rand_core = "0.6.3"
56fixed = "1.10.0" 65fixed = "1.10.0"
57embedded-storage = "0.2.0" 66embedded-storage = "0.2.0"
67cfg-if = "1.0.0"
58 68
59nrf52805-pac = { version = "0.10.1", optional = true, features = [ "rt" ] } 69nrf52805-pac = { version = "0.10.1", optional = true, features = [ "rt" ] }
60nrf52810-pac = { version = "0.10.1", optional = true, features = [ "rt" ] } 70nrf52810-pac = { version = "0.10.1", optional = true, features = [ "rt" ] }
@@ -63,4 +73,6 @@ nrf52820-pac = { version = "0.10.1", optional = true, features = [ "rt" ] }
63nrf52832-pac = { version = "0.10.1", optional = true, features = [ "rt" ] } 73nrf52832-pac = { version = "0.10.1", optional = true, features = [ "rt" ] }
64nrf52833-pac = { version = "0.10.1", optional = true, features = [ "rt" ] } 74nrf52833-pac = { version = "0.10.1", optional = true, features = [ "rt" ] }
65nrf52840-pac = { version = "0.10.1", optional = true, features = [ "rt" ] } 75nrf52840-pac = { version = "0.10.1", optional = true, features = [ "rt" ] }
76nrf5340-app-pac = { version = "0.10.1", optional = true, features = [ "rt" ] }
77nrf5340-net-pac = { version = "0.10.1", optional = true, features = [ "rt" ] }
66nrf9160-pac = { version = "0.10.1", optional = true, features = [ "rt" ] } 78nrf9160-pac = { version = "0.10.1", optional = true, features = [ "rt" ] }
diff --git a/embassy-nrf/src/chips/nrf5340_app.rs b/embassy-nrf/src/chips/nrf5340_app.rs
new file mode 100644
index 000000000..ca761893f
--- /dev/null
+++ b/embassy-nrf/src/chips/nrf5340_app.rs
@@ -0,0 +1,506 @@
1#[allow(unused_imports)]
2#[rustfmt::skip]
3pub mod pac {
4 // The nRF5340 has a secure and non-secure (NS) mode.
5 // To avoid cfg spam, we remove _ns or _s suffixes here.
6
7 pub use nrf5340_app_pac::{
8 interrupt,
9 Interrupt,
10 Peripherals,
11
12 cache_s as cache,
13 cachedata_s as cachedata,
14 cacheinfo_s as cacheinfo,
15 clock_ns as clock,
16 comp_ns as comp,
17 cryptocell_s as cryptocell,
18 cti_s as cti,
19 ctrlap_ns as ctrlap,
20 dcnf_ns as dcnf,
21 dppic_ns as dppic,
22 egu0_ns as egu0,
23 ficr_s as ficr,
24 fpu_ns as fpu,
25 gpiote0_s as gpiote,
26 i2s0_ns as i2s0,
27 ipc_ns as ipc,
28 kmu_ns as kmu,
29 lpcomp_ns as lpcomp,
30 mutex_ns as mutex,
31 nfct_ns as nfct,
32 nvmc_ns as nvmc,
33 oscillators_ns as oscillators,
34 p0_ns as p0,
35 pdm0_ns as pdm0,
36 power_ns as power,
37 pwm0_ns as pwm0,
38 qdec0_ns as qdec0,
39 qspi_ns as qspi,
40 regulators_ns as regulators,
41 reset_ns as reset,
42 rtc0_ns as rtc0,
43 saadc_ns as saadc,
44 spim0_ns as spim0,
45 spis0_ns as spis0,
46 spu_s as spu,
47 tad_s as tad,
48 timer0_ns as timer0,
49 twim0_ns as twim0,
50 twis0_ns as twis0,
51 uarte0_ns as uarte0,
52 uicr_s as uicr,
53 usbd_ns as usbd,
54 usbregulator_ns as usbregulator,
55 vmc_ns as vmc,
56 wdt0_ns as wdt0,
57 };
58
59 #[cfg(feature = "nrf5340-app-ns")]
60 pub use nrf5340_app_pac::{
61 CLOCK_NS as CLOCK,
62 COMP_NS as COMP,
63 CTRLAP_NS as CTRLAP,
64 DCNF_NS as DCNF,
65 DPPIC_NS as DPPIC,
66 EGU0_NS as EGU0,
67 EGU1_NS as EGU1,
68 EGU2_NS as EGU2,
69 EGU3_NS as EGU3,
70 EGU4_NS as EGU4,
71 EGU5_NS as EGU5,
72 FPU_NS as FPU,
73 GPIOTE1_NS as GPIOTE1,
74 I2S0_NS as I2S0,
75 IPC_NS as IPC,
76 KMU_NS as KMU,
77 LPCOMP_NS as LPCOMP,
78 MUTEX_NS as MUTEX,
79 NFCT_NS as NFCT,
80 NVMC_NS as NVMC,
81 OSCILLATORS_NS as OSCILLATORS,
82 P0_NS as P0,
83 P1_NS as P1,
84 PDM0_NS as PDM0,
85 POWER_NS as POWER,
86 PWM0_NS as PWM0,
87 PWM1_NS as PWM1,
88 PWM2_NS as PWM2,
89 PWM3_NS as PWM3,
90 QDEC0_NS as QDEC0,
91 QDEC1_NS as QDEC1,
92 QSPI_NS as QSPI,
93 REGULATORS_NS as REGULATORS,
94 RESET_NS as RESET,
95 RTC0_NS as RTC0,
96 RTC1_NS as RTC1,
97 SAADC_NS as SAADC,
98 SPIM0_NS as SPIM0,
99 SPIM1_NS as SPIM1,
100 SPIM2_NS as SPIM2,
101 SPIM3_NS as SPIM3,
102 SPIM4_NS as SPIM4,
103 SPIS0_NS as SPIS0,
104 SPIS1_NS as SPIS1,
105 SPIS2_NS as SPIS2,
106 SPIS3_NS as SPIS3,
107 TIMER0_NS as TIMER0,
108 TIMER1_NS as TIMER1,
109 TIMER2_NS as TIMER2,
110 TWIM0_NS as TWIM0,
111 TWIM1_NS as TWIM1,
112 TWIM2_NS as TWIM2,
113 TWIM3_NS as TWIM3,
114 TWIS0_NS as TWIS0,
115 TWIS1_NS as TWIS1,
116 TWIS2_NS as TWIS2,
117 TWIS3_NS as TWIS3,
118 UARTE0_NS as UARTE0,
119 UARTE1_NS as UARTE1,
120 UARTE2_NS as UARTE2,
121 UARTE3_NS as UARTE3,
122 USBD_NS as USBD,
123 USBREGULATOR_NS as USBREGULATOR,
124 VMC_NS as VMC,
125 WDT0_NS as WDT0,
126 WDT1_NS as WDT1,
127 };
128
129 #[cfg(feature = "nrf5340-app-s")]
130 pub use nrf5340_app_pac::{
131 CACHEDATA_S as CACHEDATA,
132 CACHEINFO_S as CACHEINFO,
133 CACHE_S as CACHE,
134 CLOCK_S as CLOCK,
135 COMP_S as COMP,
136 CRYPTOCELL_S as CRYPTOCELL,
137 CTI_S as CTI,
138 CTRLAP_S as CTRLAP,
139 DCNF_S as DCNF,
140 DPPIC_S as DPPIC,
141 EGU0_S as EGU0,
142 EGU1_S as EGU1,
143 EGU2_S as EGU2,
144 EGU3_S as EGU3,
145 EGU4_S as EGU4,
146 EGU5_S as EGU5,
147 FICR_S as FICR,
148 FPU_S as FPU,
149 GPIOTE0_S as GPIOTE0,
150 I2S0_S as I2S0,
151 IPC_S as IPC,
152 KMU_S as KMU,
153 LPCOMP_S as LPCOMP,
154 MUTEX_S as MUTEX,
155 NFCT_S as NFCT,
156 NVMC_S as NVMC,
157 OSCILLATORS_S as OSCILLATORS,
158 P0_S as P0,
159 P1_S as P1,
160 PDM0_S as PDM0,
161 POWER_S as POWER,
162 PWM0_S as PWM0,
163 PWM1_S as PWM1,
164 PWM2_S as PWM2,
165 PWM3_S as PWM3,
166 QDEC0_S as QDEC0,
167 QDEC1_S as QDEC1,
168 QSPI_S as QSPI,
169 REGULATORS_S as REGULATORS,
170 RESET_S as RESET,
171 RTC0_S as RTC0,
172 RTC1_S as RTC1,
173 SAADC_S as SAADC,
174 SPIM0_S as SPIM0,
175 SPIM1_S as SPIM1,
176 SPIM2_S as SPIM2,
177 SPIM3_S as SPIM3,
178 SPIM4_S as SPIM4,
179 SPIS0_S as SPIS0,
180 SPIS1_S as SPIS1,
181 SPIS2_S as SPIS2,
182 SPIS3_S as SPIS3,
183 SPU_S as SPU,
184 TAD_S as TAD,
185 TIMER0_S as TIMER0,
186 TIMER1_S as TIMER1,
187 TIMER2_S as TIMER2,
188 TWIM0_S as TWIM0,
189 TWIM1_S as TWIM1,
190 TWIM2_S as TWIM2,
191 TWIM3_S as TWIM3,
192 TWIS0_S as TWIS0,
193 TWIS1_S as TWIS1,
194 TWIS2_S as TWIS2,
195 TWIS3_S as TWIS3,
196 UARTE0_S as UARTE0,
197 UARTE1_S as UARTE1,
198 UARTE2_S as UARTE2,
199 UARTE3_S as UARTE3,
200 UICR_S as UICR,
201 USBD_S as USBD,
202 USBREGULATOR_S as USBREGULATOR,
203 VMC_S as VMC,
204 WDT0_S as WDT0,
205 WDT1_S as WDT1,
206 };
207}
208
209/// The maximum buffer size that the EasyDMA can send/recv in one operation.
210pub const EASY_DMA_SIZE: usize = (1 << 16) - 1;
211pub const FORCE_COPY_BUFFER_SIZE: usize = 1024;
212
213embassy_hal_common::peripherals! {
214 // RTC
215 RTC0,
216 RTC1,
217
218 // WDT
219 WDT,
220
221 // UARTE, TWI & SPI
222 UARTETWISPI0,
223 UARTETWISPI1,
224 UARTETWISPI2,
225 UARTETWISPI3,
226
227 // SAADC
228 SAADC,
229
230 // PWM
231 PWM0,
232 PWM1,
233 PWM2,
234 PWM3,
235
236 // TIMER
237 TIMER0,
238 TIMER1,
239 TIMER2,
240
241 // GPIOTE
242 GPIOTE_CH0,
243 GPIOTE_CH1,
244 GPIOTE_CH2,
245 GPIOTE_CH3,
246 GPIOTE_CH4,
247 GPIOTE_CH5,
248 GPIOTE_CH6,
249 GPIOTE_CH7,
250
251 // PPI
252 PPI_CH0,
253 PPI_CH1,
254 PPI_CH2,
255 PPI_CH3,
256 PPI_CH4,
257 PPI_CH5,
258 PPI_CH6,
259 PPI_CH7,
260 PPI_CH8,
261 PPI_CH9,
262 PPI_CH10,
263 PPI_CH11,
264 PPI_CH12,
265 PPI_CH13,
266 PPI_CH14,
267 PPI_CH15,
268 PPI_CH16,
269 PPI_CH17,
270 PPI_CH18,
271 PPI_CH19,
272 PPI_CH20,
273 PPI_CH21,
274 PPI_CH22,
275 PPI_CH23,
276 PPI_CH24,
277 PPI_CH25,
278 PPI_CH26,
279 PPI_CH27,
280 PPI_CH28,
281 PPI_CH29,
282 PPI_CH30,
283 PPI_CH31,
284
285 PPI_GROUP0,
286 PPI_GROUP1,
287 PPI_GROUP2,
288 PPI_GROUP3,
289 PPI_GROUP4,
290 PPI_GROUP5,
291
292 // GPIO port 0
293 P0_00,
294 P0_01,
295 P0_02,
296 P0_03,
297 P0_04,
298 P0_05,
299 P0_06,
300 P0_07,
301 P0_08,
302 P0_09,
303 P0_10,
304 P0_11,
305 P0_12,
306 P0_13,
307 P0_14,
308 P0_15,
309 P0_16,
310 P0_17,
311 P0_18,
312 P0_19,
313 P0_20,
314 P0_21,
315 P0_22,
316 P0_23,
317 P0_24,
318 P0_25,
319 P0_26,
320 P0_27,
321 P0_28,
322 P0_29,
323 P0_30,
324 P0_31,
325
326 // GPIO port 1
327 P1_00,
328 P1_01,
329 P1_02,
330 P1_03,
331 P1_04,
332 P1_05,
333 P1_06,
334 P1_07,
335 P1_08,
336 P1_09,
337 P1_10,
338 P1_11,
339 P1_12,
340 P1_13,
341 P1_14,
342 P1_15,
343}
344
345impl_uarte!(UARTETWISPI0, UARTE0, SERIAL0);
346impl_uarte!(UARTETWISPI1, UARTE1, SERIAL1);
347impl_uarte!(UARTETWISPI2, UARTE2, SERIAL2);
348impl_uarte!(UARTETWISPI3, UARTE3, SERIAL3);
349
350impl_spim!(UARTETWISPI0, SPIM0, SERIAL0);
351impl_spim!(UARTETWISPI1, SPIM1, SERIAL1);
352impl_spim!(UARTETWISPI2, SPIM2, SERIAL2);
353impl_spim!(UARTETWISPI3, SPIM3, SERIAL3);
354
355impl_twim!(UARTETWISPI0, TWIM0, SERIAL0);
356impl_twim!(UARTETWISPI1, TWIM1, SERIAL1);
357impl_twim!(UARTETWISPI2, TWIM2, SERIAL2);
358impl_twim!(UARTETWISPI3, TWIM3, SERIAL3);
359
360impl_pwm!(PWM0, PWM0, PWM0);
361impl_pwm!(PWM1, PWM1, PWM1);
362impl_pwm!(PWM2, PWM2, PWM2);
363impl_pwm!(PWM3, PWM3, PWM3);
364
365impl_timer!(TIMER0, TIMER0, TIMER0);
366impl_timer!(TIMER1, TIMER1, TIMER1);
367impl_timer!(TIMER2, TIMER2, TIMER2);
368
369impl_pin!(P0_00, 0, 0);
370impl_pin!(P0_01, 0, 1);
371impl_pin!(P0_02, 0, 2);
372impl_pin!(P0_03, 0, 3);
373impl_pin!(P0_04, 0, 4);
374impl_pin!(P0_05, 0, 5);
375impl_pin!(P0_06, 0, 6);
376impl_pin!(P0_07, 0, 7);
377impl_pin!(P0_08, 0, 8);
378impl_pin!(P0_09, 0, 9);
379impl_pin!(P0_10, 0, 10);
380impl_pin!(P0_11, 0, 11);
381impl_pin!(P0_12, 0, 12);
382impl_pin!(P0_13, 0, 13);
383impl_pin!(P0_14, 0, 14);
384impl_pin!(P0_15, 0, 15);
385impl_pin!(P0_16, 0, 16);
386impl_pin!(P0_17, 0, 17);
387impl_pin!(P0_18, 0, 18);
388impl_pin!(P0_19, 0, 19);
389impl_pin!(P0_20, 0, 20);
390impl_pin!(P0_21, 0, 21);
391impl_pin!(P0_22, 0, 22);
392impl_pin!(P0_23, 0, 23);
393impl_pin!(P0_24, 0, 24);
394impl_pin!(P0_25, 0, 25);
395impl_pin!(P0_26, 0, 26);
396impl_pin!(P0_27, 0, 27);
397impl_pin!(P0_28, 0, 28);
398impl_pin!(P0_29, 0, 29);
399impl_pin!(P0_30, 0, 30);
400impl_pin!(P0_31, 0, 31);
401
402impl_pin!(P1_00, 1, 0);
403impl_pin!(P1_01, 1, 1);
404impl_pin!(P1_02, 1, 2);
405impl_pin!(P1_03, 1, 3);
406impl_pin!(P1_04, 1, 4);
407impl_pin!(P1_05, 1, 5);
408impl_pin!(P1_06, 1, 6);
409impl_pin!(P1_07, 1, 7);
410impl_pin!(P1_08, 1, 8);
411impl_pin!(P1_09, 1, 9);
412impl_pin!(P1_10, 1, 10);
413impl_pin!(P1_11, 1, 11);
414impl_pin!(P1_12, 1, 12);
415impl_pin!(P1_13, 1, 13);
416impl_pin!(P1_14, 1, 14);
417impl_pin!(P1_15, 1, 15);
418
419impl_ppi_channel!(PPI_CH0, 0 => configurable);
420impl_ppi_channel!(PPI_CH1, 1 => configurable);
421impl_ppi_channel!(PPI_CH2, 2 => configurable);
422impl_ppi_channel!(PPI_CH3, 3 => configurable);
423impl_ppi_channel!(PPI_CH4, 4 => configurable);
424impl_ppi_channel!(PPI_CH5, 5 => configurable);
425impl_ppi_channel!(PPI_CH6, 6 => configurable);
426impl_ppi_channel!(PPI_CH7, 7 => configurable);
427impl_ppi_channel!(PPI_CH8, 8 => configurable);
428impl_ppi_channel!(PPI_CH9, 9 => configurable);
429impl_ppi_channel!(PPI_CH10, 10 => configurable);
430impl_ppi_channel!(PPI_CH11, 11 => configurable);
431impl_ppi_channel!(PPI_CH12, 12 => configurable);
432impl_ppi_channel!(PPI_CH13, 13 => configurable);
433impl_ppi_channel!(PPI_CH14, 14 => configurable);
434impl_ppi_channel!(PPI_CH15, 15 => configurable);
435impl_ppi_channel!(PPI_CH16, 16 => configurable);
436impl_ppi_channel!(PPI_CH17, 17 => configurable);
437impl_ppi_channel!(PPI_CH18, 18 => configurable);
438impl_ppi_channel!(PPI_CH19, 19 => configurable);
439impl_ppi_channel!(PPI_CH20, 20 => configurable);
440impl_ppi_channel!(PPI_CH21, 21 => configurable);
441impl_ppi_channel!(PPI_CH22, 22 => configurable);
442impl_ppi_channel!(PPI_CH23, 23 => configurable);
443impl_ppi_channel!(PPI_CH24, 24 => configurable);
444impl_ppi_channel!(PPI_CH25, 25 => configurable);
445impl_ppi_channel!(PPI_CH26, 26 => configurable);
446impl_ppi_channel!(PPI_CH27, 27 => configurable);
447impl_ppi_channel!(PPI_CH28, 28 => configurable);
448impl_ppi_channel!(PPI_CH29, 29 => configurable);
449impl_ppi_channel!(PPI_CH30, 30 => configurable);
450impl_ppi_channel!(PPI_CH31, 31 => configurable);
451
452impl_saadc_input!(P0_13, ANALOGINPUT0);
453impl_saadc_input!(P0_14, ANALOGINPUT1);
454impl_saadc_input!(P0_15, ANALOGINPUT2);
455impl_saadc_input!(P0_16, ANALOGINPUT3);
456impl_saadc_input!(P0_17, ANALOGINPUT4);
457impl_saadc_input!(P0_18, ANALOGINPUT5);
458impl_saadc_input!(P0_19, ANALOGINPUT6);
459impl_saadc_input!(P0_20, ANALOGINPUT7);
460
461pub mod irqs {
462 use crate::pac::Interrupt as InterruptEnum;
463 use embassy_macros::interrupt_declare as declare;
464
465 declare!(FPU);
466 declare!(CACHE);
467 declare!(SPU);
468 declare!(CLOCK_POWER);
469 declare!(SERIAL0);
470 declare!(SERIAL1);
471 declare!(SPIM4);
472 declare!(SERIAL2);
473 declare!(SERIAL3);
474 declare!(GPIOTE0);
475 declare!(SAADC);
476 declare!(TIMER0);
477 declare!(TIMER1);
478 declare!(TIMER2);
479 declare!(RTC0);
480 declare!(RTC1);
481 declare!(WDT0);
482 declare!(WDT1);
483 declare!(COMP_LPCOMP);
484 declare!(EGU0);
485 declare!(EGU1);
486 declare!(EGU2);
487 declare!(EGU3);
488 declare!(EGU4);
489 declare!(EGU5);
490 declare!(PWM0);
491 declare!(PWM1);
492 declare!(PWM2);
493 declare!(PWM3);
494 declare!(PDM0);
495 declare!(I2S0);
496 declare!(IPC);
497 declare!(QSPI);
498 declare!(NFCT);
499 declare!(GPIOTE1);
500 declare!(QDEC0);
501 declare!(QDEC1);
502 declare!(USBD);
503 declare!(USBREGULATOR);
504 declare!(KMU);
505 declare!(CRYPTOCELL);
506}
diff --git a/embassy-nrf/src/chips/nrf5340_net.rs b/embassy-nrf/src/chips/nrf5340_net.rs
new file mode 100644
index 000000000..ea09f8d78
--- /dev/null
+++ b/embassy-nrf/src/chips/nrf5340_net.rs
@@ -0,0 +1,353 @@
1#[allow(unused_imports)]
2#[rustfmt::skip]
3pub mod pac {
4 // The nRF5340 has a secure and non-secure (NS) mode.
5 // To avoid cfg spam, we remove _ns or _s suffixes here.
6
7 pub use nrf5340_net_pac::{
8 interrupt,
9 Interrupt,
10 Peripherals,
11
12 aar_ns as aar,
13 acl_ns as acl,
14 appmutex_ns as appmutex,
15 ccm_ns as ccm,
16 clock_ns as clock,
17 cti_ns as cti,
18 ctrlap_ns as ctrlap,
19 dcnf_ns as dcnf,
20 dppic_ns as dppic,
21 ecb_ns as ecb,
22 egu0_ns as egu0,
23 ficr_ns as ficr,
24 gpiote_ns as gpiote,
25 ipc_ns as ipc,
26 nvmc_ns as nvmc,
27 p0_ns as p0,
28 power_ns as power,
29 radio_ns as radio,
30 reset_ns as reset,
31 rng_ns as rng,
32 rtc0_ns as rtc0,
33 spim0_ns as spim0,
34 spis0_ns as spis0,
35 swi0_ns as swi0,
36 temp_ns as temp,
37 timer0_ns as timer0,
38 twim0_ns as twim0,
39 twis0_ns as twis0,
40 uarte0_ns as uarte0,
41 uicr_ns as uicr,
42 vmc_ns as vmc,
43 vreqctrl_ns as vreqctrl,
44 wdt_ns as wdt,
45
46 AAR_NS as AAR,
47 ACL_NS as ACL,
48 APPMUTEX_NS as APPMUTEX,
49 APPMUTEX_S as APPMUTEX_S,
50 CBP as CBP,
51 CCM_NS as CCM,
52 CLOCK_NS as CLOCK,
53 CPUID as CPUID,
54 CTI_NS as CTI,
55 CTRLAP_NS as CTRLAP,
56 DCB as DCB,
57 DCNF_NS as DCNF,
58 DPPIC_NS as DPPIC,
59 DWT as DWT,
60 ECB_NS as ECB,
61 EGU0_NS as EGU0,
62 FICR_NS as FICR,
63 FPB as FPB,
64 GPIOTE_NS as GPIOTE,
65 IPC_NS as IPC,
66 ITM as ITM,
67 MPU as MPU,
68 NVIC as NVIC,
69 NVMC_NS as NVMC,
70 P0_NS as P0,
71 P1_NS as P1,
72 POWER_NS as POWER,
73 RADIO_NS as RADIO,
74 RESET_NS as RESET,
75 RNG_NS as RNG,
76 RTC0_NS as RTC0,
77 RTC1_NS as RTC1,
78 SCB as SCB,
79 SPIM0_NS as SPIM0,
80 SPIS0_NS as SPIS0,
81 SWI0_NS as SWI0,
82 SWI1_NS as SWI1,
83 SWI2_NS as SWI2,
84 SWI3_NS as SWI3,
85 SYST as SYST,
86 TEMP_NS as TEMP,
87 TIMER0_NS as TIMER0,
88 TIMER1_NS as TIMER1,
89 TIMER2_NS as TIMER2,
90 TPIU as TPIU,
91 TWIM0_NS as TWIM0,
92 TWIS0_NS as TWIS0,
93 UARTE0_NS as UARTE0,
94 UICR_NS as UICR,
95 VMC_NS as VMC,
96 VREQCTRL_NS as VREQCTRL,
97 WDT_NS as WDT,
98 };
99
100}
101
102/// The maximum buffer size that the EasyDMA can send/recv in one operation.
103pub const EASY_DMA_SIZE: usize = (1 << 16) - 1;
104pub const FORCE_COPY_BUFFER_SIZE: usize = 1024;
105
106embassy_hal_common::peripherals! {
107 // RTC
108 RTC0,
109 RTC1,
110
111 // WDT
112 WDT,
113
114 // UARTE, TWI & SPI
115 UARTETWISPI0,
116 UARTETWISPI1,
117 UARTETWISPI2,
118 UARTETWISPI3,
119
120 // SAADC
121 SAADC,
122
123 // PWM
124 PWM0,
125 PWM1,
126 PWM2,
127 PWM3,
128
129 // TIMER
130 TIMER0,
131 TIMER1,
132 TIMER2,
133
134 // GPIOTE
135 GPIOTE_CH0,
136 GPIOTE_CH1,
137 GPIOTE_CH2,
138 GPIOTE_CH3,
139 GPIOTE_CH4,
140 GPIOTE_CH5,
141 GPIOTE_CH6,
142 GPIOTE_CH7,
143
144 // PPI
145 PPI_CH0,
146 PPI_CH1,
147 PPI_CH2,
148 PPI_CH3,
149 PPI_CH4,
150 PPI_CH5,
151 PPI_CH6,
152 PPI_CH7,
153 PPI_CH8,
154 PPI_CH9,
155 PPI_CH10,
156 PPI_CH11,
157 PPI_CH12,
158 PPI_CH13,
159 PPI_CH14,
160 PPI_CH15,
161 PPI_CH16,
162 PPI_CH17,
163 PPI_CH18,
164 PPI_CH19,
165 PPI_CH20,
166 PPI_CH21,
167 PPI_CH22,
168 PPI_CH23,
169 PPI_CH24,
170 PPI_CH25,
171 PPI_CH26,
172 PPI_CH27,
173 PPI_CH28,
174 PPI_CH29,
175 PPI_CH30,
176 PPI_CH31,
177
178 PPI_GROUP0,
179 PPI_GROUP1,
180 PPI_GROUP2,
181 PPI_GROUP3,
182 PPI_GROUP4,
183 PPI_GROUP5,
184
185 // GPIO port 0
186 P0_00,
187 P0_01,
188 P0_02,
189 P0_03,
190 P0_04,
191 P0_05,
192 P0_06,
193 P0_07,
194 P0_08,
195 P0_09,
196 P0_10,
197 P0_11,
198 P0_12,
199 P0_13,
200 P0_14,
201 P0_15,
202 P0_16,
203 P0_17,
204 P0_18,
205 P0_19,
206 P0_20,
207 P0_21,
208 P0_22,
209 P0_23,
210 P0_24,
211 P0_25,
212 P0_26,
213 P0_27,
214 P0_28,
215 P0_29,
216 P0_30,
217 P0_31,
218
219 // GPIO port 1
220 P1_00,
221 P1_01,
222 P1_02,
223 P1_03,
224 P1_04,
225 P1_05,
226 P1_06,
227 P1_07,
228 P1_08,
229 P1_09,
230 P1_10,
231 P1_11,
232 P1_12,
233 P1_13,
234 P1_14,
235 P1_15,
236}
237
238impl_uarte!(UARTETWISPI0, UARTE0, SERIAL0);
239impl_spim!(UARTETWISPI0, SPIM0, SERIAL0);
240impl_twim!(UARTETWISPI0, TWIM0, SERIAL0);
241
242impl_timer!(TIMER0, TIMER0, TIMER0);
243impl_timer!(TIMER1, TIMER1, TIMER1);
244impl_timer!(TIMER2, TIMER2, TIMER2);
245
246impl_pin!(P0_00, 0, 0);
247impl_pin!(P0_01, 0, 1);
248impl_pin!(P0_02, 0, 2);
249impl_pin!(P0_03, 0, 3);
250impl_pin!(P0_04, 0, 4);
251impl_pin!(P0_05, 0, 5);
252impl_pin!(P0_06, 0, 6);
253impl_pin!(P0_07, 0, 7);
254impl_pin!(P0_08, 0, 8);
255impl_pin!(P0_09, 0, 9);
256impl_pin!(P0_10, 0, 10);
257impl_pin!(P0_11, 0, 11);
258impl_pin!(P0_12, 0, 12);
259impl_pin!(P0_13, 0, 13);
260impl_pin!(P0_14, 0, 14);
261impl_pin!(P0_15, 0, 15);
262impl_pin!(P0_16, 0, 16);
263impl_pin!(P0_17, 0, 17);
264impl_pin!(P0_18, 0, 18);
265impl_pin!(P0_19, 0, 19);
266impl_pin!(P0_20, 0, 20);
267impl_pin!(P0_21, 0, 21);
268impl_pin!(P0_22, 0, 22);
269impl_pin!(P0_23, 0, 23);
270impl_pin!(P0_24, 0, 24);
271impl_pin!(P0_25, 0, 25);
272impl_pin!(P0_26, 0, 26);
273impl_pin!(P0_27, 0, 27);
274impl_pin!(P0_28, 0, 28);
275impl_pin!(P0_29, 0, 29);
276impl_pin!(P0_30, 0, 30);
277impl_pin!(P0_31, 0, 31);
278
279impl_pin!(P1_00, 1, 0);
280impl_pin!(P1_01, 1, 1);
281impl_pin!(P1_02, 1, 2);
282impl_pin!(P1_03, 1, 3);
283impl_pin!(P1_04, 1, 4);
284impl_pin!(P1_05, 1, 5);
285impl_pin!(P1_06, 1, 6);
286impl_pin!(P1_07, 1, 7);
287impl_pin!(P1_08, 1, 8);
288impl_pin!(P1_09, 1, 9);
289impl_pin!(P1_10, 1, 10);
290impl_pin!(P1_11, 1, 11);
291impl_pin!(P1_12, 1, 12);
292impl_pin!(P1_13, 1, 13);
293impl_pin!(P1_14, 1, 14);
294impl_pin!(P1_15, 1, 15);
295
296impl_ppi_channel!(PPI_CH0, 0 => configurable);
297impl_ppi_channel!(PPI_CH1, 1 => configurable);
298impl_ppi_channel!(PPI_CH2, 2 => configurable);
299impl_ppi_channel!(PPI_CH3, 3 => configurable);
300impl_ppi_channel!(PPI_CH4, 4 => configurable);
301impl_ppi_channel!(PPI_CH5, 5 => configurable);
302impl_ppi_channel!(PPI_CH6, 6 => configurable);
303impl_ppi_channel!(PPI_CH7, 7 => configurable);
304impl_ppi_channel!(PPI_CH8, 8 => configurable);
305impl_ppi_channel!(PPI_CH9, 9 => configurable);
306impl_ppi_channel!(PPI_CH10, 10 => configurable);
307impl_ppi_channel!(PPI_CH11, 11 => configurable);
308impl_ppi_channel!(PPI_CH12, 12 => configurable);
309impl_ppi_channel!(PPI_CH13, 13 => configurable);
310impl_ppi_channel!(PPI_CH14, 14 => configurable);
311impl_ppi_channel!(PPI_CH15, 15 => configurable);
312impl_ppi_channel!(PPI_CH16, 16 => configurable);
313impl_ppi_channel!(PPI_CH17, 17 => configurable);
314impl_ppi_channel!(PPI_CH18, 18 => configurable);
315impl_ppi_channel!(PPI_CH19, 19 => configurable);
316impl_ppi_channel!(PPI_CH20, 20 => configurable);
317impl_ppi_channel!(PPI_CH21, 21 => configurable);
318impl_ppi_channel!(PPI_CH22, 22 => configurable);
319impl_ppi_channel!(PPI_CH23, 23 => configurable);
320impl_ppi_channel!(PPI_CH24, 24 => configurable);
321impl_ppi_channel!(PPI_CH25, 25 => configurable);
322impl_ppi_channel!(PPI_CH26, 26 => configurable);
323impl_ppi_channel!(PPI_CH27, 27 => configurable);
324impl_ppi_channel!(PPI_CH28, 28 => configurable);
325impl_ppi_channel!(PPI_CH29, 29 => configurable);
326impl_ppi_channel!(PPI_CH30, 30 => configurable);
327impl_ppi_channel!(PPI_CH31, 31 => configurable);
328
329pub mod irqs {
330 use crate::pac::Interrupt as InterruptEnum;
331 use embassy_macros::interrupt_declare as declare;
332
333 declare!(CLOCK_POWER);
334 declare!(RADIO);
335 declare!(RNG);
336 declare!(GPIOTE);
337 declare!(WDT);
338 declare!(TIMER0);
339 declare!(ECB);
340 declare!(AAR_CCM);
341 declare!(TEMP);
342 declare!(RTC0);
343 declare!(IPC);
344 declare!(SERIAL0);
345 declare!(EGU0);
346 declare!(RTC1);
347 declare!(TIMER1);
348 declare!(TIMER2);
349 declare!(SWI0);
350 declare!(SWI1);
351 declare!(SWI2);
352 declare!(SWI3);
353}
diff --git a/embassy-nrf/src/chips/nrf9160.rs b/embassy-nrf/src/chips/nrf9160.rs
index 3db1e77f2..3678e6d31 100644
--- a/embassy-nrf/src/chips/nrf9160.rs
+++ b/embassy-nrf/src/chips/nrf9160.rs
@@ -2,27 +2,49 @@
2#[rustfmt::skip] 2#[rustfmt::skip]
3pub mod pac { 3pub mod pac {
4 // The nRF9160 has a secure and non-secure (NS) mode. 4 // The nRF9160 has a secure and non-secure (NS) mode.
5 // For now we only support the NS mode, but those peripherals have `_ns` appended to them. 5 // To avoid cfg spam, we remove _ns or _s suffixes here.
6 // To avoid cfg spam, weŕe going to rename the ones we use here.
7 6
8 pub use nrf9160_pac::{ 7 pub use nrf9160_pac::{
9 interrupt, 8 interrupt,
10 Interrupt, 9 Interrupt,
11 10
11 cc_host_rgf_s as cc_host_rgf,
12 clock_ns as clock,
13 cryptocell_s as cryptocell,
14 ctrl_ap_peri_s as ctrl_ap_peri,
15 dppic_ns as dppic,
16 egu0_ns as egu0,
17 ficr_s as ficr,
18 fpu_ns as fpu,
19 gpiote0_s as gpiote0,
20 i2s_ns as i2s,
21 ipc_ns as ipc,
22 kmu_ns as kmu,
23 nvmc_ns as nvmc,
12 p0_ns as p0, 24 p0_ns as p0,
25 pdm_ns as pdm,
26 power_ns as power,
13 pwm0_ns as pwm0, 27 pwm0_ns as pwm0,
28 regulators_ns as regulators,
14 rtc0_ns as rtc0, 29 rtc0_ns as rtc0,
30 saadc_ns as saadc,
15 spim0_ns as spim0, 31 spim0_ns as spim0,
32 spis0_ns as spis0,
33 spu_s as spu,
34 tad_s as tad,
16 timer0_ns as timer0, 35 timer0_ns as timer0,
17 twim0_ns as twim0, 36 twim0_ns as twim0,
37 twis0_ns as twis0,
18 uarte0_ns as uarte0, 38 uarte0_ns as uarte0,
19 saadc_ns as saadc, 39 uicr_s as uicr,
40 vmc_ns as vmc,
41 wdt_ns as wdt,
20 }; 42 };
21 43
22 #[cfg(feature = "nrf9160-ns")] 44 #[cfg(feature = "nrf9160-ns")]
23 pub use nrf9160_pac::{ 45 pub use nrf9160_pac::{
24 CLOCK_NS as CLOCK, 46 CLOCK_NS as CLOCK,
25 DPPIC_NS as PPI, 47 DPPIC_NS as DPPIC,
26 EGU0_NS as EGU0, 48 EGU0_NS as EGU0,
27 EGU1_NS as EGU1, 49 EGU1_NS as EGU1,
28 EGU2_NS as EGU2, 50 EGU2_NS as EGU2,
@@ -79,7 +101,7 @@ pub mod pac {
79 CLOCK_S as CLOCK, 101 CLOCK_S as CLOCK,
80 CRYPTOCELL_S as CRYPTOCELL, 102 CRYPTOCELL_S as CRYPTOCELL,
81 CTRL_AP_PERI_S as CTRL_AP_PERI, 103 CTRL_AP_PERI_S as CTRL_AP_PERI,
82 DPPIC_S as PPI, 104 DPPIC_S as DPPIC,
83 EGU0_S as EGU0, 105 EGU0_S as EGU0,
84 EGU1_S as EGU1, 106 EGU1_S as EGU1,
85 EGU2_S as EGU2, 107 EGU2_S as EGU2,
diff --git a/embassy-nrf/src/gpio.rs b/embassy-nrf/src/gpio.rs
index 7896945fb..91b2e585a 100644
--- a/embassy-nrf/src/gpio.rs
+++ b/embassy-nrf/src/gpio.rs
@@ -4,6 +4,7 @@ use core::convert::Infallible;
4use core::hint::unreachable_unchecked; 4use core::hint::unreachable_unchecked;
5use core::marker::PhantomData; 5use core::marker::PhantomData;
6 6
7use cfg_if::cfg_if;
7use embassy::util::Unborrow; 8use embassy::util::Unborrow;
8use embassy_hal_common::{unborrow, unsafe_impl_unborrow}; 9use embassy_hal_common::{unborrow, unsafe_impl_unborrow};
9use embedded_hal::digital::v2::{InputPin, OutputPin, StatefulOutputPin}; 10use embedded_hal::digital::v2::{InputPin, OutputPin, StatefulOutputPin};
@@ -20,8 +21,8 @@ pub enum Port {
20 /// Port 0, available on nRF9160 and all nRF52 and nRF51 MCUs. 21 /// Port 0, available on nRF9160 and all nRF52 and nRF51 MCUs.
21 Port0, 22 Port0,
22 23
23 /// Port 1, only available on some nRF52 MCUs. 24 /// Port 1, only available on some MCUs.
24 #[cfg(any(feature = "nrf52833", feature = "nrf52840"))] 25 #[cfg(feature = "_gpio-p1")]
25 Port1, 26 Port1,
26} 27}
27 28
@@ -284,14 +285,12 @@ pub(crate) mod sealed {
284 285
285 #[inline] 286 #[inline]
286 fn _pin(&self) -> u8 { 287 fn _pin(&self) -> u8 {
287 #[cfg(any(feature = "nrf52833", feature = "nrf52840"))] 288 cfg_if! {
288 { 289 if #[cfg(feature = "_gpio-p1")] {
289 self.pin_port() % 32 290 self.pin_port() % 32
290 } 291 } else {
291 292 self.pin_port()
292 #[cfg(not(any(feature = "nrf52833", feature = "nrf52840")))] 293 }
293 {
294 self.pin_port()
295 } 294 }
296 } 295 }
297 296
@@ -300,7 +299,7 @@ pub(crate) mod sealed {
300 unsafe { 299 unsafe {
301 match self.pin_port() / 32 { 300 match self.pin_port() / 32 {
302 0 => &*pac::P0::ptr(), 301 0 => &*pac::P0::ptr(),
303 #[cfg(any(feature = "nrf52833", feature = "nrf52840"))] 302 #[cfg(feature = "_gpio-p1")]
304 1 => &*pac::P1::ptr(), 303 1 => &*pac::P1::ptr(),
305 _ => unreachable_unchecked(), 304 _ => unreachable_unchecked(),
306 } 305 }
@@ -344,7 +343,7 @@ pub trait Pin: Unborrow<Target = Self> + sealed::Pin + Sized + 'static {
344 fn port(&self) -> Port { 343 fn port(&self) -> Port {
345 match self.pin_port() / 32 { 344 match self.pin_port() / 32 {
346 0 => Port::Port0, 345 0 => Port::Port0,
347 #[cfg(any(feature = "nrf52833", feature = "nrf52840"))] 346 #[cfg(feature = "_gpio-p1")]
348 1 => Port::Port1, 347 1 => Port::Port1,
349 _ => unsafe { unreachable_unchecked() }, 348 _ => unsafe { unreachable_unchecked() },
350 } 349 }
diff --git a/embassy-nrf/src/gpiote.rs b/embassy-nrf/src/gpiote.rs
index 03688859f..ee638aeac 100644
--- a/embassy-nrf/src/gpiote.rs
+++ b/embassy-nrf/src/gpiote.rs
@@ -41,6 +41,18 @@ pub enum OutputChannelPolarity {
41 Toggle, 41 Toggle,
42} 42}
43 43
44fn regs() -> &'static pac::gpiote::RegisterBlock {
45 cfg_if::cfg_if! {
46 if #[cfg(any(feature="nrf5340-app-s", feature="nrf9160-s"))] {
47 unsafe { &*pac::GPIOTE0::ptr() }
48 } else if #[cfg(any(feature="nrf5340-app-ns", feature="nrf9160-ns"))] {
49 unsafe { &*pac::GPIOTE1::ptr() }
50 } else {
51 unsafe { &*pac::GPIOTE::ptr() }
52 }
53 }
54}
55
44pub(crate) fn init(irq_prio: crate::interrupt::Priority) { 56pub(crate) fn init(irq_prio: crate::interrupt::Priority) {
45 #[cfg(any(feature = "nrf52833", feature = "nrf52840"))] 57 #[cfg(any(feature = "nrf52833", feature = "nrf52840"))]
46 let ports = unsafe { &[&*pac::P0::ptr(), &*pac::P1::ptr()] }; 58 let ports = unsafe { &[&*pac::P0::ptr(), &*pac::P1::ptr()] };
@@ -55,35 +67,46 @@ pub(crate) fn init(irq_prio: crate::interrupt::Priority) {
55 } 67 }
56 68
57 // Enable interrupts 69 // Enable interrupts
58 70 cfg_if::cfg_if! {
59 #[cfg(not(feature = "_nrf9160"))] 71 if #[cfg(any(feature="nrf5340-app-s", feature="nrf9160-s"))] {
60 let irq = unsafe { interrupt::GPIOTE::steal() }; 72 let irq = unsafe { interrupt::GPIOTE0::steal() };
61 #[cfg(feature = "_nrf9160")] 73 } else if #[cfg(any(feature="nrf5340-app-ns", feature="nrf9160-ns"))] {
62 let irq = unsafe { interrupt::GPIOTE1::steal() }; 74 let irq = unsafe { interrupt::GPIOTE1::steal() };
75 } else {
76 let irq = unsafe { interrupt::GPIOTE::steal() };
77 }
78 }
63 79
64 irq.unpend(); 80 irq.unpend();
65 irq.set_priority(irq_prio); 81 irq.set_priority(irq_prio);
66 irq.enable(); 82 irq.enable();
67 83
68 let g = unsafe { &*pac::GPIOTE::ptr() }; 84 let g = regs();
69 g.events_port.write(|w| w); 85 g.events_port.write(|w| w);
70 g.intenset.write(|w| w.port().set()); 86 g.intenset.write(|w| w.port().set());
71} 87}
72 88
73#[cfg(not(feature = "_nrf9160"))] 89cfg_if::cfg_if! {
74#[interrupt] 90 if #[cfg(any(feature="nrf5340-app-s", feature="nrf9160-s"))] {
75fn GPIOTE() { 91 #[interrupt]
76 unsafe { handle_gpiote_interrupt() }; 92 fn GPIOTE0() {
77} 93 unsafe { handle_gpiote_interrupt() };
78 94 }
79#[cfg(feature = "_nrf9160")] 95 } else if #[cfg(any(feature="nrf5340-app-ns", feature="nrf9160-ns"))] {
80#[interrupt] 96 #[interrupt]
81fn GPIOTE1() { 97 fn GPIOTE1() {
82 unsafe { handle_gpiote_interrupt() }; 98 unsafe { handle_gpiote_interrupt() };
99 }
100 } else {
101 #[interrupt]
102 fn GPIOTE() {
103 unsafe { handle_gpiote_interrupt() };
104 }
105 }
83} 106}
84 107
85unsafe fn handle_gpiote_interrupt() { 108unsafe fn handle_gpiote_interrupt() {
86 let g = &*pac::GPIOTE::ptr(); 109 let g = regs();
87 110
88 for i in 0..CHANNEL_COUNT { 111 for i in 0..CHANNEL_COUNT {
89 if g.events_in[i].read().bits() != 0 { 112 if g.events_in[i].read().bits() != 0 {
@@ -135,7 +158,7 @@ pub struct InputChannel<'d, C: Channel, T: GpioPin> {
135 158
136impl<'d, C: Channel, T: GpioPin> Drop for InputChannel<'d, C, T> { 159impl<'d, C: Channel, T: GpioPin> Drop for InputChannel<'d, C, T> {
137 fn drop(&mut self) { 160 fn drop(&mut self) {
138 let g = unsafe { &*pac::GPIOTE::ptr() }; 161 let g = regs();
139 let num = self.ch.number(); 162 let num = self.ch.number();
140 g.config[num].write(|w| w.mode().disabled()); 163 g.config[num].write(|w| w.mode().disabled());
141 g.intenclr.write(|w| unsafe { w.bits(1 << num) }); 164 g.intenclr.write(|w| unsafe { w.bits(1 << num) });
@@ -144,7 +167,7 @@ impl<'d, C: Channel, T: GpioPin> Drop for InputChannel<'d, C, T> {
144 167
145impl<'d, C: Channel, T: GpioPin> InputChannel<'d, C, T> { 168impl<'d, C: Channel, T: GpioPin> InputChannel<'d, C, T> {
146 pub fn new(ch: C, pin: Input<'d, T>, polarity: InputChannelPolarity) -> Self { 169 pub fn new(ch: C, pin: Input<'d, T>, polarity: InputChannelPolarity) -> Self {
147 let g = unsafe { &*pac::GPIOTE::ptr() }; 170 let g = regs();
148 let num = ch.number(); 171 let num = ch.number();
149 172
150 g.config[num].write(|w| { 173 g.config[num].write(|w| {
@@ -168,7 +191,7 @@ impl<'d, C: Channel, T: GpioPin> InputChannel<'d, C, T> {
168 } 191 }
169 192
170 pub async fn wait(&self) { 193 pub async fn wait(&self) {
171 let g = unsafe { &*pac::GPIOTE::ptr() }; 194 let g = regs();
172 let num = self.ch.number(); 195 let num = self.ch.number();
173 196
174 // Enable interrupt 197 // Enable interrupt
@@ -189,7 +212,7 @@ impl<'d, C: Channel, T: GpioPin> InputChannel<'d, C, T> {
189 212
190 /// Returns the IN event, for use with PPI. 213 /// Returns the IN event, for use with PPI.
191 pub fn event_in(&self) -> Event { 214 pub fn event_in(&self) -> Event {
192 let g = unsafe { &*pac::GPIOTE::ptr() }; 215 let g = regs();
193 Event::from_reg(&g.events_in[self.ch.number()]) 216 Event::from_reg(&g.events_in[self.ch.number()])
194 } 217 }
195} 218}
@@ -214,7 +237,7 @@ pub struct OutputChannel<'d, C: Channel, T: GpioPin> {
214 237
215impl<'d, C: Channel, T: GpioPin> Drop for OutputChannel<'d, C, T> { 238impl<'d, C: Channel, T: GpioPin> Drop for OutputChannel<'d, C, T> {
216 fn drop(&mut self) { 239 fn drop(&mut self) {
217 let g = unsafe { &*pac::GPIOTE::ptr() }; 240 let g = regs();
218 let num = self.ch.number(); 241 let num = self.ch.number();
219 g.config[num].write(|w| w.mode().disabled()); 242 g.config[num].write(|w| w.mode().disabled());
220 g.intenclr.write(|w| unsafe { w.bits(1 << num) }); 243 g.intenclr.write(|w| unsafe { w.bits(1 << num) });
@@ -223,7 +246,7 @@ impl<'d, C: Channel, T: GpioPin> Drop for OutputChannel<'d, C, T> {
223 246
224impl<'d, C: Channel, T: GpioPin> OutputChannel<'d, C, T> { 247impl<'d, C: Channel, T: GpioPin> OutputChannel<'d, C, T> {
225 pub fn new(ch: C, pin: Output<'d, T>, polarity: OutputChannelPolarity) -> Self { 248 pub fn new(ch: C, pin: Output<'d, T>, polarity: OutputChannelPolarity) -> Self {
226 let g = unsafe { &*pac::GPIOTE::ptr() }; 249 let g = regs();
227 let num = ch.number(); 250 let num = ch.number();
228 251
229 g.config[num].write(|w| { 252 g.config[num].write(|w| {
@@ -250,41 +273,41 @@ impl<'d, C: Channel, T: GpioPin> OutputChannel<'d, C, T> {
250 273
251 /// Triggers `task out` (as configured with task_out_polarity, defaults to Toggle). 274 /// Triggers `task out` (as configured with task_out_polarity, defaults to Toggle).
252 pub fn out(&self) { 275 pub fn out(&self) {
253 let g = unsafe { &*pac::GPIOTE::ptr() }; 276 let g = regs();
254 g.tasks_out[self.ch.number()].write(|w| unsafe { w.bits(1) }); 277 g.tasks_out[self.ch.number()].write(|w| unsafe { w.bits(1) });
255 } 278 }
256 279
257 /// Triggers `task set` (set associated pin high). 280 /// Triggers `task set` (set associated pin high).
258 #[cfg(not(feature = "nrf51"))] 281 #[cfg(not(feature = "nrf51"))]
259 pub fn set(&self) { 282 pub fn set(&self) {
260 let g = unsafe { &*pac::GPIOTE::ptr() }; 283 let g = regs();
261 g.tasks_set[self.ch.number()].write(|w| unsafe { w.bits(1) }); 284 g.tasks_set[self.ch.number()].write(|w| unsafe { w.bits(1) });
262 } 285 }
263 286
264 /// Triggers `task clear` (set associated pin low). 287 /// Triggers `task clear` (set associated pin low).
265 #[cfg(not(feature = "nrf51"))] 288 #[cfg(not(feature = "nrf51"))]
266 pub fn clear(&self) { 289 pub fn clear(&self) {
267 let g = unsafe { &*pac::GPIOTE::ptr() }; 290 let g = regs();
268 g.tasks_clr[self.ch.number()].write(|w| unsafe { w.bits(1) }); 291 g.tasks_clr[self.ch.number()].write(|w| unsafe { w.bits(1) });
269 } 292 }
270 293
271 /// Returns the OUT task, for use with PPI. 294 /// Returns the OUT task, for use with PPI.
272 pub fn task_out(&self) -> Task { 295 pub fn task_out(&self) -> Task {
273 let g = unsafe { &*pac::GPIOTE::ptr() }; 296 let g = regs();
274 Task::from_reg(&g.tasks_out[self.ch.number()]) 297 Task::from_reg(&g.tasks_out[self.ch.number()])
275 } 298 }
276 299
277 /// Returns the CLR task, for use with PPI. 300 /// Returns the CLR task, for use with PPI.
278 #[cfg(not(feature = "nrf51"))] 301 #[cfg(not(feature = "nrf51"))]
279 pub fn task_clr(&self) -> Task { 302 pub fn task_clr(&self) -> Task {
280 let g = unsafe { &*pac::GPIOTE::ptr() }; 303 let g = regs();
281 Task::from_reg(&g.tasks_clr[self.ch.number()]) 304 Task::from_reg(&g.tasks_clr[self.ch.number()])
282 } 305 }
283 306
284 /// Returns the SET task, for use with PPI. 307 /// Returns the SET task, for use with PPI.
285 #[cfg(not(feature = "nrf51"))] 308 #[cfg(not(feature = "nrf51"))]
286 pub fn task_set(&self) -> Task { 309 pub fn task_set(&self) -> Task {
287 let g = unsafe { &*pac::GPIOTE::ptr() }; 310 let g = regs();
288 Task::from_reg(&g.tasks_set[self.ch.number()]) 311 Task::from_reg(&g.tasks_set[self.ch.number()])
289 } 312 }
290} 313}
diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index 05bdd1904..5a73b87e0 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -12,7 +12,8 @@
12 feature = "nrf52832", 12 feature = "nrf52832",
13 feature = "nrf52833", 13 feature = "nrf52833",
14 feature = "nrf52840", 14 feature = "nrf52840",
15 feature = "nrf5340-app", 15 feature = "nrf5340-app-s",
16 feature = "nrf5340-app-ns",
16 feature = "nrf5340-net", 17 feature = "nrf5340-net",
17 feature = "nrf9160-s", 18 feature = "nrf9160-s",
18 feature = "nrf9160-ns", 19 feature = "nrf9160-ns",
@@ -30,23 +31,24 @@ pub mod buffered_uarte;
30pub mod gpio; 31pub mod gpio;
31#[cfg(feature = "gpiote")] 32#[cfg(feature = "gpiote")]
32pub mod gpiote; 33pub mod gpiote;
33#[cfg(not(feature = "_nrf9160"))] 34#[cfg(not(any(feature = "_nrf5340", feature = "_nrf9160")))]
34pub mod nvmc; 35pub mod nvmc;
35pub mod ppi; 36pub mod ppi;
36#[cfg(not(any(feature = "nrf52805", feature = "nrf52820")))] 37#[cfg(not(any(feature = "nrf52805", feature = "nrf52820", feature = "_nrf5340-net")))]
37pub mod pwm; 38pub mod pwm;
38#[cfg(feature = "nrf52840")] 39#[cfg(feature = "nrf52840")]
39pub mod qspi; 40pub mod qspi;
40#[cfg(not(feature = "_nrf9160"))] 41#[cfg(not(any(feature = "_nrf5340", feature = "_nrf9160")))]
41pub mod rng; 42pub mod rng;
42#[cfg(not(feature = "nrf52820"))] 43#[cfg(not(any(feature = "nrf52820", feature = "_nrf5340-net")))]
43pub mod saadc; 44pub mod saadc;
44pub mod spim; 45pub mod spim;
45#[cfg(not(feature = "_nrf9160"))] 46#[cfg(not(any(feature = "_nrf5340", feature = "_nrf9160")))]
46pub mod temp; 47pub mod temp;
47pub mod timer; 48pub mod timer;
48pub mod twim; 49pub mod twim;
49pub mod uarte; 50pub mod uarte;
51#[cfg(not(feature = "_nrf5340"))]
50pub mod wdt; 52pub mod wdt;
51 53
52// This mod MUST go last, so that it sees all the `impl_foo!` macros 54// This mod MUST go last, so that it sees all the `impl_foo!` macros
@@ -57,6 +59,8 @@ pub mod wdt;
57#[cfg_attr(feature = "nrf52832", path = "chips/nrf52832.rs")] 59#[cfg_attr(feature = "nrf52832", path = "chips/nrf52832.rs")]
58#[cfg_attr(feature = "nrf52833", path = "chips/nrf52833.rs")] 60#[cfg_attr(feature = "nrf52833", path = "chips/nrf52833.rs")]
59#[cfg_attr(feature = "nrf52840", path = "chips/nrf52840.rs")] 61#[cfg_attr(feature = "nrf52840", path = "chips/nrf52840.rs")]
62#[cfg_attr(feature = "_nrf5340-app", path = "chips/nrf5340_app.rs")]
63#[cfg_attr(feature = "_nrf5340-net", path = "chips/nrf5340_net.rs")]
60#[cfg_attr(feature = "_nrf9160", path = "chips/nrf9160.rs")] 64#[cfg_attr(feature = "_nrf9160", path = "chips/nrf9160.rs")]
61mod chip; 65mod chip;
62 66
@@ -67,7 +71,6 @@ pub use chip::pac;
67#[cfg(not(feature = "unstable-pac"))] 71#[cfg(not(feature = "unstable-pac"))]
68pub(crate) use chip::pac; 72pub(crate) use chip::pac;
69 73
70use crate::pac::CLOCK;
71pub use chip::{peripherals, Peripherals}; 74pub use chip::{peripherals, Peripherals};
72 75
73pub mod interrupt { 76pub mod interrupt {
@@ -86,12 +89,12 @@ pub mod config {
86 89
87 pub enum LfclkSource { 90 pub enum LfclkSource {
88 InternalRC, 91 InternalRC,
89 #[cfg(not(feature = "_nrf9160"))] 92 #[cfg(not(any(feature = "_nrf5340", feature = "_nrf9160")))]
90 Synthesized, 93 Synthesized,
91 ExternalXtal, 94 ExternalXtal,
92 #[cfg(not(feature = "_nrf9160"))] 95 #[cfg(not(any(feature = "_nrf5340", feature = "_nrf9160")))]
93 ExternalLowSwing, 96 ExternalLowSwing,
94 #[cfg(not(feature = "_nrf9160"))] 97 #[cfg(not(any(feature = "_nrf5340", feature = "_nrf9160")))]
95 ExternalFullSwing, 98 ExternalFullSwing,
96 } 99 }
97 100
@@ -127,7 +130,7 @@ pub fn init(config: config::Config) -> Peripherals {
127 // before doing anything important. 130 // before doing anything important.
128 let peripherals = Peripherals::take(); 131 let peripherals = Peripherals::take();
129 132
130 let r = unsafe { &*CLOCK::ptr() }; 133 let r = unsafe { &*pac::CLOCK::ptr() };
131 134
132 // Start HFCLK. 135 // Start HFCLK.
133 match config.hfclk_source { 136 match config.hfclk_source {
@@ -141,7 +144,7 @@ pub fn init(config: config::Config) -> Peripherals {
141 } 144 }
142 145
143 // Configure LFCLK. 146 // Configure LFCLK.
144 #[cfg(not(feature = "_nrf9160"))] 147 #[cfg(not(any(feature = "_nrf5340", feature = "_nrf9160")))]
145 match config.lfclk_source { 148 match config.lfclk_source {
146 config::LfclkSource::InternalRC => r.lfclksrc.write(|w| w.src().rc()), 149 config::LfclkSource::InternalRC => r.lfclksrc.write(|w| w.src().rc()),
147 config::LfclkSource::Synthesized => r.lfclksrc.write(|w| w.src().synth()), 150 config::LfclkSource::Synthesized => r.lfclksrc.write(|w| w.src().synth()),
diff --git a/embassy-nrf/src/ppi/dppi.rs b/embassy-nrf/src/ppi/dppi.rs
index b3676fca4..1842590b4 100644
--- a/embassy-nrf/src/ppi/dppi.rs
+++ b/embassy-nrf/src/ppi/dppi.rs
@@ -3,11 +3,17 @@ use core::marker::PhantomData;
3use embassy::util::Unborrow; 3use embassy::util::Unborrow;
4use embassy_hal_common::unborrow; 4use embassy_hal_common::unborrow;
5 5
6use crate::pac;
7
6use super::{Channel, ConfigurableChannel, Event, Ppi, Task}; 8use super::{Channel, ConfigurableChannel, Event, Ppi, Task};
7 9
8const DPPI_ENABLE_BIT: u32 = 0x8000_0000; 10const DPPI_ENABLE_BIT: u32 = 0x8000_0000;
9const DPPI_CHANNEL_MASK: u32 = 0x0000_00FF; 11const DPPI_CHANNEL_MASK: u32 = 0x0000_00FF;
10 12
13fn regs() -> &'static pac::dppic::RegisterBlock {
14 unsafe { &*pac::DPPIC::ptr() }
15}
16
11impl<'d, C: ConfigurableChannel> Ppi<'d, C, 1, 1> { 17impl<'d, C: ConfigurableChannel> Ppi<'d, C, 1, 1> {
12 pub fn new_one_to_one(ch: impl Unborrow<Target = C> + 'd, event: Event, task: Task) -> Self { 18 pub fn new_one_to_one(ch: impl Unborrow<Target = C> + 'd, event: Event, task: Task) -> Self {
13 Ppi::new_many_to_many(ch, [event], [task]) 19 Ppi::new_many_to_many(ch, [event], [task])
@@ -58,6 +64,22 @@ impl<'d, C: ConfigurableChannel, const EVENT_COUNT: usize, const TASK_COUNT: usi
58 } 64 }
59} 65}
60 66
67impl<'d, C: Channel, const EVENT_COUNT: usize, const TASK_COUNT: usize>
68 Ppi<'d, C, EVENT_COUNT, TASK_COUNT>
69{
70 /// Enables the channel.
71 pub fn enable(&mut self) {
72 let n = self.ch.number();
73 regs().chenset.write(|w| unsafe { w.bits(1 << n) });
74 }
75
76 /// Disables the channel.
77 pub fn disable(&mut self) {
78 let n = self.ch.number();
79 regs().chenclr.write(|w| unsafe { w.bits(1 << n) });
80 }
81}
82
61impl<'d, C: Channel, const EVENT_COUNT: usize, const TASK_COUNT: usize> Drop 83impl<'d, C: Channel, const EVENT_COUNT: usize, const TASK_COUNT: usize> Drop
62 for Ppi<'d, C, EVENT_COUNT, TASK_COUNT> 84 for Ppi<'d, C, EVENT_COUNT, TASK_COUNT>
63{ 85{
diff --git a/embassy-nrf/src/ppi/mod.rs b/embassy-nrf/src/ppi/mod.rs
index 96f867d18..aeccb154b 100644
--- a/embassy-nrf/src/ppi/mod.rs
+++ b/embassy-nrf/src/ppi/mod.rs
@@ -15,7 +15,7 @@
15//! many tasks and events, but any single task or event can only be coupled with one channel. 15//! many tasks and events, but any single task or event can only be coupled with one channel.
16//! 16//!
17 17
18use crate::{pac, peripherals}; 18use crate::peripherals;
19use core::marker::PhantomData; 19use core::marker::PhantomData;
20use core::ptr::NonNull; 20use core::ptr::NonNull;
21use embassy::util::Unborrow; 21use embassy::util::Unborrow;
@@ -35,24 +35,6 @@ pub struct Ppi<'d, C: Channel, const EVENT_COUNT: usize, const TASK_COUNT: usize
35 phantom: PhantomData<&'d mut C>, 35 phantom: PhantomData<&'d mut C>,
36} 36}
37 37
38impl<'d, C: Channel + 'd, const EVENT_COUNT: usize, const TASK_COUNT: usize>
39 Ppi<'d, C, EVENT_COUNT, TASK_COUNT>
40{
41 /// Enables the channel.
42 pub fn enable(&mut self) {
43 let r = unsafe { &*pac::PPI::ptr() };
44 r.chenset
45 .write(|w| unsafe { w.bits(1 << self.ch.number()) });
46 }
47
48 /// Disables the channel.
49 pub fn disable(&mut self) {
50 let r = unsafe { &*pac::PPI::ptr() };
51 r.chenclr
52 .write(|w| unsafe { w.bits(1 << self.ch.number()) });
53 }
54}
55
56const REGISTER_DPPI_CONFIG_OFFSET: usize = 0x80 / core::mem::size_of::<u32>(); 38const REGISTER_DPPI_CONFIG_OFFSET: usize = 0x80 / core::mem::size_of::<u32>();
57 39
58/// Represents a task that a peripheral can do. 40/// Represents a task that a peripheral can do.
diff --git a/embassy-nrf/src/ppi/ppi.rs b/embassy-nrf/src/ppi/ppi.rs
index c1d9794c9..cdbe046f8 100644
--- a/embassy-nrf/src/ppi/ppi.rs
+++ b/embassy-nrf/src/ppi/ppi.rs
@@ -17,12 +17,16 @@ impl Event {
17 } 17 }
18} 18}
19 19
20fn regs() -> &'static pac::ppi::RegisterBlock {
21 unsafe { &*pac::PPI::ptr() }
22}
23
20#[cfg(not(feature = "nrf51"))] // Not for nrf51 because of the fork task 24#[cfg(not(feature = "nrf51"))] // Not for nrf51 because of the fork task
21impl<'d, C: StaticChannel> Ppi<'d, C, 0, 1> { 25impl<'d, C: StaticChannel> Ppi<'d, C, 0, 1> {
22 pub fn new_zero_to_one(ch: impl Unborrow<Target = C> + 'd, task: Task) -> Self { 26 pub fn new_zero_to_one(ch: impl Unborrow<Target = C> + 'd, task: Task) -> Self {
23 unborrow!(ch); 27 unborrow!(ch);
24 28
25 let r = unsafe { &*pac::PPI::ptr() }; 29 let r = regs();
26 let n = ch.number(); 30 let n = ch.number();
27 r.fork[n].tep.write(|w| unsafe { w.bits(task.reg_val()) }); 31 r.fork[n].tep.write(|w| unsafe { w.bits(task.reg_val()) });
28 32
@@ -37,7 +41,7 @@ impl<'d, C: ConfigurableChannel> Ppi<'d, C, 1, 1> {
37 pub fn new_one_to_one(ch: impl Unborrow<Target = C> + 'd, event: Event, task: Task) -> Self { 41 pub fn new_one_to_one(ch: impl Unborrow<Target = C> + 'd, event: Event, task: Task) -> Self {
38 unborrow!(ch); 42 unborrow!(ch);
39 43
40 let r = unsafe { &*pac::PPI::ptr() }; 44 let r = regs();
41 let n = ch.number(); 45 let n = ch.number();
42 r.ch[n].eep.write(|w| unsafe { w.bits(event.reg_val()) }); 46 r.ch[n].eep.write(|w| unsafe { w.bits(event.reg_val()) });
43 r.ch[n].tep.write(|w| unsafe { w.bits(task.reg_val()) }); 47 r.ch[n].tep.write(|w| unsafe { w.bits(task.reg_val()) });
@@ -59,7 +63,7 @@ impl<'d, C: ConfigurableChannel> Ppi<'d, C, 1, 2> {
59 ) -> Self { 63 ) -> Self {
60 unborrow!(ch); 64 unborrow!(ch);
61 65
62 let r = unsafe { &*pac::PPI::ptr() }; 66 let r = regs();
63 let n = ch.number(); 67 let n = ch.number();
64 r.ch[n].eep.write(|w| unsafe { w.bits(event.reg_val()) }); 68 r.ch[n].eep.write(|w| unsafe { w.bits(event.reg_val()) });
65 r.ch[n].tep.write(|w| unsafe { w.bits(task1.reg_val()) }); 69 r.ch[n].tep.write(|w| unsafe { w.bits(task1.reg_val()) });
@@ -72,13 +76,29 @@ impl<'d, C: ConfigurableChannel> Ppi<'d, C, 1, 2> {
72 } 76 }
73} 77}
74 78
79impl<'d, C: Channel, const EVENT_COUNT: usize, const TASK_COUNT: usize>
80 Ppi<'d, C, EVENT_COUNT, TASK_COUNT>
81{
82 /// Enables the channel.
83 pub fn enable(&mut self) {
84 let n = self.ch.number();
85 regs().chenset.write(|w| unsafe { w.bits(1 << n) });
86 }
87
88 /// Disables the channel.
89 pub fn disable(&mut self) {
90 let n = self.ch.number();
91 regs().chenclr.write(|w| unsafe { w.bits(1 << n) });
92 }
93}
94
75impl<'d, C: Channel, const EVENT_COUNT: usize, const TASK_COUNT: usize> Drop 95impl<'d, C: Channel, const EVENT_COUNT: usize, const TASK_COUNT: usize> Drop
76 for Ppi<'d, C, EVENT_COUNT, TASK_COUNT> 96 for Ppi<'d, C, EVENT_COUNT, TASK_COUNT>
77{ 97{
78 fn drop(&mut self) { 98 fn drop(&mut self) {
79 self.disable(); 99 self.disable();
80 100
81 let r = unsafe { &*pac::PPI::ptr() }; 101 let r = regs();
82 let n = self.ch.number(); 102 let n = self.ch.number();
83 r.ch[n].eep.write(|w| unsafe { w.bits(0) }); 103 r.ch[n].eep.write(|w| unsafe { w.bits(0) });
84 r.ch[n].tep.write(|w| unsafe { w.bits(0) }); 104 r.ch[n].tep.write(|w| unsafe { w.bits(0) });
generated by cgit (git 2.34.1) at 2026-04-05 20:16:46 +0000