diff options
| -rw-r--r-- | embassy-rp/Cargo.toml | 2 | ||||
| -rw-r--r-- | embassy-rp/src/gpio.rs | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/embassy-rp/Cargo.toml b/embassy-rp/Cargo.toml index af7c8ee6e..0e53d3a35 100644 --- a/embassy-rp/Cargo.toml +++ b/embassy-rp/Cargo.toml | |||
| @@ -30,7 +30,7 @@ unstable-traits = ["embedded-hal-1"] | |||
| 30 | embassy-util = { version = "0.1.0", path = "../embassy-util" } | 30 | embassy-util = { version = "0.1.0", path = "../embassy-util" } |
| 31 | embassy-executor = { version = "0.1.0", path = "../embassy-executor" } | 31 | embassy-executor = { version = "0.1.0", path = "../embassy-executor" } |
| 32 | embassy-time = { version = "0.1.0", path = "../embassy-time", features = [ "tick-1mhz" ] } | 32 | embassy-time = { version = "0.1.0", path = "../embassy-time", features = [ "tick-1mhz" ] } |
| 33 | embassy-cortex-m = { version = "0.1.0", path = "../embassy-cortex-m", features = ["prio-bits-3"]} | 33 | embassy-cortex-m = { version = "0.1.0", path = "../embassy-cortex-m", features = ["prio-bits-2"]} |
| 34 | embassy-hal-common = {version = "0.1.0", path = "../embassy-hal-common" } | 34 | embassy-hal-common = {version = "0.1.0", path = "../embassy-hal-common" } |
| 35 | embassy-embedded-hal = {version = "0.1.0", path = "../embassy-embedded-hal" } | 35 | embassy-embedded-hal = {version = "0.1.0", path = "../embassy-embedded-hal" } |
| 36 | atomic-polyfill = "1.0.1" | 36 | atomic-polyfill = "1.0.1" |
diff --git a/embassy-rp/src/gpio.rs b/embassy-rp/src/gpio.rs index f9fa8378b..90862fa32 100644 --- a/embassy-rp/src/gpio.rs +++ b/embassy-rp/src/gpio.rs | |||
| @@ -189,7 +189,7 @@ impl<'d, T: Pin> InputFuture<'d, T> { | |||
| 189 | unsafe { | 189 | unsafe { |
| 190 | let irq = interrupt::IO_IRQ_BANK0::steal(); | 190 | let irq = interrupt::IO_IRQ_BANK0::steal(); |
| 191 | irq.disable(); | 191 | irq.disable(); |
| 192 | irq.set_priority(interrupt::Priority::P6); | 192 | irq.set_priority(interrupt::Priority::P3); |
| 193 | 193 | ||
| 194 | // Each INTR register is divided into 8 groups, one group for each | 194 | // Each INTR register is divided into 8 groups, one group for each |
| 195 | // pin, and each group consists of LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, | 195 | // pin, and each group consists of LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, |
