95 files changed, 5567 insertions, 3317 deletions
diff --git a/.helix/languages.toml b/.helix/languages.toml
new file mode 100644
index 000000000..d34df4b24
--- /dev/null
+++ b/.helix/languages.toml
@@ -0,0 +1,11 @@
+[language-server.rust-analyzer.config.cargo]
+allTargets = false
+noDefaultFeatures = true
+target = "thumbv8m.main-none-eabihf"
+features = ["stm32n657x0", "time-driver-any", "unstable-pac", "exti"]
+[language-server.rust-analyzer.config.check]
+allTargets = false
+noDefaultFeatures = true
+target = "thumbv8m.main-none-eabihf"
+features = ["stm32n657x0", "time-driver-any", "unstable-pac", "exti"]
diff --git a/embassy-nrf/CHANGELOG.md b/embassy-nrf/CHANGELOG.md
index 72ecb116a..f6fe1e14f 100644
--- a/embassy-nrf/CHANGELOG.md
+++ b/embassy-nrf/CHANGELOG.md
@@ -23,6 +23,10 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - bugfix: Do not write to UICR from non-secure code on nrf53
 - bugfix: Add delay to uart init anomaly fix
 - changed: `BufferedUarte::read_ready` now uses the same definition for 'empty' so following read calls will not block when true is returned
+- added: add `gpiote::InputChannel::wait_for_high()` and `wait_for_low()` to wait for specific signal level
+- changed: `gpiote::InputChannel::wait()` now takes a mutable reference to `self` to avoid interference from concurrent calls
+- changed: `gpiote::InputChannel::wait()` now ensures events are seen as soon as the function is called, even if the future is not polled
+- bugfix: use correct flash size for nRF54l
 ## 0.8.0 - 2025-09-30
diff --git a/embassy-nrf/src/chips/nrf54l15_app.rs b/embassy-nrf/src/chips/nrf54l15_app.rs
index 0724f2ff6..8846717db 100644
--- a/embassy-nrf/src/chips/nrf54l15_app.rs
+++ b/embassy-nrf/src/chips/nrf54l15_app.rs
@@ -204,7 +204,7 @@ pub const FORCE_COPY_BUFFER_SIZE: usize = 1024;
 // 1.5 MB NVM
 #[allow(unused)]
-pub const FLASH_SIZE: usize = 1536 * 1024;
+pub const FLASH_SIZE: usize = 1524 * 1024;
 embassy_hal_internal::peripherals! {
    // PPI
diff --git a/embassy-nrf/src/gpiote.rs b/embassy-nrf/src/gpiote.rs
index 91944d8cd..d4f6668f3 100644
--- a/embassy-nrf/src/gpiote.rs
+++ b/embassy-nrf/src/gpiote.rs
@@ -349,16 +349,73 @@ impl<'d> InputChannel<'d> {
    }
    /// Asynchronously wait for an event in this channel.
-    pub async fn wait(&self) {
+    ///
-        let g = self.ch.regs();
+    /// It is possible to call this function and await the returned future later.
-        let num = self.ch.number();
+    /// If an even occurs in the mean time, the future will immediately report ready.
-        let waker = self.ch.waker();
+    pub fn wait(&mut self) -> impl Future<Output = ()> {
+        // NOTE: This is `-> impl Future` and not an `async fn` on purpose.
+        // Otherwise, events will only be detected starting at the first poll of the returned future.
+        Self::wait_internal(&mut self.ch)
+    }
+    /// Asynchronously wait for the pin to become high.
+    ///
+    /// The channel must be configured with [`InputChannelPolarity::LoToHi`] or [`InputChannelPolarity::Toggle`].
+    /// If the channel is not configured to detect rising edges, it is unspecified when the returned future completes.
+    ///
+    /// It is possible to call this function and await the returned future later.
+    /// If an even occurs in the mean time, the future will immediately report ready.
+    pub fn wait_for_high(&mut self) -> impl Future<Output = ()> {
+        // NOTE: This is `-> impl Future` and not an `async fn` on purpose.
+        // Otherwise, events will only be detected starting at the first poll of the returned future.
+        // Subscribe to the event before checking the pin level.
+        let wait = Self::wait_internal(&mut self.ch);
+        let pin = &self.pin;
+        async move {
+            if pin.is_high() {
+                return;
+            }
+            wait.await;
+        }
+    }
+    /// Asynchronously wait for the pin to become low.
+    ///
+    /// The channel must be configured with [`InputChannelPolarity::HiToLo`] or [`InputChannelPolarity::Toggle`].
+    /// If the channel is not configured to detect falling edges, it is unspecified when the returned future completes.
+    ///
+    /// It is possible to call this function and await the returned future later.
+    /// If an even occurs in the mean time, the future will immediately report ready.
+    pub fn wait_for_low(&mut self) -> impl Future<Output = ()> {
+        // NOTE: This is `-> impl Future` and not an `async fn` on purpose.
+        // Otherwise, events will only be detected starting at the first poll of the returned future.
+        // Subscribe to the event before checking the pin level.
+        let wait = Self::wait_internal(&mut self.ch);
+        let pin = &self.pin;
+        async move {
+            if pin.is_low() {
+                return;
+            }
+            wait.await;
+        }
+    }
+    /// Internal implementation for `wait()` and friends.
+    fn wait_internal(channel: &mut Peri<'_, AnyChannel>) -> impl Future<Output = ()> {
+        // NOTE: This is `-> impl Future` and not an `async fn` on purpose.
+        // Otherwise, events will only be detected starting at the first poll of the returned future.
+        let g = channel.regs();
+        let num = channel.number();
+        let waker = channel.waker();
        // Enable interrupt
        g.events_in(num).write_value(0);
        g.intenset(INTNUM).write(|w| w.0 = 1 << num);
-        poll_fn(|cx| {
+        poll_fn(move |cx| {
            CHANNEL_WAKERS[waker].register(cx.waker());
            if g.events_in(num).read() != 0 {
@@ -367,7 +424,6 @@ impl<'d> InputChannel<'d> {
                Poll::Pending
            }
        })
-        .await;
    }
    /// Get the associated input pin.
diff --git a/embassy-rp/CHANGELOG.md b/embassy-rp/CHANGELOG.md
index 3b3cb5351..4b0d738a7 100644
--- a/embassy-rp/CHANGELOG.md
+++ b/embassy-rp/CHANGELOG.md
@@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 <!-- next-header -->
 ## Unreleased - ReleaseDate
+- Add documentation for pio `get_x` about autopush.
 - Fix several minor typos in documentation
 - Add PIO SPI
 - Add PIO I2S input
@@ -114,3 +115,4 @@ Small release fixing a few gnarly bugs, upgrading is strongly recommended.
 - rename the Channel trait to Slice and the PwmPin to PwmChannel
 - i2c: Fix race condition that appears on fast repeated transfers.
 - Add a basic "read to break" function
diff --git a/embassy-rp/src/pio/instr.rs b/embassy-rp/src/pio/instr.rs
index b15d507de..304ddb20a 100644
--- a/embassy-rp/src/pio/instr.rs
+++ b/embassy-rp/src/pio/instr.rs
@@ -5,6 +5,10 @@ use crate::pio::{Instance, StateMachine};
 impl<'d, PIO: Instance, const SM: usize> StateMachine<'d, PIO, SM> {
    /// Set value of scratch register X.
+    ///
+    /// SAFETY: autopull enabled else it will write undefined data.
+    /// Make sure to have setup the according configuration see
+    /// [shift_out](crate::pio::Config::shift_out) and [auto_fill](crate::pio::ShiftConfig::auto_fill).
    pub unsafe fn set_x(&mut self, value: u32) {
        const OUT: u16 = InstructionOperands::OUT {
            destination: OutDestination::X,
@@ -16,6 +20,10 @@ impl<'d, PIO: Instance, const SM: usize> StateMachine<'d, PIO, SM> {
    }
    /// Get value of scratch register X.
+    ///
+    /// SAFETY: autopush enabled else it will read undefined data.
+    /// Make sure to have setup the according configurations see
+    /// [shift_in](crate::pio::Config::shift_in) and [auto_fill](crate::pio::ShiftConfig::auto_fill).
    pub unsafe fn get_x(&mut self) -> u32 {
        const IN: u16 = InstructionOperands::IN {
            source: InSource::X,
@@ -27,6 +35,10 @@ impl<'d, PIO: Instance, const SM: usize> StateMachine<'d, PIO, SM> {
    }
    /// Set value of scratch register Y.
+    ///
+    /// SAFETY: autopull enabled else it will write undefined data.
+    /// Make sure to have setup the according configuration see
+    /// [shift_out](crate::pio::Config::shift_out) and [auto_fill](crate::pio::ShiftConfig::auto_fill).
    pub unsafe fn set_y(&mut self, value: u32) {
        const OUT: u16 = InstructionOperands::OUT {
            destination: OutDestination::Y,
@@ -38,6 +50,10 @@ impl<'d, PIO: Instance, const SM: usize> StateMachine<'d, PIO, SM> {
    }
    /// Get value of scratch register Y.
+    ///
+    /// SAFETY: autopush enabled else it will read undefined data.
+    /// Make sure to have setup the according configurations see
+    /// [shift_in](crate::pio::Config::shift_in) and [auto_fill](crate::pio::ShiftConfig::auto_fill).
    pub unsafe fn get_y(&mut self) -> u32 {
        const IN: u16 = InstructionOperands::IN {
            source: InSource::Y,
diff --git a/embassy-stm32/CHANGELOG.md b/embassy-stm32/CHANGELOG.md
index 95d844dc8..c3b3cb3ab 100644
--- a/embassy-stm32/CHANGELOG.md
+++ b/embassy-stm32/CHANGELOG.md
@@ -8,6 +8,9 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ## Unreleased - ReleaseDate
 - fix: Allow setting SAI peripheral `frame_length` to `256`
+- fix: flash erase on dual-bank STM32Gxxx
+- feat: Add support for STM32N657X0
+- feat: timer: Add 32-bit timer support to SimplePwm waveform_up method following waveform pattern ([#4717](https://github.com/embassy-rs/embassy/pull/4717))
 - feat: Add support for injected ADC measurements for g4 ([#4840](https://github.com/embassy-rs/embassy/pull/4840))
 - feat: Implement into_ring_buffered for g4 ([#4840](https://github.com/embassy-rs/embassy/pull/4840))
 - feat: Add support for 13-bit address and 16-bit data SDRAM chips
@@ -42,7 +45,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - fix: sdmmc: don't wait for DBCKEND flag on sdmmc_v2 devices as it never fires (Fixes #4723)
 - fix: usart: fix race condition in ringbuffered usart
 - feat: Add backup_sram::init() for H5 devices to access BKPSRAM
- feat: Add I2C MultiMaster (Slave) support for I2C v1
+- feat: stm32/i2c v1: Add I2C MultiMaster (Slave) support
+- feat: stm32/i2c v2: Add transaction() and blocking_transaction() methods with contract-compliant operation merging
 - feat: stm32/fdcan: add ability to control automatic recovery from bus off ([#4821](https://github.com/embassy-rs/embassy/pull/4821))
 - low-power: update rtc api to allow reconfig
 - adc: consolidate ringbuffer
@@ -52,6 +56,11 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - feat: stm32/dsi support zero parameter commands in `write_cmd` ([#4847](https://github.com/embassy-rs/embassy/pull/4847))
 - feat: stm32/spi: added support for slave mode ([#4388](https://github.com/embassy-rs/embassy/pull/4388))
 - chore: Updated stm32-metapac and stm32-data dependencies
+- adc: reogranize and cleanup somewhat. require sample_time to be passed on conversion
+- fix: stm32/i2c v2 slave: prevent misaligned reads, error false positives, and incorrect counts of bytes read/written
+- feat: add flash support for c0 family ([#4874](https://github.com/embassy-rs/embassy/pull/4874))
+- fix: fixing channel numbers on vbat and vddcore for adc on adc
+- adc: adding disable to vbat
 ## 0.4.0 - 2025-08-26
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 108321d0a..2f4f2ce51 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -99,6 +99,7 @@ build = [
    {target = "thumbv8m.main-none-eabihf", features = ["defmt", "exti", "low-power", "stm32wba65ri", "time", "time-driver-any"]},
    {target = "thumbv8m.main-none-eabihf", features = ["defmt", "exti", "stm32u5f9zj", "time", "time-driver-any"]},
    {target = "thumbv8m.main-none-eabihf", features = ["defmt", "exti", "stm32u5g9nj", "time", "time-driver-any"]},
+    {target = "thumbv8m.main-none-eabihf", features = ["defmt", "exti", "stm32n657x0", "time", "time-driver-any"]},
    {target = "thumbv7em-none-eabi", features = ["defmt", "exti", "stm32wb35ce", "time", "time-driver-any"]},
    {target = "thumbv7em-none-eabi", features = ["defmt", "exti", "low-power", "stm32wb55rg", "time", "time-driver-any"]},
    {target = "thumbv6m-none-eabi", features = ["defmt", "exti", "stm32u031r8", "time", "time-driver-any"]},
@@ -138,6 +139,7 @@ flavors = [
    { regex_feature = "stm32wb.*", target = "thumbv7em-none-eabi" },
    { regex_feature = "stm32wba.*", target = "thumbv8m.main-none-eabihf" },
    { regex_feature = "stm32wl.*", target = "thumbv7em-none-eabi" },
+    { regex_feature = "stm32n6.*", target = "thumbv8m.main-none-eabihf" },
 ]
 [package.metadata.docs.rs]
@@ -186,6 +188,7 @@ embedded-io = { version = "0.6.0" }
 embedded-io-async = { version = "0.6.1" }
 chrono = { version = "^0.4", default-features = false, optional = true }
 bit_field = "0.10.2"
+trait-set = "0.3.0"
 document-features = "0.2.7"
 static_assertions = { version = "1.1" }
@@ -197,11 +200,11 @@ aligned = "0.4.1"
 heapless = "0.9.1"
 #stm32-metapac = { version = "18" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-22374e3344a2c9150b9b3d4da45c03f398fdc54e" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-b77c8d968f53b18d6bdcd052e354b5070ec2bbc2" }
 [build-dependencies]
 #stm32-metapac = { version = "18", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-22374e3344a2c9150b9b3d4da45c03f398fdc54e", default-features = false, features = ["metadata"] }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-b77c8d968f53b18d6bdcd052e354b5070ec2bbc2", default-features = false, features = ["metadata"] }
 proc-macro2 = "1.0.36"
 quote = "1.0.15"
@@ -213,7 +216,6 @@ proptest = "1.5.0"
 proptest-state-machine = "0.3.0"
 [features]
 default = ["rt"]
@@ -1642,6 +1644,30 @@ stm32l562qe = [ "stm32-metapac/stm32l562qe" ]
 stm32l562re = [ "stm32-metapac/stm32l562re" ]
 stm32l562ve = [ "stm32-metapac/stm32l562ve" ]
 stm32l562ze = [ "stm32-metapac/stm32l562ze" ]
+stm32n645a0 = [ "stm32-metapac/stm32n645a0" ]
+stm32n645b0 = [ "stm32-metapac/stm32n645b0" ]
+stm32n645i0 = [ "stm32-metapac/stm32n645i0" ]
+stm32n645l0 = [ "stm32-metapac/stm32n645l0" ]
+stm32n645x0 = [ "stm32-metapac/stm32n645x0" ]
+stm32n645z0 = [ "stm32-metapac/stm32n645z0" ]
+stm32n647a0 = [ "stm32-metapac/stm32n647a0" ]
+stm32n647b0 = [ "stm32-metapac/stm32n647b0" ]
+stm32n647i0 = [ "stm32-metapac/stm32n647i0" ]
+stm32n647l0 = [ "stm32-metapac/stm32n647l0" ]
+stm32n647x0 = [ "stm32-metapac/stm32n647x0" ]
+stm32n647z0 = [ "stm32-metapac/stm32n647z0" ]
+stm32n655a0 = [ "stm32-metapac/stm32n655a0" ]
+stm32n655b0 = [ "stm32-metapac/stm32n655b0" ]
+stm32n655i0 = [ "stm32-metapac/stm32n655i0" ]
+stm32n655l0 = [ "stm32-metapac/stm32n655l0" ]
+stm32n655x0 = [ "stm32-metapac/stm32n655x0" ]
+stm32n655z0 = [ "stm32-metapac/stm32n655z0" ]
+stm32n657a0 = [ "stm32-metapac/stm32n657a0" ]
+stm32n657b0 = [ "stm32-metapac/stm32n657b0" ]
+stm32n657i0 = [ "stm32-metapac/stm32n657i0" ]
+stm32n657l0 = [ "stm32-metapac/stm32n657l0" ]
+stm32n657x0 = [ "stm32-metapac/stm32n657x0" ]
+stm32n657z0 = [ "stm32-metapac/stm32n657z0" ]
 stm32u031c6 = [ "stm32-metapac/stm32u031c6" ]
 stm32u031c8 = [ "stm32-metapac/stm32u031c8" ]
 stm32u031f4 = [ "stm32-metapac/stm32u031f4" ]
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 940e29417..1e11eb8dc 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -363,101 +363,108 @@ fn main() {
    // ========
    // Generate FLASH regions
-    let mut flash_regions = TokenStream::new();
+    cfgs.declare("flash");
-    let flash_memory_regions: Vec<_> = memory
+    let mut has_flash = false;
-        .iter()
+    if !chip_name.starts_with("stm32n6") {
-        .filter(|x| x.kind == MemoryRegionKind::Flash && x.settings.is_some())
+        cfgs.enable("flash");
-        .collect();
+        has_flash = true;
-    for region in flash_memory_regions.iter() {
-        let region_name = format_ident!("{}", get_flash_region_name(region.name));
+        let mut flash_regions = TokenStream::new();
-        let bank_variant = format_ident!(
+        let flash_memory_regions: Vec<_> = memory
-            "{}",
+            .iter()
-            if region.name.starts_with("BANK_1") {
+            .filter(|x| x.kind == MemoryRegionKind::Flash && x.settings.is_some())
-                "Bank1"
+            .collect();
-            } else if region.name.starts_with("BANK_2") {
+        for region in flash_memory_regions.iter() {
-                "Bank2"
+            let region_name = format_ident!("{}", get_flash_region_name(region.name));
-            } else if region.name == "OTP" {
+            let bank_variant = format_ident!(
-                "Otp"
+                "{}",
-            } else {
+                if region.name.starts_with("BANK_1") {
-                continue;
+                    "Bank1"
-            }
+                } else if region.name.starts_with("BANK_2") {
-        );
+                    "Bank2"
-        let base = region.address;
+                } else if region.name == "OTP" {
-        let size = region.size;
+                    "Otp"
-        let settings = region.settings.as_ref().unwrap();
+                } else {
-        let erase_size = settings.erase_size;
+                    continue;
-        let write_size = settings.write_size;
+                }
-        let erase_value = settings.erase_value;
+            );
+            let base = region.address;
-        flash_regions.extend(quote! {
+            let size = region.size;
-            pub const #region_name: crate::flash::FlashRegion = crate::flash::FlashRegion {
+            let settings = region.settings.as_ref().unwrap();
-                bank: crate::flash::FlashBank::#bank_variant,
+            let erase_size = settings.erase_size;
-                base: #base,
+            let write_size = settings.write_size;
-                size: #size,
+            let erase_value = settings.erase_value;
-                erase_size: #erase_size,
-                write_size: #write_size,
+            flash_regions.extend(quote! {
-                erase_value: #erase_value,
+                pub const #region_name: crate::flash::FlashRegion = crate::flash::FlashRegion {
-                _ensure_internal: (),
+                    bank: crate::flash::FlashBank::#bank_variant,
-            };
+                    base: #base,
-        });
+                    size: #size,
+                    erase_size: #erase_size,
+                    write_size: #write_size,
+                    erase_value: #erase_value,
+                    _ensure_internal: (),
+                };
+            });
-        let region_type = format_ident!("{}", get_flash_region_type_name(region.name));
+            let region_type = format_ident!("{}", get_flash_region_type_name(region.name));
-        flash_regions.extend(quote! {
+            flash_regions.extend(quote! {
            #[cfg(flash)]
            pub struct #region_type<'d, MODE = crate::flash::Async>(pub &'static crate::flash::FlashRegion, pub(crate) embassy_hal_internal::Peri<'d, crate::peripherals::FLASH>, pub(crate) core::marker::PhantomData<MODE>);
        });
-    }
+        }
-    let (fields, (inits, region_names)): (Vec<TokenStream>, (Vec<TokenStream>, Vec<Ident>)) = flash_memory_regions
+        let (fields, (inits, region_names)): (Vec<TokenStream>, (Vec<TokenStream>, Vec<Ident>)) = flash_memory_regions
-        .iter()
+            .iter()
-        .map(|f| {
+            .map(|f| {
-            let region_name = get_flash_region_name(f.name);
+                let region_name = get_flash_region_name(f.name);
-            let field_name = format_ident!("{}", region_name.to_lowercase());
+                let field_name = format_ident!("{}", region_name.to_lowercase());
-            let field_type = format_ident!("{}", get_flash_region_type_name(f.name));
+                let field_type = format_ident!("{}", get_flash_region_type_name(f.name));
-            let field = quote! {
+                let field = quote! {
-                pub #field_name: #field_type<'d, MODE>
+                    pub #field_name: #field_type<'d, MODE>
-            };
+                };
-            let region_name = format_ident!("{}", region_name);
+                let region_name = format_ident!("{}", region_name);
-            let init = quote! {
+                let init = quote! {
-                #field_name: #field_type(&#region_name, unsafe { p.clone_unchecked()}, core::marker::PhantomData)
+                    #field_name: #field_type(&#region_name, unsafe { p.clone_unchecked()}, core::marker::PhantomData)
-            };
+                };
-            (field, (init, region_name))
+                (field, (init, region_name))
-        })
+            })
-        .unzip();
+            .unzip();
-    let regions_len = flash_memory_regions.len();
+        let regions_len = flash_memory_regions.len();
-    flash_regions.extend(quote! {
+        flash_regions.extend(quote! {
-        #[cfg(flash)]
+            #[cfg(flash)]
-        pub struct FlashLayout<'d, MODE = crate::flash::Async> {
+            pub struct FlashLayout<'d, MODE = crate::flash::Async> {
-            #(#fields),*,
+                #(#fields),*,
-            _mode: core::marker::PhantomData<MODE>,
+                _mode: core::marker::PhantomData<MODE>,
-        }
+            }
-        #[cfg(flash)]
+            #[cfg(flash)]
-        impl<'d, MODE> FlashLayout<'d, MODE> {
+            impl<'d, MODE> FlashLayout<'d, MODE> {
-            pub(crate) fn new(p: embassy_hal_internal::Peri<'d, crate::peripherals::FLASH>) -> Self {
+                pub(crate) fn new(p: embassy_hal_internal::Peri<'d, crate::peripherals::FLASH>) -> Self {
-                Self {
+                    Self {
-                    #(#inits),*,
+                        #(#inits),*,
-                    _mode: core::marker::PhantomData,
+                        _mode: core::marker::PhantomData,
+                    }
                }
            }
-        }
-        pub const FLASH_REGIONS: [&crate::flash::FlashRegion; #regions_len] = [
+            pub const FLASH_REGIONS: [&crate::flash::FlashRegion; #regions_len] = [
-            #(&#region_names),*
+                #(&#region_names),*
-        ];
+            ];
-    });
+        });
-    let max_erase_size = flash_memory_regions
+        let max_erase_size = flash_memory_regions
-        .iter()
+            .iter()
-        .map(|region| region.settings.as_ref().unwrap().erase_size)
+            .map(|region| region.settings.as_ref().unwrap().erase_size)
-        .max()
+            .max()
-        .unwrap();
+            .unwrap();
-    g.extend(quote! { pub const MAX_ERASE_SIZE: usize = #max_erase_size as usize; });
+        g.extend(quote! { pub const MAX_ERASE_SIZE: usize = #max_erase_size as usize; });
-    g.extend(quote! { pub mod flash_regions { #flash_regions } });
+        g.extend(quote! { pub mod flash_regions { #flash_regions } });
+    }
    // ========
    // Extract the rcc registers
@@ -1346,6 +1353,8 @@ fn main() {
    for p in METADATA.peripherals {
        if let Some(regs) = &p.registers {
+            let mut adc_pairs: BTreeMap<u8, (Option<Ident>, Option<Ident>)> = BTreeMap::new();
            for pin in p.pins {
                let key = (regs.kind, pin.signal);
                if let Some(tr) = signals.get(&key) {
@@ -1467,25 +1476,29 @@ fn main() {
                    };
                    // H7 has differential voltage measurements
-                    let ch: Option<u8> = if pin.signal.starts_with("INP") {
+                    let ch: Option<(u8, bool)> = if pin.signal.starts_with("INP") {
-                        Some(pin.signal.strip_prefix("INP").unwrap().parse().unwrap())
+                        Some((pin.signal.strip_prefix("INP").unwrap().parse().unwrap(), false))
                    } else if pin.signal.starts_with("INN") {
-                        // TODO handle in the future when embassy supports differential measurements
+                        Some((pin.signal.strip_prefix("INN").unwrap().parse().unwrap(), true))
-                        None
                    } else if pin.signal.starts_with("IN") && pin.signal.ends_with('b') {
                        // we number STM32L1 ADC bank 1 as 0..=31, bank 2 as 32..=63
                        let signal = pin.signal.strip_prefix("IN").unwrap().strip_suffix('b').unwrap();
-                        Some(32u8 + signal.parse::<u8>().unwrap())
+                        Some((32u8 + signal.parse::<u8>().unwrap(), false))
                    } else if pin.signal.starts_with("IN") {
-                        Some(pin.signal.strip_prefix("IN").unwrap().parse().unwrap())
+                        Some((pin.signal.strip_prefix("IN").unwrap().parse().unwrap(), false))
                    } else {
                        None
                    };
-                    if let Some(ch) = ch {
+                    if let Some((ch, false)) = ch {
+                        adc_pairs.entry(ch).or_insert((None, None)).0.replace(pin_name.clone());
                        g.extend(quote! {
                        impl_adc_pin!( #peri, #pin_name, #ch);
                        })
                    }
+                    if let Some((ch, true)) = ch {
+                        adc_pairs.entry(ch).or_insert((None, None)).1.replace(pin_name.clone());
+                    }
                }
                if regs.kind == "opamp" {
@@ -1524,6 +1537,23 @@ fn main() {
                    })
                }
            }
+            {
+                let peri = format_ident!("{}", p.name);
+                for (ch, (pin, npin)) in adc_pairs {
+                    let (pin_name, npin_name) = match (pin, npin) {
+                        (Some(pin), Some(npin)) => (pin, npin),
+                        _ => {
+                            continue;
+                        }
+                    };
+                    g.extend(quote! {
+                    impl_adc_pair!( #peri, #pin_name, #npin_name, #ch);
+                    })
+                }
+            }
        }
    }
@@ -1572,13 +1602,13 @@ fn main() {
    .into();
    if chip_name.starts_with("stm32u5") {
-        signals.insert(("adc", "ADC4"), quote!(crate::adc::RxDma4));
+        signals.insert(("adc", "ADC4"), quote!(crate::adc::RxDma));
    } else {
        signals.insert(("adc", "ADC4"), quote!(crate::adc::RxDma));
    }
    if chip_name.starts_with("stm32wba") {
-        signals.insert(("adc", "ADC4"), quote!(crate::adc::RxDma4));
+        signals.insert(("adc", "ADC4"), quote!(crate::adc::RxDma));
    }
    if chip_name.starts_with("stm32g4") {
@@ -1665,70 +1695,88 @@ fn main() {
    }
    // ========
-    // Generate Div/Mul impls for RCC prescalers/dividers/multipliers.
+    // Generate Div/Mul impls for RCC and ADC prescalers/dividers/multipliers.
-    for e in rcc_registers.ir.enums {
+    for (kind, psc_enums) in ["rcc", "adc", "adccommon"].iter().filter_map(|kind| {
-        fn is_rcc_name(e: &str) -> bool {
+        METADATA
-            match e {
+            .peripherals
-                "Pllp" | "Pllq" | "Pllr" | "Plldivst" | "Pllm" | "Plln" | "Prediv1" | "Prediv2" | "Hpre5" => true,
+            .iter()
-                "Timpre" | "Pllrclkpre" => false,
+            .filter_map(|p| p.registers.as_ref())
-                e if e.ends_with("pre") || e.ends_with("pres") || e.ends_with("div") || e.ends_with("mul") => true,
+            .find(|r| r.kind == *kind)
-                _ => false,
+            .map(|r| (*kind, r.ir.enums))
+    }) {
+        for e in psc_enums.iter() {
+            fn is_adc_name(e: &str) -> bool {
+                match e {
+                    "Presc" | "Adc4Presc" | "Adcpre" => true,
+                    _ => false,
+                }
            }
-        }
-        fn parse_num(n: &str) -> Result<Frac, ()> {
+            fn is_rcc_name(e: &str) -> bool {
-            for prefix in ["DIV", "MUL"] {
+                match e {
-                if let Some(n) = n.strip_prefix(prefix) {
+                    "Pllp" | "Pllq" | "Pllr" | "Plldivst" | "Pllm" | "Plln" | "Prediv1" | "Prediv2" | "Hpre5" => true,
-                    let exponent = n.find('_').map(|e| n.len() - 1 - e).unwrap_or(0) as u32;
+                    "Timpre" | "Pllrclkpre" => false,
-                    let mantissa = n.replace('_', "").parse().map_err(|_| ())?;
+                    e if e.ends_with("pre") || e.ends_with("pres") || e.ends_with("div") || e.ends_with("mul") => true,
-                    let f = Frac {
+                    _ => false,
-                        num: mantissa,
-                        denom: 10u32.pow(exponent),
-                    };
-                    return Ok(f.simplify());
                }
            }
-            Err(())
-        }
-        if is_rcc_name(e.name) {
+            fn parse_num(n: &str) -> Result<Frac, ()> {
-            let enum_name = format_ident!("{}", e.name);
+                for prefix in ["DIV", "MUL"] {
-            let mut muls = Vec::new();
+                    if let Some(n) = n.strip_prefix(prefix) {
-            let mut divs = Vec::new();
+                        let exponent = n.find('_').map(|e| n.len() - 1 - e).unwrap_or(0) as u32;
-            for v in e.variants {
+                        let mantissa = n.replace('_', "").parse().map_err(|_| ())?;
-                let Ok(val) = parse_num(v.name) else {
+                        let f = Frac {
-                    panic!("could not parse mul/div. enum={} variant={}", e.name, v.name)
+                            num: mantissa,
-                };
+                            denom: 10u32.pow(exponent),
-                let variant_name = format_ident!("{}", v.name);
+                        };
-                let variant = quote!(crate::pac::rcc::vals::#enum_name::#variant_name);
+                        return Ok(f.simplify());
-                let num = val.num;
+                    }
-                let denom = val.denom;
+                }
-                muls.push(quote!(#variant => self * #num / #denom,));
+                Err(())
-                divs.push(quote!(#variant => self * #denom / #num,));
            }
-            g.extend(quote! {
+            if (kind == "rcc" && is_rcc_name(e.name)) || ((kind == "adccommon" || kind == "adc") && is_adc_name(e.name))
-                impl core::ops::Div<crate::pac::rcc::vals::#enum_name> for crate::time::Hertz {
+            {
-                    type Output = crate::time::Hertz;
+                let kind = format_ident!("{}", kind);
-                    fn div(self, rhs: crate::pac::rcc::vals::#enum_name) -> Self::Output {
+                let enum_name = format_ident!("{}", e.name);
-                        match rhs {
+                let mut muls = Vec::new();
-                            #(#divs)*
+                let mut divs = Vec::new();
-                            #[allow(unreachable_patterns)]
+                for v in e.variants {
-                            _ => unreachable!(),
+                    let Ok(val) = parse_num(v.name) else {
+                        panic!("could not parse mul/div. enum={} variant={}", e.name, v.name)
+                    };
+                    let variant_name = format_ident!("{}", v.name);
+                    let variant = quote!(crate::pac::#kind::vals::#enum_name::#variant_name);
+                    let num = val.num;
+                    let denom = val.denom;
+                    muls.push(quote!(#variant => self * #num / #denom,));
+                    divs.push(quote!(#variant => self * #denom / #num,));
+                }
+                g.extend(quote! {
+                    impl core::ops::Div<crate::pac::#kind::vals::#enum_name> for crate::time::Hertz {
+                        type Output = crate::time::Hertz;
+                        fn div(self, rhs: crate::pac::#kind::vals::#enum_name) -> Self::Output {
+                            match rhs {
+                                #(#divs)*
+                                #[allow(unreachable_patterns)]
+                                _ => unreachable!(),
+                            }
                        }
                    }
-                }
+                    impl core::ops::Mul<crate::pac::#kind::vals::#enum_name> for crate::time::Hertz {
-                impl core::ops::Mul<crate::pac::rcc::vals::#enum_name> for crate::time::Hertz {
+                        type Output = crate::time::Hertz;
-                    type Output = crate::time::Hertz;
+                        fn mul(self, rhs: crate::pac::#kind::vals::#enum_name) -> Self::Output {
-                    fn mul(self, rhs: crate::pac::rcc::vals::#enum_name) -> Self::Output {
+                            match rhs {
-                        match rhs {
+                                #(#muls)*
-                            #(#muls)*
+                                #[allow(unreachable_patterns)]
-                            #[allow(unreachable_patterns)]
+                                _ => unreachable!(),
-                            _ => unreachable!(),
+                            }
                        }
                    }
-                }
+                });
-            });
+            }
        }
    }
@@ -1855,7 +1903,12 @@ fn main() {
            if r.kind == "dma" || r.kind == "bdma" || r.kind == "gpdma" || r.kind == "lpdma" {
                for irq in p.interrupts {
                    let ch_name = format!("{}_{}", p.name, irq.signal);
-                    let ch = METADATA.dma_channels.iter().find(|c| c.name == ch_name).unwrap();
+                    let ch = METADATA.dma_channels.iter().find(|c| c.name == ch_name);
+                    if ch.is_none() {
+                        continue;
+                    }
+                    let ch = ch.unwrap();
                    // Some H7 chips have BDMA1 hardcoded for DFSDM, ie no DMAMUX. It's unsupported, skip it.
                    if has_dmamux && ch.dmamux.is_none() {
@@ -2008,31 +2061,33 @@ fn main() {
    // ========
    // Generate flash constants
-    let flash_regions: Vec<&MemoryRegion> = memory
+    if has_flash {
-        .iter()
+        let flash_regions: Vec<&MemoryRegion> = memory
-        .filter(|x| x.kind == MemoryRegionKind::Flash && x.name.starts_with("BANK_"))
+            .iter()
-        .collect();
+            .filter(|x| x.kind == MemoryRegionKind::Flash && x.name.starts_with("BANK_"))
-    let first_flash = flash_regions.first().unwrap();
+            .collect();
-    let total_flash_size = flash_regions
+        let first_flash = flash_regions.first().unwrap();
-        .iter()
+        let total_flash_size = flash_regions
-        .map(|x| x.size)
+            .iter()
-        .reduce(|acc, item| acc + item)
+            .map(|x| x.size)
-        .unwrap();
+            .reduce(|acc, item| acc + item)
-    let write_sizes: HashSet<_> = flash_regions
+            .unwrap();
-        .iter()
+        let write_sizes: HashSet<_> = flash_regions
-        .map(|r| r.settings.as_ref().unwrap().write_size)
+            .iter()
-        .collect();
+            .map(|r| r.settings.as_ref().unwrap().write_size)
-    assert_eq!(1, write_sizes.len());
+            .collect();
+        assert_eq!(1, write_sizes.len());
-    let flash_base = first_flash.address as usize;
+        let flash_base = first_flash.address as usize;
-    let total_flash_size = total_flash_size as usize;
+        let total_flash_size = total_flash_size as usize;
-    let write_size = (*write_sizes.iter().next().unwrap()) as usize;
+        let write_size = (*write_sizes.iter().next().unwrap()) as usize;
-    g.extend(quote!(
+        g.extend(quote!(
-        pub const FLASH_BASE: usize = #flash_base;
+            pub const FLASH_BASE: usize = #flash_base;
-        pub const FLASH_SIZE: usize = #total_flash_size;
+            pub const FLASH_SIZE: usize = #total_flash_size;
-        pub const WRITE_SIZE: usize = #write_size;
+            pub const WRITE_SIZE: usize = #write_size;
-    ));
+        ));
+    }
    // ========
    // Generate EEPROM constants
diff --git a/embassy-stm32/src/adc/adc4.rs b/embassy-stm32/src/adc/adc4.rs
index 2608160a3..babdebfdb 100644
--- a/embassy-stm32/src/adc/adc4.rs
+++ b/embassy-stm32/src/adc/adc4.rs
@@ -4,8 +4,8 @@ use pac::adc::vals::{Adc4Dmacfg as Dmacfg, Adc4Exten as Exten, Adc4OversamplingR
 #[cfg(stm32wba)]
 use pac::adc::vals::{Chselrmod, Cont, Dmacfg, Exten, OversamplingRatio, Ovss, Smpsel};
-use super::{AdcChannel, AnyAdcChannel, RxDma4, SealedAdcChannel, blocking_delay_us};
+use super::blocking_delay_us;
-use crate::dma::Transfer;
+use crate::adc::ConversionMode;
 #[cfg(stm32u5)]
 pub use crate::pac::adc::regs::Adc4Chselrmod0 as Chselr;
 #[cfg(stm32wba)]
@@ -24,56 +24,24 @@ pub const VREF_DEFAULT_MV: u32 = 3300;
 /// VREF voltage used for factory calibration of VREFINTCAL register.
 pub const VREF_CALIB_MV: u32 = 3300;
-const VREF_CHANNEL: u8 = 0;
+impl<'d, T: Instance> super::SealedSpecialConverter<super::VrefInt> for Adc4<'d, T> {
-const VCORE_CHANNEL: u8 = 12;
+    const CHANNEL: u8 = 0;
-const TEMP_CHANNEL: u8 = 13;
-const VBAT_CHANNEL: u8 = 14;
-const DAC_CHANNEL: u8 = 21;
-// NOTE: Vrefint/Temperature/Vbat are not available on all ADCs, this currently cannot be modeled with stm32-data, so these are available from the software on all ADCs
-/// Internal voltage reference channel.
-pub struct VrefInt;
-impl<T: Instance> AdcChannel<T> for VrefInt {}
-impl<T: Instance> SealedAdcChannel<T> for VrefInt {
-    fn channel(&self) -> u8 {
-        VREF_CHANNEL
-    }
 }
-/// Internal temperature channel.
+impl<'d, T: Instance> super::SealedSpecialConverter<super::Temperature> for Adc4<'d, T> {
-pub struct Temperature;
+    const CHANNEL: u8 = 13;
-impl<T: Instance> AdcChannel<T> for Temperature {}
-impl<T: Instance> SealedAdcChannel<T> for Temperature {
-    fn channel(&self) -> u8 {
-        TEMP_CHANNEL
-    }
 }
-/// Internal battery voltage channel.
+impl<'d, T: Instance> super::SealedSpecialConverter<super::Vcore> for Adc4<'d, T> {
-pub struct Vbat;
+    const CHANNEL: u8 = 12;
-impl<T: Instance> AdcChannel<T> for Vbat {}
-impl<T: Instance> SealedAdcChannel<T> for Vbat {
-    fn channel(&self) -> u8 {
-        VBAT_CHANNEL
-    }
 }
-/// Internal DAC channel.
+impl<'d, T: Instance> super::SealedSpecialConverter<super::Vbat> for Adc4<'d, T> {
-pub struct Dac;
+    const CHANNEL: u8 = 14;
-impl<T: Instance> AdcChannel<T> for Dac {}
-impl<T: Instance> SealedAdcChannel<T> for Dac {
-    fn channel(&self) -> u8 {
-        DAC_CHANNEL
-    }
 }
-/// Internal Vcore channel.
+impl<'d, T: Instance> super::SealedSpecialConverter<super::Dac> for Adc4<'d, T> {
-pub struct Vcore;
+    const CHANNEL: u8 = 21;
-impl<T: Instance> AdcChannel<T> for Vcore {}
-impl<T: Instance> SealedAdcChannel<T> for Vcore {
-    fn channel(&self) -> u8 {
-        VCORE_CHANNEL
-    }
 }
 #[derive(Copy, Clone)]
@@ -108,71 +76,17 @@ pub const fn resolution_to_max_count(res: Resolution) -> u32 {
    }
 }
-// NOTE (unused): The prescaler enum closely copies the hardware capabilities,
+fn from_ker_ck(frequency: Hertz) -> Presc {
-// but high prescaling doesn't make a lot of sense in the current implementation and is ommited.
+    let raw_prescaler = frequency.0 / MAX_ADC_CLK_FREQ.0;
-#[allow(unused)]
+    match raw_prescaler {
-enum Prescaler {
+        0 => Presc::DIV1,
-    NotDivided,
+        1 => Presc::DIV2,
-    DividedBy2,
+        2..=3 => Presc::DIV4,
-    DividedBy4,
+        4..=5 => Presc::DIV6,
-    DividedBy6,
+        6..=7 => Presc::DIV8,
-    DividedBy8,
+        8..=9 => Presc::DIV10,
-    DividedBy10,
+        10..=11 => Presc::DIV12,
-    DividedBy12,
+        _ => unimplemented!(),
-    DividedBy16,
-    DividedBy32,
-    DividedBy64,
-    DividedBy128,
-    DividedBy256,
-}
-impl Prescaler {
-    fn from_ker_ck(frequency: Hertz) -> Self {
-        let raw_prescaler = frequency.0 / MAX_ADC_CLK_FREQ.0;
-        match raw_prescaler {
-            0 => Self::NotDivided,
-            1 => Self::DividedBy2,
-            2..=3 => Self::DividedBy4,
-            4..=5 => Self::DividedBy6,
-            6..=7 => Self::DividedBy8,
-            8..=9 => Self::DividedBy10,
-            10..=11 => Self::DividedBy12,
-            _ => unimplemented!(),
-        }
-    }
-    fn divisor(&self) -> u32 {
-        match self {
-            Prescaler::NotDivided => 1,
-            Prescaler::DividedBy2 => 2,
-            Prescaler::DividedBy4 => 4,
-            Prescaler::DividedBy6 => 6,
-            Prescaler::DividedBy8 => 8,
-            Prescaler::DividedBy10 => 10,
-            Prescaler::DividedBy12 => 12,
-            Prescaler::DividedBy16 => 16,
-            Prescaler::DividedBy32 => 32,
-            Prescaler::DividedBy64 => 64,
-            Prescaler::DividedBy128 => 128,
-            Prescaler::DividedBy256 => 256,
-        }
-    }
-    fn presc(&self) -> Presc {
-        match self {
-            Prescaler::NotDivided => Presc::DIV1,
-            Prescaler::DividedBy2 => Presc::DIV2,
-            Prescaler::DividedBy4 => Presc::DIV4,
-            Prescaler::DividedBy6 => Presc::DIV6,
-            Prescaler::DividedBy8 => Presc::DIV8,
-            Prescaler::DividedBy10 => Presc::DIV10,
-            Prescaler::DividedBy12 => Presc::DIV12,
-            Prescaler::DividedBy16 => Presc::DIV16,
-            Prescaler::DividedBy32 => Presc::DIV32,
-            Prescaler::DividedBy64 => Presc::DIV64,
-            Prescaler::DividedBy128 => Presc::DIV128,
-            Prescaler::DividedBy256 => Presc::DIV256,
-        }
    }
 }
@@ -185,6 +99,122 @@ pub trait Instance: SealedInstance + crate::PeripheralType + crate::rcc::RccPeri
    type Interrupt: crate::interrupt::typelevel::Interrupt;
 }
+foreach_adc!(
+    (ADC4, $common_inst:ident, $clock:ident) => {
+        use crate::peripherals::ADC4;
+        impl super::BasicAnyInstance for ADC4 {
+            type SampleTime = SampleTime;
+        }
+        impl super::SealedAnyInstance for ADC4 {
+            fn dr() -> *mut u16 {
+                ADC4::regs().dr().as_ptr() as *mut u16
+            }
+            fn enable() {
+                ADC4::regs().isr().write(|w| w.set_adrdy(true));
+                ADC4::regs().cr().modify(|w| w.set_aden(true));
+                while !ADC4::regs().isr().read().adrdy() {}
+                ADC4::regs().isr().write(|w| w.set_adrdy(true));
+            }
+            fn start() {
+                // Start conversion
+                ADC4::regs().cr().modify(|reg| {
+                    reg.set_adstart(true);
+                });
+            }
+            fn stop() {
+                if ADC4::regs().cr().read().adstart() && !ADC4::regs().cr().read().addis() {
+                    ADC4::regs().cr().modify(|reg| {
+                        reg.set_adstp(true);
+                    });
+                    while ADC4::regs().cr().read().adstart() {}
+                }
+                // Reset configuration.
+                ADC4::regs().cfgr1().modify(|reg| {
+                    reg.set_dmaen(false);
+                });
+            }
+            fn configure_dma(conversion_mode: ConversionMode) {
+                match conversion_mode {
+                    ConversionMode::Singular => {
+                        ADC4::regs().isr().modify(|reg| {
+                            reg.set_ovr(true);
+                            reg.set_eos(true);
+                            reg.set_eoc(true);
+                        });
+                        ADC4::regs().cfgr1().modify(|reg| {
+                            reg.set_dmaen(true);
+                            reg.set_dmacfg(Dmacfg::ONE_SHOT);
+                            #[cfg(stm32u5)]
+                            reg.set_chselrmod(false);
+                            #[cfg(stm32wba)]
+                            reg.set_chselrmod(Chselrmod::ENABLE_INPUT)
+                        });
+                    }
+                    #[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
+                    _ => unreachable!(),
+                }
+            }
+            fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
+                let mut prev_channel: i16 = -1;
+                #[cfg(stm32wba)]
+                ADC4::regs().chselr().write_value(Chselr(0_u32));
+                #[cfg(stm32u5)]
+                ADC4::regs().chselrmod0().write_value(Chselr(0_u32));
+                for (_i, ((channel, _), sample_time)) in sequence.enumerate() {
+                    ADC4::regs().smpr().modify(|w| {
+                        w.set_smp(_i, sample_time);
+                    });
+                    let channel_num = channel;
+                    if channel_num as i16 <= prev_channel {
+                        return;
+                    };
+                    prev_channel = channel_num as i16;
+                    #[cfg(stm32wba)]
+                    ADC4::regs().chselr().modify(|w| {
+                        w.set_chsel0(channel as usize, true);
+                    });
+                    #[cfg(stm32u5)]
+                    ADC4::regs().chselrmod0().modify(|w| {
+                        w.set_chsel(channel as usize, true);
+                    });
+                }
+            }
+            fn convert() -> u16 {
+                // Reset interrupts
+                ADC4::regs().isr().modify(|reg| {
+                    reg.set_eos(true);
+                    reg.set_eoc(true);
+                });
+                // Start conversion
+                ADC4::regs().cr().modify(|reg| {
+                    reg.set_adstart(true);
+                });
+                while !ADC4::regs().isr().read().eos() {
+                    // spin
+                }
+                ADC4::regs().dr().read().0 as u16
+            }
+        }
+        impl super::AnyInstance for ADC4 {}
+    };
+);
 pub struct Adc4<'d, T: Instance> {
    #[allow(unused)]
    adc: crate::Peri<'d, T>,
@@ -196,15 +226,15 @@ pub enum Adc4Error {
    DMAError,
 }
-impl<'d, T: Instance> Adc4<'d, T> {
+impl<'d, T: Instance + super::AnyInstance> super::Adc<'d, T> {
    /// Create a new ADC driver.
-    pub fn new(adc: Peri<'d, T>) -> Self {
+    pub fn new_adc4(adc: Peri<'d, T>) -> Self {
        rcc::enable_and_reset::<T>();
-        let prescaler = Prescaler::from_ker_ck(T::frequency());
+        let prescaler = from_ker_ck(T::frequency());
-        T::regs().ccr().modify(|w| w.set_presc(prescaler.presc()));
+        T::regs().ccr().modify(|w| w.set_presc(prescaler));
-        let frequency = Hertz(T::frequency().0 / prescaler.divisor());
+        let frequency = T::frequency() / prescaler;
        info!("ADC4 frequency set to {}", frequency);
        if frequency > MAX_ADC_CLK_FREQ {
@@ -214,20 +244,6 @@ impl<'d, T: Instance> Adc4<'d, T> {
            );
        }
-        let mut s = Self { adc };
-        s.power_up();
-        s.calibrate();
-        blocking_delay_us(1);
-        s.enable();
-        s.configure();
-        s
-    }
-    fn power_up(&mut self) {
        T::regs().isr().modify(|w| {
            w.set_ldordy(true);
        });
@@ -239,22 +255,15 @@ impl<'d, T: Instance> Adc4<'d, T> {
        T::regs().isr().modify(|w| {
            w.set_ldordy(true);
        });
-    }
-    fn calibrate(&mut self) {
        T::regs().cr().modify(|w| w.set_adcal(true));
        while T::regs().cr().read().adcal() {}
        T::regs().isr().modify(|w| w.set_eocal(true));
-    }
-    fn enable(&mut self) {
+        blocking_delay_us(1);
-        T::regs().isr().write(|w| w.set_adrdy(true));
-        T::regs().cr().modify(|w| w.set_aden(true));
+        T::enable();
-        while !T::regs().isr().read().adrdy() {}
-        T::regs().isr().write(|w| w.set_adrdy(true));
-    }
-    fn configure(&mut self) {
        // single conversion mode, software trigger
        T::regs().cfgr1().modify(|w| {
            #[cfg(stm32u5)]
@@ -280,73 +289,63 @@ impl<'d, T: Instance> Adc4<'d, T> {
                w.set_smpsel(i, Smpsel::SMP1);
            }
        });
+        Self { adc }
    }
    /// Enable reading the voltage reference internal channel.
-    pub fn enable_vrefint(&self) -> VrefInt {
+    pub fn enable_vrefint_adc4(&self) -> super::VrefInt {
        T::regs().ccr().modify(|w| {
            w.set_vrefen(true);
        });
-        VrefInt {}
+        super::VrefInt {}
    }
    /// Enable reading the temperature internal channel.
-    pub fn enable_temperature(&self) -> Temperature {
+    pub fn enable_temperature_adc4(&self) -> super::Temperature {
        T::regs().ccr().modify(|w| {
            w.set_vsensesel(true);
        });
-        Temperature {}
+        super::Temperature {}
    }
    /// Enable reading the vbat internal channel.
    #[cfg(stm32u5)]
-    pub fn enable_vbat(&self) -> Vbat {
+    pub fn enable_vbat_adc4(&self) -> super::Vbat {
        T::regs().ccr().modify(|w| {
            w.set_vbaten(true);
        });
-        Vbat {}
+        super::Vbat {}
    }
    /// Enable reading the vbat internal channel.
-    pub fn enable_vcore(&self) -> Vcore {
+    pub fn enable_vcore_adc4(&self) -> super::Vcore {
-        Vcore {}
+        super::Vcore {}
    }
    /// Enable reading the vbat internal channel.
    #[cfg(stm32u5)]
-    pub fn enable_dac_channel(&self, dac: DacChannel) -> Dac {
+    pub fn enable_dac_channel_adc4(&self, dac: DacChannel) -> super::Dac {
        let mux;
        match dac {
            DacChannel::OUT1 => mux = false,
            DacChannel::OUT2 => mux = true,
        }
        T::regs().or().modify(|w| w.set_chn21sel(mux));
-        Dac {}
+        super::Dac {}
-    }
-    /// Set the ADC sample time.
-    pub fn set_sample_time(&mut self, sample_time: SampleTime) {
-        T::regs().smpr().modify(|w| {
-            w.set_smp(0, sample_time);
-        });
-    }
-    /// Get the ADC sample time.
-    pub fn sample_time(&self) -> SampleTime {
-        T::regs().smpr().read().smp(0)
    }
    /// Set the ADC resolution.
-    pub fn set_resolution(&mut self, resolution: Resolution) {
+    pub fn set_resolution_adc4(&mut self, resolution: Resolution) {
        T::regs().cfgr1().modify(|w| w.set_res(resolution.into()));
    }
    /// Set hardware averaging.
    #[cfg(stm32u5)]
-    pub fn set_averaging(&mut self, averaging: Averaging) {
+    pub fn set_averaging_adc4(&mut self, averaging: Averaging) {
        let (enable, samples, right_shift) = match averaging {
            Averaging::Disabled => (false, OversamplingRatio::OVERSAMPLE2X, 0),
            Averaging::Samples2 => (true, OversamplingRatio::OVERSAMPLE2X, 1),
@@ -366,7 +365,7 @@ impl<'d, T: Instance> Adc4<'d, T> {
        })
    }
    #[cfg(stm32wba)]
-    pub fn set_averaging(&mut self, averaging: Averaging) {
+    pub fn set_averaging_adc4(&mut self, averaging: Averaging) {
        let (enable, samples, right_shift) = match averaging {
            Averaging::Disabled => (false, OversamplingRatio::OVERSAMPLE2X, Ovss::SHIFT0),
            Averaging::Samples2 => (true, OversamplingRatio::OVERSAMPLE2X, Ovss::SHIFT1),
@@ -385,164 +384,4 @@ impl<'d, T: Instance> Adc4<'d, T> {
            w.set_ovse(enable)
        })
    }
-    /// Read an ADC channel.
-    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
-        channel.setup();
-        // Select channel
-        #[cfg(stm32wba)]
-        {
-            T::regs().chselr().write_value(Chselr(0_u32));
-            T::regs().chselr().modify(|w| {
-                w.set_chsel0(channel.channel() as usize, true);
-            });
-        }
-        #[cfg(stm32u5)]
-        {
-            T::regs().chselrmod0().write_value(Chselr(0_u32));
-            T::regs().chselrmod0().modify(|w| {
-                w.set_chsel(channel.channel() as usize, true);
-            });
-        }
-        // Reset interrupts
-        T::regs().isr().modify(|reg| {
-            reg.set_eos(true);
-            reg.set_eoc(true);
-        });
-        // Start conversion
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
-        });
-        while !T::regs().isr().read().eos() {
-            // spin
-        }
-        T::regs().dr().read().0 as u16
-    }
-    /// Read one or multiple ADC channels using DMA.
-    ///
-    /// `sequence` iterator and `readings` must have the same length.
-    /// The channels in `sequence` must be in ascending order.
-    ///
-    /// Example
-    /// ```rust,ignore
-    /// use embassy_stm32::adc::adc4;
-    /// use embassy_stm32::adc::AdcChannel;
-    ///
-    /// let mut adc4 = adc4::Adc4::new(p.ADC4);
-    /// let mut adc4_pin1 = p.PC1;
-    /// let mut adc4_pin2 = p.PC0;
-    /// let mut.into()d41 = adc4_pin1.into();
-    /// let mut.into()d42 = adc4_pin2.into();
-    /// let mut measurements = [0u16; 2];
-    /// // not that the channels must be in ascending order
-    /// adc4.read(
-    ///     &mut p.GPDMA1_CH1,
-    ///    [
-    ///        &mut.into()d42,
-    ///        &mut.into()d41,
-    ///    ]
-    ///    .into_iter(),
-    ///    &mut measurements,
-    /// ).await.unwrap();
-    /// ```
-    pub async fn read(
-        &mut self,
-        rx_dma: Peri<'_, impl RxDma4<T>>,
-        sequence: impl ExactSizeIterator<Item = &mut AnyAdcChannel<T>>,
-        readings: &mut [u16],
-    ) -> Result<(), Adc4Error> {
-        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
-        assert!(
-            sequence.len() == readings.len(),
-            "Sequence length must be equal to readings length"
-        );
-        // Ensure no conversions are ongoing
-        Self::cancel_conversions();
-        T::regs().isr().modify(|reg| {
-            reg.set_ovr(true);
-            reg.set_eos(true);
-            reg.set_eoc(true);
-        });
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_dmaen(true);
-            reg.set_dmacfg(Dmacfg::ONE_SHOT);
-            #[cfg(stm32u5)]
-            reg.set_chselrmod(false);
-            #[cfg(stm32wba)]
-            reg.set_chselrmod(Chselrmod::ENABLE_INPUT)
-        });
-        // Verify and activate sequence
-        let mut prev_channel: i16 = -1;
-        #[cfg(stm32wba)]
-        T::regs().chselr().write_value(Chselr(0_u32));
-        #[cfg(stm32u5)]
-        T::regs().chselrmod0().write_value(Chselr(0_u32));
-        for channel in sequence {
-            let channel_num = channel.channel;
-            if channel_num as i16 <= prev_channel {
-                return Err(Adc4Error::InvalidSequence);
-            };
-            prev_channel = channel_num as i16;
-            #[cfg(stm32wba)]
-            T::regs().chselr().modify(|w| {
-                w.set_chsel0(channel.channel as usize, true);
-            });
-            #[cfg(stm32u5)]
-            T::regs().chselrmod0().modify(|w| {
-                w.set_chsel(channel.channel as usize, true);
-            });
-        }
-        let request = rx_dma.request();
-        let transfer = unsafe {
-            Transfer::new_read(
-                rx_dma,
-                request,
-                T::regs().dr().as_ptr() as *mut u16,
-                readings,
-                Default::default(),
-            )
-        };
-        // Start conversion
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
-        });
-        transfer.await;
-        // Ensure conversions are finished.
-        Self::cancel_conversions();
-        // Reset configuration.
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_dmaen(false);
-        });
-        if T::regs().isr().read().ovr() {
-            Err(Adc4Error::DMAError)
-        } else {
-            Ok(())
-        }
-    }
-    fn cancel_conversions() {
-        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
-            T::regs().cr().modify(|reg| {
-                reg.set_adstp(true);
-            });
-            while T::regs().cr().read().adstart() {}
-        }
-    }
 }
diff --git a/embassy-stm32/src/adc/c0.rs b/embassy-stm32/src/adc/c0.rs
index fc28df346..d87bd1ed4 100644
--- a/embassy-stm32/src/adc/c0.rs
+++ b/embassy-stm32/src/adc/c0.rs
@@ -1,12 +1,10 @@
-use pac::adc::vals::Scandir;
 #[allow(unused)]
 use pac::adc::vals::{Adstp, Align, Ckmode, Dmacfg, Exten, Ovrmod, Ovsr};
 use pac::adccommon::vals::Presc;
+use stm32_metapac::adc::vals::{SampleTime, Scandir};
-use super::{
+use super::{Adc, Instance, Resolution, blocking_delay_us};
-    Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel, blocking_delay_us,
+use crate::adc::{AnyInstance, ConversionMode};
-};
-use crate::dma::Transfer;
 use crate::time::Hertz;
 use crate::{Peri, pac, rcc};
@@ -19,152 +17,181 @@ const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(25);
 const TIME_ADC_VOLTAGE_REGUALTOR_STARTUP_US: u32 = 20;
-const TEMP_CHANNEL: u8 = 9;
-const VREF_CHANNEL: u8 = 10;
-const NUM_HW_CHANNELS: u8 = 22;
 const CHSELR_SQ_SIZE: usize = 8;
 const CHSELR_SQ_MAX_CHANNEL: u8 = 14;
 const CHSELR_SQ_SEQUENCE_END_MARKER: u8 = 0b1111;
-// NOTE: Vrefint/Temperature/Vbat are not available on all ADCs,
+impl<T: Instance> super::SealedSpecialConverter<super::VrefInt> for T {
-// this currently cannot be modeled with stm32-data,
+    const CHANNEL: u8 = 10;
-// so these are available from the software on all ADCs.
-/// Internal voltage reference channel.
-pub struct VrefInt;
-impl<T: Instance> AdcChannel<T> for VrefInt {}
-impl<T: Instance> SealedAdcChannel<T> for VrefInt {
-    fn channel(&self) -> u8 {
-        VREF_CHANNEL
-    }
 }
-/// Internal temperature channel.
+impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
-pub struct Temperature;
+    const CHANNEL: u8 = 9;
-impl<T: Instance> AdcChannel<T> for Temperature {}
-impl<T: Instance> SealedAdcChannel<T> for Temperature {
-    fn channel(&self) -> u8 {
-        TEMP_CHANNEL
-    }
 }
-#[derive(Copy, Clone, Debug)]
+fn from_ker_ck(frequency: Hertz) -> Presc {
-pub enum Prescaler {
+    let raw_prescaler = frequency.0 / MAX_ADC_CLK_FREQ.0;
-    NotDivided,
+    match raw_prescaler {
-    DividedBy2,
+        0 => Presc::DIV1,
-    DividedBy4,
+        1 => Presc::DIV2,
-    DividedBy6,
+        2..=3 => Presc::DIV4,
-    DividedBy8,
+        4..=5 => Presc::DIV6,
-    DividedBy10,
+        6..=7 => Presc::DIV8,
-    DividedBy12,
+        8..=9 => Presc::DIV10,
-    DividedBy16,
+        10..=11 => Presc::DIV12,
-    DividedBy32,
+        _ => unimplemented!(),
-    DividedBy64,
+    }
-    DividedBy128,
-    DividedBy256,
 }
-impl Prescaler {
+impl<T: Instance> super::SealedAnyInstance for T {
-    fn from_ker_ck(frequency: Hertz) -> Self {
+    fn dr() -> *mut u16 {
-        let raw_prescaler = frequency.0 / MAX_ADC_CLK_FREQ.0;
+        T::regs().dr().as_ptr() as *mut u16
-        match raw_prescaler {
+    }
-            0 => Self::NotDivided,
-            1 => Self::DividedBy2,
+    fn enable() {
-            2..=3 => Self::DividedBy4,
+        T::regs().isr().modify(|w| w.set_adrdy(true));
-            4..=5 => Self::DividedBy6,
+        T::regs().cr().modify(|w| w.set_aden(true));
-            6..=7 => Self::DividedBy8,
+        // ADRDY is "ADC ready". Wait until it will be True.
-            8..=9 => Self::DividedBy10,
+        while !T::regs().isr().read().adrdy() {}
-            10..=11 => Self::DividedBy12,
+    }
-            _ => unimplemented!(),
-        }
+    fn start() {
+        // Start conversion
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
    }
-    #[allow(unused)]
+    fn stop() {
-    fn divisor(&self) -> u32 {
+        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
-        match self {
+            T::regs().cr().modify(|reg| {
-            Prescaler::NotDivided => 1,
+                reg.set_adstp(Adstp::STOP);
-            Prescaler::DividedBy2 => 2,
+            });
-            Prescaler::DividedBy4 => 4,
+            while T::regs().cr().read().adstart() {}
-            Prescaler::DividedBy6 => 6,
-            Prescaler::DividedBy8 => 8,
-            Prescaler::DividedBy10 => 10,
-            Prescaler::DividedBy12 => 12,
-            Prescaler::DividedBy16 => 16,
-            Prescaler::DividedBy32 => 32,
-            Prescaler::DividedBy64 => 64,
-            Prescaler::DividedBy128 => 128,
-            Prescaler::DividedBy256 => 256,
        }
+        // Reset configuration.
+        T::regs().cfgr1().modify(|reg| {
+            reg.set_cont(false);
+            reg.set_dmacfg(Dmacfg::from_bits(0));
+            reg.set_dmaen(false);
+        });
    }
-    fn presc(&self) -> Presc {
+    fn configure_dma(conversion_mode: super::ConversionMode) {
-        match self {
+        match conversion_mode {
-            Prescaler::NotDivided => Presc::DIV1,
+            ConversionMode::Singular => {
-            Prescaler::DividedBy2 => Presc::DIV2,
+                // Enable overrun control, so no new DMA requests will be generated until
-            Prescaler::DividedBy4 => Presc::DIV4,
+                // previous DR values is read.
-            Prescaler::DividedBy6 => Presc::DIV6,
+                T::regs().isr().modify(|reg| {
-            Prescaler::DividedBy8 => Presc::DIV8,
+                    reg.set_ovr(true);
-            Prescaler::DividedBy10 => Presc::DIV10,
+                });
-            Prescaler::DividedBy12 => Presc::DIV12,
-            Prescaler::DividedBy16 => Presc::DIV16,
+                // Set continuous mode with oneshot dma.
-            Prescaler::DividedBy32 => Presc::DIV32,
+                T::regs().cfgr1().modify(|reg| {
-            Prescaler::DividedBy64 => Presc::DIV64,
+                    reg.set_discen(false);
-            Prescaler::DividedBy128 => Presc::DIV128,
+                    reg.set_cont(true);
-            Prescaler::DividedBy256 => Presc::DIV256,
+                    reg.set_dmacfg(Dmacfg::DMA_ONE_SHOT);
+                    reg.set_dmaen(true);
+                    reg.set_ovrmod(Ovrmod::PRESERVE);
+                });
+            }
        }
    }
-}
-#[cfg(feature = "defmt")]
+    fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), Self::SampleTime)>) {
-impl<'a> defmt::Format for Prescaler {
+        let mut needs_hw = sequence.len() == 1 || sequence.len() > CHSELR_SQ_SIZE;
-    fn format(&self, fmt: defmt::Formatter) {
+        let mut is_ordered_up = true;
-        match self {
+        let mut is_ordered_down = true;
-            Prescaler::NotDivided => defmt::write!(fmt, "Prescaler::NotDivided"),
-            Prescaler::DividedBy2 => defmt::write!(fmt, "Prescaler::DividedBy2"),
+        let sequence_len = sequence.len();
-            Prescaler::DividedBy4 => defmt::write!(fmt, "Prescaler::DividedBy4"),
+        let mut hw_channel_selection: u32 = 0;
-            Prescaler::DividedBy6 => defmt::write!(fmt, "Prescaler::DividedBy6"),
+        let mut last_channel: u8 = 0;
-            Prescaler::DividedBy8 => defmt::write!(fmt, "Prescaler::DividedBy8"),
+        let mut sample_time: Self::SampleTime = SampleTime::CYCLES2_5;
-            Prescaler::DividedBy10 => defmt::write!(fmt, "Prescaler::DividedBy10"),
-            Prescaler::DividedBy12 => defmt::write!(fmt, "Prescaler::DividedBy12"),
+        T::regs().chselr_sq().write(|w| {
-            Prescaler::DividedBy16 => defmt::write!(fmt, "Prescaler::DividedBy16"),
+            for (i, ((channel, _), _sample_time)) in sequence.enumerate() {
-            Prescaler::DividedBy32 => defmt::write!(fmt, "Prescaler::DividedBy32"),
+                assert!(
-            Prescaler::DividedBy64 => defmt::write!(fmt, "Prescaler::DividedBy64"),
+                    sample_time == _sample_time || i == 0,
-            Prescaler::DividedBy128 => defmt::write!(fmt, "Prescaler::DividedBy128"),
+                    "C0 only supports one sample time for the sequence."
-            Prescaler::DividedBy256 => defmt::write!(fmt, "Prescaler::DividedBy256"),
+                );
+                sample_time = _sample_time;
+                needs_hw = needs_hw || channel > CHSELR_SQ_MAX_CHANNEL;
+                is_ordered_up = is_ordered_up && (channel > last_channel || i == 0);
+                is_ordered_down = is_ordered_down && (channel < last_channel || i == 0);
+                hw_channel_selection += 1 << channel;
+                last_channel = channel;
+                if !needs_hw {
+                    w.set_sq(i, channel);
+                }
+            }
+            for i in sequence_len..CHSELR_SQ_SIZE {
+                w.set_sq(i, CHSELR_SQ_SEQUENCE_END_MARKER);
+            }
+        });
+        if needs_hw {
+            assert!(
+                sequence_len <= CHSELR_SQ_SIZE || is_ordered_up || is_ordered_down,
+                "Sequencer is required because of unordered channels, but read set cannot be more than {} in size.",
+                CHSELR_SQ_SIZE
+            );
+            assert!(
+                sequence_len > CHSELR_SQ_SIZE || is_ordered_up || is_ordered_down,
+                "Sequencer is required because of unordered channels, but only support HW channels smaller than {}.",
+                CHSELR_SQ_MAX_CHANNEL
+            );
+            // Set required channels for multi-convert.
+            unsafe { (T::regs().chselr().as_ptr() as *mut u32).write_volatile(hw_channel_selection) }
        }
+        T::regs().smpr().modify(|w| {
+            w.smpsel(0);
+            w.set_smp1(sample_time);
+        });
+        T::regs().cfgr1().modify(|reg| {
+            reg.set_chselrmod(!needs_hw);
+            reg.set_align(Align::RIGHT);
+            reg.set_scandir(if is_ordered_up { Scandir::UP } else { Scandir::BACK });
+        });
+        // Trigger and wait for the channel selection procedure to complete.
+        T::regs().isr().modify(|w| w.set_ccrdy(false));
+        while !T::regs().isr().read().ccrdy() {}
    }
-}
-/// Number of samples used for averaging.
+    fn convert() -> u16 {
-/// TODO: Implement hardware averaging setting.
+        // Set single conversion mode.
-#[allow(unused)]
+        T::regs().cfgr1().modify(|w| w.set_cont(false));
-#[derive(Copy, Clone, Debug)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+        // Start conversion
-pub enum Averaging {
+        T::regs().cr().modify(|reg| {
-    Disabled,
+            reg.set_adstart(true);
-    Samples2,
+        });
-    Samples4,
-    Samples8,
+        // Waiting for End Of Conversion (EOC).
-    Samples16,
+        while !T::regs().isr().read().eoc() {}
-    Samples32,
-    Samples64,
+        T::regs().dr().read().data() as u16
-    Samples128,
+    }
-    Samples256,
-    Samples512,
-    Samples1024,
 }
-impl<'d, T: Instance> Adc<'d, T> {
+impl<'d, T: AnyInstance> Adc<'d, T> {
    /// Create a new ADC driver.
-    pub fn new(adc: Peri<'d, T>, sample_time: SampleTime, resolution: Resolution) -> Self {
+    pub fn new(adc: Peri<'d, T>, resolution: Resolution) -> Self {
        rcc::enable_and_reset::<T>();
        T::regs().cfgr2().modify(|w| w.set_ckmode(Ckmode::SYSCLK));
-        let prescaler = Prescaler::from_ker_ck(T::frequency());
+        let prescaler = from_ker_ck(T::frequency());
-        T::common_regs().ccr().modify(|w| w.set_presc(prescaler.presc()));
+        T::common_regs().ccr().modify(|w| w.set_presc(prescaler));
-        let frequency = Hertz(T::frequency().0 / prescaler.divisor());
+        let frequency = T::frequency() / prescaler;
        debug!("ADC frequency set to {}", frequency);
        if frequency > MAX_ADC_CLK_FREQ {
@@ -174,37 +201,16 @@ impl<'d, T: Instance> Adc<'d, T> {
            );
        }
-        let mut s = Self {
-            adc,
-            sample_time: SampleTime::from_bits(0),
-        };
-        s.power_up();
-        s.set_resolution(resolution);
-        s.calibrate();
-        s.enable();
-        s.configure_default();
-        s.set_sample_time_all_channels(sample_time);
-        s
-    }
-    fn power_up(&mut self) {
        T::regs().cr().modify(|reg| {
            reg.set_advregen(true);
        });
        // "The software must wait for the ADC voltage regulator startup time."
        // See datasheet for the value.
-        blocking_delay_us(TIME_ADC_VOLTAGE_REGUALTOR_STARTUP_US + 1);
+        blocking_delay_us(TIME_ADC_VOLTAGE_REGUALTOR_STARTUP_US as u64 + 1);
-    }
+        T::regs().cfgr1().modify(|reg| reg.set_res(resolution));
-    fn calibrate(&mut self) {
        // We have to make sure AUTOFF is OFF, but keep its value after calibration.
        let autoff_value = T::regs().cfgr1().read().autoff();
        T::regs().cfgr1().modify(|w| w.set_autoff(false));
@@ -218,255 +224,35 @@ impl<'d, T: Instance> Adc<'d, T> {
        debug!("ADC calibration value: {}.", T::regs().dr().read().data());
        T::regs().cfgr1().modify(|w| w.set_autoff(autoff_value));
-    }
-    fn enable(&mut self) {
+        T::enable();
-        T::regs().isr().modify(|w| w.set_adrdy(true));
-        T::regs().cr().modify(|w| w.set_aden(true));
-        // ADRDY is "ADC ready". Wait until it will be True.
-        while !T::regs().isr().read().adrdy() {}
-    }
-    fn configure_default(&mut self) {
        // single conversion mode, software trigger
        T::regs().cfgr1().modify(|w| {
            w.set_cont(false);
            w.set_exten(Exten::DISABLED);
            w.set_align(Align::RIGHT);
        });
+        Self { adc }
    }
    /// Enable reading the voltage reference internal channel.
-    pub fn enable_vrefint(&self) -> VrefInt {
+    pub fn enable_vrefint(&self) -> super::VrefInt {
        T::common_regs().ccr().modify(|reg| {
            reg.set_vrefen(true);
        });
-        VrefInt {}
+        super::VrefInt {}
    }
    /// Enable reading the temperature internal channel.
-    pub fn enable_temperature(&self) -> Temperature {
+    pub fn enable_temperature(&self) -> super::Temperature {
        debug!("Ensure that sample time is set to more than temperature sensor T_start from the datasheet!");
        T::common_regs().ccr().modify(|reg| {
            reg.set_tsen(true);
        });
-        Temperature {}
+        super::Temperature {}
-    }
-    /// Set the ADC sample time.
-    /// Shall only be called when ADC is not converting.
-    pub fn set_sample_time_all_channels(&mut self, sample_time: SampleTime) {
-        self.sample_time = sample_time;
-        // Set all channels to use SMP1 field as source.
-        T::regs().smpr().modify(|w| {
-            w.smpsel(0);
-            w.set_smp1(sample_time);
-        });
-    }
-    /// Set the ADC resolution.
-    pub fn set_resolution(&mut self, resolution: Resolution) {
-        T::regs().cfgr1().modify(|reg| reg.set_res(resolution));
-    }
-    /// Perform a single conversion.
-    fn convert(&mut self) -> u16 {
-        // Set single conversion mode.
-        T::regs().cfgr1().modify(|w| w.set_cont(false));
-        // Start conversion
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
-        });
-        // Waiting for End Of Conversion (EOC).
-        while !T::regs().isr().read().eoc() {}
-        T::regs().dr().read().data() as u16
-    }
-    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
-        Self::configure_channel(channel);
-        T::regs().cfgr1().write(|reg| {
-            reg.set_chselrmod(false);
-            reg.set_align(Align::RIGHT);
-        });
-        self.convert()
-    }
-    fn setup_channel_sequencer<'a>(channel_sequence: impl ExactSizeIterator<Item = &'a mut AnyAdcChannel<T>>) {
-        assert!(
-            channel_sequence.len() <= CHSELR_SQ_SIZE,
-            "Seqenced read set cannot be more than {} in size.",
-            CHSELR_SQ_SIZE
-        );
-        let mut last_sq_set: usize = 0;
-        T::regs().chselr_sq().write(|w| {
-            for (i, channel) in channel_sequence.enumerate() {
-                assert!(
-                    channel.channel() <= CHSELR_SQ_MAX_CHANNEL,
-                    "Sequencer only support HW channels smaller than {}.",
-                    CHSELR_SQ_MAX_CHANNEL
-                );
-                w.set_sq(i, channel.channel());
-                last_sq_set = i;
-            }
-            for i in (last_sq_set + 1)..CHSELR_SQ_SIZE {
-                w.set_sq(i, CHSELR_SQ_SEQUENCE_END_MARKER);
-            }
-        });
-        Self::apply_channel_conf()
-    }
-    async fn dma_convert(&mut self, rx_dma: Peri<'_, impl RxDma<T>>, readings: &mut [u16]) {
-        // Enable overrun control, so no new DMA requests will be generated until
-        // previous DR values is read.
-        T::regs().isr().modify(|reg| {
-            reg.set_ovr(true);
-        });
-        // Set continuous mode with oneshot dma.
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_discen(false);
-            reg.set_cont(true);
-            reg.set_dmacfg(Dmacfg::DMA_ONE_SHOT);
-            reg.set_dmaen(true);
-            reg.set_ovrmod(Ovrmod::PRESERVE);
-        });
-        let request = rx_dma.request();
-        let transfer = unsafe {
-            Transfer::new_read(
-                rx_dma,
-                request,
-                T::regs().dr().as_ptr() as *mut u16,
-                readings,
-                Default::default(),
-            )
-        };
-        // Start conversion.
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
-        });
-        // Wait for conversion sequence to finish.
-        transfer.await;
-        // Ensure conversions are finished.
-        Self::cancel_conversions();
-        // Reset configuration.
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_cont(false);
-            reg.set_dmacfg(Dmacfg::from_bits(0));
-            reg.set_dmaen(false);
-        });
-    }
-    /// Read one or multiple ADC channels using DMA in hardware order.
-    /// Readings will be ordered based on **hardware** ADC channel number and `scandir` setting.
-    /// Readings won't be in the same order as in the `set`!
-    ///
-    /// In STM32C0, channels bigger than 14 cannot be read using sequencer, so you have to use
-    /// either blocking reads or use the mechanism to read in HW order (CHSELRMOD=0).
-    /// TODO(chudsaviet): externalize generic code and merge with read().
-    pub async fn read_in_hw_order(
-        &mut self,
-        rx_dma: Peri<'_, impl RxDma<T>>,
-        hw_channel_selection: u32,
-        scandir: Scandir,
-        readings: &mut [u16],
-    ) {
-        assert!(
-            hw_channel_selection != 0,
-            "Some bits in `hw_channel_selection` shall be set."
-        );
-        assert!(
-            (hw_channel_selection >> NUM_HW_CHANNELS) == 0,
-            "STM32C0 only have {} ADC channels. `hw_channel_selection` cannot have bits higher than this number set.",
-            NUM_HW_CHANNELS
-        );
-        // To check for correct readings slice size, we shall solve Hamming weight problem,
-        // which is either slow or memory consuming.
-        // Since we have limited resources, we don't do it here.
-        // Not doing this have a great potential for a bug through.
-        // Ensure no conversions are ongoing.
-        Self::cancel_conversions();
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_chselrmod(false);
-            reg.set_scandir(scandir);
-            reg.set_align(Align::RIGHT);
-        });
-        // Set required channels for multi-convert.
-        unsafe { (T::regs().chselr().as_ptr() as *mut u32).write_volatile(hw_channel_selection) }
-        Self::apply_channel_conf();
-        self.dma_convert(rx_dma, readings).await
-    }
-    // Read ADC channels in specified order using DMA (CHSELRMOD = 1).
-    // In STM32C0, only lower 14 ADC channels can be read this way.
-    // For other channels, use `read_in_hw_order()` or blocking read.
-    pub async fn read(
-        &mut self,
-        rx_dma: Peri<'_, impl RxDma<T>>,
-        channel_sequence: impl ExactSizeIterator<Item = &mut AnyAdcChannel<T>>,
-        readings: &mut [u16],
-    ) {
-        assert!(
-            channel_sequence.len() != 0,
-            "Asynchronous read channel sequence cannot be empty."
-        );
-        assert!(
-            channel_sequence.len() == readings.len(),
-            "Channel sequence length must be equal to readings length."
-        );
-        // Ensure no conversions are ongoing.
-        Self::cancel_conversions();
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_chselrmod(true);
-            reg.set_align(Align::RIGHT);
-        });
-        Self::setup_channel_sequencer(channel_sequence);
-        self.dma_convert(rx_dma, readings).await
-    }
-    fn configure_channel(channel: &mut impl AdcChannel<T>) {
-        channel.setup();
-        // write() because we want all other bits to be set to 0.
-        T::regs()
-            .chselr()
-            .write(|w| w.set_chsel(channel.channel().into(), true));
-        Self::apply_channel_conf();
-    }
-    fn apply_channel_conf() {
-        // Trigger and wait for the channel selection procedure to complete.
-        T::regs().isr().modify(|w| w.set_ccrdy(false));
-        while !T::regs().isr().read().ccrdy() {}
-    }
-    fn cancel_conversions() {
-        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
-            T::regs().cr().modify(|reg| {
-                reg.set_adstp(Adstp::STOP);
-            });
-            while T::regs().cr().read().adstart() {}
-        }
    }
 }
diff --git a/embassy-stm32/src/adc/f1.rs b/embassy-stm32/src/adc/f1.rs
index f9c23d72b..d6c6f480b 100644
--- a/embassy-stm32/src/adc/f1.rs
+++ b/embassy-stm32/src/adc/f1.rs
@@ -3,7 +3,7 @@ use core::marker::PhantomData;
 use core::task::Poll;
 use super::blocking_delay_us;
-use crate::adc::{Adc, AdcChannel, Instance, SampleTime};
+use crate::adc::{Adc, AdcChannel, Instance, SampleTime, VrefInt};
 use crate::interrupt::typelevel::Interrupt;
 use crate::interrupt::{self};
 use crate::time::Hertz;
@@ -28,20 +28,12 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
    }
 }
-pub struct Vref;
+impl<T: Instance> super::SealedSpecialConverter<VrefInt> for T {
-impl<T: Instance> AdcChannel<T> for Vref {}
+    const CHANNEL: u8 = 17;
-impl<T: Instance> super::SealedAdcChannel<T> for Vref {
-    fn channel(&self) -> u8 {
-        17
-    }
 }
-pub struct Temperature;
+impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
-impl<T: Instance> AdcChannel<T> for Temperature {}
+    const CHANNEL: u8 = 16;
-impl<T: Instance> super::SealedAdcChannel<T> for Temperature {
-    fn channel(&self) -> u8 {
-        16
-    }
 }
 impl<'d, T: Instance> Adc<'d, T> {
@@ -51,7 +43,7 @@ impl<'d, T: Instance> Adc<'d, T> {
        // 11.4: Before starting a calibration, the ADC must have been in power-on state (ADON bit = ‘1’)
        // for at least two ADC clock cycles.
-        blocking_delay_us((1_000_000 * 2) / Self::freq().0 + 1);
+        blocking_delay_us((1_000_000 * 2) / Self::freq().0 as u64 + 1);
        // Reset calibration
        T::regs().cr2().modify(|reg| reg.set_rstcal(true));
@@ -66,15 +58,12 @@ impl<'d, T: Instance> Adc<'d, T> {
        }
        // One cycle after calibration
-        blocking_delay_us((1_000_000 * 1) / Self::freq().0 + 1);
+        blocking_delay_us((1_000_000 * 1) / Self::freq().0 as u64 + 1);
        T::Interrupt::unpend();
        unsafe { T::Interrupt::enable() };
-        Self {
+        Self { adc }
-            adc,
-            sample_time: SampleTime::from_bits(0),
-        }
    }
    fn freq() -> Hertz {
@@ -94,22 +83,18 @@ impl<'d, T: Instance> Adc<'d, T> {
        }
    }
-    pub fn enable_vref(&self) -> Vref {
+    pub fn enable_vref(&self) -> super::VrefInt {
        T::regs().cr2().modify(|reg| {
            reg.set_tsvrefe(true);
        });
-        Vref {}
+        super::VrefInt {}
    }
-    pub fn enable_temperature(&self) -> Temperature {
+    pub fn enable_temperature(&self) -> super::Temperature {
        T::regs().cr2().modify(|reg| {
            reg.set_tsvrefe(true);
        });
-        Temperature {}
+        super::Temperature {}
-    }
-    pub fn set_sample_time(&mut self, sample_time: SampleTime) {
-        self.sample_time = sample_time;
    }
    /// Perform a single conversion.
@@ -134,8 +119,8 @@ impl<'d, T: Instance> Adc<'d, T> {
        T::regs().dr().read().0 as u16
    }
-    pub async fn read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
+    pub async fn read(&mut self, channel: &mut impl AdcChannel<T>, sample_time: SampleTime) -> u16 {
-        Self::set_channel_sample_time(channel.channel(), self.sample_time);
+        Self::set_channel_sample_time(channel.channel(), sample_time);
        T::regs().cr1().modify(|reg| {
            reg.set_scan(false);
            reg.set_discen(false);
diff --git a/embassy-stm32/src/adc/f3.rs b/embassy-stm32/src/adc/f3.rs
index 73ceb087a..29bfdac97 100644
--- a/embassy-stm32/src/adc/f3.rs
+++ b/embassy-stm32/src/adc/f3.rs
@@ -3,7 +3,7 @@ use core::marker::PhantomData;
 use core::task::Poll;
 use super::blocking_delay_us;
-use crate::adc::{Adc, AdcChannel, Instance, SampleTime};
+use crate::adc::{Adc, AdcChannel, Instance, SampleTime, VrefInt};
 use crate::interrupt::typelevel::Interrupt;
 use crate::time::Hertz;
 use crate::{Peri, interrupt, rcc};
@@ -29,27 +29,12 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
    }
 }
-pub struct Vref;
+impl<T: Instance> super::SealedSpecialConverter<VrefInt> for T {
-impl<T: Instance> AdcChannel<T> for Vref {}
+    const CHANNEL: u8 = 18;
-impl<T: Instance> super::SealedAdcChannel<T> for Vref {
-    fn channel(&self) -> u8 {
-        18
-    }
-}
-impl Vref {
-    /// The value that vref would be if vdda was at 3300mv
-    pub fn value(&self) -> u16 {
-        crate::pac::VREFINTCAL.data().read()
-    }
 }
-pub struct Temperature;
+impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
-impl<T: Instance> AdcChannel<T> for Temperature {}
+    const CHANNEL: u8 = 16;
-impl<T: Instance> super::SealedAdcChannel<T> for Temperature {
-    fn channel(&self) -> u8 {
-        16
-    }
 }
 impl<'d, T: Instance> Adc<'d, T> {
@@ -77,7 +62,7 @@ impl<'d, T: Instance> Adc<'d, T> {
        while T::regs().cr().read().adcal() {}
        // Wait more than 4 clock cycles after adcal is cleared (RM0364 p. 223).
-        blocking_delay_us((1_000_000 * 4) / Self::freq().0 + 1);
+        blocking_delay_us((1_000_000 * 4) / Self::freq().0 as u64 + 1);
        // Enable the adc
        T::regs().cr().modify(|w| w.set_aden(true));
@@ -90,10 +75,7 @@ impl<'d, T: Instance> Adc<'d, T> {
            T::Interrupt::enable();
        }
-        Self {
+        Self { adc }
-            adc,
-            sample_time: SampleTime::from_bits(0),
-        }
    }
    fn freq() -> Hertz {
@@ -112,20 +94,16 @@ impl<'d, T: Instance> Adc<'d, T> {
        }
    }
-    pub fn enable_vref(&self) -> Vref {
+    pub fn enable_vref(&self) -> super::VrefInt {
        T::common_regs().ccr().modify(|w| w.set_vrefen(true));
-        Vref {}
+        super::VrefInt {}
    }
-    pub fn enable_temperature(&self) -> Temperature {
+    pub fn enable_temperature(&self) -> super::Temperature {
        T::common_regs().ccr().modify(|w| w.set_tsen(true));
-        Temperature {}
+        super::Temperature {}
-    }
-    pub fn set_sample_time(&mut self, sample_time: SampleTime) {
-        self.sample_time = sample_time;
    }
    /// Perform a single conversion.
@@ -150,8 +128,8 @@ impl<'d, T: Instance> Adc<'d, T> {
        T::regs().dr().read().rdata()
    }
-    pub async fn read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
+    pub async fn read(&mut self, channel: &mut impl AdcChannel<T>, sample_time: SampleTime) -> u16 {
-        Self::set_channel_sample_time(channel.channel(), self.sample_time);
+        Self::set_channel_sample_time(channel.channel(), sample_time);
        // Configure the channel to sample
        T::regs().sqr1().write(|w| w.set_sq(0, channel.channel()));
diff --git a/embassy-stm32/src/adc/f3_v1_1.rs b/embassy-stm32/src/adc/f3_v1_1.rs
index cd5de54f5..919ac3cc0 100644
--- a/embassy-stm32/src/adc/f3_v1_1.rs
+++ b/embassy-stm32/src/adc/f3_v1_1.rs
@@ -79,7 +79,7 @@ impl<T: Instance> Vref<T> {
    }
    pub async fn calibrate(&mut self, adc: &mut Adc<'_, T>) -> Calibration {
-        let vref_val = adc.read(self).await;
+        let vref_val = adc.read(self, SampleTime::from(0)).await;
        Calibration {
            vref_cal: self.calibrated_value(),
            vref_val,
@@ -270,7 +270,8 @@ impl<'d, T: Instance> Adc<'d, T> {
        }
    }
-    pub async fn read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
+    pub async fn read(&mut self, channel: &mut impl AdcChannel<T>, sample_time: SampleTime) -> u16 {
+        self.set_sample_time(channel, sample_time).await;
        self.set_sample_sequence(&[channel.channel()]).await;
        self.convert().await
    }
diff --git a/embassy-stm32/src/adc/g4.rs b/embassy-stm32/src/adc/g4.rs
index 3767820cf..bd8ccbf17 100644
--- a/embassy-stm32/src/adc/g4.rs
+++ b/embassy-stm32/src/adc/g4.rs
@@ -1,5 +1,5 @@
-use core::mem;
+#[cfg(stm32g4)]
+use pac::adc::regs::Difsel as DifselReg;
 #[allow(unused)]
 #[cfg(stm32h7)]
 use pac::adc::vals::{Adcaldif, Difsel, Exten};
@@ -10,15 +10,14 @@ pub use pac::adccommon::vals::Presc;
 pub use stm32_metapac::adc::vals::{Adstp, Dmacfg, Dmaen};
 pub use stm32_metapac::adccommon::vals::Dual;
-use super::{Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, blocking_delay_us};
+use super::{
-use crate::adc::SealedAdcChannel;
+    Adc, AnyAdcChannel, ConversionMode, Instance, RegularConversionMode, Resolution, RxDma, SampleTime,
-use crate::dma::Transfer;
+    blocking_delay_us,
+};
+use crate::adc::{AnyInstance, SealedAdcChannel};
 use crate::time::Hertz;
 use crate::{Peri, pac, rcc};
-mod ringbuffered;
-pub use ringbuffered::RingBufferedAdc;
 mod injected;
 pub use injected::InjectedAdc;
@@ -35,100 +34,31 @@ const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(60);
 #[cfg(stm32h7)]
 const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(50);
-// NOTE: Vrefint/Temperature/Vbat are not available on all ADCs, this currently cannot be modeled with stm32-data, so these are available from the software on all ADCs
+fn from_ker_ck(frequency: Hertz) -> Presc {
-/// Internal voltage reference channel.
+    let raw_prescaler = frequency.0 / MAX_ADC_CLK_FREQ.0;
-pub struct VrefInt;
+    match raw_prescaler {
-impl<T: Instance + VrefChannel> AdcChannel<T> for VrefInt {}
+        0 => Presc::DIV1,
-impl<T: Instance + VrefChannel> super::SealedAdcChannel<T> for VrefInt {
+        1 => Presc::DIV2,
-    fn channel(&self) -> u8 {
+        2..=3 => Presc::DIV4,
-        T::CHANNEL
+        4..=5 => Presc::DIV6,
-    }
+        6..=7 => Presc::DIV8,
-}
+        8..=9 => Presc::DIV10,
+        10..=11 => Presc::DIV12,
-/// Internal temperature channel.
+        _ => unimplemented!(),
-pub struct Temperature;
-impl<T: Instance + TemperatureChannel> AdcChannel<T> for Temperature {}
-impl<T: Instance + TemperatureChannel> super::SealedAdcChannel<T> for Temperature {
-    fn channel(&self) -> u8 {
-        T::CHANNEL
    }
 }
-/// Internal battery voltage channel.
+/// ADC configuration
-pub struct Vbat;
+#[derive(Default)]
-impl<T: Instance + VBatChannel> AdcChannel<T> for Vbat {}
+pub struct AdcConfig {
-impl<T: Instance + VBatChannel> super::SealedAdcChannel<T> for Vbat {
+    pub dual_mode: Option<Dual>,
-    fn channel(&self) -> u8 {
+    pub resolution: Option<Resolution>,
-        T::CHANNEL
+    #[cfg(stm32g4)]
-    }
+    pub oversampling_shift: Option<u8>,
-}
+    #[cfg(stm32g4)]
+    pub oversampling_ratio: Option<u8>,
-// NOTE (unused): The prescaler enum closely copies the hardware capabilities,
+    #[cfg(stm32g4)]
-// but high prescaling doesn't make a lot of sense in the current implementation and is ommited.
+    pub oversampling_mode: Option<(Rovsm, Trovs, bool)>,
-#[allow(unused)]
-enum Prescaler {
-    NotDivided,
-    DividedBy2,
-    DividedBy4,
-    DividedBy6,
-    DividedBy8,
-    DividedBy10,
-    DividedBy12,
-    DividedBy16,
-    DividedBy32,
-    DividedBy64,
-    DividedBy128,
-    DividedBy256,
-}
-impl Prescaler {
-    fn from_ker_ck(frequency: Hertz) -> Self {
-        let raw_prescaler = frequency.0 / MAX_ADC_CLK_FREQ.0;
-        match raw_prescaler {
-            0 => Self::NotDivided,
-            1 => Self::DividedBy2,
-            2..=3 => Self::DividedBy4,
-            4..=5 => Self::DividedBy6,
-            6..=7 => Self::DividedBy8,
-            8..=9 => Self::DividedBy10,
-            10..=11 => Self::DividedBy12,
-            _ => unimplemented!(),
-        }
-    }
-    fn divisor(&self) -> u32 {
-        match self {
-            Prescaler::NotDivided => 1,
-            Prescaler::DividedBy2 => 2,
-            Prescaler::DividedBy4 => 4,
-            Prescaler::DividedBy6 => 6,
-            Prescaler::DividedBy8 => 8,
-            Prescaler::DividedBy10 => 10,
-            Prescaler::DividedBy12 => 12,
-            Prescaler::DividedBy16 => 16,
-            Prescaler::DividedBy32 => 32,
-            Prescaler::DividedBy64 => 64,
-            Prescaler::DividedBy128 => 128,
-            Prescaler::DividedBy256 => 256,
-        }
-    }
-    fn presc(&self) -> Presc {
-        match self {
-            Prescaler::NotDivided => Presc::DIV1,
-            Prescaler::DividedBy2 => Presc::DIV2,
-            Prescaler::DividedBy4 => Presc::DIV4,
-            Prescaler::DividedBy6 => Presc::DIV6,
-            Prescaler::DividedBy8 => Presc::DIV8,
-            Prescaler::DividedBy10 => Presc::DIV10,
-            Prescaler::DividedBy12 => Presc::DIV12,
-            Prescaler::DividedBy16 => Presc::DIV16,
-            Prescaler::DividedBy32 => Presc::DIV32,
-            Prescaler::DividedBy64 => Presc::DIV64,
-            Prescaler::DividedBy128 => Presc::DIV128,
-            Prescaler::DividedBy256 => Presc::DIV256,
-        }
-    }
 }
 // Trigger source for ADC conversions¨
@@ -140,90 +70,12 @@ pub struct ConversionTrigger {
    pub edge: Exten,
 }
-// Conversion mode for regular ADC channels
+impl<T: Instance> super::SealedAnyInstance for T {
-#[derive(Copy, Clone)]
+    fn dr() -> *mut u16 {
-pub enum RegularConversionMode {
+        T::regs().dr().as_ptr() as *mut u16
-    // Samples as fast as possible
-    Continuous,
-    // Sample at rate determined by external trigger
-    Triggered(ConversionTrigger),
-}
-impl<'d, T: Instance> Adc<'d, T> {
-    /// Create a new ADC driver.
-    pub fn new(adc: Peri<'d, T>) -> Self {
-        rcc::enable_and_reset::<T>();
-        let prescaler = Prescaler::from_ker_ck(T::frequency());
-        T::common_regs().ccr().modify(|w| w.set_presc(prescaler.presc()));
-        let frequency = Hertz(T::frequency().0 / prescaler.divisor());
-        trace!("ADC frequency set to {}", frequency);
-        if frequency > MAX_ADC_CLK_FREQ {
-            panic!(
-                "Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.",
-                MAX_ADC_CLK_FREQ.0 / 1_000_000
-            );
-        }
-        let mut s = Self {
-            adc,
-            sample_time: SampleTime::from_bits(0),
-        };
-        s.power_up();
-        s.configure_differential_inputs();
-        s.calibrate();
-        blocking_delay_us(1);
-        s.enable();
-        s.configure();
-        s
-    }
-    fn power_up(&mut self) {
-        T::regs().cr().modify(|reg| {
-            reg.set_deeppwd(false);
-            reg.set_advregen(true);
-        });
-        blocking_delay_us(20);
-    }
-    fn configure_differential_inputs(&mut self) {
-        T::regs().difsel().modify(|w| {
-            for n in 0..18 {
-                w.set_difsel(n, Difsel::SINGLE_ENDED);
-            }
-        });
    }
-    fn calibrate(&mut self) {
+    fn enable() {
-        T::regs().cr().modify(|w| {
-            w.set_adcaldif(Adcaldif::SINGLE_ENDED);
-        });
-        T::regs().cr().modify(|w| w.set_adcal(true));
-        while T::regs().cr().read().adcal() {}
-        blocking_delay_us(20);
-        T::regs().cr().modify(|w| {
-            w.set_adcaldif(Adcaldif::DIFFERENTIAL);
-        });
-        T::regs().cr().modify(|w| w.set_adcal(true));
-        while T::regs().cr().read().adcal() {}
-        blocking_delay_us(20);
-    }
-    fn enable(&mut self) {
        // Make sure bits are off
        while T::regs().cr().read().addis() {
            // spin
@@ -244,124 +96,30 @@ impl<'d, T: Instance> Adc<'d, T> {
        }
    }
-    fn configure(&mut self) {
+    fn start() {
-        // single conversion mode, software trigger
+        T::regs().cr().modify(|reg| {
-        T::regs().cfgr().modify(|w| {
+            reg.set_adstart(true);
-            w.set_cont(false);
-            w.set_exten(Exten::DISABLED);
-        });
-    }
-    /// Enable reading the voltage reference internal channel.
-    pub fn enable_vrefint(&self) -> VrefInt
-    where
-        T: VrefChannel,
-    {
-        T::common_regs().ccr().modify(|reg| {
-            reg.set_vrefen(true);
-        });
-        VrefInt {}
-    }
-    /// Enable reading the temperature internal channel.
-    pub fn enable_temperature(&self) -> Temperature
-    where
-        T: TemperatureChannel,
-    {
-        T::common_regs().ccr().modify(|reg| {
-            reg.set_vsenseen(true);
        });
-        Temperature {}
    }
-    /// Enable reading the vbat internal channel.
+    fn stop() {
-    pub fn enable_vbat(&self) -> Vbat
+        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
-    where
+            T::regs().cr().modify(|reg| {
-        T: VBatChannel,
+                reg.set_adstp(Adstp::STOP);
-    {
+            });
-        T::common_regs().ccr().modify(|reg| {
+            // The software must poll ADSTART until the bit is reset before assuming the
-            reg.set_vbaten(true);
+            // ADC is completely stopped
-        });
+            while T::regs().cr().read().adstart() {}
+        }
-        Vbat {}
-    }
-    /// Enable differential channel.
+        // Disable dma control and continuous conversion, if enabled
-    /// Caution:
+        T::regs().cfgr().modify(|reg| {
-    /// : When configuring the channel “i” in differential input mode, its negative input voltage VINN[i]
+            reg.set_cont(false);
-    /// is connected to another channel. As a consequence, this channel is no longer usable in
+            reg.set_dmaen(Dmaen::DISABLE);
-    /// single-ended mode or in differential mode and must never be configured to be converted.
-    /// Some channels are shared between ADC1/ADC2/ADC3/ADC4/ADC5: this can make the
-    /// channel on the other ADC unusable. The only exception is when ADC master and the slave
-    /// operate in interleaved mode.
-    #[cfg(stm32g4)]
-    pub fn set_differential_channel(&mut self, ch: usize, enable: bool) {
-        T::regs().cr().modify(|w| w.set_aden(false)); // disable adc
-        T::regs().difsel().modify(|w| {
-            w.set_difsel(
-                ch,
-                if enable {
-                    Difsel::DIFFERENTIAL
-                } else {
-                    Difsel::SINGLE_ENDED
-                },
-            );
        });
-        T::regs().cr().modify(|w| w.set_aden(true));
-    }
-    #[cfg(stm32g4)]
-    pub fn set_differential(&mut self, channel: &mut impl AdcChannel<T>, enable: bool) {
-        self.set_differential_channel(channel.channel() as usize, enable);
-    }
-    /// Set oversampling shift.
-    #[cfg(stm32g4)]
-    pub fn set_oversampling_shift(&mut self, shift: u8) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
-    }
-    /// Set oversampling ratio.
-    #[cfg(stm32g4)]
-    pub fn set_oversampling_ratio(&mut self, ratio: u8) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
-    }
-    /// Enable oversampling in regular mode.
-    #[cfg(stm32g4)]
-    pub fn enable_regular_oversampling_mode(&mut self, mode: Rovsm, trig_mode: Trovs, enable: bool) {
-        T::regs().cfgr2().modify(|reg| reg.set_trovs(trig_mode));
-        T::regs().cfgr2().modify(|reg| reg.set_rovsm(mode));
-        T::regs().cfgr2().modify(|reg| reg.set_rovse(enable));
-    }
-    // Reads that are not implemented as INJECTED in "blocking_read"
-    // #[cfg(stm32g4)]
-    // pub fn enalble_injected_oversampling_mode(&mut self, enable: bool) {
-    //     T::regs().cfgr2().modify(|reg| reg.set_jovse(enable));
-    // }
-    // #[cfg(stm32g4)]
-    // pub fn enable_oversampling_regular_injected_mode(&mut self, enable: bool) {
-    //     // the regularoversampling mode is forced to resumed mode (ROVSM bit ignored),
-    //     T::regs().cfgr2().modify(|reg| reg.set_rovse(enable));
-    //     T::regs().cfgr2().modify(|reg| reg.set_jovse(enable));
-    // }
-    /// Set the ADC sample time.
-    pub fn set_sample_time(&mut self, sample_time: SampleTime) {
-        self.sample_time = sample_time;
-    }
-    /// Set the ADC resolution.
-    pub fn set_resolution(&mut self, resolution: Resolution) {
-        T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
    }
-    /// Perform a single conversion.
+    fn convert() -> u16 {
-    fn convert(&mut self) -> u16 {
        T::regs().isr().modify(|reg| {
            reg.set_eos(true);
            reg.set_eoc(true);
@@ -379,277 +137,249 @@ impl<'d, T: Instance> Adc<'d, T> {
        T::regs().dr().read().0 as u16
    }
-    /// Read an ADC pin.
+    fn configure_dma(conversion_mode: ConversionMode) {
-    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
+        T::regs().isr().modify(|reg| {
-        channel.setup();
+            reg.set_ovr(true);
-        self.read_channel(channel)
-    }
-    /// Start regular adc conversion
-    pub(super) fn start() {
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
        });
-    }
-    /// Stop regular conversions
-    pub(super) fn stop() {
-        Self::stop_regular_conversions();
-    }
-    /// Teardown method for stopping regular ADC conversions
-    pub(super) fn teardown_adc() {
-        Self::stop_regular_conversions();
-        // Disable dma control
        T::regs().cfgr().modify(|reg| {
-            reg.set_dmaen(Dmaen::DISABLE);
+            reg.set_discen(false); // Convert all channels for each trigger
+            reg.set_dmacfg(match conversion_mode {
+                ConversionMode::Singular => Dmacfg::ONE_SHOT,
+                ConversionMode::Repeated(_) => Dmacfg::CIRCULAR,
+            });
+            reg.set_dmaen(Dmaen::ENABLE);
        });
-    }
-    /// Read one or multiple ADC regular channels using DMA.
+        if let ConversionMode::Repeated(mode) = conversion_mode {
-    ///
+            match mode {
-    /// `sequence` iterator and `readings` must have the same length.
+                RegularConversionMode::Continuous => {
-    ///
+                    T::regs().cfgr().modify(|reg| {
-    /// Example
+                        reg.set_cont(true);
-    /// ```rust,ignore
+                    });
-    /// use embassy_stm32::adc::{Adc, AdcChannel}
+                }
-    ///
+                RegularConversionMode::Triggered(trigger) => {
-    /// let mut adc = Adc::new(p.ADC1);
+                    T::regs().cfgr().modify(|r| {
-    /// let mut adc_pin0 = p.PA0.into();
+                        r.set_cont(false); // New trigger is neede for each sample to be read
-    /// let mut adc_pin1 = p.PA1.into();
+                    });
-    /// let mut measurements = [0u16; 2];
-    ///
-    /// adc.read(
-    ///     p.DMA1_CH2.reborrow(),
-    ///     [
-    ///         (&mut *adc_pin0, SampleTime::CYCLES160_5),
-    ///         (&mut *adc_pin1, SampleTime::CYCLES160_5),
-    ///     ]
-    ///     .into_iter(),
-    ///     &mut measurements,
-    /// )
-    /// .await;
-    /// defmt::info!("measurements: {}", measurements);
-    /// ```
-    ///
-    /// Note: This is not very efficient as the ADC needs to be reconfigured for each read. Use
-    /// `into_ring_buffered`, `into_ring_buffered_and_injected`
-    pub async fn read(
-        &mut self,
-        rx_dma: Peri<'_, impl RxDma<T>>,
-        sequence: impl ExactSizeIterator<Item = (&mut AnyAdcChannel<T>, SampleTime)>,
-        readings: &mut [u16],
-    ) {
-        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
-        assert!(
-            sequence.len() == readings.len(),
-            "Sequence length must be equal to readings length"
-        );
-        assert!(
-            sequence.len() <= 16,
-            "Asynchronous read sequence cannot be more than 16 in length"
-        );
-        // Ensure no conversions are ongoing and ADC is enabled.
+                    T::regs().cfgr().modify(|r| {
-        Self::stop_regular_conversions();
+                        r.set_extsel(trigger.channel);
-        self.enable();
+                        r.set_exten(trigger.edge);
+                    });
+                    // Regular conversions uses DMA so no need to generate interrupt
+                    T::regs().ier().modify(|r| r.set_eosie(false));
+                }
+            }
+        }
+    }
+    fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
        // Set sequence length
        T::regs().sqr1().modify(|w| {
            w.set_l(sequence.len() as u8 - 1);
        });
+        #[cfg(stm32g4)]
+        let mut difsel = DifselReg::default();
        // Configure channels and ranks
-        for (_i, (channel, sample_time)) in sequence.enumerate() {
+        for (_i, ((ch, is_differential), sample_time)) in sequence.enumerate() {
-            Self::configure_channel(channel, sample_time);
+            let sample_time = sample_time.into();
+            if ch <= 9 {
+                T::regs().smpr().modify(|reg| reg.set_smp(ch as _, sample_time));
+            } else {
+                T::regs().smpr2().modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
+            }
            match _i {
                0..=3 => {
                    T::regs().sqr1().modify(|w| {
-                        w.set_sq(_i, channel.channel());
+                        w.set_sq(_i, ch);
                    });
                }
                4..=8 => {
                    T::regs().sqr2().modify(|w| {
-                        w.set_sq(_i - 4, channel.channel());
+                        w.set_sq(_i - 4, ch);
                    });
                }
                9..=13 => {
                    T::regs().sqr3().modify(|w| {
-                        w.set_sq(_i - 9, channel.channel());
+                        w.set_sq(_i - 9, ch);
                    });
                }
                14..=15 => {
                    T::regs().sqr4().modify(|w| {
-                        w.set_sq(_i - 14, channel.channel());
+                        w.set_sq(_i - 14, ch);
                    });
                }
                _ => unreachable!(),
            }
+            #[cfg(stm32g4)]
+            {
+                if ch < 18 {
+                    difsel.set_difsel(
+                        ch.into(),
+                        if is_differential {
+                            Difsel::DIFFERENTIAL
+                        } else {
+                            Difsel::SINGLE_ENDED
+                        },
+                    );
+                }
+            }
        }
-        // Set continuous mode with oneshot dma.
+        #[cfg(stm32g4)]
-        // Clear overrun flag before starting transfer.
+        {
-        T::regs().isr().modify(|reg| {
+            T::regs().cr().modify(|w| w.set_aden(false));
-            reg.set_ovr(true);
+            T::regs().difsel().write_value(difsel);
-        });
+            T::enable();
+        }
+    }
+}
-        T::regs().cfgr().modify(|reg| {
+impl<'d, T: Instance + AnyInstance> Adc<'d, T> {
-            reg.set_discen(false);
+    /// Create a new ADC driver.
-            reg.set_cont(true);
+    pub fn new(adc: Peri<'d, T>, config: AdcConfig) -> Self {
-            reg.set_dmacfg(Dmacfg::ONE_SHOT);
+        rcc::enable_and_reset::<T>();
-            reg.set_dmaen(Dmaen::ENABLE);
-        });
-        let request = rx_dma.request();
+        let prescaler = from_ker_ck(T::frequency());
-        let transfer = unsafe {
-            Transfer::new_read(
+        T::common_regs().ccr().modify(|w| w.set_presc(prescaler));
-                rx_dma,
-                request,
+        let frequency = T::frequency() / prescaler;
-                T::regs().dr().as_ptr() as *mut u16,
+        trace!("ADC frequency set to {}", frequency);
-                readings,
-                Default::default(),
+        if frequency > MAX_ADC_CLK_FREQ {
-            )
+            panic!(
-        };
+                "Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.",
+                MAX_ADC_CLK_FREQ.0 / 1_000_000
+            );
+        }
-        // Start conversion
        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
+            reg.set_deeppwd(false);
+            reg.set_advregen(true);
        });
-        // Wait for conversion sequence to finish.
+        blocking_delay_us(20);
-        transfer.await;
-        // Ensure conversions are finished.
+        T::regs().difsel().modify(|w| {
-        Self::stop_regular_conversions();
+            for n in 0..18 {
+                w.set_difsel(n, Difsel::SINGLE_ENDED);
+            }
+        });
-        // Reset configuration.
+        T::regs().cr().modify(|w| {
-        T::regs().cfgr().modify(|reg| {
+            w.set_adcaldif(Adcaldif::SINGLE_ENDED);
-            reg.set_cont(false);
        });
-    }
-    /// Set external trigger for regular conversion sequence
+        T::regs().cr().modify(|w| w.set_adcal(true));
-    fn set_regular_conversion_trigger(&mut self, trigger: ConversionTrigger) {
-        T::regs().cfgr().modify(|r| {
+        while T::regs().cr().read().adcal() {}
-            r.set_extsel(trigger.channel);
-            r.set_exten(trigger.edge);
+        blocking_delay_us(20);
+        T::regs().cr().modify(|w| {
+            w.set_adcaldif(Adcaldif::DIFFERENTIAL);
        });
-        // Regular conversions uses DMA so no need to generate interrupt
-        T::regs().ier().modify(|r| r.set_eosie(false));
-    }
-    // Dual ADC mode selection
+        T::regs().cr().modify(|w| w.set_adcal(true));
-    pub fn configure_dual_mode(&mut self, val: Dual) {
-        T::common_regs().ccr().modify(|reg| {
-            reg.set_dual(val);
-        })
-    }
-    /// Configures the ADC to use a DMA ring buffer for continuous data acquisition.
+        while T::regs().cr().read().adcal() {}
-    ///
-    /// Use the [`read`] method to retrieve measurements from the DMA ring buffer. The read buffer
-    /// should be exactly half the size of `dma_buf`. When using triggered mode, it is recommended
-    /// to configure `dma_buf` as a double buffer so that one half can be read while the other half
-    /// is being filled by the DMA, preventing data loss. The trigger period of the ADC effectively
-    /// defines the period at which the buffer should be read.
-    ///
-    /// If continous conversion mode is selected, the provided `dma_buf` must be large enough to prevent
-    /// DMA buffer overruns. Its length should be a multiple of the number of ADC channels being measured.
-    /// For example, if 3 channels are measured and you want to store 40 samples per channel,
-    /// the buffer length should be `3 * 40 = 120`.
-    ///
-    /// # Parameters
-    /// - `dma`: The DMA peripheral used to transfer ADC data into the buffer.
-    /// - `dma_buf`: The buffer where DMA stores ADC samples.
-    /// - `regular_sequence`: Sequence of channels and sample times for regular ADC conversions.
-    /// - `regular_conversion_mode`: Mode for regular conversions (continuous or triggered).
-    ///
-    /// # Returns
-    /// A `RingBufferedAdc<'a, T>` instance configured for continuous DMA-based sampling.
-    pub fn into_ring_buffered<'a>(
-        mut self,
-        dma: Peri<'a, impl RxDma<T>>,
-        dma_buf: &'a mut [u16],
-        sequence: impl ExactSizeIterator<Item = (AnyAdcChannel<T>, SampleTime)>,
-        mode: RegularConversionMode,
-    ) -> RingBufferedAdc<'a, T> {
-        assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
-        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
-        assert!(
-            sequence.len() <= 16,
-            "Asynchronous read sequence cannot be more than 16 in length"
-        );
-        // reset conversions and enable the adc
-        Self::stop_regular_conversions();
-        self.enable();
-        //adc side setup
+        blocking_delay_us(20);
-        // Set sequence length
+        T::enable();
-        T::regs().sqr1().modify(|w| {
-            w.set_l(sequence.len() as u8 - 1);
+        // single conversion mode, software trigger
+        T::regs().cfgr().modify(|w| {
+            w.set_cont(false);
+            w.set_exten(Exten::DISABLED);
        });
-        // Configure channels and ranks
+        if let Some(dual) = config.dual_mode {
-        for (_i, (mut channel, sample_time)) in sequence.enumerate() {
+            T::common_regs().ccr().modify(|reg| {
-            Self::configure_channel(&mut channel, sample_time);
+                reg.set_dual(dual);
+            })
+        }
-            match _i {
+        if let Some(resolution) = config.resolution {
-                0..=3 => {
+            T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
-                    T::regs().sqr1().modify(|w| {
-                        w.set_sq(_i, channel.channel());
-                    });
-                }
-                4..=8 => {
-                    T::regs().sqr2().modify(|w| {
-                        w.set_sq(_i - 4, channel.channel());
-                    });
-                }
-                9..=13 => {
-                    T::regs().sqr3().modify(|w| {
-                        w.set_sq(_i - 9, channel.channel());
-                    });
-                }
-                14..=15 => {
-                    T::regs().sqr4().modify(|w| {
-                        w.set_sq(_i - 14, channel.channel());
-                    });
-                }
-                _ => unreachable!(),
-            }
        }
-        // Clear overrun flag before starting transfer.
+        #[cfg(stm32g4)]
-        T::regs().isr().modify(|reg| {
+        if let Some(shift) = config.oversampling_shift {
-            reg.set_ovr(true);
+            T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
+        }
+        #[cfg(stm32g4)]
+        if let Some(ratio) = config.oversampling_ratio {
+            T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
+        }
+        #[cfg(stm32g4)]
+        if let Some((mode, trig_mode, enable)) = config.oversampling_mode {
+            T::regs().cfgr2().modify(|reg| reg.set_trovs(trig_mode));
+            T::regs().cfgr2().modify(|reg| reg.set_rovsm(mode));
+            T::regs().cfgr2().modify(|reg| reg.set_rovse(enable));
+        }
+        Self { adc }
+    }
+    /// Enable reading the voltage reference internal channel.
+    pub fn enable_vrefint(&self) -> super::VrefInt
+    where
+        T: super::SpecialConverter<super::VrefInt>,
+    {
+        T::common_regs().ccr().modify(|reg| {
+            reg.set_vrefen(true);
        });
-        T::regs().cfgr().modify(|reg| {
+        super::VrefInt {}
-            reg.set_discen(false); // Convert all channels for each trigger
+    }
-            reg.set_dmacfg(Dmacfg::CIRCULAR);
-            reg.set_dmaen(Dmaen::ENABLE);
+    /// Enable reading the temperature internal channel.
+    pub fn enable_temperature(&self) -> super::Temperature
+    where
+        T: super::SpecialConverter<super::Temperature>,
+    {
+        T::common_regs().ccr().modify(|reg| {
+            reg.set_vsenseen(true);
        });
-        match mode {
+        super::Temperature {}
-            RegularConversionMode::Continuous => {
+    }
-                T::regs().cfgr().modify(|reg| {
-                    reg.set_cont(true);
-                });
-            }
-            RegularConversionMode::Triggered(trigger) => {
-                T::regs().cfgr().modify(|r| {
-                    r.set_cont(false); // New trigger is neede for each sample to be read
-                });
-                self.set_regular_conversion_trigger(trigger);
-            }
-        }
-        mem::forget(self);
+    /// Enable reading the vbat internal channel.
+    pub fn enable_vbat(&self) -> super::Vbat
+    where
+        T: super::SpecialConverter<super::Vbat>,
+    {
+        T::common_regs().ccr().modify(|reg| {
+            reg.set_vbaten(true);
+        });
-        RingBufferedAdc::new(dma, dma_buf)
+        super::Vbat {}
    }
+    // Reads that are not implemented as INJECTED in "blocking_read"
+    // #[cfg(stm32g4)]
+    // pub fn enalble_injected_oversampling_mode(&mut self, enable: bool) {
+    //     T::regs().cfgr2().modify(|reg| reg.set_jovse(enable));
+    // }
+    // #[cfg(stm32g4)]
+    // pub fn enable_oversampling_regular_injected_mode(&mut self, enable: bool) {
+    //     // the regularoversampling mode is forced to resumed mode (ROVSM bit ignored),
+    //     T::regs().cfgr2().modify(|reg| reg.set_rovse(enable));
+    //     T::regs().cfgr2().modify(|reg| reg.set_jovse(enable));
+    // }
    /// Configures the ADC for injected conversions.
    ///
    /// Injected conversions are separate from the regular conversion sequence and are typically
@@ -678,7 +408,7 @@ impl<'d, T: Instance> Adc<'d, T> {
    /// - Accessing samples beyond `N` will result in a panic; use the returned type
    ///   `InjectedAdc<T, N>` to enforce bounds at compile time.
    pub fn setup_injected_conversions<'a, const N: usize>(
-        mut self,
+        self,
        sequence: [(AnyAdcChannel<T>, SampleTime); N],
        trigger: ConversionTrigger,
        interrupt: bool,
@@ -690,13 +420,21 @@ impl<'d, T: Instance> Adc<'d, T> {
            NR_INJECTED_RANKS
        );
-        Self::stop_regular_conversions();
+        T::enable();
-        self.enable();
        T::regs().jsqr().modify(|w| w.set_jl(N as u8 - 1));
-        for (n, (mut channel, sample_time)) in sequence.into_iter().enumerate() {
+        for (n, (channel, sample_time)) in sequence.into_iter().enumerate() {
-            Self::configure_channel(&mut channel, sample_time);
+            let sample_time = sample_time.into();
+            if channel.channel() <= 9 {
+                T::regs()
+                    .smpr()
+                    .modify(|reg| reg.set_smp(channel.channel() as _, sample_time));
+            } else {
+                T::regs()
+                    .smpr2()
+                    .modify(|reg| reg.set_smp((channel.channel() - 10) as _, sample_time));
+            }
            let idx = match n {
                0..=3 => n,
@@ -711,8 +449,16 @@ impl<'d, T: Instance> Adc<'d, T> {
        T::regs().cfgr().modify(|reg| reg.set_jdiscen(false));
-        self.set_injected_conversion_trigger(trigger);
+        // Set external trigger for injected conversion sequence
-        self.enable_injected_eos_interrupt(interrupt);
+        // Possible trigger values are seen in Table 167 in RM0440 Rev 9
+        T::regs().jsqr().modify(|r| {
+            r.set_jextsel(trigger.channel);
+            r.set_jexten(trigger.edge);
+        });
+        // Enable end of injected sequence interrupt
+        T::regs().ier().modify(|r| r.set_jeosie(interrupt));
        Self::start_injected_conversions();
        InjectedAdc::new(sequence) // InjectedAdc<'a, T, N> now borrows the channels
@@ -745,22 +491,20 @@ impl<'d, T: Instance> Adc<'d, T> {
        self,
        dma: Peri<'a, impl RxDma<T>>,
        dma_buf: &'a mut [u16],
-        regular_sequence: impl ExactSizeIterator<Item = (AnyAdcChannel<T>, SampleTime)>,
+        regular_sequence: impl ExactSizeIterator<Item = (AnyAdcChannel<T>, T::SampleTime)>,
        regular_conversion_mode: RegularConversionMode,
        injected_sequence: [(AnyAdcChannel<T>, SampleTime); N],
        injected_trigger: ConversionTrigger,
        injected_interrupt: bool,
-    ) -> (RingBufferedAdc<'a, T>, InjectedAdc<T, N>) {
+    ) -> (super::RingBufferedAdc<'a, T>, InjectedAdc<T, N>) {
        unsafe {
            (
                Self {
                    adc: self.adc.clone_unchecked(),
-                    sample_time: self.sample_time,
                }
                .into_ring_buffered(dma, dma_buf, regular_sequence, regular_conversion_mode),
                Self {
                    adc: self.adc.clone_unchecked(),
-                    sample_time: self.sample_time,
                }
                .setup_injected_conversions(injected_sequence, injected_trigger, injected_interrupt),
            )
@@ -785,64 +529,6 @@ impl<'d, T: Instance> Adc<'d, T> {
            reg.set_jadstart(true);
        });
    }
-    /// Set external trigger for injected conversion sequence
-    /// Possible trigger values are seen in Table 167 in RM0440 Rev 9
-    fn set_injected_conversion_trigger(&mut self, trigger: ConversionTrigger) {
-        T::regs().jsqr().modify(|r| {
-            r.set_jextsel(trigger.channel);
-            r.set_jexten(trigger.edge);
-        });
-    }
-    /// Enable end of injected sequence interrupt
-    fn enable_injected_eos_interrupt(&mut self, enable: bool) {
-        T::regs().ier().modify(|r| r.set_jeosie(enable));
-    }
-    fn configure_channel(channel: &mut impl AdcChannel<T>, sample_time: SampleTime) {
-        // Configure channel
-        Self::set_channel_sample_time(channel.channel(), sample_time);
-    }
-    fn read_channel(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
-        Self::configure_channel(channel, self.sample_time);
-        #[cfg(stm32h7)]
-        {
-            T::regs().cfgr2().modify(|w| w.set_lshift(0));
-            T::regs()
-                .pcsel()
-                .write(|w| w.set_pcsel(channel.channel() as _, Pcsel::PRESELECTED));
-        }
-        T::regs().sqr1().write(|reg| {
-            reg.set_sq(0, channel.channel());
-            reg.set_l(0);
-        });
-        self.convert()
-    }
-    fn set_channel_sample_time(ch: u8, sample_time: SampleTime) {
-        let sample_time = sample_time.into();
-        if ch <= 9 {
-            T::regs().smpr().modify(|reg| reg.set_smp(ch as _, sample_time));
-        } else {
-            T::regs().smpr2().modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
-        }
-    }
-    // Stop regular conversions
-    fn stop_regular_conversions() {
-        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
-            T::regs().cr().modify(|reg| {
-                reg.set_adstp(Adstp::STOP);
-            });
-            // The software must poll ADSTART until the bit is reset before assuming the
-            // ADC is completely stopped
-            while T::regs().cr().read().adstart() {}
-        }
-    }
 }
 impl<T: Instance, const N: usize> InjectedAdc<T, N> {
@@ -860,62 +546,49 @@ impl<T: Instance, const N: usize> InjectedAdc<T, N> {
    }
 }
-/// Implemented for ADCs that have a Temperature channel
-pub trait TemperatureChannel {
-    const CHANNEL: u8;
-}
-/// Implemented for ADCs that have a Vref channel
-pub trait VrefChannel {
-    const CHANNEL: u8;
-}
-/// Implemented for ADCs that have a VBat channel
-pub trait VBatChannel {
-    const CHANNEL: u8;
-}
 #[cfg(stm32g4)]
 mod g4 {
-    pub use super::*;
+    use crate::adc::{SealedSpecialConverter, Temperature, Vbat, VrefInt};
-    impl TemperatureChannel for crate::peripherals::ADC1 {
+    impl SealedSpecialConverter<Temperature> for crate::peripherals::ADC1 {
        const CHANNEL: u8 = 16;
    }
-    impl VrefChannel for crate::peripherals::ADC1 {
+    impl SealedSpecialConverter<VrefInt> for crate::peripherals::ADC1 {
        const CHANNEL: u8 = 18;
    }
-    impl VBatChannel for crate::peripherals::ADC1 {
+    impl SealedSpecialConverter<Vbat> for crate::peripherals::ADC1 {
        const CHANNEL: u8 = 17;
    }
    #[cfg(peri_adc3_common)]
-    impl VrefChannel for crate::peripherals::ADC3 {
+    impl SealedSpecialConverter<VrefInt> for crate::peripherals::ADC3 {
        const CHANNEL: u8 = 18;
    }
    #[cfg(peri_adc3_common)]
-    impl VBatChannel for crate::peripherals::ADC3 {
+    impl SealedSpecialConverter<Vbat> for crate::peripherals::ADC3 {
        const CHANNEL: u8 = 17;
    }
    #[cfg(not(stm32g4x1))]
-    impl VrefChannel for crate::peripherals::ADC4 {
+    impl SealedSpecialConverter<VrefInt> for crate::peripherals::ADC4 {
        const CHANNEL: u8 = 18;
    }
    #[cfg(not(stm32g4x1))]
-    impl TemperatureChannel for crate::peripherals::ADC5 {
+    impl SealedSpecialConverter<Temperature> for crate::peripherals::ADC5 {
        const CHANNEL: u8 = 4;
    }
    #[cfg(not(stm32g4x1))]
-    impl VrefChannel for crate::peripherals::ADC5 {
+    impl SealedSpecialConverter<VrefInt> for crate::peripherals::ADC5 {
        const CHANNEL: u8 = 18;
    }
    #[cfg(not(stm32g4x1))]
-    impl VBatChannel for crate::peripherals::ADC5 {
+    impl SealedSpecialConverter<Vbat> for crate::peripherals::ADC5 {
        const CHANNEL: u8 = 17;
    }
 }
@@ -923,13 +596,13 @@ mod g4 {
 // TODO this should look at each ADC individually and impl the correct channels
 #[cfg(stm32h7)]
 mod h7 {
-    impl<T: Instance> TemperatureChannel for T {
+    impl<T: Instance> SealedSpecialConverter<Temperature> for T {
        const CHANNEL: u8 = 18;
    }
-    impl<T: Instance> VrefChannel for T {
+    impl<T: Instance> SealedSpecialConverter<VrefInt> for T {
        const CHANNEL: u8 = 19;
    }
-    impl<T: Instance> VBatChannel for T {
+    impl<T: Instance> SealedSpecialConverter<Vbat> for T {
        // TODO this should be 14 for H7a/b/35
        const CHANNEL: u8 = 17;
    }
diff --git a/embassy-stm32/src/adc/injected.rs b/embassy-stm32/src/adc/injected.rs
index 0e4fe5847..ccaa5d1b2 100644
--- a/embassy-stm32/src/adc/injected.rs
+++ b/embassy-stm32/src/adc/injected.rs
@@ -5,9 +5,9 @@ use core::sync::atomic::{Ordering, compiler_fence};
 use embassy_hal_internal::Peri;
 use super::{AnyAdcChannel, SampleTime};
-use crate::adc::Adc;
 #[allow(unused_imports)]
 use crate::adc::Instance;
+use crate::adc::{Adc, AnyInstance};
 /// Injected ADC sequence with owned channels.
 pub struct InjectedAdc<T: Instance, const N: usize> {
@@ -36,9 +36,9 @@ impl<T: Instance, const N: usize> InjectedAdc<T, N> {
    }
 }
-impl<T: Instance, const N: usize> Drop for InjectedAdc<T, N> {
+impl<T: Instance + AnyInstance, const N: usize> Drop for InjectedAdc<T, N> {
    fn drop(&mut self) {
-        Adc::<T>::teardown_adc();
+        T::stop();
        compiler_fence(Ordering::SeqCst);
    }
 }
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index ea7341f75..13f8a1544 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -17,6 +17,9 @@
 #[cfg_attr(adc_c0, path = "c0.rs")]
 mod _version;
+#[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
+mod ringbuffered;
 use core::marker::PhantomData;
 #[allow(unused)]
@@ -25,30 +28,27 @@ pub use _version::*;
 use embassy_hal_internal::{PeripheralType, impl_peripheral};
 #[cfg(any(adc_f1, adc_f3v1, adc_v1, adc_l0, adc_f3v2))]
 use embassy_sync::waitqueue::AtomicWaker;
+#[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
+pub use ringbuffered::RingBufferedAdc;
 #[cfg(any(adc_u5, adc_wba))]
 #[path = "adc4.rs"]
 pub mod adc4;
+#[allow(unused)]
+pub(self) use crate::block_for_us as blocking_delay_us;
 pub use crate::pac::adc::vals;
 #[cfg(not(any(adc_f1, adc_f3v3)))]
 pub use crate::pac::adc::vals::Res as Resolution;
 pub use crate::pac::adc::vals::SampleTime;
 use crate::peripherals;
-#[cfg(not(adc_wba))]
+dma_trait!(RxDma, AnyInstance);
-dma_trait!(RxDma, Instance);
-#[cfg(adc_u5)]
-dma_trait!(RxDma4, adc4::Instance);
-#[cfg(adc_wba)]
-dma_trait!(RxDma4, adc4::Instance);
 /// Analog to Digital driver.
-pub struct Adc<'d, T: Instance> {
+pub struct Adc<'d, T: AnyInstance> {
    #[allow(unused)]
    adc: crate::Peri<'d, T>,
-    #[cfg(not(any(adc_f3v3, adc_f3v2, adc_wba)))]
-    sample_time: SampleTime,
 }
 #[cfg(any(adc_f1, adc_f3v1, adc_v1, adc_l0, adc_f3v2))]
@@ -82,26 +82,294 @@ pub(crate) trait SealedAdcChannel<T> {
    #[allow(unused)]
    fn channel(&self) -> u8;
+    #[allow(unused)]
+    fn is_differential(&self) -> bool {
+        false
+    }
 }
-/// Performs a busy-wait delay for a specified number of microseconds.
+// Temporary patch for ADCs that have not implemented the standard iface yet
-#[allow(unused)]
+#[cfg(any(adc_v1, adc_l0, adc_f1, adc_f3v1, adc_f3v2, adc_f3v3, adc_v1))]
-pub(crate) fn blocking_delay_us(us: u32) {
+trait_set::trait_set! {
-    cfg_if::cfg_if! {
+    pub trait AnyInstance = Instance;
-        // this does strange things on stm32wlx in low power mode depending on exactly when it's called
+}
-        // as in sometimes 15 us (1 tick) would take > 20 seconds.
-        if #[cfg(all(feature = "time", all(not(feature = "low-power"), not(stm32wlex))))] {
+#[cfg(any(
-            let duration = embassy_time::Duration::from_micros(us as u64);
+    adc_v2, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_g4, adc_c0
-            embassy_time::block_for(duration);
+))]
-        } else {
+pub trait BasicAnyInstance {
-            let freq = unsafe { crate::rcc::get_freqs() }.sys.to_hertz().unwrap().0 as u64;
+    type SampleTime;
-            let us = us as u64;
+}
-            let cycles = freq * us / 1_000_000;
-            cortex_m::asm::delay(cycles as u32);
+#[cfg(any(
-        }
+    adc_v2, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_g4, adc_c0
+))]
+pub(self) trait SealedAnyInstance: BasicAnyInstance {
+    fn enable();
+    fn start();
+    fn stop();
+    fn convert() -> u16;
+    fn configure_dma(conversion_mode: ConversionMode);
+    fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), Self::SampleTime)>);
+    #[allow(dead_code)]
+    fn dr() -> *mut u16;
+}
+// On chips without ADC4, AnyInstance is an Instance
+#[cfg(any(adc_v2, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_g4, adc_c0))]
+#[allow(private_bounds)]
+pub trait AnyInstance: SealedAnyInstance + Instance {}
+// On chips with ADC4, AnyInstance is an Instance or adc4::Instance
+#[cfg(any(adc_v4, adc_u5, adc_wba))]
+#[allow(private_bounds)]
+pub trait AnyInstance: SealedAnyInstance + crate::PeripheralType + crate::rcc::RccPeripheral {}
+// Implement AnyInstance automatically for SealedAnyInstance
+#[cfg(any(
+    adc_v2, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_g4, adc_c0
+))]
+impl<T: SealedAnyInstance + Instance> BasicAnyInstance for T {
+    type SampleTime = SampleTime;
+}
+#[cfg(any(
+    adc_v2, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_g4, adc_c0
+))]
+impl<T: SealedAnyInstance + Instance> AnyInstance for T {}
+#[cfg(any(adc_c0, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5))]
+/// Number of samples used for averaging.
+#[derive(Copy, Clone, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Averaging {
+    Disabled,
+    Samples2,
+    Samples4,
+    Samples8,
+    Samples16,
+    Samples32,
+    Samples64,
+    Samples128,
+    Samples256,
+    #[cfg(any(adc_c0, adc_v4, adc_u5))]
+    Samples512,
+    #[cfg(any(adc_c0, adc_v4, adc_u5))]
+    Samples1024,
+}
+#[cfg(any(
+    adc_v2, adc_g4, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_c0
+))]
+pub(crate) enum ConversionMode {
+    // Should match the cfg on "read" below
+    #[cfg(any(adc_g4, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_c0))]
+    Singular,
+    // Should match the cfg on "into_ring_buffered" below
+    #[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
+    Repeated(RegularConversionMode),
+}
+// Should match the cfg on "into_ring_buffered" below
+#[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
+// Conversion mode for regular ADC channels
+#[derive(Copy, Clone)]
+pub enum RegularConversionMode {
+    // Samples as fast as possible
+    Continuous,
+    #[cfg(adc_g4)]
+    // Sample at rate determined by external trigger
+    Triggered(ConversionTrigger),
+}
+impl<'d, T: AnyInstance> Adc<'d, T> {
+    #[cfg(any(
+        adc_v2, adc_g4, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_u5, adc_v4, adc_wba, adc_c0
+    ))]
+    /// Read an ADC pin.
+    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>, sample_time: T::SampleTime) -> u16 {
+        #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5, adc_wba))]
+        channel.setup();
+        #[cfg(not(adc_v4))]
+        T::enable();
+        T::configure_sequence([((channel.channel(), channel.is_differential()), sample_time)].into_iter());
+        T::convert()
    }
+    #[cfg(any(adc_g4, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_c0))]
+    /// Read one or multiple ADC regular channels using DMA.
+    ///
+    /// `sequence` iterator and `readings` must have the same length.
+    ///
+    /// Example
+    /// ```rust,ignore
+    /// use embassy_stm32::adc::{Adc, AdcChannel}
+    ///
+    /// let mut adc = Adc::new(p.ADC1);
+    /// let mut adc_pin0 = p.PA0.into();
+    /// let mut adc_pin1 = p.PA1.into();
+    /// let mut measurements = [0u16; 2];
+    ///
+    /// adc.read(
+    ///     p.DMA1_CH2.reborrow(),
+    ///     [
+    ///         (&mut *adc_pin0, SampleTime::CYCLES160_5),
+    ///         (&mut *adc_pin1, SampleTime::CYCLES160_5),
+    ///     ]
+    ///     .into_iter(),
+    ///     &mut measurements,
+    /// )
+    /// .await;
+    /// defmt::info!("measurements: {}", measurements);
+    /// ```
+    ///
+    /// Note: This is not very efficient as the ADC needs to be reconfigured for each read. Use
+    /// `into_ring_buffered`, `into_ring_buffered_and_injected`
+    ///
+    /// In STM32C0, channels bigger than 14 cannot be read using sequencer, so you have to use
+    /// either blocking reads or use the mechanism to read in HW order (CHSELRMOD=0).
+    ///
+    /// In addtion, on STM320, this method will panic if the channels are not passed in order
+    pub async fn read(
+        &mut self,
+        rx_dma: embassy_hal_internal::Peri<'_, impl RxDma<T>>,
+        sequence: impl ExactSizeIterator<Item = (&mut AnyAdcChannel<T>, T::SampleTime)>,
+        readings: &mut [u16],
+    ) {
+        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
+        assert!(
+            sequence.len() == readings.len(),
+            "Sequence length must be equal to readings length"
+        );
+        assert!(
+            sequence.len() <= 16,
+            "Asynchronous read sequence cannot be more than 16 in length"
+        );
+        // Ensure no conversions are ongoing and ADC is enabled.
+        T::stop();
+        T::enable();
+        T::configure_sequence(
+            sequence.map(|(channel, sample_time)| ((channel.channel, channel.is_differential), sample_time)),
+        );
+        T::configure_dma(ConversionMode::Singular);
+        let request = rx_dma.request();
+        let transfer =
+            unsafe { crate::dma::Transfer::new_read(rx_dma, request, T::dr(), readings, Default::default()) };
+        T::start();
+        // Wait for conversion sequence to finish.
+        transfer.await;
+        // Ensure conversions are finished.
+        T::stop();
+    }
+    #[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
+    /// Configures the ADC to use a DMA ring buffer for continuous data acquisition.
+    ///
+    /// Use the [`read`] method to retrieve measurements from the DMA ring buffer. The read buffer
+    /// should be exactly half the size of `dma_buf`. When using triggered mode, it is recommended
+    /// to configure `dma_buf` as a double buffer so that one half can be read while the other half
+    /// is being filled by the DMA, preventing data loss. The trigger period of the ADC effectively
+    /// defines the period at which the buffer should be read.
+    ///
+    /// If continous conversion mode is selected, the provided `dma_buf` must be large enough to prevent
+    /// DMA buffer overruns. Its length should be a multiple of the number of ADC channels being measured.
+    /// For example, if 3 channels are measured and you want to store 40 samples per channel,
+    /// the buffer length should be `3 * 40 = 120`.
+    ///
+    /// # Parameters
+    /// - `dma`: The DMA peripheral used to transfer ADC data into the buffer.
+    /// - `dma_buf`: The buffer where DMA stores ADC samples.
+    /// - `regular_sequence`: Sequence of channels and sample times for regular ADC conversions.
+    /// - `regular_conversion_mode`: Mode for regular conversions (continuous or triggered).
+    ///
+    /// # Returns
+    /// A `RingBufferedAdc<'a, T>` instance configured for continuous DMA-based sampling.
+    pub fn into_ring_buffered<'a>(
+        self,
+        dma: embassy_hal_internal::Peri<'a, impl RxDma<T>>,
+        dma_buf: &'a mut [u16],
+        sequence: impl ExactSizeIterator<Item = (AnyAdcChannel<T>, T::SampleTime)>,
+        mode: RegularConversionMode,
+    ) -> RingBufferedAdc<'a, T> {
+        assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
+        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
+        assert!(
+            sequence.len() <= 16,
+            "Asynchronous read sequence cannot be more than 16 in length"
+        );
+        // reset conversions and enable the adc
+        T::stop();
+        T::enable();
+        //adc side setup
+        T::configure_sequence(
+            sequence.map(|(channel, sample_time)| ((channel.channel, channel.is_differential), sample_time)),
+        );
+        T::configure_dma(ConversionMode::Repeated(mode));
+        core::mem::forget(self);
+        RingBufferedAdc::new(dma, dma_buf)
+    }
+}
+pub(self) trait SpecialChannel {}
+/// Implemented for ADCs that have a special channel
+trait SealedSpecialConverter<T: SpecialChannel + Sized> {
+    const CHANNEL: u8;
 }
+#[allow(private_bounds)]
+pub trait SpecialConverter<T: SpecialChannel + Sized>: SealedSpecialConverter<T> {}
+impl<C: SpecialChannel + Sized, T: SealedSpecialConverter<C>> SpecialConverter<C> for T {}
+impl<C: SpecialChannel, T: Instance + SealedSpecialConverter<C>> AdcChannel<T> for C {}
+impl<C: SpecialChannel, T: Instance + SealedSpecialConverter<C>> SealedAdcChannel<T> for C {
+    fn channel(&self) -> u8 {
+        T::CHANNEL
+    }
+}
+pub struct VrefInt;
+impl SpecialChannel for VrefInt {}
+impl VrefInt {
+    #[cfg(any(adc_f3v1, adc_f3v2))]
+    /// The value that vref would be if vdda was at 3300mv
+    pub fn calibrated_value(&self) -> u16 {
+        crate::pac::VREFINTCAL.data().read()
+    }
+}
+/// Internal temperature channel.
+pub struct Temperature;
+impl SpecialChannel for Temperature {}
+/// Internal battery voltage channel.
+pub struct Vbat;
+impl SpecialChannel for Vbat {}
+/// Vcore channel.
+pub struct Vcore;
+impl SpecialChannel for Vcore {}
+/// Internal dac channel.
+pub struct Dac;
+impl SpecialChannel for Dac {}
 /// ADC instance.
 #[cfg(not(any(
    adc_f1, adc_v1, adc_l0, adc_v2, adc_v3, adc_v4, adc_g4, adc_f3v1, adc_f3v2, adc_g0, adc_u0, adc_h5, adc_h7rs,
@@ -131,6 +399,7 @@ pub trait AdcChannel<T>: SealedAdcChannel<T> + Sized {
        AnyAdcChannel {
            channel: self.channel(),
+            is_differential: self.is_differential(),
            _phantom: PhantomData,
        }
    }
@@ -142,6 +411,7 @@ pub trait AdcChannel<T>: SealedAdcChannel<T> + Sized {
 /// storing them in an array.
 pub struct AnyAdcChannel<T> {
    channel: u8,
+    is_differential: bool,
    _phantom: PhantomData<T>,
 }
 impl_peripheral!(AnyAdcChannel<T: Instance>);
@@ -150,6 +420,10 @@ impl<T: Instance> SealedAdcChannel<T> for AnyAdcChannel<T> {
    fn channel(&self) -> u8 {
        self.channel
    }
+    fn is_differential(&self) -> bool {
+        self.is_differential
+    }
 }
 impl<T> AnyAdcChannel<T> {
@@ -268,6 +542,39 @@ macro_rules! impl_adc_pin {
    };
 }
+#[allow(unused_macros)]
+macro_rules! impl_adc_pair {
+    ($inst:ident, $pin:ident, $npin:ident, $ch:expr) => {
+        impl crate::adc::AdcChannel<peripherals::$inst>
+            for (
+                crate::Peri<'_, crate::peripherals::$pin>,
+                crate::Peri<'_, crate::peripherals::$npin>,
+            )
+        {
+        }
+        impl crate::adc::SealedAdcChannel<peripherals::$inst>
+            for (
+                crate::Peri<'_, crate::peripherals::$pin>,
+                crate::Peri<'_, crate::peripherals::$npin>,
+            )
+        {
+            #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5, adc_wba))]
+            fn setup(&mut self) {
+                <crate::peripherals::$pin as crate::gpio::SealedPin>::set_as_analog(&mut self.0);
+                <crate::peripherals::$npin as crate::gpio::SealedPin>::set_as_analog(&mut self.1);
+            }
+            fn channel(&self) -> u8 {
+                $ch
+            }
+            fn is_differential(&self) -> bool {
+                true
+            }
+        }
+    };
+}
 /// Get the maximum reading value for this resolution.
 ///
 /// This is `2**n - 1`.
diff --git a/embassy-stm32/src/adc/ringbuffered.rs b/embassy-stm32/src/adc/ringbuffered.rs
index 971c8195c..a56f8ca0b 100644
--- a/embassy-stm32/src/adc/ringbuffered.rs
+++ b/embassy-stm32/src/adc/ringbuffered.rs
@@ -4,7 +4,7 @@ use core::sync::atomic::{Ordering, compiler_fence};
 #[allow(unused_imports)]
 use embassy_hal_internal::Peri;
-use crate::adc::Adc;
+use crate::adc::AnyInstance;
 #[allow(unused_imports)]
 use crate::adc::{Instance, RxDma};
 #[allow(unused_imports)]
@@ -19,7 +19,7 @@ pub struct RingBufferedAdc<'d, T: Instance> {
    ring_buf: ReadableRingBuffer<'d, u16>,
 }
-impl<'d, T: Instance> RingBufferedAdc<'d, T> {
+impl<'d, T: Instance + AnyInstance> RingBufferedAdc<'d, T> {
    pub(crate) fn new(dma: Peri<'d, impl RxDma<T>>, dma_buf: &'d mut [u16]) -> Self {
        //dma side setup
        let opts = TransferOptions {
@@ -45,11 +45,11 @@ impl<'d, T: Instance> RingBufferedAdc<'d, T> {
        compiler_fence(Ordering::SeqCst);
        self.ring_buf.start();
-        Adc::<T>::start();
+        T::start();
    }
    pub fn stop(&mut self) {
-        Adc::<T>::stop();
+        T::stop();
        self.ring_buf.request_pause();
@@ -170,9 +170,9 @@ impl<'d, T: Instance> RingBufferedAdc<'d, T> {
    }
 }
-impl<T: Instance> Drop for RingBufferedAdc<'_, T> {
+impl<T: Instance + AnyInstance> Drop for RingBufferedAdc<'_, T> {
    fn drop(&mut self) {
-        Adc::<T>::teardown_adc();
+        T::stop();
        compiler_fence(Ordering::SeqCst);
diff --git a/embassy-stm32/src/adc/v1.rs b/embassy-stm32/src/adc/v1.rs
index a5869d110..58c30935f 100644
--- a/embassy-stm32/src/adc/v1.rs
+++ b/embassy-stm32/src/adc/v1.rs
@@ -5,10 +5,11 @@ use core::task::Poll;
 #[cfg(adc_l0)]
 use stm32_metapac::adc::vals::Ckmode;
-use super::blocking_delay_us;
+#[cfg(not(adc_l0))]
+use super::Vbat;
+use super::{Temperature, VrefInt, blocking_delay_us};
 use crate::adc::{Adc, AdcChannel, Instance, Resolution, SampleTime};
 use crate::interrupt::typelevel::Interrupt;
-use crate::peripherals::ADC1;
 use crate::{Peri, interrupt, rcc};
 mod watchdog_v1;
@@ -42,32 +43,23 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
 }
 #[cfg(not(adc_l0))]
-pub struct Vbat;
+impl super::SealedSpecialConverter<super::Vbat> for crate::peripherals::ADC1 {
+    const CHANNEL: u8 = 18;
-#[cfg(not(adc_l0))]
+}
-impl AdcChannel<ADC1> for Vbat {}
 #[cfg(not(adc_l0))]
-impl super::SealedAdcChannel<ADC1> for Vbat {
+impl super::SealedSpecialConverter<super::VrefInt> for crate::peripherals::ADC1 {
-    fn channel(&self) -> u8 {
+    const CHANNEL: u8 = 17;
-        18
-    }
 }
-pub struct Vref;
+#[cfg(adc_l0)]
-impl AdcChannel<ADC1> for Vref {}
+impl super::SealedSpecialConverter<super::VrefInt> for crate::peripherals::ADC1 {
-impl super::SealedAdcChannel<ADC1> for Vref {
+    const CHANNEL: u8 = 18;
-    fn channel(&self) -> u8 {
-        17
-    }
 }
-pub struct Temperature;
+#[cfg(not(adc_l0))]
-impl AdcChannel<ADC1> for Temperature {}
+impl super::SealedSpecialConverter<super::Temperature> for crate::peripherals::ADC1 {
-impl super::SealedAdcChannel<ADC1> for Temperature {
+    const CHANNEL: u8 = 16;
-    fn channel(&self) -> u8 {
-        if cfg!(adc_l0) { 18 } else { 16 }
-    }
 }
 impl<'d, T: Instance> Adc<'d, T> {
@@ -114,10 +106,7 @@ impl<'d, T: Instance> Adc<'d, T> {
            T::Interrupt::enable();
        }
-        Self {
+        Self { adc }
-            adc,
-            sample_time: SampleTime::from_bits(0),
-        }
    }
    #[cfg(not(adc_l0))]
@@ -130,12 +119,12 @@ impl<'d, T: Instance> Adc<'d, T> {
        Vbat
    }
-    pub fn enable_vref(&self) -> Vref {
+    pub fn enable_vref(&self) -> VrefInt {
        // Table 28. Embedded internal reference voltage
        // tstart = 10μs
        T::regs().ccr().modify(|reg| reg.set_vrefen(true));
        blocking_delay_us(10);
-        Vref
+        VrefInt
    }
    pub fn enable_temperature(&self) -> Temperature {
@@ -149,10 +138,6 @@ impl<'d, T: Instance> Adc<'d, T> {
        Temperature
    }
-    pub fn set_sample_time(&mut self, sample_time: SampleTime) {
-        self.sample_time = sample_time;
-    }
    pub fn set_resolution(&mut self, resolution: Resolution) {
        T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into()));
    }
@@ -163,12 +148,13 @@ impl<'d, T: Instance> Adc<'d, T> {
        T::regs().cfgr2().modify(|reg| reg.set_ckmode(ckmode));
    }
-    pub async fn read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
+    pub async fn read(&mut self, channel: &mut impl AdcChannel<T>, sample_time: SampleTime) -> u16 {
        let ch_num = channel.channel();
        channel.setup();
        // A.7.5 Single conversion sequence code example - Software trigger
        T::regs().chselr().write(|reg| reg.set_chsel_x(ch_num as usize, true));
+        T::regs().smpr().modify(|reg| reg.set_smp(sample_time.into()));
        self.convert().await
    }
@@ -179,7 +165,6 @@ impl<'d, T: Instance> Adc<'d, T> {
            reg.set_eosmp(true);
        });
-        T::regs().smpr().modify(|reg| reg.set_smp(self.sample_time.into()));
        T::regs().ier().modify(|w| w.set_eocie(true));
        T::regs().cr().modify(|reg| reg.set_adstart(true));
diff --git a/embassy-stm32/src/adc/v2.rs b/embassy-stm32/src/adc/v2.rs
index 90c6294d2..07eaebf7c 100644
--- a/embassy-stm32/src/adc/v2.rs
+++ b/embassy-stm32/src/adc/v2.rs
@@ -1,16 +1,12 @@
-use core::mem;
 use core::sync::atomic::{Ordering, compiler_fence};
-use super::blocking_delay_us;
+use super::{ConversionMode, Temperature, Vbat, VrefInt, blocking_delay_us};
-use crate::adc::{Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel};
+use crate::adc::{Adc, Instance, Resolution, SampleTime};
 use crate::pac::adc::vals;
-use crate::peripherals::ADC1;
+pub use crate::pac::adccommon::vals::Adcpre;
 use crate::time::Hertz;
 use crate::{Peri, rcc};
-mod ringbuffered;
-pub use ringbuffered::RingBufferedAdc;
 fn clear_interrupt_flags(r: crate::pac::adc::Adc) {
    r.sr().modify(|regs| {
        regs.set_eoc(false);
@@ -23,12 +19,22 @@ pub const VREF_DEFAULT_MV: u32 = 3300;
 /// VREF voltage used for factory calibration of VREFINTCAL register.
 pub const VREF_CALIB_MV: u32 = 3300;
-pub struct VrefInt;
+impl super::SealedSpecialConverter<super::VrefInt> for crate::peripherals::ADC1 {
-impl AdcChannel<ADC1> for VrefInt {}
+    const CHANNEL: u8 = 17;
-impl super::SealedAdcChannel<ADC1> for VrefInt {
+}
-    fn channel(&self) -> u8 {
-        17
+#[cfg(any(stm32f2, stm32f40x, stm32f41x))]
-    }
+impl super::SealedSpecialConverter<super::Temperature> for crate::peripherals::ADC1 {
+    const CHANNEL: u8 = 16;
+}
+#[cfg(not(any(stm32f2, stm32f40x, stm32f41x)))]
+impl super::SealedSpecialConverter<super::Temperature> for crate::peripherals::ADC1 {
+    const CHANNEL: u8 = 18;
+}
+impl super::SealedSpecialConverter<super::Vbat> for crate::peripherals::ADC1 {
+    const CHANNEL: u8 = 18;
 }
 impl VrefInt {
@@ -38,20 +44,6 @@ impl VrefInt {
    }
 }
-pub struct Temperature;
-impl AdcChannel<ADC1> for Temperature {}
-impl super::SealedAdcChannel<ADC1> for Temperature {
-    fn channel(&self) -> u8 {
-        cfg_if::cfg_if! {
-            if #[cfg(any(stm32f2, stm32f40x, stm32f41x))] {
-                16
-            } else {
-                18
-            }
-        }
-    }
-}
 impl Temperature {
    /// Time needed for temperature sensor readings to stabilize
    pub fn start_time_us() -> u32 {
@@ -59,168 +51,175 @@ impl Temperature {
    }
 }
-pub struct Vbat;
+fn from_pclk2(freq: Hertz) -> Adcpre {
-impl AdcChannel<ADC1> for Vbat {}
+    // Datasheet for F2 specifies min frequency 0.6 MHz, and max 30 MHz (with VDDA 2.4-3.6V).
-impl super::SealedAdcChannel<ADC1> for Vbat {
+    #[cfg(stm32f2)]
-    fn channel(&self) -> u8 {
+    const MAX_FREQUENCY: Hertz = Hertz(30_000_000);
-        18
+    // Datasheet for both F4 and F7 specifies min frequency 0.6 MHz, typ freq. 30 MHz and max 36 MHz.
+    #[cfg(not(stm32f2))]
+    const MAX_FREQUENCY: Hertz = Hertz(36_000_000);
+    let raw_div = freq.0 / MAX_FREQUENCY.0;
+    match raw_div {
+        0..=1 => Adcpre::DIV2,
+        2..=3 => Adcpre::DIV4,
+        4..=5 => Adcpre::DIV6,
+        6..=7 => Adcpre::DIV8,
+        _ => panic!("Selected PCLK2 frequency is too high for ADC with largest possible prescaler."),
    }
 }
-enum Prescaler {
+/// ADC configuration
-    Div2,
+#[derive(Default)]
-    Div4,
+pub struct AdcConfig {
-    Div6,
+    resolution: Option<Resolution>,
-    Div8,
 }
-impl Prescaler {
+impl<T: Instance> super::SealedAnyInstance for T {
-    fn from_pclk2(freq: Hertz) -> Self {
+    fn dr() -> *mut u16 {
-        // Datasheet for F2 specifies min frequency 0.6 MHz, and max 30 MHz (with VDDA 2.4-3.6V).
+        T::regs().dr().as_ptr() as *mut u16
-        #[cfg(stm32f2)]
-        const MAX_FREQUENCY: Hertz = Hertz(30_000_000);
-        // Datasheet for both F4 and F7 specifies min frequency 0.6 MHz, typ freq. 30 MHz and max 36 MHz.
-        #[cfg(not(stm32f2))]
-        const MAX_FREQUENCY: Hertz = Hertz(36_000_000);
-        let raw_div = freq.0 / MAX_FREQUENCY.0;
-        match raw_div {
-            0..=1 => Self::Div2,
-            2..=3 => Self::Div4,
-            4..=5 => Self::Div6,
-            6..=7 => Self::Div8,
-            _ => panic!("Selected PCLK2 frequency is too high for ADC with largest possible prescaler."),
-        }
    }
-    fn adcpre(&self) -> crate::pac::adccommon::vals::Adcpre {
+    fn enable() {}
-        match self {
-            Prescaler::Div2 => crate::pac::adccommon::vals::Adcpre::DIV2,
-            Prescaler::Div4 => crate::pac::adccommon::vals::Adcpre::DIV4,
-            Prescaler::Div6 => crate::pac::adccommon::vals::Adcpre::DIV6,
-            Prescaler::Div8 => crate::pac::adccommon::vals::Adcpre::DIV8,
-        }
-    }
-}
-impl<'d, T> Adc<'d, T>
+    fn start() {
-where
+        // Begin ADC conversions
-    T: Instance,
-{
-    pub fn new(adc: Peri<'d, T>) -> Self {
-        rcc::enable_and_reset::<T>();
-        let presc = Prescaler::from_pclk2(T::frequency());
-        T::common_regs().ccr().modify(|w| w.set_adcpre(presc.adcpre()));
        T::regs().cr2().modify(|reg| {
            reg.set_adon(true);
+            reg.set_swstart(true);
        });
-        blocking_delay_us(3);
-        Self {
-            adc,
-            sample_time: SampleTime::from_bits(0),
-        }
    }
-    /// Configures the ADC to use a DMA ring buffer for continuous data acquisition.
+    fn stop() {
-    ///
+        let r = T::regs();
-    /// The `dma_buf` should be large enough to prevent DMA buffer overrun.
-    /// The length of the `dma_buf` should be a multiple of the ADC channel count.
-    /// For example, if 3 channels are measured, its length can be 3 * 40 = 120 measurements.
-    ///
-    /// `read` method is used to read out measurements from the DMA ring buffer, and its buffer should be exactly half of the `dma_buf` length.
-    /// It is critical to call `read` frequently to prevent DMA buffer overrun.
-    ///
-    /// [`read`]: #method.read
-    pub fn into_ring_buffered<'a>(
-        self,
-        dma: Peri<'d, impl RxDma<T>>,
-        dma_buf: &'d mut [u16],
-        sequence: impl ExactSizeIterator<Item = (&'a mut AnyAdcChannel<T>, SampleTime)>,
-    ) -> RingBufferedAdc<'d, T> {
-        assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
-        T::regs().cr2().modify(|reg| {
+        // Stop ADC
-            reg.set_adon(true);
+        r.cr2().modify(|reg| {
+            // Stop ADC
+            reg.set_swstart(false);
+            // Stop ADC
+            reg.set_adon(false);
+            // Stop DMA
+            reg.set_dma(false);
        });
-        // Check the sequence is long enough
+        r.cr1().modify(|w| {
-        T::regs().sqr1().modify(|r| {
+            // Disable interrupt for end of conversion
-            r.set_l((sequence.len() - 1).try_into().unwrap());
+            w.set_eocie(false);
+            // Disable interrupt for overrun
+            w.set_ovrie(false);
        });
-        for (i, (channel, sample_time)) in sequence.enumerate() {
+        clear_interrupt_flags(r);
-            // Set this GPIO as an analog input.
-            channel.setup();
-            // Set the channel in the right sequence field.
-            T::regs().sqr3().modify(|w| w.set_sq(i, channel.channel()));
-            Self::set_channel_sample_time(channel.channel(), sample_time);
-        }
        compiler_fence(Ordering::SeqCst);
+    }
-        let r = T::regs();
+    fn convert() -> u16 {
+        // clear end of conversion flag
-        // Clear all interrupts
+        T::regs().sr().modify(|reg| {
-        r.sr().modify(|regs| {
+            reg.set_eoc(false);
-            regs.set_eoc(false);
-            regs.set_ovr(false);
-            regs.set_strt(false);
        });
-        r.cr1().modify(|w| {
+        // Start conversion
-            // Enable interrupt for end of conversion
+        T::regs().cr2().modify(|reg| {
-            w.set_eocie(true);
+            reg.set_swstart(true);
-            // Enable interrupt for overrun
-            w.set_ovrie(true);
-            // Scanning converisons of multiple channels
-            w.set_scan(true);
-            // Continuous conversion mode
-            w.set_discen(false);
        });
-        r.cr2().modify(|w| {
+        while T::regs().sr().read().strt() == false {
-            // Enable DMA mode
+            // spin //wait for actual start
-            w.set_dma(true);
+        }
-            // Enable continuous conversions
+        while T::regs().sr().read().eoc() == false {
-            w.set_cont(true);
+            // spin //wait for finish
-            // DMA requests are issues as long as DMA=1 and data are converted.
+        }
-            w.set_dds(vals::Dds::CONTINUOUS);
-            // EOC flag is set at the end of each conversion.
-            w.set_eocs(vals::Eocs::EACH_CONVERSION);
-        });
-        // Don't disable the clock
+        T::regs().dr().read().0 as u16
-        mem::forget(self);
+    }
-        RingBufferedAdc::new(dma, dma_buf)
+    fn configure_dma(conversion_mode: ConversionMode) {
+        match conversion_mode {
+            ConversionMode::Repeated(_) => {
+                let r = T::regs();
+                // Clear all interrupts
+                r.sr().modify(|regs| {
+                    regs.set_eoc(false);
+                    regs.set_ovr(false);
+                    regs.set_strt(false);
+                });
+                r.cr1().modify(|w| {
+                    // Enable interrupt for end of conversion
+                    w.set_eocie(true);
+                    // Enable interrupt for overrun
+                    w.set_ovrie(true);
+                    // Scanning converisons of multiple channels
+                    w.set_scan(true);
+                    // Continuous conversion mode
+                    w.set_discen(false);
+                });
+                r.cr2().modify(|w| {
+                    // Enable DMA mode
+                    w.set_dma(true);
+                    // Enable continuous conversions
+                    w.set_cont(true);
+                    // DMA requests are issues as long as DMA=1 and data are converted.
+                    w.set_dds(vals::Dds::CONTINUOUS);
+                    // EOC flag is set at the end of each conversion.
+                    w.set_eocs(vals::Eocs::EACH_CONVERSION);
+                });
+            }
+        }
    }
-    pub(super) fn start() {
+    fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
-        // Begin ADC conversions
        T::regs().cr2().modify(|reg| {
            reg.set_adon(true);
-            reg.set_swstart(true);
        });
-    }
-    pub(super) fn stop() {
+        // Check the sequence is long enough
-        // Stop ADC
+        T::regs().sqr1().modify(|r| {
-        T::regs().cr2().modify(|reg| {
+            r.set_l((sequence.len() - 1).try_into().unwrap());
-            // Stop ADC
-            reg.set_swstart(false);
        });
+        for (i, ((ch, _), sample_time)) in sequence.enumerate() {
+            // Set the channel in the right sequence field.
+            T::regs().sqr3().modify(|w| w.set_sq(i, ch));
+            let sample_time = sample_time.into();
+            if ch <= 9 {
+                T::regs().smpr2().modify(|reg| reg.set_smp(ch as _, sample_time));
+            } else {
+                T::regs().smpr1().modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
+            }
+        }
    }
+}
-    pub fn set_sample_time(&mut self, sample_time: SampleTime) {
+impl<'d, T> Adc<'d, T>
-        self.sample_time = sample_time;
+where
+    T: Instance,
+{
+    pub fn new(adc: Peri<'d, T>) -> Self {
+        Self::new_with_config(adc, Default::default())
    }
-    pub fn set_resolution(&mut self, resolution: Resolution) {
+    pub fn new_with_config(adc: Peri<'d, T>, config: AdcConfig) -> Self {
-        T::regs().cr1().modify(|reg| reg.set_res(resolution.into()));
+        rcc::enable_and_reset::<T>();
+        let presc = from_pclk2(T::frequency());
+        T::common_regs().ccr().modify(|w| w.set_adcpre(presc));
+        T::regs().cr2().modify(|reg| {
+            reg.set_adon(true);
+        });
+        blocking_delay_us(3);
+        if let Some(resolution) = config.resolution {
+            T::regs().cr1().modify(|reg| reg.set_res(resolution.into()));
+        }
+        Self { adc }
    }
    /// Enables internal voltage reference and returns [VrefInt], which can be used in
@@ -255,77 +254,6 @@ where
        Vbat {}
    }
-    /// Perform a single conversion.
-    fn convert(&mut self) -> u16 {
-        // clear end of conversion flag
-        T::regs().sr().modify(|reg| {
-            reg.set_eoc(false);
-        });
-        // Start conversion
-        T::regs().cr2().modify(|reg| {
-            reg.set_swstart(true);
-        });
-        while T::regs().sr().read().strt() == false {
-            // spin //wait for actual start
-        }
-        while T::regs().sr().read().eoc() == false {
-            // spin //wait for finish
-        }
-        T::regs().dr().read().0 as u16
-    }
-    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
-        channel.setup();
-        // Configure ADC
-        let channel = channel.channel();
-        // Select channel
-        T::regs().sqr3().write(|reg| reg.set_sq(0, channel));
-        // Configure channel
-        Self::set_channel_sample_time(channel, self.sample_time);
-        self.convert()
-    }
-    fn set_channel_sample_time(ch: u8, sample_time: SampleTime) {
-        let sample_time = sample_time.into();
-        if ch <= 9 {
-            T::regs().smpr2().modify(|reg| reg.set_smp(ch as _, sample_time));
-        } else {
-            T::regs().smpr1().modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
-        }
-    }
-    pub(super) fn teardown_adc() {
-        let r = T::regs();
-        // Stop ADC
-        r.cr2().modify(|reg| {
-            // Stop ADC
-            reg.set_swstart(false);
-            // Stop ADC
-            reg.set_adon(false);
-            // Stop DMA
-            reg.set_dma(false);
-        });
-        r.cr1().modify(|w| {
-            // Disable interrupt for end of conversion
-            w.set_eocie(false);
-            // Disable interrupt for overrun
-            w.set_ovrie(false);
-        });
-        clear_interrupt_flags(r);
-        compiler_fence(Ordering::SeqCst);
-    }
 }
 impl<'d, T: Instance> Drop for Adc<'d, T> {
diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs
index 170b08a25..81eb1e3ee 100644
--- a/embassy-stm32/src/adc/v3.rs
+++ b/embassy-stm32/src/adc/v3.rs
@@ -1,25 +1,18 @@
 use cfg_if::cfg_if;
 #[cfg(adc_g0)]
 use heapless::Vec;
-use pac::adc::vals::Dmacfg;
 #[cfg(adc_g0)]
-use pac::adc::vals::{Ckmode, Smpsel};
+use pac::adc::vals::Ckmode;
+use pac::adc::vals::Dmacfg;
 #[cfg(adc_v3)]
 use pac::adc::vals::{OversamplingRatio, OversamplingShift, Rovsm, Trovs};
 #[cfg(adc_g0)]
 pub use pac::adc::vals::{Ovsr, Ovss, Presc};
-use super::{
+#[allow(unused_imports)]
-    Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel, blocking_delay_us,
+use super::SealedAdcChannel;
-};
+use super::{Adc, Averaging, Instance, Resolution, SampleTime, Temperature, Vbat, VrefInt, blocking_delay_us};
+use crate::adc::ConversionMode;
-#[cfg(any(adc_v3, adc_g0, adc_u0))]
-mod ringbuffered;
-#[cfg(any(adc_v3, adc_g0, adc_u0))]
-use ringbuffered::RingBufferedAdc;
-use crate::dma::Transfer;
 use crate::{Peri, pac, rcc};
 /// Default VREF voltage used for sample conversion to millivolts.
@@ -32,70 +25,64 @@ pub const VREF_CALIB_MV: u32 = 3000;
 // TODO: Use [#![feature(variant_count)]](https://github.com/rust-lang/rust/issues/73662) when stable
 const SAMPLE_TIMES_CAPACITY: usize = 2;
-pub struct VrefInt;
+#[cfg(adc_g0)]
-impl<T: Instance> AdcChannel<T> for VrefInt {}
+impl<T: Instance> super::SealedSpecialConverter<super::VrefInt> for T {
-impl<T: Instance> SealedAdcChannel<T> for VrefInt {
+    const CHANNEL: u8 = 13;
-    fn channel(&self) -> u8 {
+}
-        cfg_if! {
+#[cfg(any(adc_h5, adc_h7rs))]
-            if #[cfg(adc_g0)] {
+impl<T: Instance> super::SealedSpecialConverter<super::VrefInt> for T {
-                let val = 13;
+    const CHANNEL: u8 = 17;
-            } else if #[cfg(any(adc_h5, adc_h7rs))] {
+}
-                let val = 17;
+#[cfg(adc_u0)]
-            } else if #[cfg(adc_u0)] {
+impl<T: Instance> super::SealedSpecialConverter<super::VrefInt> for T {
-                let val = 12;
+    const CHANNEL: u8 = 12;
-            } else {
+}
-                let val = 0;
+#[cfg(not(any(adc_g0, adc_h5, adc_h7rs, adc_u0)))]
-            }
+impl<T: Instance> super::SealedSpecialConverter<super::VrefInt> for T {
-        }
+    const CHANNEL: u8 = 0;
-        val
-    }
 }
-pub struct Temperature;
+#[cfg(adc_g0)]
-impl<T: Instance> AdcChannel<T> for Temperature {}
+impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
-impl<T: Instance> SealedAdcChannel<T> for Temperature {
+    const CHANNEL: u8 = 12;
-    fn channel(&self) -> u8 {
+}
-        cfg_if! {
+#[cfg(any(adc_h5, adc_h7rs))]
-            if #[cfg(adc_g0)] {
+impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
-                let val = 12;
+    const CHANNEL: u8 = 16;
-            } else if #[cfg(any(adc_h5, adc_h7rs))] {
+}
-                let val = 16;
+#[cfg(adc_u0)]
-            } else if #[cfg(adc_u0)] {
+impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
-                let val = 11;
+    const CHANNEL: u8 = 11;
-            } else {
+}
-                let val = 17;
+#[cfg(not(any(adc_g0, adc_h5, adc_h7rs, adc_u0)))]
-            }
+impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
-        }
+    const CHANNEL: u8 = 17;
-        val
-    }
 }
-pub struct Vbat;
+#[cfg(adc_g0)]
-impl<T: Instance> AdcChannel<T> for Vbat {}
+impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
-impl<T: Instance> SealedAdcChannel<T> for Vbat {
+    const CHANNEL: u8 = 14;
-    fn channel(&self) -> u8 {
+}
-        cfg_if! {
+#[cfg(any(adc_h5, adc_h7rs))]
-            if #[cfg(adc_g0)] {
+impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
-                let val = 14;
+    const CHANNEL: u8 = 16;
-            } else if #[cfg(any(adc_h5, adc_h7rs))] {
+}
-                let val = 2;
+#[cfg(adc_u0)]
-            } else if #[cfg(any(adc_h5, adc_h7rs))] {
+impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
-                let val = 13;
+    const CHANNEL: u8 = 13;
-            } else {
+}
-                let val = 18;
+#[cfg(not(any(adc_g0, adc_h5, adc_h7rs, adc_u0)))]
-            }
+impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
-        }
+    const CHANNEL: u8 = 18;
-        val
-    }
 }
 cfg_if! {
    if #[cfg(any(adc_h5, adc_h7rs))] {
        pub struct VddCore;
-        impl<T: Instance> AdcChannel<T> for VddCore {}
+        impl<T: Instance> super::AdcChannel<T> for VddCore {}
        impl<T: Instance> super::SealedAdcChannel<T> for VddCore {
            fn channel(&self) -> u8 {
-                6
+                17
            }
        }
    }
@@ -104,7 +91,7 @@ cfg_if! {
 cfg_if! {
    if #[cfg(adc_u0)] {
        pub struct DacOut;
-        impl<T: Instance> AdcChannel<T> for DacOut {}
+        impl<T: Instance> super::AdcChannel<T> for DacOut {}
        impl<T: Instance> super::SealedAdcChannel<T> for DacOut {
            fn channel(&self) -> u8 {
                19
@@ -113,21 +100,6 @@ cfg_if! {
    }
 }
-/// Number of samples used for averaging.
-#[derive(Copy, Clone, Debug)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Averaging {
-    Disabled,
-    Samples2,
-    Samples4,
-    Samples8,
-    Samples16,
-    Samples32,
-    Samples64,
-    Samples128,
-    Samples256,
-}
 cfg_if! { if #[cfg(adc_g0)] {
 /// Synchronous PCLK prescaler
@@ -148,327 +120,146 @@ pub enum Clock {
 }}
-impl<'d, T: Instance> Adc<'d, T> {
+#[cfg(adc_u0)]
-    /// Enable the voltage regulator
+type Ovss = u8;
-    fn init_regulator() {
+#[cfg(adc_u0)]
-        rcc::enable_and_reset::<T>();
+type Ovsr = u8;
-        T::regs().cr().modify(|reg| {
+#[cfg(adc_v3)]
-            #[cfg(not(any(adc_g0, adc_u0)))]
+type Ovss = OversamplingShift;
-            reg.set_deeppwd(false);
+#[cfg(adc_v3)]
-            reg.set_advregen(true);
+type Ovsr = OversamplingRatio;
-        });
+/// Adc configuration
-        // If this is false then each ADC_CHSELR bit enables an input channel.
+#[derive(Default)]
-        // This is the reset value, so has no effect.
+pub struct AdcConfig {
-        #[cfg(any(adc_g0, adc_u0))]
+    #[cfg(any(adc_u0, adc_g0, adc_v3))]
-        T::regs().cfgr1().modify(|reg| {
+    pub oversampling_shift: Option<Ovss>,
-            reg.set_chselrmod(false);
+    #[cfg(any(adc_u0, adc_g0, adc_v3))]
-        });
+    pub oversampling_ratio: Option<Ovsr>,
+    #[cfg(any(adc_u0, adc_g0))]
+    pub oversampling_enable: Option<bool>,
+    #[cfg(adc_v3)]
+    pub oversampling_mode: Option<(Rovsm, Trovs, bool)>,
+    #[cfg(adc_g0)]
+    pub clock: Option<Clock>,
+    pub resolution: Option<Resolution>,
+    pub averaging: Option<Averaging>,
+}
-        blocking_delay_us(20);
+impl<T: Instance> super::SealedAnyInstance for T {
+    fn dr() -> *mut u16 {
+        T::regs().dr().as_ptr() as *mut u16
    }
-    /// Calibrate to remove conversion offset
+    // Enable ADC only when it is not already running.
-    fn init_calibrate() {
+    fn enable() {
-        T::regs().cr().modify(|reg| {
+        // Make sure bits are off
-            reg.set_adcal(true);
+        while T::regs().cr().read().addis() {
-        });
-        while T::regs().cr().read().adcal() {
            // spin
        }
-        blocking_delay_us(1);
+        if !T::regs().cr().read().aden() {
+            // Enable ADC
+            T::regs().isr().modify(|reg| {
+                reg.set_adrdy(true);
+            });
+            T::regs().cr().modify(|reg| {
+                reg.set_aden(true);
+            });
+            while !T::regs().isr().read().adrdy() {
+                // spin
+            }
+        }
    }
-    #[cfg(any(adc_v3, adc_g0, adc_u0))]
+    fn start() {
-    pub(super) fn start() {
-        // Start adc conversion
        T::regs().cr().modify(|reg| {
            reg.set_adstart(true);
        });
    }
-    #[cfg(any(adc_v3, adc_g0, adc_u0))]
+    fn stop() {
-    pub(super) fn stop() {
+        // Ensure conversions are finished.
-        // Stop adc conversion
        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
            T::regs().cr().modify(|reg| {
                reg.set_adstp(true);
            });
            while T::regs().cr().read().adstart() {}
        }
-    }
-    #[cfg(any(adc_v3, adc_g0, adc_u0))]
+        // Reset configuration.
-    pub(super) fn teardown_adc() {
-        //disable dma control
        #[cfg(not(any(adc_g0, adc_u0)))]
        T::regs().cfgr().modify(|reg| {
+            reg.set_cont(false);
            reg.set_dmaen(false);
        });
        #[cfg(any(adc_g0, adc_u0))]
        T::regs().cfgr1().modify(|reg| {
+            reg.set_cont(false);
            reg.set_dmaen(false);
        });
    }
-    /// Initialize the ADC leaving any analog clock at reset value.
+    /// Perform a single conversion.
-    /// For G0 and WL, this is the async clock without prescaler.
+    fn convert() -> u16 {
-    pub fn new(adc: Peri<'d, T>) -> Self {
+        // Some models are affected by an erratum:
-        Self::init_regulator();
+        // If we perform conversions slower than 1 kHz, the first read ADC value can be
-        Self::init_calibrate();
+        // corrupted, so we discard it and measure again.
-        Self {
+        //
-            adc,
+        // STM32L471xx: Section 2.7.3
-            sample_time: SampleTime::from_bits(0),
+        // STM32G4: Section 2.7.3
-        }
+        #[cfg(any(rcc_l4, rcc_g4))]
-    }
+        let len = 2;
-    #[cfg(adc_g0)]
-    /// Initialize ADC with explicit clock for the analog ADC
-    pub fn new_with_clock(adc: Peri<'d, T>, clock: Clock) -> Self {
-        Self::init_regulator();
-        #[cfg(any(stm32wl5x))]
-        {
-            // Reset value 0 is actually _No clock selected_ in the STM32WL5x reference manual
-            let async_clock_available = pac::RCC.ccipr().read().adcsel() != pac::rcc::vals::Adcsel::_RESERVED_0;
-            match clock {
-                Clock::Async { div: _ } => {
-                    assert!(async_clock_available);
-                }
-                Clock::Sync { div: _ } => {
-                    if async_clock_available {
-                        warn!("Not using configured ADC clock");
-                    }
-                }
-            }
-        }
-        match clock {
-            Clock::Async { div } => T::regs().ccr().modify(|reg| reg.set_presc(div)),
-            Clock::Sync { div } => T::regs().cfgr2().modify(|reg| {
-                reg.set_ckmode(match div {
-                    CkModePclk::DIV1 => Ckmode::PCLK,
-                    CkModePclk::DIV2 => Ckmode::PCLK_DIV2,
-                    CkModePclk::DIV4 => Ckmode::PCLK_DIV4,
-                })
-            }),
-        }
-        Self::init_calibrate();
-        Self {
-            adc,
-            sample_time: SampleTime::from_bits(0),
-        }
-    }
-    // Enable ADC only when it is not already running.
+        #[cfg(not(any(rcc_l4, rcc_g4)))]
-    fn enable(&mut self) {
+        let len = 1;
-        // Make sure bits are off
-        while T::regs().cr().read().addis() {
-            // spin
-        }
-        if !T::regs().cr().read().aden() {
+        for _ in 0..len {
-            // Enable ADC
            T::regs().isr().modify(|reg| {
-                reg.set_adrdy(true);
+                reg.set_eos(true);
+                reg.set_eoc(true);
            });
+            // Start conversion
            T::regs().cr().modify(|reg| {
-                reg.set_aden(true);
+                reg.set_adstart(true);
            });
-            while !T::regs().isr().read().adrdy() {
+            while !T::regs().isr().read().eos() {
                // spin
            }
        }
-    }
-    pub fn enable_vrefint(&self) -> VrefInt {
-        #[cfg(not(any(adc_g0, adc_u0)))]
-        T::common_regs().ccr().modify(|reg| {
-            reg.set_vrefen(true);
-        });
-        #[cfg(any(adc_g0, adc_u0))]
-        T::regs().ccr().modify(|reg| {
-            reg.set_vrefen(true);
-        });
-        // "Table 24. Embedded internal voltage reference" states that it takes a maximum of 12 us
-        // to stabilize the internal voltage reference.
-        blocking_delay_us(15);
-        VrefInt {}
-    }
-    pub fn enable_temperature(&self) -> Temperature {
-        cfg_if! {
-            if #[cfg(any(adc_g0, adc_u0))] {
-                T::regs().ccr().modify(|reg| {
-                    reg.set_tsen(true);
-                });
-            } else if #[cfg(any(adc_h5, adc_h7rs))] {
-                T::common_regs().ccr().modify(|reg| {
-                    reg.set_tsen(true);
-                });
-            } else {
-                T::common_regs().ccr().modify(|reg| {
-                    reg.set_ch17sel(true);
-                });
-            }
-        }
-        Temperature {}
-    }
-    pub fn enable_vbat(&self) -> Vbat {
-        cfg_if! {
-            if #[cfg(any(adc_g0, adc_u0))] {
-                T::regs().ccr().modify(|reg| {
-                    reg.set_vbaten(true);
-                });
-            } else if #[cfg(any(adc_h5, adc_h7rs))] {
-                T::common_regs().ccr().modify(|reg| {
-                    reg.set_vbaten(true);
-                });
-            } else {
-                T::common_regs().ccr().modify(|reg| {
-                    reg.set_ch18sel(true);
-                });
-            }
-        }
-        Vbat {}
-    }
-    /// Set the ADC sample time.
-    pub fn set_sample_time(&mut self, sample_time: SampleTime) {
-        self.sample_time = sample_time;
-    }
-    /// Get the ADC sample time.
-    pub fn sample_time(&self) -> SampleTime {
-        self.sample_time
-    }
-    /// Set the ADC resolution.
+        T::regs().dr().read().0 as u16
-    pub fn set_resolution(&mut self, resolution: Resolution) {
-        #[cfg(not(any(adc_g0, adc_u0)))]
-        T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
-        #[cfg(any(adc_g0, adc_u0))]
-        T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into()));
-    }
-    pub fn set_averaging(&mut self, averaging: Averaging) {
-        let (enable, samples, right_shift) = match averaging {
-            Averaging::Disabled => (false, 0, 0),
-            Averaging::Samples2 => (true, 0, 1),
-            Averaging::Samples4 => (true, 1, 2),
-            Averaging::Samples8 => (true, 2, 3),
-            Averaging::Samples16 => (true, 3, 4),
-            Averaging::Samples32 => (true, 4, 5),
-            Averaging::Samples64 => (true, 5, 6),
-            Averaging::Samples128 => (true, 6, 7),
-            Averaging::Samples256 => (true, 7, 8),
-        };
-        T::regs().cfgr2().modify(|reg| {
-            #[cfg(not(any(adc_g0, adc_u0)))]
-            reg.set_rovse(enable);
-            #[cfg(any(adc_g0, adc_u0))]
-            reg.set_ovse(enable);
-            #[cfg(any(adc_h5, adc_h7rs))]
-            reg.set_ovsr(samples.into());
-            #[cfg(not(any(adc_h5, adc_h7rs)))]
-            reg.set_ovsr(samples.into());
-            reg.set_ovss(right_shift.into());
-        })
-    }
-    /*
-    /// Convert a raw sample from the `Temperature` to deg C
-    pub fn to_degrees_centigrade(sample: u16) -> f32 {
-        (130.0 - 30.0) / (VtempCal130::get().read() as f32 - VtempCal30::get().read() as f32)
-            * (sample as f32 - VtempCal30::get().read() as f32)
-            + 30.0
    }
-     */
-    /// Perform a single conversion.
+    fn configure_dma(conversion_mode: ConversionMode) {
-    fn convert(&mut self) -> u16 {
+        // Set continuous mode with oneshot dma.
+        // Clear overrun flag before starting transfer.
        T::regs().isr().modify(|reg| {
-            reg.set_eos(true);
+            reg.set_ovr(true);
-            reg.set_eoc(true);
-        });
-        // Start conversion
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
        });
-        while !T::regs().isr().read().eos() {
+        #[cfg(not(any(adc_g0, adc_u0)))]
-            // spin
+        let regs = T::regs().cfgr();
-        }
-        T::regs().dr().read().0 as u16
+        #[cfg(any(adc_g0, adc_u0))]
-    }
+        let regs = T::regs().cfgr1();
-    /// Read an ADC channel.
+        regs.modify(|reg| {
-    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
+            reg.set_discen(false);
-        self.read_channel(channel)
+            reg.set_cont(true);
+            reg.set_dmacfg(match conversion_mode {
+                ConversionMode::Singular => Dmacfg::ONE_SHOT,
+                #[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
+                ConversionMode::Repeated(_) => Dmacfg::CIRCULAR,
+            });
+            reg.set_dmaen(true);
+        });
    }
-    /// Read one or multiple ADC channels using DMA.
+    fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
-    ///
-    /// `readings` must have a length that is a multiple of the length of the
-    /// `sequence` iterator.
-    ///
-    /// Note: The order of values in `readings` is defined by the pin ADC
-    /// channel number and not the pin order in `sequence`.
-    ///
-    /// Example
-    /// ```rust,ignore
-    /// use embassy_stm32::adc::{Adc, AdcChannel}
-    ///
-    /// let mut adc = Adc::new(p.ADC1);
-    /// let mut adc_pin0 = p.PA0.degrade_adc();
-    /// let mut adc_pin1 = p.PA1.degrade_adc();
-    /// let mut measurements = [0u16; 2];
-    ///
-    /// adc.read(
-    ///     p.DMA1_CH2.reborrow(),
-    ///     [
-    ///         (&mut *adc_pin0, SampleTime::CYCLES160_5),
-    ///         (&mut *adc_pin1, SampleTime::CYCLES160_5),
-    ///     ]
-    ///     .into_iter(),
-    ///     &mut measurements,
-    /// )
-    /// .await;
-    /// defmt::info!("measurements: {}", measurements);
-    /// ```
-    pub async fn read(
-        &mut self,
-        rx_dma: Peri<'_, impl RxDma<T>>,
-        sequence: impl ExactSizeIterator<Item = (&mut AnyAdcChannel<T>, SampleTime)>,
-        readings: &mut [u16],
-    ) {
-        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
-        assert!(
-            readings.len() % sequence.len() == 0,
-            "Readings length must be a multiple of sequence length"
-        );
-        assert!(
-            sequence.len() <= 16,
-            "Asynchronous read sequence cannot be more than 16 in length"
-        );
-        #[cfg(all(feature = "low-power", stm32wlex))]
-        let _device_busy = crate::low_power::DeviceBusy::new_stop1();
-        // Ensure no conversions are ongoing and ADC is enabled.
-        Self::cancel_conversions();
-        self.enable();
        // Set sequence length
        #[cfg(not(any(adc_g0, adc_u0)))]
        T::regs().sqr1().modify(|w| {
@@ -481,10 +272,10 @@ impl<'d, T: Instance> Adc<'d, T> {
            T::regs().chselr().write(|chselr| {
                T::regs().smpr().write(|smpr| {
-                    for (channel, sample_time) in sequence {
+                    for ((channel, _), sample_time) in sequence {
-                        chselr.set_chsel(channel.channel.into(), true);
+                        chselr.set_chsel(channel.into(), true);
                        if let Some(i) = sample_times.iter().position(|&t| t == sample_time) {
-                            smpr.set_smpsel(channel.channel.into(), (i as u8).into());
+                            smpr.set_smpsel(channel.into(), (i as u8).into());
                        } else {
                            smpr.set_sample_time(sample_times.len(), sample_time);
                            if let Err(_) = sample_times.push(sample_time) {
@@ -504,30 +295,63 @@ impl<'d, T: Instance> Adc<'d, T> {
            let mut channel_mask = 0;
            // Configure channels and ranks
-            for (_i, (channel, sample_time)) in sequence.enumerate() {
+            for (_i, ((channel, _), sample_time)) in sequence.enumerate() {
-                Self::configure_channel(channel, sample_time);
+                // RM0492, RM0481, etc.
+                // "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
+                #[cfg(any(adc_h5, adc_h7rs))]
+                if channel == 0 {
+                    T::regs().or().modify(|reg| reg.set_op0(true));
+                }
+                // Configure channel
+                cfg_if! {
+                    if #[cfg(adc_u0)] {
+                        // On G0 and U6 all channels use the same sampling time.
+                        T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into()));
+                    } else if #[cfg(any(adc_h5, adc_h7rs))] {
+                        match channel {
+                            0..=9 => T::regs().smpr1().modify(|w| w.set_smp(channel as usize % 10, sample_time.into())),
+                            _ => T::regs().smpr2().modify(|w| w.set_smp(channel as usize % 10, sample_time.into())),
+                        }
+                    } else {
+                        let sample_time = sample_time.into();
+                        T::regs()
+                            .smpr(channel as usize / 10)
+                            .modify(|reg| reg.set_smp(channel as usize % 10, sample_time));
+                    }
+                }
+                #[cfg(stm32h7)]
+                {
+                    use crate::pac::adc::vals::Pcsel;
+                    T::regs().cfgr2().modify(|w| w.set_lshift(0));
+                    T::regs()
+                        .pcsel()
+                        .write(|w| w.set_pcsel(channel.channel() as _, Pcsel::PRESELECTED));
+                }
                // Each channel is sampled according to sequence
                #[cfg(not(any(adc_g0, adc_u0)))]
                match _i {
                    0..=3 => {
                        T::regs().sqr1().modify(|w| {
-                            w.set_sq(_i, channel.channel());
+                            w.set_sq(_i, channel);
                        });
                    }
                    4..=8 => {
                        T::regs().sqr2().modify(|w| {
-                            w.set_sq(_i - 4, channel.channel());
+                            w.set_sq(_i - 4, channel);
                        });
                    }
                    9..=13 => {
                        T::regs().sqr3().modify(|w| {
-                            w.set_sq(_i - 9, channel.channel());
+                            w.set_sq(_i - 9, channel);
                        });
                    }
                    14..=15 => {
                        T::regs().sqr4().modify(|w| {
-                            w.set_sq(_i - 14, channel.channel());
+                            w.set_sq(_i - 14, channel);
                        });
                    }
                    _ => unreachable!(),
@@ -535,7 +359,7 @@ impl<'d, T: Instance> Adc<'d, T> {
                #[cfg(adc_u0)]
                {
-                    channel_mask |= 1 << channel.channel();
+                    channel_mask |= 1 << channel;
                }
            }
@@ -547,312 +371,234 @@ impl<'d, T: Instance> Adc<'d, T> {
                reg.set_chsel(channel_mask);
            });
        }
-        // Set continuous mode with oneshot dma.
+    }
-        // Clear overrun flag before starting transfer.
+}
-        T::regs().isr().modify(|reg| {
-            reg.set_ovr(true);
-        });
-        #[cfg(not(any(adc_g0, adc_u0)))]
+impl<'d, T: Instance> Adc<'d, T> {
-        T::regs().cfgr().modify(|reg| {
+    /// Enable the voltage regulator
-            reg.set_discen(false);
+    fn init_regulator() {
-            reg.set_cont(true);
+        rcc::enable_and_reset::<T>();
-            reg.set_dmacfg(Dmacfg::ONE_SHOT);
+        T::regs().cr().modify(|reg| {
-            reg.set_dmaen(true);
+            #[cfg(not(any(adc_g0, adc_u0)))]
+            reg.set_deeppwd(false);
+            reg.set_advregen(true);
        });
+        // If this is false then each ADC_CHSELR bit enables an input channel.
+        // This is the reset value, so has no effect.
        #[cfg(any(adc_g0, adc_u0))]
        T::regs().cfgr1().modify(|reg| {
-            reg.set_discen(false);
+            reg.set_chselrmod(false);
-            reg.set_cont(true);
-            reg.set_dmacfg(Dmacfg::ONE_SHOT);
-            reg.set_dmaen(true);
        });
-        let request = rx_dma.request();
+        blocking_delay_us(20);
-        let transfer = unsafe {
+    }
-            Transfer::new_read(
-                rx_dma,
-                request,
-                T::regs().dr().as_ptr() as *mut u16,
-                readings,
-                Default::default(),
-            )
-        };
-        // Start conversion
+    /// Calibrate to remove conversion offset
+    fn init_calibrate() {
        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
+            reg.set_adcal(true);
        });
-        // Wait for conversion sequence to finish.
+        while T::regs().cr().read().adcal() {
-        transfer.await;
+            // spin
+        }
-        // Ensure conversions are finished.
-        Self::cancel_conversions();
-        // Reset configuration.
+        blocking_delay_us(1);
-        #[cfg(not(any(adc_g0, adc_u0)))]
-        T::regs().cfgr().modify(|reg| {
-            reg.set_cont(false);
-        });
-        #[cfg(any(adc_g0, adc_u0))]
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_cont(false);
-        });
    }
-    /// Configures the ADC to use a DMA ring buffer for continuous data acquisition.
+    /// Initialize the ADC leaving any analog clock at reset value.
-    ///
+    /// For G0 and WL, this is the async clock without prescaler.
-    /// The `dma_buf` should be large enough to prevent DMA buffer overrun.
+    pub fn new(adc: Peri<'d, T>) -> Self {
-    /// The length of the `dma_buf` should be a multiple of the ADC channel count.
+        Self::init_regulator();
-    /// For example, if 3 channels are measured, its length can be 3 * 40 = 120 measurements.
+        Self::init_calibrate();
-    ///
+        Self { adc }
-    /// `read` method is used to read out measurements from the DMA ring buffer, and its buffer should be exactly half of the `dma_buf` length.
+    }
-    /// It is critical to call `read` frequently to prevent DMA buffer overrun.
-    ///
-    /// [`read`]: #method.read
-    #[cfg(any(adc_v3, adc_g0, adc_u0))]
-    pub fn into_ring_buffered<'a>(
-        &mut self,
-        dma: Peri<'a, impl RxDma<T>>,
-        dma_buf: &'a mut [u16],
-        sequence: impl ExactSizeIterator<Item = (&'a mut AnyAdcChannel<T>, SampleTime)>,
-    ) -> RingBufferedAdc<'a, T> {
-        assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
-        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
-        assert!(
-            sequence.len() <= 16,
-            "Asynchronous read sequence cannot be more than 16 in length"
-        );
-        // reset conversions and enable the adc
-        Self::cancel_conversions();
-        self.enable();
-        //adc side setup
-        // Set sequence length
+    pub fn new_with_config(adc: Peri<'d, T>, config: AdcConfig) -> Self {
-        #[cfg(not(any(adc_g0, adc_u0)))]
+        #[cfg(not(adc_g0))]
-        T::regs().sqr1().modify(|w| {
+        let s = Self::new(adc);
-            w.set_l(sequence.len() as u8 - 1);
-        });
        #[cfg(adc_g0)]
-        {
+        let s = match config.clock {
-            let mut sample_times = Vec::<SampleTime, SAMPLE_TIMES_CAPACITY>::new();
+            Some(clock) => Self::new_with_clock(adc, clock),
+            None => Self::new(adc),
+        };
-            T::regs().chselr().write(|chselr| {
+        #[cfg(any(adc_g0, adc_u0, adc_v3))]
-                T::regs().smpr().write(|smpr| {
+        if let Some(shift) = config.oversampling_shift {
-                    for (channel, sample_time) in sequence {
+            T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
-                        chselr.set_chsel(channel.channel.into(), true);
-                        if let Some(i) = sample_times.iter().position(|&t| t == sample_time) {
-                            smpr.set_smpsel(channel.channel.into(), (i as u8).into());
-                        } else {
-                            smpr.set_sample_time(sample_times.len(), sample_time);
-                            if let Err(_) = sample_times.push(sample_time) {
-                                panic!(
-                                    "Implementation is limited to {} unique sample times among all channels.",
-                                    SAMPLE_TIMES_CAPACITY
-                                );
-                            }
-                        }
-                    }
-                })
-            });
        }
-        #[cfg(not(adc_g0))]
-        {
-            #[cfg(adc_u0)]
-            let mut channel_mask = 0;
-            // Configure channels and ranks
+        #[cfg(any(adc_g0, adc_u0, adc_v3))]
-            for (_i, (channel, sample_time)) in sequence.enumerate() {
+        if let Some(ratio) = config.oversampling_ratio {
-                Self::configure_channel(channel, sample_time);
+            T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
+        }
-                // Each channel is sampled according to sequence
+        #[cfg(any(adc_g0, adc_u0))]
-                #[cfg(not(any(adc_g0, adc_u0)))]
+        if let Some(enable) = config.oversampling_enable {
-                match _i {
+            T::regs().cfgr2().modify(|reg| reg.set_ovse(enable));
-                    0..=3 => {
+        }
-                        T::regs().sqr1().modify(|w| {
-                            w.set_sq(_i, channel.channel());
-                        });
-                    }
-                    4..=8 => {
-                        T::regs().sqr2().modify(|w| {
-                            w.set_sq(_i - 4, channel.channel());
-                        });
-                    }
-                    9..=13 => {
-                        T::regs().sqr3().modify(|w| {
-                            w.set_sq(_i - 9, channel.channel());
-                        });
-                    }
-                    14..=15 => {
-                        T::regs().sqr4().modify(|w| {
-                            w.set_sq(_i - 14, channel.channel());
-                        });
-                    }
-                    _ => unreachable!(),
-                }
-                #[cfg(adc_u0)]
+        #[cfg(adc_v3)]
-                {
+        if let Some((mode, trig_mode, enable)) = config.oversampling_mode {
-                    channel_mask |= 1 << channel.channel();
+            T::regs().cfgr2().modify(|reg| reg.set_trovs(trig_mode));
-                }
+            T::regs().cfgr2().modify(|reg| reg.set_rovsm(mode));
-            }
+            T::regs().cfgr2().modify(|reg| reg.set_rovse(enable));
+        }
-            // On G0 and U0 enabled channels are sampled from 0 to last channel.
+        if let Some(resolution) = config.resolution {
-            // It is possible to add up to 8 sequences if CHSELRMOD = 1.
+            #[cfg(not(any(adc_g0, adc_u0)))]
-            // However for supporting more than 8 channels alternative CHSELRMOD = 0 approach is used.
+            T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
-            #[cfg(adc_u0)]
+            #[cfg(any(adc_g0, adc_u0))]
-            T::regs().chselr().modify(|reg| {
+            T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into()));
-                reg.set_chsel(channel_mask);
-            });
        }
-        // Set continuous mode with Circular dma.
-        // Clear overrun flag before starting transfer.
-        T::regs().isr().modify(|reg| {
-            reg.set_ovr(true);
-        });
-        #[cfg(not(any(adc_g0, adc_u0)))]
+        if let Some(averaging) = config.averaging {
-        T::regs().cfgr().modify(|reg| {
+            let (enable, samples, right_shift) = match averaging {
-            reg.set_discen(false);
+                Averaging::Disabled => (false, 0, 0),
-            reg.set_cont(true);
+                Averaging::Samples2 => (true, 0, 1),
-            reg.set_dmacfg(Dmacfg::CIRCULAR);
+                Averaging::Samples4 => (true, 1, 2),
-            reg.set_dmaen(true);
+                Averaging::Samples8 => (true, 2, 3),
-        });
+                Averaging::Samples16 => (true, 3, 4),
-        #[cfg(any(adc_g0, adc_u0))]
+                Averaging::Samples32 => (true, 4, 5),
-        T::regs().cfgr1().modify(|reg| {
+                Averaging::Samples64 => (true, 5, 6),
-            reg.set_discen(false);
+                Averaging::Samples128 => (true, 6, 7),
-            reg.set_cont(true);
+                Averaging::Samples256 => (true, 7, 8),
-            reg.set_dmacfg(Dmacfg::CIRCULAR);
+            };
-            reg.set_dmaen(true);
+            T::regs().cfgr2().modify(|reg| {
-        });
+                #[cfg(not(any(adc_g0, adc_u0)))]
+                reg.set_rovse(enable);
+                #[cfg(any(adc_g0, adc_u0))]
+                reg.set_ovse(enable);
+                #[cfg(any(adc_h5, adc_h7rs))]
+                reg.set_ovsr(samples.into());
+                #[cfg(not(any(adc_h5, adc_h7rs)))]
+                reg.set_ovsr(samples.into());
+                reg.set_ovss(right_shift.into());
+            })
+        }
-        RingBufferedAdc::new(dma, dma_buf)
+        s
    }
-    #[cfg(not(adc_g0))]
+    #[cfg(adc_g0)]
-    fn configure_channel(channel: &mut impl AdcChannel<T>, sample_time: SampleTime) {
+    /// Initialize ADC with explicit clock for the analog ADC
-        // RM0492, RM0481, etc.
+    pub fn new_with_clock(adc: Peri<'d, T>, clock: Clock) -> Self {
-        // "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
+        Self::init_regulator();
-        #[cfg(any(adc_h5, adc_h7rs))]
-        if channel.channel() == 0 {
+        #[cfg(any(stm32wl5x))]
-            T::regs().or().modify(|reg| reg.set_op0(true));
+        {
+            // Reset value 0 is actually _No clock selected_ in the STM32WL5x reference manual
+            let async_clock_available = pac::RCC.ccipr().read().adcsel() != pac::rcc::vals::Adcsel::_RESERVED_0;
+            match clock {
+                Clock::Async { div: _ } => {
+                    assert!(async_clock_available);
+                }
+                Clock::Sync { div: _ } => {
+                    if async_clock_available {
+                        warn!("Not using configured ADC clock");
+                    }
+                }
+            }
        }
+        match clock {
+            Clock::Async { div } => T::regs().ccr().modify(|reg| reg.set_presc(div)),
+            Clock::Sync { div } => T::regs().cfgr2().modify(|reg| {
+                reg.set_ckmode(match div {
+                    CkModePclk::DIV1 => Ckmode::PCLK,
+                    CkModePclk::DIV2 => Ckmode::PCLK_DIV2,
+                    CkModePclk::DIV4 => Ckmode::PCLK_DIV4,
+                })
+            }),
+        }
+        Self::init_calibrate();
-        // Configure channel
+        Self { adc }
-        Self::set_channel_sample_time(channel.channel(), sample_time);
    }
-    fn read_channel(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
+    pub fn enable_vrefint(&self) -> VrefInt {
-        self.enable();
-        #[cfg(not(adc_g0))]
-        Self::configure_channel(channel, self.sample_time);
-        #[cfg(adc_g0)]
-        T::regs().smpr().write(|reg| {
-            reg.set_sample_time(0, self.sample_time);
-            reg.set_smpsel(channel.channel().into(), Smpsel::SMP1);
-        });
-        // Select channel
        #[cfg(not(any(adc_g0, adc_u0)))]
-        T::regs().sqr1().write(|reg| reg.set_sq(0, channel.channel()));
+        T::common_regs().ccr().modify(|reg| {
+            reg.set_vrefen(true);
+        });
        #[cfg(any(adc_g0, adc_u0))]
-        T::regs().chselr().write(|reg| {
+        T::regs().ccr().modify(|reg| {
-            #[cfg(adc_g0)]
+            reg.set_vrefen(true);
-            reg.set_chsel(channel.channel().into(), true);
-            #[cfg(adc_u0)]
-            reg.set_chsel(1 << channel.channel());
        });
-        // Some models are affected by an erratum:
+        // "Table 24. Embedded internal voltage reference" states that it takes a maximum of 12 us
-        // If we perform conversions slower than 1 kHz, the first read ADC value can be
+        // to stabilize the internal voltage reference.
-        // corrupted, so we discard it and measure again.
+        blocking_delay_us(15);
-        //
-        // STM32L471xx: Section 2.7.3
-        // STM32G4: Section 2.7.3
-        #[cfg(any(rcc_l4, rcc_g4))]
-        let _ = self.convert();
-        let val = self.convert();
-        T::regs().cr().modify(|reg| reg.set_addis(true));
-        // RM0492, RM0481, etc.
-        // "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
-        #[cfg(any(adc_h5, adc_h7rs))]
-        if channel.channel() == 0 {
-            T::regs().or().modify(|reg| reg.set_op0(false));
-        }
-        val
-    }
-    #[cfg(adc_g0)]
-    pub fn set_oversampling_shift(&mut self, shift: Ovss) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
-    }
-    #[cfg(adc_u0)]
-    pub fn set_oversampling_shift(&mut self, shift: u8) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
-    }
-    #[cfg(adc_g0)]
+        VrefInt {}
-    pub fn set_oversampling_ratio(&mut self, ratio: Ovsr) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
-    }
-    #[cfg(adc_u0)]
-    pub fn set_oversampling_ratio(&mut self, ratio: u8) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
    }
-    #[cfg(any(adc_g0, adc_u0))]
+    pub fn enable_temperature(&self) -> Temperature {
-    pub fn oversampling_enable(&mut self, enable: bool) {
+        cfg_if! {
-        T::regs().cfgr2().modify(|reg| reg.set_ovse(enable));
+            if #[cfg(any(adc_g0, adc_u0))] {
-    }
+                T::regs().ccr().modify(|reg| {
+                    reg.set_tsen(true);
+                });
+            } else if #[cfg(any(adc_h5, adc_h7rs))] {
+                T::common_regs().ccr().modify(|reg| {
+                    reg.set_tsen(true);
+                });
+            } else {
+                T::common_regs().ccr().modify(|reg| {
+                    reg.set_ch17sel(true);
+                });
+            }
+        }
-    #[cfg(adc_v3)]
+        Temperature {}
-    pub fn enable_regular_oversampling_mode(&mut self, mode: Rovsm, trig_mode: Trovs, enable: bool) {
-        T::regs().cfgr2().modify(|reg| reg.set_trovs(trig_mode));
-        T::regs().cfgr2().modify(|reg| reg.set_rovsm(mode));
-        T::regs().cfgr2().modify(|reg| reg.set_rovse(enable));
    }
-    #[cfg(adc_v3)]
+    pub fn enable_vbat(&self) -> Vbat {
-    pub fn set_oversampling_ratio(&mut self, ratio: OversamplingRatio) {
+        cfg_if! {
-        T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
+            if #[cfg(any(adc_g0, adc_u0))] {
-    }
+                T::regs().ccr().modify(|reg| {
+                    reg.set_vbaten(true);
+                });
+            } else if #[cfg(any(adc_h5, adc_h7rs))] {
+                T::common_regs().ccr().modify(|reg| {
+                    reg.set_vbaten(true);
+                });
+            } else {
+                T::common_regs().ccr().modify(|reg| {
+                    reg.set_ch18sel(true);
+                });
+            }
+        }
-    #[cfg(adc_v3)]
+        Vbat {}
-    pub fn set_oversampling_shift(&mut self, shift: OversamplingShift) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
    }
-    #[cfg(not(adc_g0))]
+    pub fn disable_vbat(&self) {
-    fn set_channel_sample_time(_ch: u8, sample_time: SampleTime) {
        cfg_if! {
-            if #[cfg(adc_u0)] {
+            if #[cfg(any(adc_g0, adc_u0))] {
-                // On G0 and U6 all channels use the same sampling time.
+                T::regs().ccr().modify(|reg| {
-                T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into()));
+                    reg.set_vbaten(false);
+                });
            } else if #[cfg(any(adc_h5, adc_h7rs))] {
-                match _ch {
+                T::common_regs().ccr().modify(|reg| {
-                    0..=9 => T::regs().smpr1().modify(|w| w.set_smp(_ch as usize % 10, sample_time.into())),
+                    reg.set_vbaten(false);
-                    _ => T::regs().smpr2().modify(|w| w.set_smp(_ch as usize % 10, sample_time.into())),
+                });
-                }
            } else {
-                let sample_time = sample_time.into();
+                T::common_regs().ccr().modify(|reg| {
-                T::regs()
+                    reg.set_ch18sel(false);
-                    .smpr(_ch as usize / 10)
+                });
-                    .modify(|reg| reg.set_smp(_ch as usize % 10, sample_time));
            }
        }
    }
-    fn cancel_conversions() {
+    /*
-        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
+    /// Convert a raw sample from the `Temperature` to deg C
-            T::regs().cr().modify(|reg| {
+    pub fn to_degrees_centigrade(sample: u16) -> f32 {
-                reg.set_adstp(true);
+        (130.0 - 30.0) / (VtempCal130::get().read() as f32 - VtempCal30::get().read() as f32)
-            });
+            * (sample as f32 - VtempCal30::get().read() as f32)
-            while T::regs().cr().read().adstart() {}
+            + 30.0
-        }
    }
+     */
 }
diff --git a/embassy-stm32/src/adc/v4.rs b/embassy-stm32/src/adc/v4.rs
index c7d0103a6..804e63db6 100644
--- a/embassy-stm32/src/adc/v4.rs
+++ b/embassy-stm32/src/adc/v4.rs
@@ -4,10 +4,8 @@ use pac::adc::vals::{Adcaldif, Boost};
 use pac::adc::vals::{Adstp, Difsel, Dmngt, Exten, Pcsel};
 use pac::adccommon::vals::Presc;
-use super::{
+use super::{Adc, Averaging, Instance, Resolution, SampleTime, Temperature, Vbat, VrefInt, blocking_delay_us};
-    Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel, blocking_delay_us,
+use crate::adc::ConversionMode;
-};
-use crate::dma::Transfer;
 use crate::time::Hertz;
 use crate::{Peri, pac, rcc};
@@ -25,149 +23,227 @@ const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(50);
 const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(55);
 #[cfg(stm32g4)]
-const VREF_CHANNEL: u8 = 18;
+impl<T: Instance> super::SealedSpecialConverter<super::VrefInt> for T {
+    const CHANNEL: u8 = 18;
+}
 #[cfg(stm32g4)]
-const TEMP_CHANNEL: u8 = 16;
+impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
+    const CHANNEL: u8 = 16;
+}
 #[cfg(stm32h7)]
-const VREF_CHANNEL: u8 = 19;
+impl<T: Instance> super::SealedSpecialConverter<super::VrefInt> for T {
+    const CHANNEL: u8 = 19;
+}
 #[cfg(stm32h7)]
-const TEMP_CHANNEL: u8 = 18;
+impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
+    const CHANNEL: u8 = 18;
+}
 // TODO this should be 14 for H7a/b/35
 #[cfg(not(stm32u5))]
-const VBAT_CHANNEL: u8 = 17;
+impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
+    const CHANNEL: u8 = 17;
+}
 #[cfg(stm32u5)]
-const VREF_CHANNEL: u8 = 0;
+impl<T: Instance> super::SealedSpecialConverter<super::VrefInt> for T {
+    const CHANNEL: u8 = 0;
+}
 #[cfg(stm32u5)]
-const TEMP_CHANNEL: u8 = 19;
+impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
+    const CHANNEL: u8 = 19;
+}
 #[cfg(stm32u5)]
-const VBAT_CHANNEL: u8 = 18;
+impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
+    const CHANNEL: u8 = 18;
-// NOTE: Vrefint/Temperature/Vbat are not available on all ADCs, this currently cannot be modeled with stm32-data, so these are available from the software on all ADCs
-/// Internal voltage reference channel.
-pub struct VrefInt;
-impl<T: Instance> AdcChannel<T> for VrefInt {}
-impl<T: Instance> SealedAdcChannel<T> for VrefInt {
-    fn channel(&self) -> u8 {
-        VREF_CHANNEL
-    }
 }
-/// Internal temperature channel.
+fn from_ker_ck(frequency: Hertz) -> Presc {
-pub struct Temperature;
+    let raw_prescaler = frequency.0 / MAX_ADC_CLK_FREQ.0;
-impl<T: Instance> AdcChannel<T> for Temperature {}
+    match raw_prescaler {
-impl<T: Instance> SealedAdcChannel<T> for Temperature {
+        0 => Presc::DIV1,
-    fn channel(&self) -> u8 {
+        1 => Presc::DIV2,
-        TEMP_CHANNEL
+        2..=3 => Presc::DIV4,
+        4..=5 => Presc::DIV6,
+        6..=7 => Presc::DIV8,
+        8..=9 => Presc::DIV10,
+        10..=11 => Presc::DIV12,
+        _ => unimplemented!(),
    }
 }
-/// Internal battery voltage channel.
+/// Adc configuration
-pub struct Vbat;
+#[derive(Default)]
-impl<T: Instance> AdcChannel<T> for Vbat {}
+pub struct AdcConfig {
-impl<T: Instance> SealedAdcChannel<T> for Vbat {
+    pub resolution: Option<Resolution>,
-    fn channel(&self) -> u8 {
+    pub averaging: Option<Averaging>,
-        VBAT_CHANNEL
-    }
 }
-// NOTE (unused): The prescaler enum closely copies the hardware capabilities,
+impl<T: Instance> super::SealedAnyInstance for T {
-// but high prescaling doesn't make a lot of sense in the current implementation and is ommited.
+    fn dr() -> *mut u16 {
-#[allow(unused)]
+        T::regs().dr().as_ptr() as *mut u16
-enum Prescaler {
+    }
-    NotDivided,
-    DividedBy2,
+    fn enable() {
-    DividedBy4,
+        T::regs().isr().write(|w| w.set_adrdy(true));
-    DividedBy6,
+        T::regs().cr().modify(|w| w.set_aden(true));
-    DividedBy8,
+        while !T::regs().isr().read().adrdy() {}
-    DividedBy10,
+        T::regs().isr().write(|w| w.set_adrdy(true));
-    DividedBy12,
+    }
-    DividedBy16,
-    DividedBy32,
-    DividedBy64,
-    DividedBy128,
-    DividedBy256,
-}
-impl Prescaler {
+    fn start() {
-    fn from_ker_ck(frequency: Hertz) -> Self {
+        // Start conversion
-        let raw_prescaler = frequency.0 / MAX_ADC_CLK_FREQ.0;
+        T::regs().cr().modify(|reg| {
-        match raw_prescaler {
+            reg.set_adstart(true);
-            0 => Self::NotDivided,
+        });
-            1 => Self::DividedBy2,
+    }
-            2..=3 => Self::DividedBy4,
-            4..=5 => Self::DividedBy6,
+    fn stop() {
-            6..=7 => Self::DividedBy8,
+        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
-            8..=9 => Self::DividedBy10,
+            T::regs().cr().modify(|reg| {
-            10..=11 => Self::DividedBy12,
+                reg.set_adstp(Adstp::STOP);
-            _ => unimplemented!(),
+            });
+            while T::regs().cr().read().adstart() {}
        }
+        // Reset configuration.
+        T::regs().cfgr().modify(|reg| {
+            reg.set_cont(false);
+            reg.set_dmngt(Dmngt::from_bits(0));
+        });
    }
-    fn divisor(&self) -> u32 {
+    fn convert() -> u16 {
-        match self {
+        T::regs().isr().modify(|reg| {
-            Prescaler::NotDivided => 1,
+            reg.set_eos(true);
-            Prescaler::DividedBy2 => 2,
+            reg.set_eoc(true);
-            Prescaler::DividedBy4 => 4,
+        });
-            Prescaler::DividedBy6 => 6,
-            Prescaler::DividedBy8 => 8,
+        // Start conversion
-            Prescaler::DividedBy10 => 10,
+        T::regs().cr().modify(|reg| {
-            Prescaler::DividedBy12 => 12,
+            reg.set_adstart(true);
-            Prescaler::DividedBy16 => 16,
+        });
-            Prescaler::DividedBy32 => 32,
-            Prescaler::DividedBy64 => 64,
+        while !T::regs().isr().read().eos() {
-            Prescaler::DividedBy128 => 128,
+            // spin
-            Prescaler::DividedBy256 => 256,
        }
+        T::regs().dr().read().0 as u16
    }
-    fn presc(&self) -> Presc {
+    fn configure_dma(conversion_mode: ConversionMode) {
-        match self {
+        match conversion_mode {
-            Prescaler::NotDivided => Presc::DIV1,
+            ConversionMode::Singular => {
-            Prescaler::DividedBy2 => Presc::DIV2,
+                T::regs().isr().modify(|reg| {
-            Prescaler::DividedBy4 => Presc::DIV4,
+                    reg.set_ovr(true);
-            Prescaler::DividedBy6 => Presc::DIV6,
+                });
-            Prescaler::DividedBy8 => Presc::DIV8,
+                T::regs().cfgr().modify(|reg| {
-            Prescaler::DividedBy10 => Presc::DIV10,
+                    reg.set_cont(true);
-            Prescaler::DividedBy12 => Presc::DIV12,
+                    reg.set_dmngt(Dmngt::DMA_ONE_SHOT);
-            Prescaler::DividedBy16 => Presc::DIV16,
+                });
-            Prescaler::DividedBy32 => Presc::DIV32,
+            }
-            Prescaler::DividedBy64 => Presc::DIV64,
+            #[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
-            Prescaler::DividedBy128 => Presc::DIV128,
+            _ => unreachable!(),
-            Prescaler::DividedBy256 => Presc::DIV256,
        }
    }
-}
-/// Number of samples used for averaging.
+    fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
-#[derive(Copy, Clone, Debug)]
+        // Set sequence length
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+        T::regs().sqr1().modify(|w| {
-pub enum Averaging {
+            w.set_l(sequence.len() as u8 - 1);
-    Disabled,
+        });
-    Samples2,
-    Samples4,
+        // Configure channels and ranks
-    Samples8,
+        for (i, ((channel, _), sample_time)) in sequence.enumerate() {
-    Samples16,
+            let sample_time = sample_time.into();
-    Samples32,
+            if channel <= 9 {
-    Samples64,
+                T::regs().smpr(0).modify(|reg| reg.set_smp(channel as _, sample_time));
-    Samples128,
+            } else {
-    Samples256,
+                T::regs()
-    Samples512,
+                    .smpr(1)
-    Samples1024,
+                    .modify(|reg| reg.set_smp((channel - 10) as _, sample_time));
+            }
+            #[cfg(any(stm32h7, stm32u5))]
+            {
+                T::regs().cfgr2().modify(|w| w.set_lshift(0));
+                T::regs()
+                    .pcsel()
+                    .modify(|w| w.set_pcsel(channel as _, Pcsel::PRESELECTED));
+            }
+            match i {
+                0..=3 => {
+                    T::regs().sqr1().modify(|w| {
+                        w.set_sq(i, channel);
+                    });
+                }
+                4..=8 => {
+                    T::regs().sqr2().modify(|w| {
+                        w.set_sq(i - 4, channel);
+                    });
+                }
+                9..=13 => {
+                    T::regs().sqr3().modify(|w| {
+                        w.set_sq(i - 9, channel);
+                    });
+                }
+                14..=15 => {
+                    T::regs().sqr4().modify(|w| {
+                        w.set_sq(i - 14, channel);
+                    });
+                }
+                _ => unreachable!(),
+            }
+        }
+    }
 }
-impl<'d, T: Instance> Adc<'d, T> {
+impl<'d, T: Instance + super::AnyInstance> Adc<'d, T> {
+    pub fn new_with_config(adc: Peri<'d, T>, config: AdcConfig) -> Self {
+        let s = Self::new(adc);
+        // Set the ADC resolution.
+        if let Some(resolution) = config.resolution {
+            T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
+        }
+        // Set hardware averaging.
+        if let Some(averaging) = config.averaging {
+            let (enable, samples, right_shift) = match averaging {
+                Averaging::Disabled => (false, 0, 0),
+                Averaging::Samples2 => (true, 1, 1),
+                Averaging::Samples4 => (true, 3, 2),
+                Averaging::Samples8 => (true, 7, 3),
+                Averaging::Samples16 => (true, 15, 4),
+                Averaging::Samples32 => (true, 31, 5),
+                Averaging::Samples64 => (true, 63, 6),
+                Averaging::Samples128 => (true, 127, 7),
+                Averaging::Samples256 => (true, 255, 8),
+                Averaging::Samples512 => (true, 511, 9),
+                Averaging::Samples1024 => (true, 1023, 10),
+            };
+            T::regs().cfgr2().modify(|reg| {
+                reg.set_rovse(enable);
+                reg.set_ovsr(samples);
+                reg.set_ovss(right_shift);
+            })
+        }
+        s
+    }
    /// Create a new ADC driver.
    pub fn new(adc: Peri<'d, T>) -> Self {
        rcc::enable_and_reset::<T>();
-        let prescaler = Prescaler::from_ker_ck(T::frequency());
+        let prescaler = from_ker_ck(T::frequency());
-        T::common_regs().ccr().modify(|w| w.set_presc(prescaler.presc()));
+        T::common_regs().ccr().modify(|w| w.set_presc(prescaler));
-        let frequency = Hertz(T::frequency().0 / prescaler.divisor());
+        let frequency = T::frequency() / prescaler;
        info!("ADC frequency set to {}", frequency);
        if frequency > MAX_ADC_CLK_FREQ {
@@ -190,40 +266,20 @@ impl<'d, T: Instance> Adc<'d, T> {
            };
            T::regs().cr().modify(|w| w.set_boost(boost));
        }
-        let mut s = Self {
-            adc,
-            sample_time: SampleTime::from_bits(0),
-        };
-        s.power_up();
-        s.configure_differential_inputs();
-        s.calibrate();
-        blocking_delay_us(1);
-        s.enable();
-        s.configure();
-        s
-    }
-    fn power_up(&mut self) {
        T::regs().cr().modify(|reg| {
            reg.set_deeppwd(false);
            reg.set_advregen(true);
        });
        blocking_delay_us(10);
-    }
-    fn configure_differential_inputs(&mut self) {
        T::regs().difsel().modify(|w| {
            for n in 0..20 {
                w.set_difsel(n, Difsel::SINGLE_ENDED);
            }
        });
-    }
-    fn calibrate(&mut self) {
        T::regs().cr().modify(|w| {
            #[cfg(not(adc_u5))]
            w.set_adcaldif(Adcaldif::SINGLE_ENDED);
@@ -233,21 +289,18 @@ impl<'d, T: Instance> Adc<'d, T> {
        T::regs().cr().modify(|w| w.set_adcal(true));
        while T::regs().cr().read().adcal() {}
-    }
-    fn enable(&mut self) {
+        blocking_delay_us(1);
-        T::regs().isr().write(|w| w.set_adrdy(true));
-        T::regs().cr().modify(|w| w.set_aden(true));
+        T::enable();
-        while !T::regs().isr().read().adrdy() {}
-        T::regs().isr().write(|w| w.set_adrdy(true));
-    }
-    fn configure(&mut self) {
        // single conversion mode, software trigger
        T::regs().cfgr().modify(|w| {
            w.set_cont(false);
            w.set_exten(Exten::DISABLED);
        });
+        Self { adc }
    }
    /// Enable reading the voltage reference internal channel.
@@ -276,228 +329,4 @@ impl<'d, T: Instance> Adc<'d, T> {
        Vbat {}
    }
-    /// Set the ADC sample time.
-    pub fn set_sample_time(&mut self, sample_time: SampleTime) {
-        self.sample_time = sample_time;
-    }
-    /// Get the ADC sample time.
-    pub fn sample_time(&self) -> SampleTime {
-        self.sample_time
-    }
-    /// Set the ADC resolution.
-    pub fn set_resolution(&mut self, resolution: Resolution) {
-        T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
-    }
-    /// Set hardware averaging.
-    pub fn set_averaging(&mut self, averaging: Averaging) {
-        let (enable, samples, right_shift) = match averaging {
-            Averaging::Disabled => (false, 0, 0),
-            Averaging::Samples2 => (true, 1, 1),
-            Averaging::Samples4 => (true, 3, 2),
-            Averaging::Samples8 => (true, 7, 3),
-            Averaging::Samples16 => (true, 15, 4),
-            Averaging::Samples32 => (true, 31, 5),
-            Averaging::Samples64 => (true, 63, 6),
-            Averaging::Samples128 => (true, 127, 7),
-            Averaging::Samples256 => (true, 255, 8),
-            Averaging::Samples512 => (true, 511, 9),
-            Averaging::Samples1024 => (true, 1023, 10),
-        };
-        T::regs().cfgr2().modify(|reg| {
-            reg.set_rovse(enable);
-            reg.set_ovsr(samples);
-            reg.set_ovss(right_shift);
-        })
-    }
-    /// Perform a single conversion.
-    fn convert(&mut self) -> u16 {
-        T::regs().isr().modify(|reg| {
-            reg.set_eos(true);
-            reg.set_eoc(true);
-        });
-        // Start conversion
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
-        });
-        while !T::regs().isr().read().eos() {
-            // spin
-        }
-        T::regs().dr().read().0 as u16
-    }
-    /// Read an ADC channel.
-    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
-        self.read_channel(channel)
-    }
-    /// Read one or multiple ADC channels using DMA.
-    ///
-    /// `sequence` iterator and `readings` must have the same length.
-    ///
-    /// Example
-    /// ```rust,ignore
-    /// use embassy_stm32::adc::{Adc, AdcChannel}
-    ///
-    /// let mut adc = Adc::new(p.ADC1);
-    /// let mut adc_pin0 = p.PA0.into();
-    /// let mut adc_pin2 = p.PA2.into();
-    /// let mut measurements = [0u16; 2];
-    ///
-    /// adc.read(
-    ///     p.DMA2_CH0.reborrow(),
-    ///     [
-    ///         (&mut *adc_pin0, SampleTime::CYCLES112),
-    ///         (&mut *adc_pin2, SampleTime::CYCLES112),
-    ///     ]
-    ///     .into_iter(),
-    ///     &mut measurements,
-    /// )
-    /// .await;
-    /// defmt::info!("measurements: {}", measurements);
-    /// ```
-    pub async fn read(
-        &mut self,
-        rx_dma: Peri<'_, impl RxDma<T>>,
-        sequence: impl ExactSizeIterator<Item = (&mut AnyAdcChannel<T>, SampleTime)>,
-        readings: &mut [u16],
-    ) {
-        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
-        assert!(
-            sequence.len() == readings.len(),
-            "Sequence length must be equal to readings length"
-        );
-        assert!(
-            sequence.len() <= 16,
-            "Asynchronous read sequence cannot be more than 16 in length"
-        );
-        // Ensure no conversions are ongoing
-        Self::cancel_conversions();
-        // Set sequence length
-        T::regs().sqr1().modify(|w| {
-            w.set_l(sequence.len() as u8 - 1);
-        });
-        // Configure channels and ranks
-        for (i, (channel, sample_time)) in sequence.enumerate() {
-            Self::configure_channel(channel, sample_time);
-            match i {
-                0..=3 => {
-                    T::regs().sqr1().modify(|w| {
-                        w.set_sq(i, channel.channel());
-                    });
-                }
-                4..=8 => {
-                    T::regs().sqr2().modify(|w| {
-                        w.set_sq(i - 4, channel.channel());
-                    });
-                }
-                9..=13 => {
-                    T::regs().sqr3().modify(|w| {
-                        w.set_sq(i - 9, channel.channel());
-                    });
-                }
-                14..=15 => {
-                    T::regs().sqr4().modify(|w| {
-                        w.set_sq(i - 14, channel.channel());
-                    });
-                }
-                _ => unreachable!(),
-            }
-        }
-        // Set continuous mode with oneshot dma.
-        // Clear overrun flag before starting transfer.
-        T::regs().isr().modify(|reg| {
-            reg.set_ovr(true);
-        });
-        T::regs().cfgr().modify(|reg| {
-            reg.set_cont(true);
-            reg.set_dmngt(Dmngt::DMA_ONE_SHOT);
-        });
-        let request = rx_dma.request();
-        let transfer = unsafe {
-            Transfer::new_read(
-                rx_dma,
-                request,
-                T::regs().dr().as_ptr() as *mut u16,
-                readings,
-                Default::default(),
-            )
-        };
-        // Start conversion
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
-        });
-        // Wait for conversion sequence to finish.
-        transfer.await;
-        // Ensure conversions are finished.
-        Self::cancel_conversions();
-        // Reset configuration.
-        T::regs().cfgr().modify(|reg| {
-            reg.set_cont(false);
-            reg.set_dmngt(Dmngt::from_bits(0));
-        });
-    }
-    fn configure_channel(channel: &mut impl AdcChannel<T>, sample_time: SampleTime) {
-        channel.setup();
-        let channel = channel.channel();
-        Self::set_channel_sample_time(channel, sample_time);
-        #[cfg(any(stm32h7, stm32u5))]
-        {
-            T::regs().cfgr2().modify(|w| w.set_lshift(0));
-            T::regs()
-                .pcsel()
-                .modify(|w| w.set_pcsel(channel as _, Pcsel::PRESELECTED));
-        }
-    }
-    fn read_channel(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
-        Self::configure_channel(channel, self.sample_time);
-        T::regs().sqr1().modify(|reg| {
-            reg.set_sq(0, channel.channel());
-            reg.set_l(0);
-        });
-        self.convert()
-    }
-    fn set_channel_sample_time(ch: u8, sample_time: SampleTime) {
-        let sample_time = sample_time.into();
-        if ch <= 9 {
-            T::regs().smpr(0).modify(|reg| reg.set_smp(ch as _, sample_time));
-        } else {
-            T::regs().smpr(1).modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
-        }
-    }
-    fn cancel_conversions() {
-        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
-            T::regs().cr().modify(|reg| {
-                reg.set_adstp(Adstp::STOP);
-            });
-            while T::regs().cr().read().adstart() {}
-        }
-    }
 }
diff --git a/embassy-stm32/src/adc/watchdog_v1.rs b/embassy-stm32/src/adc/watchdog_v1.rs
index bbe8e1971..b12e0d333 100644
--- a/embassy-stm32/src/adc/watchdog_v1.rs
+++ b/embassy-stm32/src/adc/watchdog_v1.rs
@@ -1,7 +1,7 @@
 use core::future::poll_fn;
 use core::task::Poll;
-use stm32_metapac::adc::vals::{Align, Awdsgl, Res};
+use stm32_metapac::adc::vals::{Align, Awdsgl, Res, SampleTime};
 use crate::adc::{Adc, AdcChannel, Instance};
@@ -67,7 +67,7 @@ impl<'d, T: Instance> Adc<'d, T> {
    /// let v_high = adc.monitor_watchdog().await;
    /// info!("ADC sample is high {}", v_high);
    /// ```
-    pub async fn monitor_watchdog(&mut self) -> u16 {
+    pub async fn monitor_watchdog(&mut self, sample_time: SampleTime) -> u16 {
        assert!(
            match T::regs().cfgr1().read().awdsgl() {
                Awdsgl::SINGLE_CHANNEL => T::regs().cfgr1().read().awdch() != 0,
@@ -76,7 +76,7 @@ impl<'d, T: Instance> Adc<'d, T> {
            "`set_channel` should be called before `monitor`",
        );
        assert!(T::regs().chselr().read().0 != 0);
-        T::regs().smpr().modify(|reg| reg.set_smp(self.sample_time.into()));
+        T::regs().smpr().modify(|reg| reg.set_smp(sample_time.into()));
        Self::start_awd();
        let sample = poll_fn(|cx| {
diff --git a/embassy-stm32/src/dma/gpdma/mod.rs b/embassy-stm32/src/dma/gpdma/mod.rs
index 3e117c331..106558d20 100644
--- a/embassy-stm32/src/dma/gpdma/mod.rs
+++ b/embassy-stm32/src/dma/gpdma/mod.rs
@@ -136,6 +136,7 @@ pub(crate) unsafe fn init(cs: critical_section::CriticalSection, irq_priority: c
 impl AnyChannel {
    /// Safety: Must be called with a matching set of parameters for a valid dma channel
+    #[cfg(not(stm32n6))]
    pub(crate) unsafe fn on_irq(&self) {
        let info = self.info();
        #[cfg(feature = "_dual-core")]
diff --git a/embassy-stm32/src/dma/mod.rs b/embassy-stm32/src/dma/mod.rs
index 297fa3674..de7a2c175 100644
--- a/embassy-stm32/src/dma/mod.rs
+++ b/embassy-stm32/src/dma/mod.rs
@@ -46,9 +46,11 @@ pub type Request = u8;
 pub type Request = ();
 pub(crate) trait SealedChannel {
+    #[cfg(not(stm32n6))]
    fn id(&self) -> u8;
 }
+#[cfg(not(stm32n6))]
 pub(crate) trait ChannelInterrupt {
    #[cfg_attr(not(feature = "rt"), allow(unused))]
    unsafe fn on_irq();
@@ -58,6 +60,7 @@ pub(crate) trait ChannelInterrupt {
 #[allow(private_bounds)]
 pub trait Channel: SealedChannel + PeripheralType + Into<AnyChannel> + 'static {}
+#[cfg(not(stm32n6))]
 macro_rules! dma_channel_impl {
    ($channel_peri:ident, $index:expr) => {
        impl crate::dma::SealedChannel for crate::peripherals::$channel_peri {
@@ -96,6 +99,7 @@ impl AnyChannel {
 }
 impl SealedChannel for AnyChannel {
+    #[cfg(not(stm32n6))]
    fn id(&self) -> u8 {
        self.id
    }
diff --git a/embassy-stm32/src/dsihost.rs b/embassy-stm32/src/dsihost.rs
index 59a2cbcdb..b8945820c 100644
--- a/embassy-stm32/src/dsihost.rs
+++ b/embassy-stm32/src/dsihost.rs
@@ -5,18 +5,11 @@ use core::marker::PhantomData;
 use embassy_hal_internal::PeripheralType;
 //use crate::gpio::{AnyPin, SealedPin};
+use crate::block_for_us;
 use crate::gpio::{AfType, AnyPin, OutputType, Speed};
 use crate::rcc::{self, RccPeripheral};
 use crate::{Peri, peripherals};
-/// Performs a busy-wait delay for a specified number of microseconds.
-pub fn blocking_delay_ms(ms: u32) {
-    #[cfg(feature = "time")]
-    embassy_time::block_for(embassy_time::Duration::from_millis(ms as u64));
-    #[cfg(not(feature = "time"))]
-    cortex_m::asm::delay(unsafe { crate::rcc::get_freqs() }.sys.to_hertz().unwrap().0 / 1_000 * ms);
-}
 /// PacketTypes extracted from CubeMX
 #[repr(u8)]
 #[allow(dead_code)]
@@ -334,7 +327,7 @@ impl<'d, T: Instance> DsiHost<'d, T> {
            if T::regs().gpsr().read().cmdfe() {
                return Ok(());
            }
-            blocking_delay_ms(1);
+            block_for_us(1_000);
        }
        Err(Error::FifoTimeout)
    }
@@ -345,7 +338,7 @@ impl<'d, T: Instance> DsiHost<'d, T> {
            if !T::regs().gpsr().read().cmdff() {
                return Ok(());
            }
-            blocking_delay_ms(1);
+            block_for_us(1_000);
        }
        Err(Error::FifoTimeout)
    }
@@ -356,7 +349,7 @@ impl<'d, T: Instance> DsiHost<'d, T> {
            if !self.read_busy() {
                return Ok(());
            }
-            blocking_delay_ms(1);
+            block_for_us(1_000);
        }
        Err(Error::ReadTimeout)
    }
@@ -367,7 +360,7 @@ impl<'d, T: Instance> DsiHost<'d, T> {
            if !T::regs().gpsr().read().prdfe() {
                return Ok(());
            }
-            blocking_delay_ms(1);
+            block_for_us(1_000);
        }
        Err(Error::FifoTimeout)
    }
diff --git a/embassy-stm32/src/dts/tsel.rs b/embassy-stm32/src/dts/tsel.rs
index 99eab6dd8..79c697c8d 100644
--- a/embassy-stm32/src/dts/tsel.rs
+++ b/embassy-stm32/src/dts/tsel.rs
@@ -49,3 +49,20 @@ pub enum TriggerSel {
    /// EXTI13
    Exti13 = 4,
 }
+/// Trigger selection for N6
+#[cfg(stm32n6)]
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum TriggerSel {
+    /// Software triggering. Performs continuous measurements.
+    Software = 0,
+    /// LPTIM4 OUT
+    Lptim4 = 1,
+    /// LPTIM2 CH1
+    Lptim2 = 2,
+    /// LPTIM3 CH1
+    Lptim3 = 3,
+    /// EXTI13
+    Exti13 = 4,
+}
diff --git a/embassy-stm32/src/eth/generic_phy.rs b/embassy-stm32/src/eth/generic_phy.rs
index 774beef80..947874d7f 100644
--- a/embassy-stm32/src/eth/generic_phy.rs
+++ b/embassy-stm32/src/eth/generic_phy.rs
@@ -8,6 +8,7 @@ use embassy_time::{Duration, Timer};
 use futures_util::FutureExt;
 use super::{Phy, StationManagement};
+use crate::block_for_us as blocking_delay_us;
 #[allow(dead_code)]
 mod phy_consts {
@@ -76,19 +77,6 @@ impl GenericPhy {
    }
 }
-// TODO: Factor out to shared functionality
-fn blocking_delay_us(us: u32) {
-    #[cfg(feature = "time")]
-    embassy_time::block_for(Duration::from_micros(us as u64));
-    #[cfg(not(feature = "time"))]
-    {
-        let freq = unsafe { crate::rcc::get_freqs() }.sys.to_hertz().unwrap().0 as u64;
-        let us = us as u64;
-        let cycles = freq * us / 1_000_000;
-        cortex_m::asm::delay(cycles as u32);
-    }
-}
 impl Phy for GenericPhy {
    fn phy_reset<S: StationManagement>(&mut self, sm: &mut S) {
        // Detect SMI address
diff --git a/embassy-stm32/src/exti.rs b/embassy-stm32/src/exti.rs
index 2f5c3406a..cb46d362c 100644
--- a/embassy-stm32/src/exti.rs
+++ b/embassy-stm32/src/exti.rs
@@ -8,7 +8,7 @@ use core::task::{Context, Poll};
 use embassy_hal_internal::{PeripheralType, impl_peripheral};
 use embassy_sync::waitqueue::AtomicWaker;
-use crate::gpio::{AnyPin, Input, Level, Pin as GpioPin, Pull};
+use crate::gpio::{AnyPin, Input, Level, Pin as GpioPin, PinNumber, Pull};
 use crate::pac::EXTI;
 use crate::pac::exti::regs::Lines;
 use crate::{Peri, interrupt, pac, peripherals};
@@ -31,11 +31,11 @@ fn cpu_regs() -> pac::exti::Exti {
    EXTI
 }
-#[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, gpio_v1, exti_u5, exti_h5, exti_h50)))]
+#[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, gpio_v1, exti_u5, exti_h5, exti_h50, exti_n6)))]
 fn exticr_regs() -> pac::syscfg::Syscfg {
    pac::SYSCFG
 }
-#[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50))]
+#[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6))]
 fn exticr_regs() -> pac::exti::Exti {
    EXTI
 }
@@ -45,9 +45,9 @@ fn exticr_regs() -> pac::afio::Afio {
 }
 unsafe fn on_irq() {
-    #[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50)))]
+    #[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6)))]
    let bits = EXTI.pr(0).read().0;
-    #[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50))]
+    #[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6))]
    let bits = EXTI.rpr(0).read().0 | EXTI.fpr(0).read().0;
    // We don't handle or change any EXTI lines above 16.
@@ -62,9 +62,9 @@ unsafe fn on_irq() {
    }
    // Clear pending
-    #[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50)))]
+    #[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6)))]
    EXTI.pr(0).write_value(Lines(bits));
-    #[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50))]
+    #[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6))]
    {
        EXTI.rpr(0).write_value(Lines(bits));
        EXTI.fpr(0).write_value(Lines(bits));
@@ -226,12 +226,12 @@ impl<'d> embedded_hal_async::digital::Wait for ExtiInput<'d> {
 #[must_use = "futures do nothing unless you `.await` or poll them"]
 struct ExtiInputFuture<'a> {
-    pin: u8,
+    pin: PinNumber,
    phantom: PhantomData<&'a mut AnyPin>,
 }
 impl<'a> ExtiInputFuture<'a> {
-    fn new(pin: u8, port: u8, rising: bool, falling: bool) -> Self {
+    fn new(pin: PinNumber, port: PinNumber, rising: bool, falling: bool) -> Self {
        critical_section::with(|_| {
            let pin = pin as usize;
            exticr_regs().exticr(pin / 4).modify(|w| w.set_exti(pin % 4, port));
@@ -239,9 +239,9 @@ impl<'a> ExtiInputFuture<'a> {
            EXTI.ftsr(0).modify(|w| w.set_line(pin, falling));
            // clear pending bit
-            #[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50)))]
+            #[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6)))]
            EXTI.pr(0).write(|w| w.set_line(pin, true));
-            #[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50))]
+            #[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6))]
            {
                EXTI.rpr(0).write(|w| w.set_line(pin, true));
                EXTI.fpr(0).write(|w| w.set_line(pin, true));
@@ -334,20 +334,20 @@ trait SealedChannel {}
 #[allow(private_bounds)]
 pub trait Channel: PeripheralType + SealedChannel + Sized {
    /// Get the EXTI channel number.
-    fn number(&self) -> u8;
+    fn number(&self) -> PinNumber;
 }
 /// Type-erased EXTI channel.
 ///
 /// This represents ownership over any EXTI channel, known at runtime.
 pub struct AnyChannel {
-    number: u8,
+    number: PinNumber,
 }
 impl_peripheral!(AnyChannel);
 impl SealedChannel for AnyChannel {}
 impl Channel for AnyChannel {
-    fn number(&self) -> u8 {
+    fn number(&self) -> PinNumber {
        self.number
    }
 }
@@ -356,7 +356,7 @@ macro_rules! impl_exti {
    ($type:ident, $number:expr) => {
        impl SealedChannel for peripherals::$type {}
        impl Channel for peripherals::$type {
-            fn number(&self) -> u8 {
+            fn number(&self) -> PinNumber {
                $number
            }
        }
@@ -364,7 +364,7 @@ macro_rules! impl_exti {
        impl From<peripherals::$type> for AnyChannel {
            fn from(val: peripherals::$type) -> Self {
                Self {
-                    number: val.number() as u8,
+                    number: val.number() as PinNumber,
                }
            }
        }
diff --git a/embassy-stm32/src/flash/c.rs b/embassy-stm32/src/flash/c.rs
new file mode 100644
index 000000000..0ad1002b0
--- /dev/null
+++ b/embassy-stm32/src/flash/c.rs
@@ -0,0 +1,131 @@
+use core::ptr::write_volatile;
+use core::sync::atomic::{Ordering, fence};
+use cortex_m::interrupt;
+use super::{FlashSector, WRITE_SIZE};
+use crate::flash::Error;
+use crate::pac;
+pub(crate) unsafe fn lock() {
+    pac::FLASH.cr().modify(|w| w.set_lock(true));
+}
+pub(crate) unsafe fn unlock() {
+    // Wait, while the memory interface is busy.
+    wait_busy();
+    // Unlock flash
+    if pac::FLASH.cr().read().lock() {
+        pac::FLASH.keyr().write_value(0x4567_0123);
+        pac::FLASH.keyr().write_value(0xCDEF_89AB);
+    }
+}
+pub(crate) unsafe fn enable_blocking_write() {
+    assert_eq!(0, WRITE_SIZE % 4);
+    pac::FLASH.cr().write(|w| w.set_pg(true));
+}
+pub(crate) unsafe fn disable_blocking_write() {
+    pac::FLASH.cr().write(|w| w.set_pg(false));
+}
+pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
+    let mut address = start_address;
+    for val in buf.chunks(4) {
+        write_volatile(address as *mut u32, u32::from_le_bytes(unwrap!(val.try_into())));
+        address += val.len() as u32;
+        // prevents parallelism errors
+        fence(Ordering::SeqCst);
+    }
+    wait_ready_blocking()
+}
+pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
+    let idx = (sector.start - super::FLASH_BASE as u32) / super::BANK1_REGION.erase_size as u32;
+    #[cfg(feature = "defmt")]
+    defmt::trace!(
+        "STM32C0 Erase: addr=0x{:08x}, idx={}, erase_size={}",
+        sector.start,
+        idx,
+        super::BANK1_REGION.erase_size
+    );
+    wait_busy();
+    clear_all_err();
+    // Explicitly unlock before erase
+    unlock();
+    interrupt::free(|_| {
+        #[cfg(feature = "defmt")]
+        {
+            let cr_before = pac::FLASH.cr().read();
+            defmt::trace!("FLASH_CR before: 0x{:08x}", cr_before.0);
+        }
+        pac::FLASH.cr().modify(|w| {
+            w.set_per(true);
+            w.set_pnb(idx as u8);
+            w.set_strt(true);
+        });
+        #[cfg(feature = "defmt")]
+        {
+            let cr_after = pac::FLASH.cr().read();
+            defmt::trace!(
+                "FLASH_CR after: 0x{:08x}, PER={}, PNB={}, STRT={}",
+                cr_after.0,
+                cr_after.per(),
+                cr_after.pnb(),
+                cr_after.strt()
+            );
+        }
+    });
+    let ret: Result<(), Error> = wait_ready_blocking();
+    // Clear erase bit
+    pac::FLASH.cr().modify(|w| w.set_per(false));
+    // Explicitly lock after erase
+    lock();
+    // Extra wait to ensure operation completes
+    wait_busy();
+    ret
+}
+pub(crate) unsafe fn wait_ready_blocking() -> Result<(), Error> {
+    while pac::FLASH.sr().read().bsy() {}
+    let sr = pac::FLASH.sr().read();
+    if sr.progerr() {
+        return Err(Error::Prog);
+    }
+    if sr.wrperr() {
+        return Err(Error::Protected);
+    }
+    if sr.pgaerr() {
+        return Err(Error::Unaligned);
+    }
+    Ok(())
+}
+pub(crate) unsafe fn clear_all_err() {
+    // read and write back the same value.
+    // This clears all "write 1 to clear" bits.
+    pac::FLASH.sr().modify(|_| {});
+}
+fn wait_busy() {
+    while pac::FLASH.sr().read().bsy() {}
+}
diff --git a/embassy-stm32/src/flash/common.rs b/embassy-stm32/src/flash/common.rs
index b595938a6..60d00e766 100644
--- a/embassy-stm32/src/flash/common.rs
+++ b/embassy-stm32/src/flash/common.rs
@@ -102,7 +102,13 @@ pub(super) unsafe fn blocking_write(
    }
    let mut address = base + offset;
-    trace!("Writing {} bytes at 0x{:x}", bytes.len(), address);
+    trace!(
+        "Writing {} bytes at 0x{:x} (base=0x{:x}, offset=0x{:x})",
+        bytes.len(),
+        address,
+        base,
+        offset
+    );
    for chunk in bytes.chunks(WRITE_SIZE) {
        write_chunk(address, chunk)?;
diff --git a/embassy-stm32/src/flash/g.rs b/embassy-stm32/src/flash/g.rs
index d026541a4..d7ba2f571 100644
--- a/embassy-stm32/src/flash/g.rs
+++ b/embassy-stm32/src/flash/g.rs
@@ -44,7 +44,6 @@ pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE])
 }
 pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
-    let idx = (sector.start - super::FLASH_BASE as u32) / super::BANK1_REGION.erase_size as u32;
    wait_busy();
    clear_all_err();
@@ -54,9 +53,9 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
            #[cfg(any(flash_g0x0, flash_g0x1, flash_g4c3))]
            w.set_bker(sector.bank == crate::flash::FlashBank::Bank2);
            #[cfg(flash_g0x0)]
-            w.set_pnb(idx as u16);
+            w.set_pnb(sector.index_in_bank as u16);
            #[cfg(not(flash_g0x0))]
-            w.set_pnb(idx as u8);
+            w.set_pnb(sector.index_in_bank as u8);
            w.set_strt(true);
        });
    });
diff --git a/embassy-stm32/src/flash/mod.rs b/embassy-stm32/src/flash/mod.rs
index 3e74d857a..39cd9b3a9 100644
--- a/embassy-stm32/src/flash/mod.rs
+++ b/embassy-stm32/src/flash/mod.rs
@@ -99,6 +99,7 @@ compile_error!("The 'eeprom' cfg is enabled for a non-L0/L1 chip family. This is
 #[cfg_attr(flash_f4, path = "f4.rs")]
 #[cfg_attr(flash_f7, path = "f7.rs")]
 #[cfg_attr(any(flash_g0x0, flash_g0x1, flash_g4c2, flash_g4c3, flash_g4c4), path = "g.rs")]
+#[cfg_attr(flash_c0, path = "c.rs")]
 #[cfg_attr(flash_h7, path = "h7.rs")]
 #[cfg_attr(flash_h7ab, path = "h7.rs")]
 #[cfg_attr(any(flash_u5, flash_wba), path = "u5.rs")]
@@ -108,7 +109,7 @@ compile_error!("The 'eeprom' cfg is enabled for a non-L0/L1 chip family. This is
 #[cfg_attr(
    not(any(
        flash_l0, flash_l1, flash_l4, flash_l5, flash_wl, flash_wb, flash_f0, flash_f1, flash_f2, flash_f3, flash_f4,
-        flash_f7, flash_g0x0, flash_g0x1, flash_g4c2, flash_g4c3, flash_g4c4, flash_h7, flash_h7ab, flash_u5,
+        flash_f7, flash_g0x0, flash_g0x1, flash_g4c2, flash_g4c3, flash_g4c4, flash_c0, flash_h7, flash_h7ab, flash_u5,
        flash_wba, flash_h50, flash_u0, flash_h5,
    )),
    path = "other.rs"
diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs
index b55baffdc..17c5a9962 100644
--- a/embassy-stm32/src/gpio.rs
+++ b/embassy-stm32/src/gpio.rs
@@ -592,7 +592,7 @@ impl AfType {
 #[inline(never)]
 #[cfg(gpio_v1)]
-fn set_as_af(pin_port: u8, af_type: AfType) {
+fn set_as_af(pin_port: PinNumber, af_type: AfType) {
    let pin = unsafe { AnyPin::steal(pin_port) };
    let r = pin.block();
    let n = pin._pin() as usize;
@@ -649,7 +649,7 @@ impl AfType {
 #[inline(never)]
 #[cfg(gpio_v2)]
-fn set_as_af(pin_port: u8, af_num: u8, af_type: AfType) {
+fn set_as_af(pin_port: PinNumber, af_num: u8, af_type: AfType) {
    let pin = unsafe { AnyPin::steal(pin_port) };
    let r = pin.block();
    let n = pin._pin() as usize;
@@ -663,7 +663,7 @@ fn set_as_af(pin_port: u8, af_num: u8, af_type: AfType) {
 #[inline(never)]
 #[cfg(gpio_v2)]
-fn set_speed(pin_port: u8, speed: Speed) {
+fn set_speed(pin_port: PinNumber, speed: Speed) {
    let pin = unsafe { AnyPin::steal(pin_port) };
    let r = pin.block();
    let n = pin._pin() as usize;
@@ -672,7 +672,7 @@ fn set_speed(pin_port: u8, speed: Speed) {
 }
 #[inline(never)]
-fn set_as_analog(pin_port: u8) {
+fn set_as_analog(pin_port: PinNumber) {
    let pin = unsafe { AnyPin::steal(pin_port) };
    let r = pin.block();
    let n = pin._pin() as usize;
@@ -688,7 +688,7 @@ fn set_as_analog(pin_port: u8) {
 }
 #[inline(never)]
-fn get_pull(pin_port: u8) -> Pull {
+fn get_pull(pin_port: PinNumber) -> Pull {
    let pin = unsafe { AnyPin::steal(pin_port) };
    let r = pin.block();
    let n = pin._pin() as usize;
@@ -727,15 +727,15 @@ pub struct AfioRemapBool<const V: bool>;
 pub struct AfioRemapNotApplicable;
 pub(crate) trait SealedPin {
-    fn pin_port(&self) -> u8;
+    fn pin_port(&self) -> PinNumber;
    #[inline]
-    fn _pin(&self) -> u8 {
+    fn _pin(&self) -> PinNumber {
        self.pin_port() % 16
    }
    #[inline]
-    fn _port(&self) -> u8 {
+    fn _port(&self) -> PinNumber {
        self.pin_port() / 16
    }
@@ -798,6 +798,20 @@ pub(crate) trait SealedPin {
    }
 }
+/// GPIO pin number type.
+///
+/// Some chips have a total number of ports that exceeds 8, a larger integer
+/// is needed to hold the total pin number `(ports * number)`.
+#[cfg(not(stm32n6))]
+pub type PinNumber = u8;
+/// GPIO pin number type.
+///
+/// Some chips have a total number of ports that exceeds 8, a larger integer
+/// is needed to hold the total pin number `(ports * number)`.
+#[cfg(stm32n6)]
+pub type PinNumber = u16;
 /// GPIO pin trait.
 #[allow(private_bounds)]
 pub trait Pin: PeripheralType + Into<AnyPin> + SealedPin + Sized + 'static {
@@ -809,20 +823,20 @@ pub trait Pin: PeripheralType + Into<AnyPin> + SealedPin + Sized + 'static {
    /// Number of the pin within the port (0..31)
    #[inline]
-    fn pin(&self) -> u8 {
+    fn pin(&self) -> PinNumber {
        self._pin()
    }
    /// Port of the pin
    #[inline]
-    fn port(&self) -> u8 {
+    fn port(&self) -> PinNumber {
        self._port()
    }
 }
 /// Type-erased GPIO pin
 pub struct AnyPin {
-    pin_port: u8,
+    pin_port: PinNumber,
 }
 impl AnyPin {
@@ -830,12 +844,12 @@ impl AnyPin {
    ///
    /// `pin_port` is `port_num * 16 + pin_num`, where `port_num` is 0 for port `A`, 1 for port `B`, etc...
    #[inline]
-    pub unsafe fn steal(pin_port: u8) -> Peri<'static, Self> {
+    pub unsafe fn steal(pin_port: PinNumber) -> Peri<'static, Self> {
        Peri::new_unchecked(Self { pin_port })
    }
    #[inline]
-    fn _port(&self) -> u8 {
+    fn _port(&self) -> PinNumber {
        self.pin_port / 16
    }
@@ -854,7 +868,7 @@ impl Pin for AnyPin {
 }
 impl SealedPin for AnyPin {
    #[inline]
-    fn pin_port(&self) -> u8 {
+    fn pin_port(&self) -> PinNumber {
        self.pin_port
    }
 }
@@ -869,7 +883,7 @@ foreach_pin!(
        }
        impl SealedPin for peripherals::$pin_name {
            #[inline]
-            fn pin_port(&self) -> u8 {
+            fn pin_port(&self) -> PinNumber {
                $port_num * 16 + $pin_num
            }
        }
diff --git a/embassy-stm32/src/i2c/v2.rs b/embassy-stm32/src/i2c/v2.rs
index 57a7acee7..61e550ad4 100644
--- a/embassy-stm32/src/i2c/v2.rs
+++ b/embassy-stm32/src/i2c/v2.rs
@@ -98,6 +98,27 @@ pub(crate) unsafe fn on_interrupt<T: Instance>() {
 }
 impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
+    #[inline]
+    fn to_reload(reload: bool) -> i2c::vals::Reload {
+        if reload {
+            i2c::vals::Reload::NOT_COMPLETED
+        } else {
+            i2c::vals::Reload::COMPLETED
+        }
+    }
+    /// Calculate total bytes in a group of operations
+    #[inline]
+    fn total_operation_bytes(operations: &[Operation<'_>]) -> usize {
+        operations
+            .iter()
+            .map(|op| match op {
+                Operation::Write(buf) => buf.len(),
+                Operation::Read(buf) => buf.len(),
+            })
+            .sum()
+    }
    pub(crate) fn init(&mut self, config: Config) {
        self.info.regs.cr1().modify(|reg| {
            reg.set_pe(false);
@@ -147,12 +168,6 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
        // `buffer`. The START bit can be set even if the bus
        // is BUSY or I2C is in slave mode.
-        let reload = if reload {
-            i2c::vals::Reload::NOT_COMPLETED
-        } else {
-            i2c::vals::Reload::COMPLETED
-        };
        info.regs.cr2().modify(|w| {
            w.set_sadd(address.addr() << 1);
            w.set_add10(address.add_mode());
@@ -160,7 +175,7 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
            w.set_nbytes(length as u8);
            w.set_start(true);
            w.set_autoend(stop.autoend());
-            w.set_reload(reload);
+            w.set_reload(Self::to_reload(reload));
        });
        Ok(())
@@ -172,28 +187,25 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
        length: usize,
        stop: Stop,
        reload: bool,
+        restart: bool,
        timeout: Timeout,
    ) -> Result<(), Error> {
        assert!(length < 256);
-        // Wait for any previous address sequence to end
+        if !restart {
-        // automatically. This could be up to 50% of a bus
+            // Wait for any previous address sequence to end
-        // cycle (ie. up to 0.5/freq)
+            // automatically. This could be up to 50% of a bus
-        while info.regs.cr2().read().start() {
+            // cycle (ie. up to 0.5/freq)
-            timeout.check()?;
+            while info.regs.cr2().read().start() {
-        }
+                timeout.check()?;
+            }
-        // Wait for the bus to be free
+            // Wait for the bus to be free
-        while info.regs.isr().read().busy() {
+            while info.regs.isr().read().busy() {
-            timeout.check()?;
+                timeout.check()?;
+            }
        }
-        let reload = if reload {
-            i2c::vals::Reload::NOT_COMPLETED
-        } else {
-            i2c::vals::Reload::COMPLETED
-        };
        // Set START and prepare to send `bytes`. The
        // START bit can be set even if the bus is BUSY or
        // I2C is in slave mode.
@@ -204,28 +216,36 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
            w.set_nbytes(length as u8);
            w.set_start(true);
            w.set_autoend(stop.autoend());
-            w.set_reload(reload);
+            w.set_reload(Self::to_reload(reload));
        });
        Ok(())
    }
-    fn reload(info: &'static Info, length: usize, will_reload: bool, timeout: Timeout) -> Result<(), Error> {
+    fn reload(
+        info: &'static Info,
+        length: usize,
+        will_reload: bool,
+        stop: Stop,
+        timeout: Timeout,
+    ) -> Result<(), Error> {
        assert!(length < 256 && length > 0);
-        while !info.regs.isr().read().tcr() {
+        // Wait for either TCR (Transfer Complete Reload) or TC (Transfer Complete)
+        // TCR occurs when RELOAD=1, TC occurs when RELOAD=0
+        // Both indicate the peripheral is ready for the next transfer
+        loop {
+            let isr = info.regs.isr().read();
+            if isr.tcr() || isr.tc() {
+                break;
+            }
            timeout.check()?;
        }
-        let will_reload = if will_reload {
-            i2c::vals::Reload::NOT_COMPLETED
-        } else {
-            i2c::vals::Reload::COMPLETED
-        };
        info.regs.cr2().modify(|w| {
            w.set_nbytes(length as u8);
-            w.set_reload(will_reload);
+            w.set_reload(Self::to_reload(will_reload));
+            w.set_autoend(stop.autoend());
        });
        Ok(())
@@ -369,7 +389,9 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
        loop {
            let isr = self.info.regs.isr().read();
            self.error_occurred(&isr, timeout)?;
-            if isr.tc() {
+            // Wait for either TC or TCR - both indicate transfer completion
+            // TCR occurs when RELOAD=1, TC occurs when RELOAD=0
+            if isr.tc() || isr.tcr() {
                return Ok(());
            }
            timeout.check()?;
@@ -396,14 +418,20 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
            address,
            read.len().min(255),
            Stop::Automatic,
-            last_chunk_idx != 0,
+            last_chunk_idx != 0, // reload
            restart,
            timeout,
        )?;
        for (number, chunk) in read.chunks_mut(255).enumerate() {
            if number != 0 {
-                Self::reload(self.info, chunk.len(), number != last_chunk_idx, timeout)?;
+                Self::reload(
+                    self.info,
+                    chunk.len(),
+                    number != last_chunk_idx,
+                    Stop::Automatic,
+                    timeout,
+                )?;
            }
            for byte in chunk {
@@ -441,6 +469,7 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
            write.len().min(255),
            Stop::Software,
            last_chunk_idx != 0,
+            false, // restart
            timeout,
        ) {
            if send_stop {
@@ -451,7 +480,13 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
        for (number, chunk) in write.chunks(255).enumerate() {
            if number != 0 {
-                Self::reload(self.info, chunk.len(), number != last_chunk_idx, timeout)?;
+                Self::reload(
+                    self.info,
+                    chunk.len(),
+                    number != last_chunk_idx,
+                    Stop::Software,
+                    timeout,
+                )?;
            }
            for byte in chunk {
@@ -507,9 +542,215 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
    ///
    /// [transaction contract]: embedded_hal_1::i2c::I2c::transaction
    pub fn blocking_transaction(&mut self, addr: u8, operations: &mut [Operation<'_>]) -> Result<(), Error> {
-        let _ = addr;
+        if operations.is_empty() {
-        let _ = operations;
+            return Err(Error::ZeroLengthTransfer);
-        todo!()
+        }
+        let address = addr.into();
+        let timeout = self.timeout();
+        // Group consecutive operations of the same type
+        let mut op_idx = 0;
+        let mut is_first_group = true;
+        while op_idx < operations.len() {
+            // Determine the type of current group and find all consecutive operations of same type
+            let is_read = matches!(operations[op_idx], Operation::Read(_));
+            let group_start = op_idx;
+            // Find end of this group (consecutive operations of same type)
+            while op_idx < operations.len() && matches!(operations[op_idx], Operation::Read(_)) == is_read {
+                op_idx += 1;
+            }
+            let group_end = op_idx;
+            let is_last_group = op_idx >= operations.len();
+            // Execute this group of operations
+            if is_read {
+                self.execute_read_group(
+                    address,
+                    &mut operations[group_start..group_end],
+                    is_first_group,
+                    is_last_group,
+                    timeout,
+                )?;
+            } else {
+                self.execute_write_group(
+                    address,
+                    &operations[group_start..group_end],
+                    is_first_group,
+                    is_last_group,
+                    timeout,
+                )?;
+            }
+            is_first_group = false;
+        }
+        Ok(())
+    }
+    fn execute_write_group(
+        &mut self,
+        address: Address,
+        operations: &[Operation<'_>],
+        is_first_group: bool,
+        is_last_group: bool,
+        timeout: Timeout,
+    ) -> Result<(), Error> {
+        // Calculate total bytes across all operations in this group
+        let total_bytes = Self::total_operation_bytes(operations);
+        if total_bytes == 0 {
+            // Handle empty write group - just send address
+            if is_first_group {
+                Self::master_write(self.info, address, 0, Stop::Software, false, !is_first_group, timeout)?;
+            }
+            if is_last_group {
+                self.master_stop();
+            }
+            return Ok(());
+        }
+        let mut total_remaining = total_bytes;
+        let mut first_chunk = true;
+        for operation in operations {
+            if let Operation::Write(buffer) = operation {
+                for chunk in buffer.chunks(255) {
+                    let chunk_len = chunk.len();
+                    total_remaining -= chunk_len;
+                    let is_last_chunk = total_remaining == 0;
+                    let will_reload = !is_last_chunk;
+                    if first_chunk {
+                        // First chunk: initiate transfer
+                        // If not first group, use RESTART instead of START
+                        Self::master_write(
+                            self.info,
+                            address,
+                            chunk_len,
+                            Stop::Software,
+                            will_reload,
+                            !is_first_group,
+                            timeout,
+                        )?;
+                        first_chunk = false;
+                    } else {
+                        // Subsequent chunks: use reload
+                        // Always use Software stop for writes
+                        Self::reload(self.info, chunk_len, will_reload, Stop::Software, timeout)?;
+                    }
+                    // Send data bytes
+                    for byte in chunk {
+                        self.wait_txis(timeout)?;
+                        self.info.regs.txdr().write(|w| w.set_txdata(*byte));
+                    }
+                }
+            }
+        }
+        // Wait for transfer to complete
+        if is_last_group {
+            self.wait_tc(timeout)?;
+            self.master_stop();
+            self.wait_stop(timeout)?;
+        } else {
+            // Wait for TC before next group (enables RESTART)
+            self.wait_tc(timeout)?;
+        }
+        Ok(())
+    }
+    fn execute_read_group(
+        &mut self,
+        address: Address,
+        operations: &mut [Operation<'_>],
+        is_first_group: bool,
+        is_last_group: bool,
+        timeout: Timeout,
+    ) -> Result<(), Error> {
+        // Calculate total bytes across all operations in this group
+        let total_bytes = Self::total_operation_bytes(operations);
+        if total_bytes == 0 {
+            // Handle empty read group
+            if is_first_group {
+                Self::master_read(
+                    self.info,
+                    address,
+                    0,
+                    if is_last_group { Stop::Automatic } else { Stop::Software },
+                    false, // reload
+                    !is_first_group,
+                    timeout,
+                )?;
+            }
+            if is_last_group {
+                self.wait_stop(timeout)?;
+            }
+            return Ok(());
+        }
+        let mut total_remaining = total_bytes;
+        let mut first_chunk = true;
+        for operation in operations {
+            if let Operation::Read(buffer) = operation {
+                for chunk in buffer.chunks_mut(255) {
+                    let chunk_len = chunk.len();
+                    total_remaining -= chunk_len;
+                    let is_last_chunk = total_remaining == 0;
+                    let will_reload = !is_last_chunk;
+                    if first_chunk {
+                        // First chunk: initiate transfer
+                        let stop = if is_last_group && is_last_chunk {
+                            Stop::Automatic
+                        } else {
+                            Stop::Software
+                        };
+                        Self::master_read(
+                            self.info,
+                            address,
+                            chunk_len,
+                            stop,
+                            will_reload,
+                            !is_first_group, // restart if not first group
+                            timeout,
+                        )?;
+                        first_chunk = false;
+                    } else {
+                        // Subsequent chunks: use reload
+                        let stop = if is_last_group && is_last_chunk {
+                            Stop::Automatic
+                        } else {
+                            Stop::Software
+                        };
+                        Self::reload(self.info, chunk_len, will_reload, stop, timeout)?;
+                    }
+                    // Receive data bytes
+                    for byte in chunk {
+                        self.wait_rxne(timeout)?;
+                        *byte = self.info.regs.rxdr().read().rxdata();
+                    }
+                }
+            }
+        }
+        // Wait for transfer to complete
+        if is_last_group {
+            self.wait_stop(timeout)?;
+        }
+        // For non-last read groups, don't wait for TC - the peripheral may hold SCL low
+        // in Software AUTOEND mode until the next START is issued. Just proceed directly
+        // to the next group which will issue RESTART and release the clock.
+        Ok(())
    }
    /// Blocking write multiple buffers.
@@ -531,6 +772,7 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
            first_length.min(255),
            Stop::Software,
            (first_length > 255) || (last_slice_index != 0),
+            false, // restart
            timeout,
        ) {
            self.master_stop();
@@ -552,6 +794,7 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
                    self.info,
                    slice_len.min(255),
                    (idx != last_slice_index) || (slice_len > 255),
+                    Stop::Software,
                    timeout,
                ) {
                    if err != Error::Nack {
@@ -567,6 +810,7 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
                        self.info,
                        chunk.len(),
                        (number != last_chunk_idx) || (idx != last_slice_index),
+                        Stop::Software,
                        timeout,
                    ) {
                        if err != Error::Nack {
@@ -610,6 +854,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
        first_slice: bool,
        last_slice: bool,
        send_stop: bool,
+        restart: bool,
        timeout: Timeout,
    ) -> Result<(), Error> {
        let total_len = write.len();
@@ -676,10 +921,17 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
                        total_len.min(255),
                        Stop::Software,
                        (total_len > 255) || !last_slice,
+                        restart,
                        timeout,
                    )?;
                } else {
-                    Self::reload(self.info, total_len.min(255), (total_len > 255) || !last_slice, timeout)?;
+                    Self::reload(
+                        self.info,
+                        total_len.min(255),
+                        (total_len > 255) || !last_slice,
+                        Stop::Software,
+                        timeout,
+                    )?;
                    self.info.regs.cr1().modify(|w| w.set_tcie(true));
                }
            } else if !(isr.tcr() || isr.tc()) {
@@ -688,9 +940,13 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
            } else if remaining_len == 0 {
                return Poll::Ready(Ok(()));
            } else {
-                let last_piece = (remaining_len <= 255) && last_slice;
+                if let Err(e) = Self::reload(
+                    self.info,
-                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !last_piece, timeout) {
+                    remaining_len.min(255),
+                    (remaining_len > 255) || !last_slice,
+                    Stop::Software,
+                    timeout,
+                ) {
                    return Poll::Ready(Err(e));
                }
                self.info.regs.cr1().modify(|w| w.set_tcie(true));
@@ -702,10 +958,9 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
        .await?;
        dma_transfer.await;
-        if last_slice {
-            // This should be done already
+        // Always wait for TC after DMA completes - needed for consecutive buffers
-            self.wait_tc(timeout)?;
+        self.wait_tc(timeout)?;
-        }
        if last_slice & send_stop {
            self.master_stop();
@@ -780,7 +1035,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
                    address,
                    total_len.min(255),
                    Stop::Automatic,
-                    total_len > 255,
+                    total_len > 255, // reload
                    restart,
                    timeout,
                )?;
@@ -788,12 +1043,10 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
                    return Poll::Ready(Ok(()));
                }
            } else if isr.tcr() {
-                // poll_fn was woken without an interrupt present
+                // Transfer Complete Reload - need to set up next chunk
-                return Poll::Pending;
-            } else {
                let last_piece = remaining_len <= 255;
-                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !last_piece, timeout) {
+                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !last_piece, Stop::Automatic, timeout) {
                    return Poll::Ready(Err(e));
                }
                // Return here if we are on last chunk,
@@ -802,6 +1055,9 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
                    return Poll::Ready(Ok(()));
                }
                self.info.regs.cr1().modify(|w| w.set_tcie(true));
+            } else {
+                // poll_fn was woken without TCR interrupt
+                return Poll::Pending;
            }
            remaining_len = remaining_len.saturating_sub(255);
@@ -826,7 +1082,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
            self.write_internal(address.into(), write, true, timeout)
        } else {
            timeout
-                .with(self.write_dma_internal(address.into(), write, true, true, true, timeout))
+                .with(self.write_dma_internal(address.into(), write, true, true, true, false, timeout))
                .await
        }
    }
@@ -842,16 +1098,24 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
        if write.is_empty() {
            return Err(Error::ZeroLengthTransfer);
        }
-        let mut iter = write.iter();
+        let mut iter = write.iter();
        let mut first = true;
        let mut current = iter.next();
        while let Some(c) = current {
            let next = iter.next();
            let is_last = next.is_none();
-            let fut = self.write_dma_internal(address, c, first, is_last, is_last, timeout);
+            let fut = self.write_dma_internal(
+                address, c, first,   // first_slice
+                is_last, // last_slice
+                is_last, // send_stop (only on last buffer)
+                false,   // restart (false for all - they're one continuous write)
+                timeout,
+            );
            timeout.with(fut).await?;
            first = false;
            current = next;
        }
@@ -881,7 +1145,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
        if write.is_empty() {
            self.write_internal(address.into(), write, false, timeout)?;
        } else {
-            let fut = self.write_dma_internal(address.into(), write, true, true, false, timeout);
+            let fut = self.write_dma_internal(address.into(), write, true, true, false, false, timeout);
            timeout.with(fut).await?;
        }
@@ -903,9 +1167,299 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
    pub async fn transaction(&mut self, addr: u8, operations: &mut [Operation<'_>]) -> Result<(), Error> {
        #[cfg(all(feature = "low-power", stm32wlex))]
        let _device_busy = crate::low_power::DeviceBusy::new_stop1();
-        let _ = addr;
-        let _ = operations;
+        if operations.is_empty() {
-        todo!()
+            return Err(Error::ZeroLengthTransfer);
+        }
+        let address = addr.into();
+        let timeout = self.timeout();
+        // Group consecutive operations of the same type
+        let mut op_idx = 0;
+        let mut is_first_group = true;
+        while op_idx < operations.len() {
+            // Determine the type of current group and find all consecutive operations of same type
+            let is_read = matches!(operations[op_idx], Operation::Read(_));
+            let group_start = op_idx;
+            // Find end of this group (consecutive operations of same type)
+            while op_idx < operations.len() && matches!(operations[op_idx], Operation::Read(_)) == is_read {
+                op_idx += 1;
+            }
+            let group_end = op_idx;
+            let is_last_group = op_idx >= operations.len();
+            // Execute this group of operations
+            if is_read {
+                self.execute_read_group_async(
+                    address,
+                    &mut operations[group_start..group_end],
+                    is_first_group,
+                    is_last_group,
+                    timeout,
+                )
+                .await?;
+            } else {
+                self.execute_write_group_async(
+                    address,
+                    &operations[group_start..group_end],
+                    is_first_group,
+                    is_last_group,
+                    timeout,
+                )
+                .await?;
+            }
+            is_first_group = false;
+        }
+        Ok(())
+    }
+    async fn execute_write_group_async(
+        &mut self,
+        address: Address,
+        operations: &[Operation<'_>],
+        is_first_group: bool,
+        is_last_group: bool,
+        timeout: Timeout,
+    ) -> Result<(), Error> {
+        // Calculate total bytes across all operations in this group
+        let total_bytes = Self::total_operation_bytes(operations);
+        if total_bytes == 0 {
+            // Handle empty write group using blocking call
+            if is_first_group {
+                Self::master_write(self.info, address, 0, Stop::Software, false, !is_first_group, timeout)?;
+            }
+            if is_last_group {
+                self.master_stop();
+            }
+            return Ok(());
+        }
+        // Collect all write buffers
+        let mut write_buffers: heapless::Vec<&[u8], 16> = heapless::Vec::new();
+        for operation in operations {
+            if let Operation::Write(buffer) = operation {
+                if !buffer.is_empty() {
+                    let _ = write_buffers.push(buffer);
+                }
+            }
+        }
+        if write_buffers.is_empty() {
+            return Ok(());
+        }
+        // Send each buffer using DMA
+        let num_buffers = write_buffers.len();
+        for (idx, buffer) in write_buffers.iter().enumerate() {
+            let is_first_buffer = idx == 0;
+            let is_last_buffer = idx == num_buffers - 1;
+            let fut = self.write_dma_internal(
+                address,
+                buffer,
+                is_first_buffer,                    // first_slice
+                is_last_buffer,                     // last_slice
+                is_last_buffer && is_last_group,    // send_stop
+                is_first_buffer && !is_first_group, // restart (only for first buffer if not first group)
+                timeout,
+            );
+            timeout.with(fut).await?;
+        }
+        Ok(())
+    }
+    async fn execute_read_group_async(
+        &mut self,
+        address: Address,
+        operations: &mut [Operation<'_>],
+        is_first_group: bool,
+        is_last_group: bool,
+        timeout: Timeout,
+    ) -> Result<(), Error> {
+        // Calculate total bytes across all operations in this group
+        let total_bytes = Self::total_operation_bytes(operations);
+        if total_bytes == 0 {
+            // Handle empty read group using blocking call
+            if is_first_group {
+                Self::master_read(
+                    self.info,
+                    address,
+                    0,
+                    if is_last_group { Stop::Automatic } else { Stop::Software },
+                    false, // reload
+                    !is_first_group,
+                    timeout,
+                )?;
+            }
+            if is_last_group {
+                self.wait_stop(timeout)?;
+            }
+            return Ok(());
+        }
+        // Use DMA for read operations - need to handle multiple buffers
+        let restart = !is_first_group;
+        let mut total_remaining = total_bytes;
+        let mut is_first_in_group = true;
+        for operation in operations {
+            if let Operation::Read(buffer) = operation {
+                if buffer.is_empty() {
+                    // Skip empty buffers
+                    continue;
+                }
+                let buf_len = buffer.len();
+                total_remaining -= buf_len;
+                let is_last_in_group = total_remaining == 0;
+                // Perform DMA read
+                if is_first_in_group {
+                    // First buffer: use read_dma_internal which handles restart properly
+                    // Only use Automatic stop if this is the last buffer in the last group
+                    let stop_mode = if is_last_group && is_last_in_group {
+                        Stop::Automatic
+                    } else {
+                        Stop::Software
+                    };
+                    // We need a custom DMA read that respects our stop mode
+                    self.read_dma_group_internal(address, buffer, restart, stop_mode, timeout)
+                        .await?;
+                    is_first_in_group = false;
+                } else {
+                    // Subsequent buffers: need to reload and continue
+                    let stop_mode = if is_last_group && is_last_in_group {
+                        Stop::Automatic
+                    } else {
+                        Stop::Software
+                    };
+                    self.read_dma_group_internal(
+                        address, buffer, false, // no restart for subsequent buffers in same group
+                        stop_mode, timeout,
+                    )
+                    .await?;
+                }
+            }
+        }
+        // Wait for transfer to complete
+        if is_last_group {
+            self.wait_stop(timeout)?;
+        }
+        Ok(())
+    }
+    /// Internal DMA read helper for transaction groups
+    async fn read_dma_group_internal(
+        &mut self,
+        address: Address,
+        buffer: &mut [u8],
+        restart: bool,
+        stop_mode: Stop,
+        timeout: Timeout,
+    ) -> Result<(), Error> {
+        let total_len = buffer.len();
+        let dma_transfer = unsafe {
+            let regs = self.info.regs;
+            regs.cr1().modify(|w| {
+                w.set_rxdmaen(true);
+                w.set_tcie(true);
+                w.set_nackie(true);
+                w.set_errie(true);
+            });
+            let src = regs.rxdr().as_ptr() as *mut u8;
+            self.rx_dma.as_mut().unwrap().read(src, buffer, Default::default())
+        };
+        let mut remaining_len = total_len;
+        let on_drop = OnDrop::new(|| {
+            let regs = self.info.regs;
+            regs.cr1().modify(|w| {
+                w.set_rxdmaen(false);
+                w.set_tcie(false);
+                w.set_nackie(false);
+                w.set_errie(false);
+            });
+            regs.icr().write(|w| {
+                w.set_nackcf(true);
+                w.set_berrcf(true);
+                w.set_arlocf(true);
+                w.set_ovrcf(true);
+            });
+        });
+        poll_fn(|cx| {
+            self.state.waker.register(cx.waker());
+            let isr = self.info.regs.isr().read();
+            if isr.nackf() {
+                return Poll::Ready(Err(Error::Nack));
+            }
+            if isr.arlo() {
+                return Poll::Ready(Err(Error::Arbitration));
+            }
+            if isr.berr() {
+                return Poll::Ready(Err(Error::Bus));
+            }
+            if isr.ovr() {
+                return Poll::Ready(Err(Error::Overrun));
+            }
+            if remaining_len == total_len {
+                Self::master_read(
+                    self.info,
+                    address,
+                    total_len.min(255),
+                    stop_mode,
+                    total_len > 255, // reload
+                    restart,
+                    timeout,
+                )?;
+                if total_len <= 255 {
+                    return Poll::Ready(Ok(()));
+                }
+            } else if isr.tcr() {
+                // Transfer Complete Reload - need to set up next chunk
+                let last_piece = remaining_len <= 255;
+                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !last_piece, stop_mode, timeout) {
+                    return Poll::Ready(Err(e));
+                }
+                // Return here if we are on last chunk,
+                // end of transfer will be awaited with the DMA below
+                if last_piece {
+                    return Poll::Ready(Ok(()));
+                }
+                self.info.regs.cr1().modify(|w| w.set_tcie(true));
+            } else {
+                // poll_fn was woken without TCR interrupt
+                return Poll::Pending;
+            }
+            remaining_len = remaining_len.saturating_sub(255);
+            Poll::Pending
+        })
+        .await?;
+        dma_transfer.await;
+        drop(on_drop);
+        Ok(())
    }
 }
@@ -1043,7 +1597,13 @@ impl<'d, M: Mode> I2c<'d, M, MultiMaster> {
            if number == 0 {
                Self::slave_start(self.info, chunk.len(), number != last_chunk_idx);
            } else {
-                Self::reload(self.info, chunk.len(), number != last_chunk_idx, timeout)?;
+                Self::reload(
+                    self.info,
+                    chunk.len(),
+                    number != last_chunk_idx,
+                    Stop::Software,
+                    timeout,
+                )?;
            }
            let mut index = 0;
@@ -1092,7 +1652,13 @@ impl<'d, M: Mode> I2c<'d, M, MultiMaster> {
            if number == 0 {
                Self::slave_start(self.info, chunk.len(), number != last_chunk_idx);
            } else {
-                Self::reload(self.info, chunk.len(), number != last_chunk_idx, timeout)?;
+                Self::reload(
+                    self.info,
+                    chunk.len(),
+                    number != last_chunk_idx,
+                    Stop::Software,
+                    timeout,
+                )?;
            }
            let mut index = 0;
@@ -1228,13 +1794,20 @@ impl<'d> I2c<'d, Async, MultiMaster> {
                Poll::Pending
            } else if isr.tcr() {
                let is_last_slice = remaining_len <= 255;
-                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !is_last_slice, timeout) {
+                if let Err(e) = Self::reload(
+                    self.info,
+                    remaining_len.min(255),
+                    !is_last_slice,
+                    Stop::Software,
+                    timeout,
+                ) {
                    return Poll::Ready(Err(e));
                }
                remaining_len = remaining_len.saturating_sub(255);
                regs.cr1().modify(|w| w.set_tcie(true));
                Poll::Pending
            } else if isr.stopf() {
+                remaining_len = remaining_len.saturating_add(dma_transfer.get_remaining_transfers() as usize);
                regs.icr().write(|reg| reg.set_stopcf(true));
                let poll = Poll::Ready(Ok(total_len - remaining_len));
                poll
@@ -1274,7 +1847,8 @@ impl<'d> I2c<'d, Async, MultiMaster> {
                w.set_txdmaen(false);
                w.set_stopie(false);
                w.set_tcie(false);
-            })
+            });
+            regs.isr().write(|w| w.set_txe(true));
        });
        let state = self.state;
@@ -1290,13 +1864,24 @@ impl<'d> I2c<'d, Async, MultiMaster> {
                Poll::Pending
            } else if isr.tcr() {
                let is_last_slice = remaining_len <= 255;
-                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !is_last_slice, timeout) {
+                if let Err(e) = Self::reload(
+                    self.info,
+                    remaining_len.min(255),
+                    !is_last_slice,
+                    Stop::Software,
+                    timeout,
+                ) {
                    return Poll::Ready(Err(e));
                }
                remaining_len = remaining_len.saturating_sub(255);
                self.info.regs.cr1().modify(|w| w.set_tcie(true));
                Poll::Pending
            } else if isr.stopf() {
+                let mut leftover_bytes = dma_transfer.get_remaining_transfers();
+                if !self.info.regs.isr().read().txe() {
+                    leftover_bytes = leftover_bytes.saturating_add(1);
+                }
+                remaining_len = remaining_len.saturating_add(leftover_bytes as usize);
                self.info.regs.icr().write(|reg| reg.set_stopcf(true));
                if remaining_len > 0 {
                    dma_transfer.request_pause();
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs
index e08ab30e6..6e492946a 100644
--- a/embassy-stm32/src/lib.rs
+++ b/embassy-stm32/src/lib.rs
@@ -77,6 +77,7 @@ pub mod dts;
 pub mod eth;
 #[cfg(feature = "exti")]
 pub mod exti;
+#[cfg(flash)]
 pub mod flash;
 #[cfg(fmc)]
 pub mod fmc;
@@ -177,7 +178,6 @@ pub use crate::_generated::interrupt;
 ///     }
 /// );
 /// ```
 // developer note: this macro can't be in `embassy-hal-internal` due to the use of `$crate`.
 #[macro_export]
 macro_rules! bind_interrupts {
@@ -510,6 +510,16 @@ fn init_hw(config: Config) -> Peripherals {
    critical_section::with(|cs| {
        let p = Peripherals::take_with_cs(cs);
+        #[cfg(dbgmcu_n6)]
+        {
+            crate::pac::RCC.miscensr().write(|w| w.set_dbgens(true));
+            crate::pac::RCC.miscenr().read(); // volatile read
+            crate::pac::DBGMCU
+                .cr()
+                .modify(|w| w.set_dbgclken(stm32_metapac::dbgmcu::vals::Dbgclken::B_0X1));
+            crate::pac::DBGMCU.cr().read();
+        }
        #[cfg(dbgmcu)]
        crate::pac::DBGMCU.cr().modify(|cr| {
            #[cfg(dbgmcu_h5)]
@@ -524,7 +534,7 @@ fn init_hw(config: Config) -> Peripherals {
            }
            #[cfg(any(
                dbgmcu_f1, dbgmcu_f2, dbgmcu_f3, dbgmcu_f4, dbgmcu_f7, dbgmcu_g4, dbgmcu_f7, dbgmcu_l0, dbgmcu_l1,
-                dbgmcu_l4, dbgmcu_wb, dbgmcu_wl
+                dbgmcu_l4, dbgmcu_wb, dbgmcu_wl, dbgmcu_n6
            ))]
            {
                cr.set_dbg_sleep(config.enable_debug_during_sleep);
@@ -545,7 +555,7 @@ fn init_hw(config: Config) -> Peripherals {
        rcc::enable_and_reset_with_cs::<peripherals::SYSCFG>(cs);
        #[cfg(not(any(stm32h5, stm32h7, stm32h7rs, stm32wb, stm32wl)))]
        rcc::enable_and_reset_with_cs::<peripherals::PWR>(cs);
-        #[cfg(not(any(stm32f2, stm32f4, stm32f7, stm32l0, stm32h5, stm32h7, stm32h7rs)))]
+        #[cfg(all(flash, not(any(stm32f2, stm32f4, stm32f7, stm32l0, stm32h5, stm32h7, stm32h7rs))))]
        rcc::enable_and_reset_with_cs::<peripherals::FLASH>(cs);
        // Enable the VDDIO2 power supply on chips that have it.
@@ -605,7 +615,7 @@ fn init_hw(config: Config) -> Peripherals {
            #[cfg(ucpd)]
            ucpd::init(
                cs,
-                #[cfg(peri_ucpd1)]
+                #[cfg(all(peri_ucpd1, not(stm32n6)))]
                config.enable_ucpd1_dead_battery,
                #[cfg(peri_ucpd2)]
                config.enable_ucpd2_dead_battery,
@@ -648,3 +658,17 @@ fn init_hw(config: Config) -> Peripherals {
        p
    })
 }
+/// Performs a busy-wait delay for a specified number of microseconds.
+#[allow(unused)]
+pub(crate) fn block_for_us(us: u64) {
+    cfg_if::cfg_if! {
+        // this does strange things on stm32wlx in low power mode depending on exactly when it's called
+        // as in sometimes 15 us (1 tick) would take > 20 seconds.
+        if #[cfg(all(feature = "time", all(not(feature = "low-power"), not(stm32wlex))))] {
+            embassy_time::block_for(embassy_time::Duration::from_micros(us));
+        } else {
+            cortex_m::asm::delay(unsafe { rcc::get_freqs().sys.to_hertz().unwrap().0 as u64 * us  / 1_000_000 } as u32);
+        }
+    }
+}
diff --git a/embassy-stm32/src/opamp.rs b/embassy-stm32/src/opamp.rs
index ac8d5de21..4a55f5bd3 100644
--- a/embassy-stm32/src/opamp.rs
+++ b/embassy-stm32/src/opamp.rs
@@ -4,19 +4,12 @@
 use embassy_hal_internal::PeripheralType;
 use crate::Peri;
+#[cfg(opamp_v5)]
+use crate::block_for_us;
 use crate::pac::opamp::vals::*;
 #[cfg(not(any(stm32g4, stm32f3)))]
 use crate::rcc::RccInfo;
-/// Performs a busy-wait delay for a specified number of microseconds.
-#[cfg(opamp_v5)]
-fn blocking_delay_ms(ms: u32) {
-    #[cfg(feature = "time")]
-    embassy_time::block_for(embassy_time::Duration::from_millis(ms as u64));
-    #[cfg(not(feature = "time"))]
-    cortex_m::asm::delay(unsafe { crate::rcc::get_freqs() }.sys.to_hertz().unwrap().0 / 1_000 * ms);
-}
 /// Gain
 #[allow(missing_docs)]
 #[derive(Clone, Copy)]
@@ -439,7 +432,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
            // The closer the trimming value is to the optimum trimming value, the longer it takes to stabilize
            // (with a maximum stabilization time remaining below 2 ms in any case) -- RM0440 25.3.7
-            blocking_delay_ms(2);
+            block_for_us(2_000);
            if !T::regs().csr().read().calout() {
                if mid == 0 {
diff --git a/embassy-stm32/src/rcc/bd.rs b/embassy-stm32/src/rcc/bd.rs
index 5b367c043..219be208f 100644
--- a/embassy-stm32/src/rcc/bd.rs
+++ b/embassy-stm32/src/rcc/bd.rs
@@ -1,5 +1,7 @@
+#[cfg(not(stm32n6))]
 use core::sync::atomic::{Ordering, compiler_fence};
+#[cfg(not(stm32n6))]
 use crate::pac::common::{RW, Reg};
 #[cfg(backup_sram)]
 use crate::pac::pwr::vals::Retention;
@@ -54,7 +56,7 @@ impl From<LseDrive> for crate::pac::rcc::vals::Lsedrv {
    }
 }
-#[cfg(not(any(rtc_v2_l0, rtc_v2_l1, stm32c0)))]
+#[cfg(not(any(rtc_v2_l0, rtc_v2_l1, stm32c0, stm32n6)))]
 type Bdcr = crate::pac::rcc::regs::Bdcr;
 #[cfg(any(rtc_v2_l0, rtc_v2_l1))]
 type Bdcr = crate::pac::rcc::regs::Csr;
@@ -64,19 +66,22 @@ type Bdcr = crate::pac::rcc::regs::Csr1;
 #[cfg(any(stm32c0))]
 fn unlock() {}
-#[cfg(not(any(stm32c0)))]
+#[cfg(not(any(stm32c0, stm32n6)))]
 fn unlock() {
    #[cfg(any(stm32f0, stm32f1, stm32f2, stm32f3, stm32l0, stm32l1))]
    let cr = crate::pac::PWR.cr();
-    #[cfg(not(any(stm32f0, stm32f1, stm32f2, stm32f3, stm32l0, stm32l1, stm32u5, stm32h5, stm32wba)))]
+    #[cfg(not(any(
+        stm32f0, stm32f1, stm32f2, stm32f3, stm32l0, stm32l1, stm32u5, stm32h5, stm32wba, stm32n6
+    )))]
    let cr = crate::pac::PWR.cr1();
-    #[cfg(any(stm32u5, stm32h5, stm32wba))]
+    #[cfg(any(stm32u5, stm32h5, stm32wba, stm32n6))]
    let cr = crate::pac::PWR.dbpcr();
    cr.modify(|w| w.set_dbp(true));
    while !cr.read().dbp() {}
 }
+#[cfg(not(stm32n6))]
 fn bdcr() -> Reg<Bdcr, RW> {
    #[cfg(any(rtc_v2_l0, rtc_v2_l1))]
    return crate::pac::RCC.csr();
@@ -150,6 +155,7 @@ impl Default for LsConfig {
 }
 impl LsConfig {
+    #[cfg(not(stm32n6))]
    pub(crate) fn init(&self) -> Option<Hertz> {
        let rtc_clk = match self.rtc {
            RtcClockSource::LSI => {
@@ -185,14 +191,19 @@ impl LsConfig {
        if self.lsi {
            #[cfg(any(stm32u5, stm32h5, stm32wba))]
            let csr = crate::pac::RCC.bdcr();
-            #[cfg(not(any(stm32u5, stm32h5, stm32wba, stm32c0)))]
+            #[cfg(stm32n6)]
+            let csr = crate::pac::RCC.sr();
+            #[cfg(not(any(stm32u5, stm32h5, stm32wba, stm32c0, stm32n6)))]
            let csr = crate::pac::RCC.csr();
-            #[cfg(any(stm32c0))]
+            #[cfg(stm32c0)]
            let csr = crate::pac::RCC.csr2();
-            #[cfg(not(any(rcc_wb, rcc_wba)))]
+            #[cfg(not(any(rcc_wb, rcc_wba, rcc_n6)))]
            csr.modify(|w| w.set_lsion(true));
+            #[cfg(rcc_n6)]
+            crate::pac::RCC.cr().modify(|w| w.set_lsion(true));
            #[cfg(any(rcc_wb, rcc_wba))]
            csr.modify(|w| w.set_lsi1on(true));
@@ -222,25 +233,58 @@ impl LsConfig {
        // backup domain configuration (LSEON, RTCEN, RTCSEL) is kept across resets.
        // once set, changing it requires a backup domain reset.
        // first check if the configuration matches what we want.
+        // N6 has all the fields spread across multiple registers under RCC.
        // check if it's already enabled and in the source we want.
+        #[cfg(not(rcc_n6))]
        let reg = bdcr().read();
+        #[cfg(rcc_n6)]
+        let reg = crate::pac::RCC.cr().read();
+        #[cfg(rcc_n6)]
+        let apb4lenr = crate::pac::RCC.apb4lenr().read();
+        #[cfg(rcc_n6)]
+        let ccipr7 = crate::pac::RCC.ccipr7().read();
+        #[cfg(rcc_n6)]
+        let lsecfgr = crate::pac::RCC.lsecfgr().read();
        let mut ok = true;
-        ok &= reg.rtcsel() == self.rtc;
+        #[cfg(not(rcc_n6))]
-        #[cfg(not(rcc_wba))]
+        {
+            ok &= reg.rtcsel() == self.rtc;
+        }
+        #[cfg(rcc_n6)]
+        {
+            ok &= ccipr7.rtcsel() == self.rtc;
+        }
+        #[cfg(not(any(rcc_wba, rcc_n6)))]
        {
            ok &= reg.rtcen() == (self.rtc != RtcClockSource::DISABLE);
        }
+        #[cfg(rcc_n6)]
+        {
+            ok &= apb4lenr.rtcen() == (self.rtc != RtcClockSource::DISABLE);
+        }
        ok &= reg.lseon() == lse_en;
-        ok &= reg.lsebyp() == lse_byp;
+        #[cfg(not(rcc_n6))]
+        {
+            ok &= reg.lsebyp() == lse_byp;
+        }
+        #[cfg(rcc_n6)]
+        {
+            ok &= lsecfgr.lsebyp() == lse_byp;
+        }
        #[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba, rcc_u0))]
        if let Some(lse_sysen) = lse_sysen {
            ok &= reg.lsesysen() == lse_sysen;
        }
-        #[cfg(not(any(rcc_f1, rcc_f1cl, rcc_f100, rcc_f2, rcc_f4, rcc_f410, rcc_l1)))]
+        #[cfg(not(any(rcc_f1, rcc_f1cl, rcc_f100, rcc_f2, rcc_f4, rcc_f410, rcc_l1, rcc_n6)))]
        if let Some(lse_drv) = lse_drv {
            ok &= reg.lsedrv() == lse_drv.into();
        }
+        #[cfg(rcc_n6)]
+        if let Some(lse_drv) = lse_drv {
+            ok &= lsecfgr.lsedrv() == lse_drv.into();
+        }
        // if configuration is OK, we're done.
        if ok {
@@ -249,7 +293,7 @@ impl LsConfig {
        }
        // If not OK, reset backup domain and configure it.
-        #[cfg(not(any(rcc_l0, rcc_l0_v2, rcc_l1, stm32h5, stm32h7rs, stm32c0)))]
+        #[cfg(not(any(rcc_l0, rcc_l0_v2, rcc_l1, stm32h5, stm32h7rs, stm32c0, stm32n6)))]
        {
            bdcr().modify(|w| w.set_bdrst(true));
            bdcr().modify(|w| w.set_bdrst(false));
@@ -262,7 +306,7 @@ impl LsConfig {
        // STM32H503CB/EB/KB/RB device errata - 2.2.8 SRAM2 unduly erased upon a backup domain reset
        // STM32H562xx/563xx/573xx device errata - 2.2.14 SRAM2 is erased when the backup domain is reset
        //#[cfg(any(stm32h5, stm32h7rs))]
-        #[cfg(any(stm32h7rs))]
+        #[cfg(any(stm32h7rs, stm32n6))]
        {
            bdcr().modify(|w| w.set_vswrst(true));
            bdcr().modify(|w| w.set_vswrst(false));
@@ -274,16 +318,31 @@ impl LsConfig {
        }
        if lse_en {
-            bdcr().modify(|w| {
+            #[cfg(not(rcc_n6))]
-                #[cfg(not(any(rcc_f1, rcc_f1cl, rcc_f100, rcc_f2, rcc_f4, rcc_f410, rcc_l1)))]
+            {
-                if let Some(lse_drv) = lse_drv {
+                bdcr().modify(|w| {
-                    w.set_lsedrv(lse_drv.into());
+                    #[cfg(not(any(rcc_f1, rcc_f1cl, rcc_f100, rcc_f2, rcc_f4, rcc_f410, rcc_l1)))]
-                }
+                    if let Some(lse_drv) = lse_drv {
-                w.set_lsebyp(lse_byp);
+                        w.set_lsedrv(lse_drv.into());
-                w.set_lseon(true);
+                    }
-            });
+                    w.set_lsebyp(lse_byp);
+                    w.set_lseon(true);
+                });
-            while !bdcr().read().lserdy() {}
+                while !bdcr().read().lserdy() {}
+            }
+            #[cfg(rcc_n6)]
+            {
+                crate::pac::RCC.lsecfgr().modify(|w| {
+                    if let Some(lse_drv) = lse_drv {
+                        w.set_lsedrv(lse_drv.into());
+                    }
+                    w.set_lsebyp(lse_byp);
+                });
+                crate::pac::RCC.cr().modify(|w| w.set_lseon(true));
+                while !crate::pac::RCC.sr().read().lserdy() {}
+            }
            #[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba, rcc_u0))]
            if let Some(lse_sysen) = lse_sysen {
@@ -298,6 +357,7 @@ impl LsConfig {
        }
        if self.rtc != RtcClockSource::DISABLE {
+            #[cfg(not(rcc_n6))]
            bdcr().modify(|w| {
                #[cfg(any(rtc_v2_h7, rtc_v2_l4, rtc_v2_wb, rtc_v3_base, rtc_v3_u5))]
                assert!(!w.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
@@ -306,6 +366,12 @@ impl LsConfig {
                w.set_rtcen(true);
                w.set_rtcsel(self.rtc);
            });
+            #[cfg(rcc_n6)]
+            {
+                crate::pac::RCC.ccipr7().modify(|w| w.set_rtcsel(self.rtc));
+                crate::pac::RCC.apb4lenr().modify(|w| w.set_rtcen(true))
+            }
        }
        trace!("BDCR configured: {:08x}", bdcr().read().0);
diff --git a/embassy-stm32/src/rcc/mco.rs b/embassy-stm32/src/rcc/mco.rs
index 3d961df03..0624fdf26 100644
--- a/embassy-stm32/src/rcc/mco.rs
+++ b/embassy-stm32/src/rcc/mco.rs
@@ -16,7 +16,8 @@ pub use crate::pac::rcc::vals::Mcopre as McoPrescaler;
    rcc_h7ab,
    rcc_h7rm0433,
    rcc_h7,
-    rcc_h7rs
+    rcc_h7rs,
+    rcc_n6
 )))]
 pub use crate::pac::rcc::vals::Mcosel as McoSource;
 #[cfg(any(
@@ -29,7 +30,8 @@ pub use crate::pac::rcc::vals::Mcosel as McoSource;
    rcc_h7ab,
    rcc_h7rm0433,
    rcc_h7,
-    rcc_h7rs
+    rcc_h7rs,
+    rcc_n6
 ))]
 pub use crate::pac::rcc::vals::{Mco1sel as Mco1Source, Mco2sel as Mco2Source};
 use crate::{Peri, peripherals};
@@ -59,10 +61,12 @@ macro_rules! impl_peri {
            type Source = $source;
            unsafe fn _apply_clock_settings(source: Self::Source, _prescaler: McoPrescaler) {
-                #[cfg(not(any(stm32u5, stm32wba)))]
+                #[cfg(not(any(stm32u5, stm32wba, stm32n6)))]
                let r = RCC.cfgr();
                #[cfg(any(stm32u5, stm32wba))]
                let r = RCC.cfgr1();
+                #[cfg(any(stm32n6))]
+                let r = RCC.ccipr5();
                r.modify(|w| {
                    w.$set_source(source);
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index 01fa3a475..592890777 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -28,6 +28,7 @@ pub use hsi48::*;
 #[cfg_attr(any(stm32l0, stm32l1, stm32l4, stm32l5, stm32wb, stm32wl, stm32u0), path = "l.rs")]
 #[cfg_attr(stm32u5, path = "u5.rs")]
 #[cfg_attr(stm32wba, path = "wba.rs")]
+#[cfg_attr(stm32n6, path = "n6.rs")]
 mod _version;
 pub use _version::*;
diff --git a/embassy-stm32/src/rcc/n6.rs b/embassy-stm32/src/rcc/n6.rs
new file mode 100644
index 000000000..866851bbd
--- /dev/null
+++ b/embassy-stm32/src/rcc/n6.rs
@@ -0,0 +1,1046 @@
+use stm32_metapac::rcc::vals::{
+    Cpusw, Cpusws, Hseext, Hsitrim, Icint, Icsel, Msifreqsel, Plldivm, Pllmodssdis, Pllpdiv, Pllsel, Syssw, Syssws,
+    Timpre,
+};
+pub use stm32_metapac::rcc::vals::{
+    Hpre as AhbPrescaler, Hsidiv as HsiPrescaler, Hsitrim as HsiCalibration, Ppre as ApbPrescaler,
+};
+use crate::pac::{PWR, RCC, SYSCFG};
+use crate::time::Hertz;
+pub const HSI_FREQ: Hertz = Hertz(64_000_000);
+pub const LSE_FREQ: Hertz = Hertz(32_768);
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub enum HseMode {
+    /// crystal/ceramic oscillator
+    Oscillator,
+    /// oscillator bypassed with external clock (analog)
+    Bypass,
+    /// oscillator bypassed with external digital clock
+    BypassDigital,
+}
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub struct Hse {
+    /// HSE frequency.
+    pub freq: Hertz,
+    /// HSE oscillator mode.
+    pub mode: HseMode,
+}
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub struct Hsi {
+    pub pre: HsiPrescaler,
+    pub trim: Hsitrim,
+}
+#[derive(Clone, Copy, PartialEq)]
+pub enum SupplyConfig {
+    Smps,
+    External,
+}
+#[derive(Clone, Copy, PartialEq)]
+pub enum CpuClk {
+    Hse,
+    Ic1 { source: Icsel, divider: Icint },
+    Msi,
+    Hsi,
+}
+impl CpuClk {
+    const fn to_bits(self) -> u8 {
+        match self {
+            Self::Hsi => 0x0,
+            Self::Msi => 0x1,
+            Self::Hse => 0x2,
+            Self::Ic1 { .. } => 0x3,
+        }
+    }
+}
+#[derive(Clone, Copy, PartialEq)]
+pub struct IcConfig {
+    source: Icsel,
+    divider: Icint,
+}
+#[derive(Clone, Copy, PartialEq)]
+pub enum SysClk {
+    Hse,
+    Ic2 {
+        ic2: IcConfig,
+        ic6: IcConfig,
+        ic11: IcConfig,
+    },
+    Msi,
+    Hsi,
+}
+impl SysClk {
+    const fn to_bits(self) -> u8 {
+        match self {
+            Self::Hsi => 0x0,
+            Self::Msi => 0x1,
+            Self::Hse => 0x2,
+            Self::Ic2 { .. } => 0x3,
+        }
+    }
+}
+#[derive(Clone, Copy, PartialEq)]
+pub struct Msi {
+    pub freq: Msifreqsel,
+    pub trim: u8,
+}
+#[derive(Clone, Copy, PartialEq)]
+pub enum Pll {
+    Oscillator {
+        source: Pllsel,
+        divm: Plldivm,
+        fractional: u32,
+        divn: u16,
+        divp1: Pllpdiv,
+        divp2: Pllpdiv,
+    },
+    Bypass {
+        source: Pllsel,
+    },
+}
+/// Configuration of the core clocks
+#[non_exhaustive]
+#[derive(Clone, Copy)]
+pub struct Config {
+    pub hsi: Option<Hsi>,
+    pub hse: Option<Hse>,
+    pub msi: Option<Msi>,
+    pub lsi: bool,
+    pub lse: bool,
+    pub sys: SysClk,
+    pub cpu: CpuClk,
+    pub pll1: Option<Pll>,
+    pub pll2: Option<Pll>,
+    pub pll3: Option<Pll>,
+    pub pll4: Option<Pll>,
+    pub ahb: AhbPrescaler,
+    pub apb1: ApbPrescaler,
+    pub apb2: ApbPrescaler,
+    pub apb4: ApbPrescaler,
+    pub apb5: ApbPrescaler,
+    pub supply_config: SupplyConfig,
+}
+impl Config {
+    pub const fn new() -> Self {
+        Self {
+            hsi: Some(Hsi {
+                pre: HsiPrescaler::DIV1,
+                trim: HsiCalibration::from_bits(32),
+            }),
+            hse: None,
+            msi: None,
+            lsi: true,
+            lse: false,
+            sys: SysClk::Hsi,
+            cpu: CpuClk::Hsi,
+            pll1: Some(Pll::Bypass { source: Pllsel::HSI }),
+            pll2: Some(Pll::Bypass { source: Pllsel::HSI }),
+            pll3: Some(Pll::Bypass { source: Pllsel::HSI }),
+            pll4: Some(Pll::Bypass { source: Pllsel::HSI }),
+            ahb: AhbPrescaler::DIV2,
+            apb1: ApbPrescaler::DIV1,
+            apb2: ApbPrescaler::DIV1,
+            apb4: ApbPrescaler::DIV1,
+            apb5: ApbPrescaler::DIV1,
+            supply_config: SupplyConfig::Smps,
+        }
+    }
+}
+#[allow(dead_code)]
+struct ClocksOutput {
+    cpuclk: Hertz,
+    sysclk: Hertz,
+    pclk_tim: Hertz,
+    ahb: Hertz,
+    apb1: Hertz,
+    apb2: Hertz,
+    apb4: Hertz,
+    apb5: Hertz,
+}
+struct ClocksInput {
+    hsi: Option<Hertz>,
+    msi: Option<Hertz>,
+    hse: Option<Hertz>,
+}
+fn init_clocks(config: Config, input: &ClocksInput) -> ClocksOutput {
+    // handle increasing dividers
+    debug!("configuring increasing pclk dividers");
+    RCC.cfgr2().modify(|w| {
+        if config.apb1 > w.ppre1() {
+            debug!("  - APB1");
+            w.set_ppre1(config.apb1);
+        }
+        if config.apb2 > w.ppre2() {
+            debug!("  - APB2");
+            w.set_ppre2(config.apb2);
+        }
+        if config.apb4 > w.ppre4() {
+            debug!("  - APB4");
+            w.set_ppre4(config.apb4);
+        }
+        if config.apb5 > w.ppre5() {
+            debug!("  - APB5");
+            w.set_ppre5(config.apb5);
+        }
+        if config.ahb > w.hpre() {
+            debug!("  - AHB");
+            w.set_hpre(config.ahb);
+        }
+    });
+    // cpuclk
+    debug!("configuring cpuclk");
+    match config.cpu {
+        CpuClk::Hse if !RCC.sr().read().hserdy() => panic!("HSE is not ready to be selected as CPU clock source"),
+        CpuClk::Ic1 { source, divider } => {
+            if !pll_sources_ready(RCC.iccfgr(0).read().icsel().to_bits(), source.to_bits()) {
+                panic!("ICx clock switch requires both origin and destination clock source to be active")
+            }
+            RCC.iccfgr(0).write(|w| {
+                w.set_icsel(source);
+                w.set_icint(divider);
+            });
+            RCC.divensr().modify(|w| w.set_ic1ens(true));
+        }
+        CpuClk::Msi if !RCC.sr().read().msirdy() => panic!("MSI is not ready to be selected as CPU clock source"),
+        CpuClk::Hsi if !RCC.sr().read().hsirdy() => panic!("HSI is not ready to be selected as CPU clock source"),
+        _ => {}
+    }
+    // set source
+    let cpusw = Cpusw::from_bits(config.cpu.to_bits());
+    RCC.cfgr().modify(|w| w.set_cpusw(cpusw));
+    // wait for changes to take effect
+    while RCC.cfgr().read().cpusws() != Cpusws::from_bits(config.cpu.to_bits()) {}
+    // sysclk
+    debug!("configuring sysclk");
+    match config.sys {
+        SysClk::Hse if !RCC.sr().read().hserdy() => panic!("HSE is not ready to be selected as CPU clock source"),
+        SysClk::Ic2 { ic2, ic6, ic11 } => {
+            if !pll_sources_ready(RCC.iccfgr(1).read().icsel().to_bits(), ic2.source.to_bits()) {
+                panic!("IC2 clock switch requires both origin and destination clock source to be active")
+            }
+            if !pll_sources_ready(RCC.iccfgr(5).read().icsel().to_bits(), ic6.source.to_bits()) {
+                panic!("IC6 clock switch requires both origin and destination clock source to be active")
+            }
+            if !pll_sources_ready(RCC.iccfgr(10).read().icsel().to_bits(), ic11.source.to_bits()) {
+                panic!("IC11 clock switch requires both origin and destination clock source to be active")
+            }
+            RCC.iccfgr(1).write(|w| {
+                w.set_icsel(ic2.source);
+                w.set_icint(ic2.divider);
+            });
+            RCC.iccfgr(5).write(|w| {
+                w.set_icsel(ic6.source);
+                w.set_icint(ic6.divider);
+            });
+            RCC.iccfgr(10).write(|w| {
+                w.set_icsel(ic11.source);
+                w.set_icint(ic11.divider);
+            });
+            RCC.divensr().modify(|w| {
+                w.set_ic2ens(true);
+                w.set_ic6ens(true);
+                w.set_ic11ens(true);
+            });
+        }
+        SysClk::Msi if !RCC.sr().read().msirdy() => panic!("MSI is not ready to be selected as CPU clock source"),
+        SysClk::Hsi if !RCC.sr().read().hsirdy() => panic!("HSI is not ready to be selected as CPU clock source"),
+        _ => {}
+    }
+    // switch the system bus clock
+    let syssw = Syssw::from_bits(config.sys.to_bits());
+    RCC.cfgr().modify(|w| w.set_syssw(syssw));
+    // wait for changes to be applied
+    while RCC.cfgr().read().syssws() != Syssws::from_bits(config.sys.to_bits()) {}
+    // decreasing dividers
+    debug!("configuring decreasing pclk dividers");
+    RCC.cfgr2().modify(|w| {
+        if config.ahb < w.hpre() {
+            debug!("  - AHB");
+            w.set_hpre(config.ahb);
+        }
+        if config.apb1 < w.ppre1() {
+            debug!("  - APB1");
+            w.set_ppre1(config.apb1);
+        }
+        if config.apb2 < w.ppre2() {
+            debug!("  - APB2");
+            w.set_ppre2(config.apb2);
+        }
+        if config.apb4 < w.ppre4() {
+            debug!("  - APB4");
+            w.set_ppre4(config.apb4);
+        }
+        if config.apb5 < w.ppre5() {
+            debug!("  - APB5");
+            w.set_ppre5(config.apb5);
+        }
+    });
+    let cpuclk = match config.cpu {
+        CpuClk::Hsi => unwrap!(input.hsi),
+        CpuClk::Msi => unwrap!(input.msi),
+        CpuClk::Hse => unwrap!(input.hse),
+        CpuClk::Ic1 { .. } => todo!(),
+    };
+    let sysclk = match config.sys {
+        SysClk::Hsi => unwrap!(input.hsi),
+        SysClk::Msi => unwrap!(input.msi),
+        SysClk::Hse => unwrap!(input.hse),
+        SysClk::Ic2 { .. } => todo!(),
+    };
+    let timpre: u32 = match RCC.cfgr2().read().timpre() {
+        Timpre::DIV1 => 1,
+        Timpre::DIV2 => 2,
+        Timpre::DIV4 => 4,
+        Timpre::_RESERVED_3 => 8,
+    };
+    let hpre = periph_prescaler_to_value(config.ahb.to_bits());
+    let ppre1 = periph_prescaler_to_value(config.apb1.to_bits());
+    let ppre2 = periph_prescaler_to_value(config.apb2.to_bits());
+    let ppre4 = periph_prescaler_to_value(config.apb4.to_bits());
+    let ppre5 = periph_prescaler_to_value(config.apb5.to_bits());
+    // enable all peripherals in sleep mode
+    enable_low_power_peripherals();
+    // enable interrupts
+    unsafe {
+        core::arch::asm!("cpsie i");
+    }
+    ClocksOutput {
+        sysclk,
+        cpuclk,
+        pclk_tim: sysclk / timpre,
+        ahb: Hertz(sysclk.0 / hpre as u32),
+        apb1: sysclk / hpre / ppre1,
+        apb2: sysclk / hpre / ppre2,
+        apb4: sysclk / hpre / ppre4,
+        apb5: sysclk / hpre / ppre5,
+    }
+}
+fn enable_low_power_peripherals() {
+    // AHB1-5
+    RCC.ahb1lpenr().modify(|w| {
+        w.set_adc12lpen(true);
+        w.set_gpdma1lpen(true);
+    });
+    RCC.ahb2lpenr().modify(|w| {
+        w.set_adf1lpen(true);
+        w.set_mdf1lpen(true);
+        w.set_ramcfglpen(true);
+    });
+    RCC.ahb3lpenr().modify(|w| {
+        w.set_risaflpen(true);
+        w.set_iaclpen(true);
+        w.set_rifsclpen(true);
+        w.set_pkalpen(true);
+        w.set_saeslpen(true);
+        w.set_cryplpen(true);
+        w.set_hashlpen(true);
+        w.set_rnglpen(true);
+    });
+    RCC.ahb4lpenr().modify(|w| {
+        w.set_crclpen(true);
+        w.set_pwrlpen(true);
+        w.set_gpioqlpen(true);
+        w.set_gpioplpen(true);
+        w.set_gpioolpen(true);
+        w.set_gpionlpen(true);
+        w.set_gpiohlpen(true);
+        w.set_gpioglpen(true);
+        w.set_gpioflpen(true);
+        w.set_gpioelpen(true);
+        w.set_gpiodlpen(true);
+        w.set_gpioclpen(true);
+        w.set_gpioblpen(true);
+        w.set_gpioalpen(true);
+    });
+    RCC.ahb5lpenr().modify(|w| {
+        w.set_npulpen(true);
+        w.set_npucachelpen(true);
+        w.set_otg2lpen(true);
+        w.set_otgphy2lpen(true);
+        w.set_otgphy1lpen(true);
+        w.set_otg1lpen(true);
+        w.set_eth1lpen(true);
+        w.set_eth1rxlpen(true);
+        w.set_eth1txlpen(true);
+        w.set_eth1maclpen(true);
+        w.set_gpulpen(true);
+        w.set_gfxmmulpen(true);
+        w.set_mce4lpen(true);
+        w.set_xspi3lpen(true);
+        w.set_mce3lpen(true);
+        w.set_mce2lpen(true);
+        w.set_mce1lpen(true);
+        w.set_xspimlpen(true);
+        w.set_xspi2lpen(true);
+        w.set_sdmmc1lpen(true);
+        w.set_sdmmc2lpen(true);
+        w.set_pssilpen(true);
+        w.set_xspi1lpen(true);
+        w.set_fmclpen(true);
+        w.set_jpeglpen(true);
+        w.set_dma2dlpen(true);
+        w.set_hpdma1lpen(true);
+    });
+    // APB1-5
+    RCC.apb1llpenr().modify(|w| {
+        w.set_uart8lpen(true);
+        w.set_uart7lpen(true);
+        w.set_i3c2lpen(true);
+        w.set_i3c1lpen(true);
+        w.set_i2c3lpen(true);
+        w.set_i2c2lpen(true);
+        w.set_i2c1lpen(true);
+        w.set_uart5lpen(true);
+        w.set_uart4lpen(true);
+        w.set_usart3lpen(true);
+        w.set_usart2lpen(true);
+        w.set_spdifrx1lpen(true);
+        w.set_spi3lpen(true);
+        w.set_spi2lpen(true);
+        w.set_tim11lpen(true);
+        w.set_tim10lpen(true);
+        w.set_wwdglpen(true);
+        w.set_lptim1lpen(true);
+        w.set_tim14lpen(true);
+        w.set_tim13lpen(true);
+        w.set_tim12lpen(true);
+        w.set_tim7lpen(true);
+        w.set_tim6lpen(true);
+        w.set_tim5lpen(true);
+        w.set_tim4lpen(true);
+        w.set_tim3lpen(true);
+        w.set_tim2lpen(true);
+    });
+    RCC.apb1hlpenr().modify(|w| {
+        w.set_ucpd1lpen(true);
+        w.set_fdcanlpen(true);
+        w.set_mdioslpen(true);
+    });
+    RCC.apb2lpenr().modify(|w| {
+        w.set_sai2lpen(true);
+        w.set_sai1lpen(true);
+        w.set_spi5lpen(true);
+        w.set_tim9lpen(true);
+        w.set_tim17lpen(true);
+        w.set_tim16lpen(true);
+        w.set_tim15lpen(true);
+        w.set_tim18lpen(true);
+        w.set_spi4lpen(true);
+        w.set_spi1lpen(true);
+        w.set_usart10lpen(true);
+        w.set_uart9lpen(true);
+        w.set_usart6lpen(true);
+        w.set_usart1lpen(true);
+        w.set_tim8lpen(true);
+        w.set_tim1lpen(true);
+    });
+    RCC.apb3lpenr().modify(|w| {
+        w.set_dftlpen(true);
+    });
+    RCC.apb4llpenr().modify(|w| {
+        w.set_rtcapblpen(true);
+        w.set_rtclpen(true);
+        w.set_vrefbuflpen(true);
+        w.set_lptim5lpen(true);
+        w.set_lptim4lpen(true);
+        w.set_lptim3lpen(true);
+        w.set_lptim2lpen(true);
+        w.set_i2c4lpen(true);
+        w.set_spi6lpen(true);
+        w.set_lpuart1lpen(true);
+        w.set_hdplpen(true);
+    });
+    RCC.apb4hlpenr().modify(|w| {
+        w.set_dtslpen(true);
+        w.set_bseclpen(true);
+        w.set_syscfglpen(true);
+    });
+    RCC.apb5lpenr().modify(|w| {
+        w.set_csilpen(true);
+        w.set_venclpen(true);
+        w.set_gfxtimlpen(true);
+        w.set_dcmilpen(true);
+        w.set_ltdclpen(true);
+    });
+    RCC.buslpenr().modify(|w| {
+        w.set_aclknclpen(true);
+        w.set_aclknlpen(true);
+    });
+    RCC.memlpenr().modify(|w| {
+        w.set_bootromlpen(true);
+        w.set_vencramlpen(true);
+        w.set_npucacheramlpen(true);
+        w.set_flexramlpen(true);
+        w.set_axisram2lpen(true);
+        w.set_axisram1lpen(true);
+        w.set_bkpsramlpen(true);
+        w.set_ahbsram2lpen(true);
+        w.set_ahbsram1lpen(true);
+        w.set_axisram6lpen(true);
+        w.set_axisram5lpen(true);
+        w.set_axisram4lpen(true);
+        w.set_axisram3lpen(true);
+    });
+    RCC.misclpenr().modify(|w| {
+        w.set_perlpen(true);
+        w.set_xspiphycomplpen(true);
+        w.set_dbglpen(true);
+    });
+}
+const fn periph_prescaler_to_value(bits: u8) -> u8 {
+    match bits {
+        0 => 1,
+        1 => 2,
+        2 => 4,
+        3 => 8,
+        4 => 16,
+        5 => 32,
+        6 => 64,
+        7.. => 128,
+    }
+}
+fn pll_source_ready(source: u8) -> bool {
+    match source {
+        0x0 if !RCC.sr().read().pllrdy(0) && !RCC.pllcfgr1(0).read().pllbyp() => false,
+        0x1 if !RCC.sr().read().pllrdy(1) && !RCC.pllcfgr1(1).read().pllbyp() => false,
+        0x2 if !RCC.sr().read().pllrdy(2) && !RCC.pllcfgr1(2).read().pllbyp() => false,
+        0x3 if !RCC.sr().read().pllrdy(3) && !RCC.pllcfgr1(3).read().pllbyp() => false,
+        _ => true,
+    }
+}
+fn pll_sources_ready(source1: u8, source2: u8) -> bool {
+    pll_source_ready(source1) && pll_source_ready(source2)
+}
+impl Default for Config {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+fn power_supply_config(supply_config: SupplyConfig) {
+    // power supply config
+    PWR.cr1().modify(|w| {
+        w.set_sden(match supply_config {
+            SupplyConfig::External => false,
+            SupplyConfig::Smps => true,
+        });
+    });
+    // Validate supply configuration
+    while !PWR.voscr().read().actvosrdy() {}
+}
+struct PllInput {
+    hsi: Option<Hertz>,
+    msi: Option<Hertz>,
+    hse: Option<Hertz>,
+    i2s_ckin: Option<Hertz>,
+}
+#[derive(Clone, Copy, Default)]
+#[allow(dead_code)]
+struct PllOutput {
+    divm: Option<Hertz>,
+    divn: Option<Hertz>,
+    divp1: Option<Hertz>,
+    divp2: Option<Hertz>,
+    output: Option<Hertz>,
+}
+fn init_pll(pll_config: Option<Pll>, pll_index: usize, input: &PllInput) -> PllOutput {
+    let cfgr1 = RCC.pllcfgr1(pll_index);
+    let cfgr2 = RCC.pllcfgr2(pll_index);
+    let cfgr3 = RCC.pllcfgr3(pll_index);
+    match pll_config {
+        Some(Pll::Oscillator {
+            source,
+            divm,
+            fractional,
+            divn,
+            divp1,
+            divp2,
+        }) => {
+            // ensure pll is disabled
+            RCC.ccr().write(|w| w.set_pllonc(pll_index, true));
+            while RCC.sr().read().pllrdy(pll_index) {}
+            // ensure PLLxMODSSDIS=1 to work in fractional mode
+            cfgr3.modify(|w| w.set_pllmodssdis(Pllmodssdis::FRACTIONAL_DIVIDE));
+            // clear bypass mode
+            cfgr1.modify(|w| w.set_pllbyp(false));
+            // configure the pll clock source, mul and div factors
+            cfgr1.modify(|w| {
+                w.set_pllsel(source);
+                w.set_plldivm(divm);
+                w.set_plldivn(divn);
+            });
+            let in_clk = match source {
+                Pllsel::HSI => unwrap!(input.hsi),
+                Pllsel::MSI => unwrap!(input.msi),
+                Pllsel::HSE => unwrap!(input.hse),
+                Pllsel::I2S_CKIN => unwrap!(input.i2s_ckin),
+                _ => panic!("reserved PLL source not allowed"),
+            };
+            let m = divm.to_bits() as u32;
+            let n = divn as u32;
+            cfgr3.modify(|w| {
+                w.set_pllpdiv1(divp1);
+                w.set_pllpdiv2(divp2);
+            });
+            let p1 = divp1.to_bits() as u32;
+            let p2 = divp2.to_bits() as u32;
+            // configure pll divnfrac
+            cfgr2.modify(|w| w.set_plldivnfrac(fractional));
+            // clear pllxmoddsen
+            cfgr3.modify(|w| w.set_pllmoddsen(false));
+            // fractional mode
+            if fractional != 0 {
+                cfgr3.modify(|w| {
+                    w.set_pllmoddsen(true);
+                    w.set_plldacen(true);
+                })
+            }
+            // enable pll post divider output
+            cfgr3.modify(|w| {
+                w.set_pllmodssrst(true);
+                w.set_pllpdiven(true);
+            });
+            // enable the pll
+            RCC.csr().write(|w| w.pllons(pll_index));
+            // wait until ready
+            while RCC.sr().read().pllrdy(pll_index) {}
+            PllOutput {
+                divm: Some(Hertz(m)),
+                divn: Some(Hertz(n)),
+                divp1: Some(Hertz(p1)),
+                divp2: Some(Hertz(p2)),
+                output: Some(Hertz(in_clk.0 / m / n / p1 / p2)),
+            }
+        }
+        Some(Pll::Bypass { source }) => {
+            // check if source is ready
+            if !pll_source_ready(source.to_bits()) {
+                panic!("PLL source is not ready")
+            }
+            // ensure pll is disabled
+            RCC.ccr().write(|w| w.set_pllonc(pll_index, true));
+            while RCC.sr().read().pllrdy(pll_index) {}
+            cfgr1.modify(|w| {
+                w.set_pllbyp(true);
+                w.set_pllsel(source);
+            });
+            let in_clk = match source {
+                Pllsel::HSI => unwrap!(input.hsi),
+                Pllsel::MSI => unwrap!(input.msi),
+                Pllsel::HSE => unwrap!(input.hse),
+                Pllsel::I2S_CKIN => unwrap!(input.i2s_ckin),
+                _ => panic!("reserved PLL source not allowed"),
+            };
+            PllOutput {
+                output: Some(in_clk),
+                ..Default::default()
+            }
+        }
+        None => {
+            cfgr3.modify(|w| w.set_pllpdiven(false));
+            RCC.ccr().write(|w| w.set_pllonc(pll_index, true));
+            // wait till disabled
+            while RCC.sr().read().pllrdy(pll_index) {}
+            // clear bypass mode
+            cfgr1.modify(|w| w.set_pllbyp(false));
+            PllOutput::default()
+        }
+    }
+}
+#[allow(dead_code)]
+struct OscOutput {
+    hsi: Option<Hertz>,
+    hse: Option<Hertz>,
+    msi: Option<Hertz>,
+    lsi: Option<Hertz>,
+    lse: Option<Hertz>,
+    pll1: Option<Hertz>,
+    pll2: Option<Hertz>,
+    pll3: Option<Hertz>,
+    pll4: Option<Hertz>,
+    ic1sel: Icsel,
+    ic2sel: Icsel,
+    ic6sel: Icsel,
+    ic11sel: Icsel,
+}
+fn init_osc(config: Config) -> OscOutput {
+    let (cpu_src, sys_src) = {
+        let reg = RCC.cfgr().read();
+        (reg.cpusws(), reg.syssws())
+    };
+    let pll1_src = RCC.pllcfgr1(0).read().pllsel();
+    let pll2_src = RCC.pllcfgr1(1).read().pllsel();
+    let pll3_src = RCC.pllcfgr1(2).read().pllsel();
+    let pll4_src = RCC.pllcfgr1(3).read().pllsel();
+    let rcc_sr = RCC.sr().read();
+    debug!("configuring HSE");
+    // hse configuration
+    let hse = if let Some(hse) = config.hse {
+        match hse.mode {
+            HseMode::Oscillator => {
+                debug!("HSE in oscillator mode");
+            }
+            HseMode::Bypass => {
+                debug!("HSE in bypass mode");
+                RCC.hsecfgr().modify(|w| {
+                    w.set_hsebyp(true);
+                    w.set_hseext(Hseext::ANALOG);
+                });
+            }
+            HseMode::BypassDigital => {
+                debug!("HSE in bypass digital mode");
+                RCC.hsecfgr().modify(|w| {
+                    w.set_hsebyp(true);
+                    w.set_hseext(Hseext::DIGITAL);
+                });
+            }
+        }
+        RCC.csr().write(|w| w.set_hseons(true));
+        // wait until the hse is ready
+        while !RCC.sr().read().hserdy() {}
+        Some(hse.freq)
+    } else if cpu_src == Cpusws::HSE
+        || sys_src == Syssws::HSE
+        || (pll1_src == Pllsel::HSE && rcc_sr.pllrdy(0))
+        || (pll2_src == Pllsel::HSE && rcc_sr.pllrdy(1))
+        || (pll3_src == Pllsel::HSE && rcc_sr.pllrdy(2))
+        || (pll4_src == Pllsel::HSE && rcc_sr.pllrdy(3))
+    {
+        panic!(
+            "When the HSE is used as cpu/system bus clock or clock source for any PLL, it is not allowed to be disabled"
+        );
+    } else {
+        debug!("HSE off");
+        RCC.ccr().write(|w| w.set_hseonc(true));
+        RCC.hsecfgr().modify(|w| {
+            w.set_hseext(Hseext::ANALOG);
+            w.set_hsebyp(false);
+        });
+        // wait until the hse is disabled
+        while RCC.sr().read().hserdy() {}
+        None
+    };
+    // hsi configuration
+    debug!("configuring HSI");
+    let hsi = if let Some(hsi) = config.hsi {
+        RCC.csr().write(|w| w.set_hsions(true));
+        while !RCC.sr().read().hsirdy() {}
+        // set divider and calibration
+        RCC.hsicfgr().modify(|w| {
+            w.set_hsidiv(hsi.pre);
+            w.set_hsitrim(hsi.trim);
+        });
+        Some(HSI_FREQ / hsi.pre)
+    } else if cpu_src == Cpusws::HSI
+        || sys_src == Syssws::HSI
+        || (pll1_src == Pllsel::HSI && rcc_sr.pllrdy(0))
+        || (pll2_src == Pllsel::HSI && rcc_sr.pllrdy(1))
+        || (pll3_src == Pllsel::HSI && rcc_sr.pllrdy(2))
+        || (pll4_src == Pllsel::HSI && rcc_sr.pllrdy(3))
+    {
+        panic!(
+            "When the HSI is used as cpu/system bus clock or clock source for any PLL, it is not allowed to be disabled"
+        );
+    } else {
+        debug!("HSI off");
+        RCC.ccr().write(|w| w.set_hsionc(true));
+        while RCC.sr().read().hsirdy() {}
+        None
+    };
+    // msi configuration
+    debug!("configuring MSI");
+    let msi = if let Some(msi) = config.msi {
+        RCC.msicfgr().modify(|w| w.set_msifreqsel(msi.freq));
+        RCC.csr().write(|w| w.set_msions(true));
+        while !RCC.sr().read().msirdy() {}
+        RCC.msicfgr().modify(|w| w.set_msitrim(msi.trim));
+        Some(match msi.freq {
+            Msifreqsel::_4MHZ => Hertz::mhz(4),
+            Msifreqsel::_16MHZ => Hertz::mhz(16),
+        })
+    } else if cpu_src == Cpusws::MSI
+        || sys_src == Syssws::MSI
+        || (pll1_src == Pllsel::MSI && rcc_sr.pllrdy(0))
+        || (pll2_src == Pllsel::MSI && rcc_sr.pllrdy(1))
+        || (pll3_src == Pllsel::MSI && rcc_sr.pllrdy(2))
+        || (pll4_src == Pllsel::MSI && rcc_sr.pllrdy(3))
+    {
+        panic!(
+            "When the MSI is used as cpu/system bus clock or clock source for any PLL, it is not allowed to be disabled"
+        );
+    } else {
+        RCC.ccr().write(|w| w.set_msionc(true));
+        while RCC.sr().read().msirdy() {}
+        None
+    };
+    // lsi configuration
+    debug!("configuring LSI");
+    let lsi = if config.lsi {
+        RCC.csr().write(|w| w.set_lsions(true));
+        while !RCC.sr().read().lsirdy() {}
+        Some(super::LSI_FREQ)
+    } else {
+        RCC.ccr().write(|w| w.set_lsionc(true));
+        while RCC.sr().read().lsirdy() {}
+        None
+    };
+    // lse configuration
+    debug!("configuring LSE");
+    let lse = if config.lse {
+        RCC.csr().write(|w| w.set_lseons(true));
+        while !RCC.sr().read().lserdy() {}
+        Some(LSE_FREQ)
+    } else {
+        RCC.ccr().write(|w| w.set_lseonc(true));
+        while RCC.sr().read().lserdy() {}
+        None
+    };
+    let pll_input = PllInput {
+        hse,
+        msi,
+        hsi,
+        i2s_ckin: None,
+    };
+    // pll1,2,3,4 config
+    let pll_configs = [config.pll1, config.pll2, config.pll3, config.pll4];
+    let mut pll_outputs: [PllOutput; 4] = [PllOutput::default(); 4];
+    let ic1_src = RCC.iccfgr(0).read().icsel();
+    let ic2_src = RCC.iccfgr(1).read().icsel();
+    let ic6_src = RCC.iccfgr(5).read().icsel();
+    let ic11_src = RCC.iccfgr(10).read().icsel();
+    for (n, (&pll, out)) in pll_configs.iter().zip(pll_outputs.iter_mut()).enumerate() {
+        debug!("configuring PLL{}", n + 1);
+        let pll_ready = RCC.sr().read().pllrdy(n);
+        if is_new_pll_config(pll, 0) {
+            let this_pll = Icsel::from_bits(n as u8);
+            if cpu_src == Cpusws::IC1 && ic1_src == this_pll {
+                panic!("PLL should not be disabled / reconfigured if used for IC1 (cpuclksrc)")
+            }
+            if sys_src == Syssws::IC2 && (ic2_src == this_pll || ic6_src == this_pll || ic11_src == this_pll) {
+                panic!("PLL should not be disabled / reconfigured if used for IC2, IC6 or IC11 (sysclksrc)")
+            }
+            *out = init_pll(pll, 0, &pll_input);
+        } else if pll.is_some() && !pll_ready {
+            RCC.csr().write(|w| w.pllons(n));
+            while !RCC.sr().read().pllrdy(n) {}
+        }
+    }
+    OscOutput {
+        hsi,
+        hse,
+        msi,
+        lsi,
+        lse,
+        pll1: pll_outputs[0].output,
+        pll2: pll_outputs[1].output,
+        pll3: pll_outputs[2].output,
+        pll4: pll_outputs[3].output,
+        ic1sel: ic1_src,
+        ic2sel: ic2_src,
+        ic6sel: ic6_src,
+        ic11sel: ic11_src,
+    }
+}
+fn is_new_pll_config(pll: Option<Pll>, pll_index: usize) -> bool {
+    let cfgr1 = RCC.pllcfgr1(pll_index).read();
+    let cfgr2 = RCC.pllcfgr2(pll_index).read();
+    let cfgr3 = RCC.pllcfgr3(pll_index).read();
+    let ready = RCC.sr().read().pllrdy(pll_index);
+    let bypass = cfgr1.pllbyp();
+    match (pll, ready, bypass) {
+        (None, true, _) => return true,
+        (Some(_), false, _) => return true,
+        (Some(conf), true, bypass) => match (conf, bypass) {
+            (Pll::Bypass { .. }, false) => return true,
+            (Pll::Oscillator { .. }, true) => return true,
+            _ => {}
+        },
+        _ => {}
+    }
+    match pll {
+        Some(Pll::Bypass { source }) => cfgr1.pllsel() != source,
+        Some(Pll::Oscillator {
+            source,
+            divm: m,
+            fractional,
+            divn: n,
+            divp1: p1,
+            divp2: p2,
+        }) => {
+            cfgr1.pllsel() != source
+                || cfgr1.plldivm() != m
+                || cfgr1.plldivn() != n
+                || cfgr2.plldivnfrac() != fractional
+                || cfgr3.pllpdiv1() != p1
+                || cfgr3.pllpdiv2() != p2
+        }
+        None => false,
+    }
+}
+pub(crate) unsafe fn init(config: Config) {
+    debug!("enabling SYSCFG");
+    // system configuration setup
+    RCC.apb4hensr().write(|w| w.set_syscfgens(true));
+    // delay after RCC peripheral clock enabling
+    RCC.apb4hensr().read();
+    debug!("setting VTOR");
+    let vtor = unsafe {
+        let p = cortex_m::Peripherals::steal();
+        p.SCB.vtor.read()
+    };
+    // set default vector table location after reset or standby
+    SYSCFG.initsvtorcr().write(|w| w.set_svtor_addr(vtor));
+    // read back the value to ensure it is written before deactivating SYSCFG
+    SYSCFG.initsvtorcr().read();
+    debug!("deactivating SYSCFG");
+    // deactivate SYSCFG
+    RCC.apb4hensr().write(|w| w.set_syscfgens(false));
+    debug!("enabling FPU");
+    // enable fpu
+    unsafe {
+        let p = cortex_m::Peripherals::steal();
+        p.SCB.cpacr.modify(|w| w | (3 << 20) | (3 << 22));
+    }
+    debug!("setting power supply config");
+    power_supply_config(config.supply_config);
+    let osc = init_osc(config);
+    let clock_inputs = ClocksInput {
+        hsi: osc.hsi,
+        msi: osc.msi,
+        hse: osc.hse,
+    };
+    let clocks = init_clocks(config, &clock_inputs);
+    // TODO: sysb, sysc, sysd must have the same clock source
+    set_clocks!(
+        sys: Some(clocks.sysclk),
+        hsi: osc.hsi,
+        hsi_div: None,
+        hse: osc.hse,
+        msi: osc.msi,
+        hclk1: Some(clocks.ahb),
+        hclk2: Some(clocks.ahb),
+        hclk3: Some(clocks.ahb),
+        hclk4: Some(clocks.ahb),
+        hclk5: Some(clocks.ahb),
+        pclk1: Some(clocks.apb1),
+        pclk2: Some(clocks.apb2),
+        pclk1_tim: Some(clocks.pclk_tim),
+        pclk2_tim: Some(clocks.pclk_tim),
+        pclk4: Some(clocks.apb4),
+        pclk5: Some(clocks.apb5),
+        per: None,
+        rtc: None,
+        i2s_ckin: None,
+        ic8: None,
+        ic9: None,
+        ic14: None,
+        ic17: None,
+        ic20: None,
+    );
+}
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index 06315d7f3..c338b0fd4 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -309,7 +309,9 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
    /// Generate a sequence of PWM waveform
    ///
    /// Note:
-    /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
+    /// You will need to provide corresponding `TIMx_UP` DMA channel to use this method.
+    /// Also be aware that embassy timers use one of timers internally. It is possible to
+    /// switch this timer by using `time-driver-timX` feature.
    pub async fn waveform_up(&mut self, dma: Peri<'_, impl super::UpDma<T>>, channel: Channel, duty: &[u16]) {
        #[allow(clippy::let_unit_value)] // eg. stm32f334
        let req = dma.request();
@@ -339,14 +341,33 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
                ..Default::default()
            };
-            Transfer::new_write(
+            match self.inner.bits() {
-                dma,
+                TimerBits::Bits16 => {
-                req,
+                    Transfer::new_write(
-                duty,
+                        dma,
-                self.inner.regs_1ch().ccr(channel.index()).as_ptr() as *mut u16,
+                        req,
-                dma_transfer_option,
+                        duty,
-            )
+                        self.inner.regs_1ch().ccr(channel.index()).as_ptr() as *mut u16,
-            .await
+                        dma_transfer_option,
+                    )
+                    .await
+                }
+                #[cfg(not(any(stm32l0)))]
+                TimerBits::Bits32 => {
+                    #[cfg(not(any(bdma, gpdma)))]
+                    panic!("unsupported timer bits");
+                    #[cfg(any(bdma, gpdma))]
+                    Transfer::new_write(
+                        dma,
+                        req,
+                        duty,
+                        self.inner.regs_1ch().ccr(channel.index()).as_ptr() as *mut u32,
+                        dma_transfer_option,
+                    )
+                    .await
+                }
+            };
        };
        // restore output compare state
@@ -378,18 +399,23 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
    ///
    /// For example, if using channels 1 through 4, a buffer of 4 update steps might look like:
    ///
+    /// ```rust,ignore
    /// let dma_buf: [u16; 16] = [
    ///     ch1_duty_1, ch2_duty_1, ch3_duty_1, ch4_duty_1, // update 1
    ///     ch1_duty_2, ch2_duty_2, ch3_duty_2, ch4_duty_2, // update 2
    ///     ch1_duty_3, ch2_duty_3, ch3_duty_3, ch4_duty_3, // update 3
    ///     ch1_duty_4, ch2_duty_4, ch3_duty_4, ch4_duty_4, // update 4
    /// ];
+    /// ```
    ///
-    /// Each group of N values (where N = number of channels) is transferred on one update event,
+    /// Each group of `N` values (where `N` is number of channels) is transferred on one update event,
    /// updating the duty cycles of all selected channels simultaneously.
    ///
    /// Note:
-    /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
+    /// You will need to provide corresponding `TIMx_UP` DMA channel to use this method.
+    /// Also be aware that embassy timers use one of timers internally. It is possible to
+    /// switch this timer by using `time-driver-timX` feature.
+    ///
    pub async fn waveform_up_multi_channel(
        &mut self,
        dma: Peri<'_, impl super::UpDma<T>>,
diff --git a/embassy-stm32/src/ucpd.rs b/embassy-stm32/src/ucpd.rs
index 8f259a917..ae86d28f0 100644
--- a/embassy-stm32/src/ucpd.rs
+++ b/embassy-stm32/src/ucpd.rs
@@ -32,7 +32,7 @@ use crate::{Peri, interrupt};
 pub(crate) fn init(
    _cs: critical_section::CriticalSection,
-    #[cfg(peri_ucpd1)] ucpd1_db_enable: bool,
+    #[cfg(all(peri_ucpd1, not(stm32n6)))] ucpd1_db_enable: bool,
    #[cfg(peri_ucpd2)] ucpd2_db_enable: bool,
 ) {
    #[cfg(stm32g0x1)]
@@ -349,6 +349,7 @@ impl<'d, T: Instance> CcPhy<'d, T> {
        critical_section::with(|cs| {
            init(
                cs,
+                #[cfg(not(stm32n6))]
                false,
                #[cfg(peri_ucpd2)]
                false,
diff --git a/embassy-usb/CHANGELOG.md b/embassy-usb/CHANGELOG.md
index 0a30bc24b..cfb1bf021 100644
--- a/embassy-usb/CHANGELOG.md
+++ b/embassy-usb/CHANGELOG.md
@@ -8,6 +8,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 <!-- next-header -->
 ## Unreleased - ReleaseDate
+- Add support for USB HID Boot Protocol Mode 
 ## 0.5.1 - 2025-08-26
 ## 0.5.0 - 2025-07-16
diff --git a/embassy-usb/src/class/hid.rs b/embassy-usb/src/class/hid.rs
index 182e1f83f..64e8fd59f 100644
--- a/embassy-usb/src/class/hid.rs
+++ b/embassy-usb/src/class/hid.rs
@@ -15,8 +15,6 @@ use crate::types::InterfaceNumber;
 use crate::{Builder, Handler};
 const USB_CLASS_HID: u8 = 0x03;
-const USB_SUBCLASS_NONE: u8 = 0x00;
-const USB_PROTOCOL_NONE: u8 = 0x00;
 // HID
 const HID_DESC_DESCTYPE_HID: u8 = 0x21;
@@ -31,6 +29,52 @@ const HID_REQ_SET_REPORT: u8 = 0x09;
 const HID_REQ_GET_PROTOCOL: u8 = 0x03;
 const HID_REQ_SET_PROTOCOL: u8 = 0x0b;
+/// Get/Set Protocol mapping
+/// See (7.2.5 and 7.2.6): <https://www.usb.org/sites/default/files/hid1_11.pdf>
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[repr(u8)]
+pub enum HidProtocolMode {
+    /// Hid Boot Protocol Mode
+    Boot = 0,
+    /// Hid Report Protocol Mode
+    Report = 1,
+}
+impl From<u8> for HidProtocolMode {
+    fn from(mode: u8) -> HidProtocolMode {
+        if mode == HidProtocolMode::Boot as u8 {
+            HidProtocolMode::Boot
+        } else {
+            HidProtocolMode::Report
+        }
+    }
+}
+/// USB HID interface subclass values.
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[repr(u8)]
+pub enum HidSubclass {
+    /// No subclass, standard HID device.
+    No = 0,
+    /// Boot interface subclass, supports BIOS boot protocol.
+    Boot = 1,
+}
+/// USB HID protocol values.
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[repr(u8)]
+pub enum HidBootProtocol {
+    /// No boot protocol.
+    None = 0,
+    /// Keyboard boot protocol.
+    Keyboard = 1,
+    /// Mouse boot protocol.
+    Mouse = 2,
+}
 /// Configuration for the HID class.
 pub struct Config<'d> {
    /// HID report descriptor.
@@ -48,6 +92,12 @@ pub struct Config<'d> {
    /// Max packet size for both the IN and OUT endpoints.
    pub max_packet_size: u16,
+    /// The HID subclass of this interface
+    pub hid_subclass: HidSubclass,
+    /// The HID boot protocol of this interface
+    pub hid_boot_protocol: HidBootProtocol,
 }
 /// Report ID
@@ -109,10 +159,15 @@ fn build<'d, D: Driver<'d>>(
 ) -> (Option<D::EndpointOut>, D::EndpointIn, &'d AtomicUsize) {
    let len = config.report_descriptor.len();
-    let mut func = builder.function(USB_CLASS_HID, USB_SUBCLASS_NONE, USB_PROTOCOL_NONE);
+    let mut func = builder.function(USB_CLASS_HID, config.hid_subclass as u8, config.hid_boot_protocol as u8);
    let mut iface = func.interface();
    let if_num = iface.interface_number();
-    let mut alt = iface.alt_setting(USB_CLASS_HID, USB_SUBCLASS_NONE, USB_PROTOCOL_NONE, None);
+    let mut alt = iface.alt_setting(
+        USB_CLASS_HID,
+        config.hid_subclass as u8,
+        config.hid_boot_protocol as u8,
+        None,
+    );
    // HID descriptor
    alt.descriptor(
@@ -389,6 +444,23 @@ pub trait RequestHandler {
        OutResponse::Rejected
    }
+    /// Gets the current hid protocol.
+    ///
+    /// Returns `Report` protocol by default.
+    fn get_protocol(&self) -> HidProtocolMode {
+        HidProtocolMode::Report
+    }
+    /// Sets the current hid protocol to `protocol`.
+    ///
+    /// Accepts only `Report` protocol by default.
+    fn set_protocol(&mut self, protocol: HidProtocolMode) -> OutResponse {
+        match protocol {
+            HidProtocolMode::Report => OutResponse::Accepted,
+            HidProtocolMode::Boot => OutResponse::Rejected,
+        }
+    }
    /// Get the idle rate for `id`.
    ///
    /// If `id` is `None`, get the idle rate for all reports. Returning `None`
@@ -482,11 +554,14 @@ impl<'d> Handler for Control<'d> {
                _ => Some(OutResponse::Rejected),
            },
            HID_REQ_SET_PROTOCOL => {
-                if req.value == 1 {
+                let hid_protocol = HidProtocolMode::from(req.value as u8);
-                    Some(OutResponse::Accepted)
+                match (self.request_handler.as_mut(), hid_protocol) {
-                } else {
+                    (Some(request_handler), hid_protocol) => Some(request_handler.set_protocol(hid_protocol)),
-                    warn!("HID Boot Protocol is unsupported.");
+                    (None, HidProtocolMode::Report) => Some(OutResponse::Accepted),
-                    Some(OutResponse::Rejected) // UNSUPPORTED: Boot Protocol
+                    (None, HidProtocolMode::Boot) => {
+                        info!("Received request to switch to Boot protocol mode, but it is disabled by default.");
+                        Some(OutResponse::Rejected)
+                    }
                }
            }
            _ => Some(OutResponse::Rejected),
@@ -539,8 +614,12 @@ impl<'d> Handler for Control<'d> {
                        }
                    }
                    HID_REQ_GET_PROTOCOL => {
-                        // UNSUPPORTED: Boot Protocol
+                        if let Some(request_handler) = self.request_handler.as_mut() {
-                        buf[0] = 1;
+                            buf[0] = request_handler.get_protocol() as u8;
+                        } else {
+                            // Return `Report` protocol mode by default
+                            buf[0] = HidProtocolMode::Report as u8;
+                        }
                        Some(InResponse::Accepted(&buf[0..1]))
                    }
                    _ => Some(InResponse::Rejected),
diff --git a/examples/nrf52840/src/bin/gpiote_channel.rs b/examples/nrf52840/src/bin/gpiote_channel.rs
index c7ddc1d8d..e358779b2 100644
--- a/examples/nrf52840/src/bin/gpiote_channel.rs
+++ b/examples/nrf52840/src/bin/gpiote_channel.rs
@@ -12,10 +12,10 @@ async fn main(_spawner: Spawner) {
    let p = embassy_nrf::init(Default::default());
    info!("Starting!");
-    let ch1 = InputChannel::new(p.GPIOTE_CH0, p.P0_11, Pull::Up, InputChannelPolarity::HiToLo);
+    let mut ch1 = InputChannel::new(p.GPIOTE_CH0, p.P0_11, Pull::Up, InputChannelPolarity::HiToLo);
-    let ch2 = InputChannel::new(p.GPIOTE_CH1, p.P0_12, Pull::Up, InputChannelPolarity::LoToHi);
+    let mut ch2 = InputChannel::new(p.GPIOTE_CH1, p.P0_12, Pull::Up, InputChannelPolarity::LoToHi);
-    let ch3 = InputChannel::new(p.GPIOTE_CH2, p.P0_24, Pull::Up, InputChannelPolarity::Toggle);
+    let mut ch3 = InputChannel::new(p.GPIOTE_CH2, p.P0_24, Pull::Up, InputChannelPolarity::Toggle);
-    let ch4 = InputChannel::new(p.GPIOTE_CH3, p.P0_25, Pull::Up, InputChannelPolarity::Toggle);
+    let mut ch4 = InputChannel::new(p.GPIOTE_CH3, p.P0_25, Pull::Up, InputChannelPolarity::Toggle);
    let button1 = async {
        loop {
diff --git a/examples/nrf52840/src/bin/usb_hid_keyboard.rs b/examples/nrf52840/src/bin/usb_hid_keyboard.rs
index 1cd730503..7b7303526 100644
--- a/examples/nrf52840/src/bin/usb_hid_keyboard.rs
+++ b/examples/nrf52840/src/bin/usb_hid_keyboard.rs
@@ -1,7 +1,7 @@
 #![no_std]
 #![no_main]
-use core::sync::atomic::{AtomicBool, Ordering};
+use core::sync::atomic::{AtomicBool, AtomicU8, Ordering};
 use defmt::*;
 use embassy_executor::Spawner;
@@ -13,7 +13,9 @@ use embassy_nrf::usb::vbus_detect::HardwareVbusDetect;
 use embassy_nrf::{bind_interrupts, pac, peripherals, usb};
 use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_sync::signal::Signal;
-use embassy_usb::class::hid::{HidReaderWriter, ReportId, RequestHandler, State};
+use embassy_usb::class::hid::{
+    HidBootProtocol, HidProtocolMode, HidReaderWriter, HidSubclass, ReportId, RequestHandler, State,
+};
 use embassy_usb::control::OutResponse;
 use embassy_usb::{Builder, Config, Handler};
 use usbd_hid::descriptor::{KeyboardReport, SerializedDescriptor};
@@ -26,6 +28,8 @@ bind_interrupts!(struct Irqs {
 static SUSPENDED: AtomicBool = AtomicBool::new(false);
+static HID_PROTOCOL_MODE: AtomicU8 = AtomicU8::new(HidProtocolMode::Boot as u8);
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
    let p = embassy_nrf::init(Default::default());
@@ -45,6 +49,10 @@ async fn main(_spawner: Spawner) {
    config.max_power = 100;
    config.max_packet_size_0 = 64;
    config.supports_remote_wakeup = true;
+    config.composite_with_iads = false;
+    config.device_class = 0;
+    config.device_sub_class = 0;
+    config.device_protocol = 0;
    // Create embassy-usb DeviceBuilder using the driver and config.
    // It needs some buffers for building the descriptors.
@@ -74,6 +82,8 @@ async fn main(_spawner: Spawner) {
        request_handler: None,
        poll_ms: 60,
        max_packet_size: 64,
+        hid_subclass: HidSubclass::Boot,
+        hid_boot_protocol: HidBootProtocol::Keyboard,
    };
    let hid = HidReaderWriter::<_, 1, 8>::new(&mut builder, &mut state, config);
@@ -106,6 +116,11 @@ async fn main(_spawner: Spawner) {
            if SUSPENDED.load(Ordering::Acquire) {
                info!("Triggering remote wakeup");
                remote_wakeup.signal(());
+            } else if HID_PROTOCOL_MODE.load(Ordering::Relaxed) == HidProtocolMode::Boot as u8 {
+                match writer.write(&[0, 0, 4, 0, 0, 0, 0, 0]).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send boot report: {:?}", e),
+                };
            } else {
                let report = KeyboardReport {
                    keycodes: [4, 0, 0, 0, 0, 0],
@@ -121,16 +136,23 @@ async fn main(_spawner: Spawner) {
            button.wait_for_high().await;
            info!("RELEASED");
-            let report = KeyboardReport {
+            if HID_PROTOCOL_MODE.load(Ordering::Relaxed) == HidProtocolMode::Boot as u8 {
-                keycodes: [0, 0, 0, 0, 0, 0],
+                match writer.write(&[0, 0, 0, 0, 0, 0, 0, 0]).await {
-                leds: 0,
+                    Ok(()) => {}
-                modifier: 0,
+                    Err(e) => warn!("Failed to send boot report: {:?}", e),
-                reserved: 0,
+                };
-            };
+            } else {
-            match writer.write_serialize(&report).await {
+                let report = KeyboardReport {
-                Ok(()) => {}
+                    keycodes: [0, 0, 0, 0, 0, 0],
-                Err(e) => warn!("Failed to send report: {:?}", e),
+                    leds: 0,
-            };
+                    modifier: 0,
+                    reserved: 0,
+                };
+                match writer.write_serialize(&report).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send report: {:?}", e),
+                };
+            }
        }
    };
@@ -156,6 +178,18 @@ impl RequestHandler for MyRequestHandler {
        OutResponse::Accepted
    }
+    fn get_protocol(&self) -> HidProtocolMode {
+        let protocol = HidProtocolMode::from(HID_PROTOCOL_MODE.load(Ordering::Relaxed));
+        info!("The current HID protocol mode is: {}", protocol);
+        protocol
+    }
+    fn set_protocol(&mut self, protocol: HidProtocolMode) -> OutResponse {
+        info!("Switching to HID protocol mode: {}", protocol);
+        HID_PROTOCOL_MODE.store(protocol as u8, Ordering::Relaxed);
+        OutResponse::Accepted
+    }
    fn set_idle_ms(&mut self, id: Option<ReportId>, dur: u32) {
        info!("Set idle rate for {:?} to {:?}", id, dur);
    }
diff --git a/examples/nrf52840/src/bin/usb_hid_mouse.rs b/examples/nrf52840/src/bin/usb_hid_mouse.rs
index 3c0fc04e8..6bee4546b 100644
--- a/examples/nrf52840/src/bin/usb_hid_mouse.rs
+++ b/examples/nrf52840/src/bin/usb_hid_mouse.rs
@@ -1,6 +1,8 @@
 #![no_std]
 #![no_main]
+use core::sync::atomic::{AtomicU8, Ordering};
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_futures::join::join;
@@ -8,7 +10,9 @@ use embassy_nrf::usb::Driver;
 use embassy_nrf::usb::vbus_detect::HardwareVbusDetect;
 use embassy_nrf::{bind_interrupts, pac, peripherals, usb};
 use embassy_time::Timer;
-use embassy_usb::class::hid::{HidWriter, ReportId, RequestHandler, State};
+use embassy_usb::class::hid::{
+    HidBootProtocol, HidProtocolMode, HidSubclass, HidWriter, ReportId, RequestHandler, State,
+};
 use embassy_usb::control::OutResponse;
 use embassy_usb::{Builder, Config};
 use usbd_hid::descriptor::{MouseReport, SerializedDescriptor};
@@ -19,6 +23,8 @@ bind_interrupts!(struct Irqs {
    CLOCK_POWER => usb::vbus_detect::InterruptHandler;
 });
+static HID_PROTOCOL_MODE: AtomicU8 = AtomicU8::new(HidProtocolMode::Boot as u8);
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
    let p = embassy_nrf::init(Default::default());
@@ -37,6 +43,10 @@ async fn main(_spawner: Spawner) {
    config.serial_number = Some("12345678");
    config.max_power = 100;
    config.max_packet_size_0 = 64;
+    config.composite_with_iads = false;
+    config.device_class = 0;
+    config.device_sub_class = 0;
+    config.device_protocol = 0;
    // Create embassy-usb DeviceBuilder using the driver and config.
    // It needs some buffers for building the descriptors.
@@ -63,6 +73,8 @@ async fn main(_spawner: Spawner) {
        request_handler: Some(&mut request_handler),
        poll_ms: 60,
        max_packet_size: 8,
+        hid_subclass: HidSubclass::Boot,
+        hid_boot_protocol: HidBootProtocol::Mouse,
    };
    let mut writer = HidWriter::<_, 5>::new(&mut builder, &mut state, config);
@@ -80,16 +92,26 @@ async fn main(_spawner: Spawner) {
            Timer::after_millis(500).await;
            y = -y;
-            let report = MouseReport {
-                buttons: 0,
+            if HID_PROTOCOL_MODE.load(Ordering::Relaxed) == HidProtocolMode::Boot as u8 {
-                x: 0,
+                let buttons = 0u8;
-                y,
+                let x = 0i8;
-                wheel: 0,
+                match writer.write(&[buttons, x as u8, y as u8]).await {
-                pan: 0,
+                    Ok(()) => {}
-            };
+                    Err(e) => warn!("Failed to send boot report: {:?}", e),
-            match writer.write_serialize(&report).await {
+                }
-                Ok(()) => {}
+            } else {
-                Err(e) => warn!("Failed to send report: {:?}", e),
+                let report = MouseReport {
+                    buttons: 0,
+                    x: 0,
+                    y,
+                    wheel: 0,
+                    pan: 0,
+                };
+                match writer.write_serialize(&report).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send report: {:?}", e),
+                }
            }
        }
    };
@@ -112,6 +134,18 @@ impl RequestHandler for MyRequestHandler {
        OutResponse::Accepted
    }
+    fn get_protocol(&self) -> HidProtocolMode {
+        let protocol = HidProtocolMode::from(HID_PROTOCOL_MODE.load(Ordering::Relaxed));
+        info!("The current HID protocol mode is: {}", protocol);
+        protocol
+    }
+    fn set_protocol(&mut self, protocol: HidProtocolMode) -> OutResponse {
+        info!("Switching to HID protocol mode: {}", protocol);
+        HID_PROTOCOL_MODE.store(protocol as u8, Ordering::Relaxed);
+        OutResponse::Accepted
+    }
    fn set_idle_ms(&mut self, id: Option<ReportId>, dur: u32) {
        info!("Set idle rate for {:?} to {:?}", id, dur);
    }
diff --git a/examples/nrf5340/src/bin/gpiote_channel.rs b/examples/nrf5340/src/bin/gpiote_channel.rs
index a085310ce..41ee732c3 100644
--- a/examples/nrf5340/src/bin/gpiote_channel.rs
+++ b/examples/nrf5340/src/bin/gpiote_channel.rs
@@ -12,10 +12,10 @@ async fn main(_spawner: Spawner) {
    let p = embassy_nrf::init(Default::default());
    info!("Starting!");
-    let ch1 = InputChannel::new(p.GPIOTE_CH0, p.P0_23, Pull::Up, InputChannelPolarity::HiToLo);
+    let mut ch1 = InputChannel::new(p.GPIOTE_CH0, p.P0_23, Pull::Up, InputChannelPolarity::HiToLo);
-    let ch2 = InputChannel::new(p.GPIOTE_CH1, p.P0_24, Pull::Up, InputChannelPolarity::LoToHi);
+    let mut ch2 = InputChannel::new(p.GPIOTE_CH1, p.P0_24, Pull::Up, InputChannelPolarity::LoToHi);
-    let ch3 = InputChannel::new(p.GPIOTE_CH2, p.P0_08, Pull::Up, InputChannelPolarity::Toggle);
+    let mut ch3 = InputChannel::new(p.GPIOTE_CH2, p.P0_08, Pull::Up, InputChannelPolarity::Toggle);
-    let ch4 = InputChannel::new(p.GPIOTE_CH3, p.P0_09, Pull::Up, InputChannelPolarity::Toggle);
+    let mut ch4 = InputChannel::new(p.GPIOTE_CH3, p.P0_09, Pull::Up, InputChannelPolarity::Toggle);
    let button1 = async {
        loop {
diff --git a/examples/nrf54l15/memory.x b/examples/nrf54l15/memory.x
index 1064c8a5c..332200828 100644
--- a/examples/nrf54l15/memory.x
+++ b/examples/nrf54l15/memory.x
@@ -1,5 +1,5 @@
 MEMORY
 {
-  FLASH : ORIGIN = 0x00000000, LENGTH = 1536K
+  FLASH : ORIGIN = 0x00000000, LENGTH = 1524K
  RAM : ORIGIN = 0x20000000, LENGTH = 256K
 }
diff --git a/examples/nrf54l15/src/bin/gpiote_channel.rs b/examples/nrf54l15/src/bin/gpiote_channel.rs
index 6333250ba..cac8823f8 100644
--- a/examples/nrf54l15/src/bin/gpiote_channel.rs
+++ b/examples/nrf54l15/src/bin/gpiote_channel.rs
@@ -12,10 +12,10 @@ async fn main(_spawner: Spawner) {
    let p = embassy_nrf::init(Default::default());
    info!("Starting!");
-    let ch1 = InputChannel::new(p.GPIOTE20_CH0, p.P1_13, Pull::Up, InputChannelPolarity::HiToLo);
+    let mut ch1 = InputChannel::new(p.GPIOTE20_CH0, p.P1_13, Pull::Up, InputChannelPolarity::HiToLo);
-    let ch2 = InputChannel::new(p.GPIOTE20_CH1, p.P1_09, Pull::Up, InputChannelPolarity::LoToHi);
+    let mut ch2 = InputChannel::new(p.GPIOTE20_CH1, p.P1_09, Pull::Up, InputChannelPolarity::LoToHi);
-    let ch3 = InputChannel::new(p.GPIOTE20_CH2, p.P1_08, Pull::Up, InputChannelPolarity::Toggle);
+    let mut ch3 = InputChannel::new(p.GPIOTE20_CH2, p.P1_08, Pull::Up, InputChannelPolarity::Toggle);
-    let ch4 = InputChannel::new(p.GPIOTE30_CH0, p.P0_04, Pull::Up, InputChannelPolarity::Toggle);
+    let mut ch4 = InputChannel::new(p.GPIOTE30_CH0, p.P0_04, Pull::Up, InputChannelPolarity::Toggle);
    let button1 = async {
        loop {
diff --git a/examples/rp/src/bin/usb_hid_keyboard.rs b/examples/rp/src/bin/usb_hid_keyboard.rs
index a7cb322d8..2f6d169bf 100644
--- a/examples/rp/src/bin/usb_hid_keyboard.rs
+++ b/examples/rp/src/bin/usb_hid_keyboard.rs
@@ -1,7 +1,7 @@
 #![no_std]
 #![no_main]
-use core::sync::atomic::{AtomicBool, Ordering};
+use core::sync::atomic::{AtomicBool, AtomicU8, Ordering};
 use defmt::*;
 use embassy_executor::Spawner;
@@ -10,7 +10,9 @@ use embassy_rp::bind_interrupts;
 use embassy_rp::gpio::{Input, Pull};
 use embassy_rp::peripherals::USB;
 use embassy_rp::usb::{Driver, InterruptHandler};
-use embassy_usb::class::hid::{HidReaderWriter, ReportId, RequestHandler, State};
+use embassy_usb::class::hid::{
+    HidBootProtocol, HidProtocolMode, HidReaderWriter, HidSubclass, ReportId, RequestHandler, State,
+};
 use embassy_usb::control::OutResponse;
 use embassy_usb::{Builder, Config, Handler};
 use usbd_hid::descriptor::{KeyboardReport, SerializedDescriptor};
@@ -20,6 +22,8 @@ bind_interrupts!(struct Irqs {
    USBCTRL_IRQ => InterruptHandler<USB>;
 });
+static HID_PROTOCOL_MODE: AtomicU8 = AtomicU8::new(HidProtocolMode::Boot as u8);
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
    let p = embassy_rp::init(Default::default());
@@ -33,6 +37,10 @@ async fn main(_spawner: Spawner) {
    config.serial_number = Some("12345678");
    config.max_power = 100;
    config.max_packet_size_0 = 64;
+    config.composite_with_iads = false;
+    config.device_class = 0;
+    config.device_sub_class = 0;
+    config.device_protocol = 0;
    // Create embassy-usb DeviceBuilder using the driver and config.
    // It needs some buffers for building the descriptors.
@@ -63,6 +71,8 @@ async fn main(_spawner: Spawner) {
        request_handler: None,
        poll_ms: 60,
        max_packet_size: 64,
+        hid_subclass: HidSubclass::Boot,
+        hid_boot_protocol: HidBootProtocol::Keyboard,
    };
    let hid = HidReaderWriter::<_, 1, 8>::new(&mut builder, &mut state, config);
@@ -86,30 +96,46 @@ async fn main(_spawner: Spawner) {
            info!("Waiting for HIGH on pin 16");
            signal_pin.wait_for_high().await;
            info!("HIGH DETECTED");
-            // Create a report with the A key pressed. (no shift modifier)
-            let report = KeyboardReport {
+            if HID_PROTOCOL_MODE.load(Ordering::Relaxed) == HidProtocolMode::Boot as u8 {
-                keycodes: [4, 0, 0, 0, 0, 0],
+                match writer.write(&[0, 0, 4, 0, 0, 0, 0, 0]).await {
-                leds: 0,
+                    Ok(()) => {}
-                modifier: 0,
+                    Err(e) => warn!("Failed to send boot report: {:?}", e),
-                reserved: 0,
+                };
-            };
+            } else {
-            // Send the report.
+                // Create a report with the A key pressed. (no shift modifier)
-            match writer.write_serialize(&report).await {
+                let report = KeyboardReport {
-                Ok(()) => {}
+                    keycodes: [4, 0, 0, 0, 0, 0],
-                Err(e) => warn!("Failed to send report: {:?}", e),
+                    leds: 0,
-            };
+                    modifier: 0,
+                    reserved: 0,
+                };
+                // Send the report.
+                match writer.write_serialize(&report).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send report: {:?}", e),
+                };
+            }
            signal_pin.wait_for_low().await;
            info!("LOW DETECTED");
-            let report = KeyboardReport {
+            if HID_PROTOCOL_MODE.load(Ordering::Relaxed) == HidProtocolMode::Boot as u8 {
-                keycodes: [0, 0, 0, 0, 0, 0],
+                match writer.write(&[0, 0, 0, 0, 0, 0, 0, 0]).await {
-                leds: 0,
+                    Ok(()) => {}
-                modifier: 0,
+                    Err(e) => warn!("Failed to send boot report: {:?}", e),
-                reserved: 0,
+                };
-            };
+            } else {
-            match writer.write_serialize(&report).await {
+                let report = KeyboardReport {
-                Ok(()) => {}
+                    keycodes: [0, 0, 0, 0, 0, 0],
-                Err(e) => warn!("Failed to send report: {:?}", e),
+                    leds: 0,
-            };
+                    modifier: 0,
+                    reserved: 0,
+                };
+                match writer.write_serialize(&report).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send report: {:?}", e),
+                };
+            }
        }
    };
@@ -135,6 +161,18 @@ impl RequestHandler for MyRequestHandler {
        OutResponse::Accepted
    }
+    fn get_protocol(&self) -> HidProtocolMode {
+        let protocol = HidProtocolMode::from(HID_PROTOCOL_MODE.load(Ordering::Relaxed));
+        info!("The current HID protocol mode is: {}", protocol);
+        protocol
+    }
+    fn set_protocol(&mut self, protocol: HidProtocolMode) -> OutResponse {
+        info!("Switching to HID protocol mode: {}", protocol);
+        HID_PROTOCOL_MODE.store(protocol as u8, Ordering::Relaxed);
+        OutResponse::Accepted
+    }
    fn set_idle_ms(&mut self, id: Option<ReportId>, dur: u32) {
        info!("Set idle rate for {:?} to {:?}", id, dur);
    }
diff --git a/examples/rp/src/bin/usb_hid_mouse.rs b/examples/rp/src/bin/usb_hid_mouse.rs
index 4454c593c..dc331cbdd 100755
--- a/examples/rp/src/bin/usb_hid_mouse.rs
+++ b/examples/rp/src/bin/usb_hid_mouse.rs
@@ -1,7 +1,7 @@
 #![no_std]
 #![no_main]
-use core::sync::atomic::{AtomicBool, Ordering};
+use core::sync::atomic::{AtomicBool, AtomicU8, Ordering};
 use defmt::*;
 use embassy_executor::Spawner;
@@ -11,7 +11,9 @@ use embassy_rp::clocks::RoscRng;
 use embassy_rp::peripherals::USB;
 use embassy_rp::usb::{Driver, InterruptHandler};
 use embassy_time::Timer;
-use embassy_usb::class::hid::{HidReaderWriter, ReportId, RequestHandler, State};
+use embassy_usb::class::hid::{
+    HidBootProtocol, HidProtocolMode, HidReaderWriter, HidSubclass, ReportId, RequestHandler, State,
+};
 use embassy_usb::control::OutResponse;
 use embassy_usb::{Builder, Config, Handler};
 use rand::Rng;
@@ -22,6 +24,8 @@ bind_interrupts!(struct Irqs {
    USBCTRL_IRQ => InterruptHandler<USB>;
 });
+static HID_PROTOCOL_MODE: AtomicU8 = AtomicU8::new(HidProtocolMode::Boot as u8);
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
    let p = embassy_rp::init(Default::default());
@@ -35,6 +39,10 @@ async fn main(_spawner: Spawner) {
    config.serial_number = Some("12345678");
    config.max_power = 100;
    config.max_packet_size_0 = 64;
+    config.composite_with_iads = false;
+    config.device_class = 0;
+    config.device_sub_class = 0;
+    config.device_protocol = 0;
    // Create embassy-usb DeviceBuilder using the driver and config.
    // It needs some buffers for building the descriptors.
@@ -65,6 +73,8 @@ async fn main(_spawner: Spawner) {
        request_handler: None,
        poll_ms: 60,
        max_packet_size: 64,
+        hid_subclass: HidSubclass::Boot,
+        hid_boot_protocol: HidBootProtocol::Mouse,
    };
    let hid = HidReaderWriter::<_, 1, 8>::new(&mut builder, &mut state, config);
@@ -83,17 +93,29 @@ async fn main(_spawner: Spawner) {
        loop {
            // every 1 second
            _ = Timer::after_secs(1).await;
-            let report = MouseReport {
-                buttons: 0,
+            let x = rng.random_range(-100..100); // random small x movement
-                x: rng.random_range(-100..100), // random small x movement
+            let y = rng.random_range(-100..100); // random small y movement
-                y: rng.random_range(-100..100), // random small y movement
-                wheel: 0,
+            if HID_PROTOCOL_MODE.load(Ordering::Relaxed) == HidProtocolMode::Boot as u8 {
-                pan: 0,
+                let buttons = 0u8;
-            };
+                match writer.write(&[buttons, x as u8, y as u8]).await {
-            // Send the report.
+                    Ok(()) => {}
-            match writer.write_serialize(&report).await {
+                    Err(e) => warn!("Failed to send boot report: {:?}", e),
-                Ok(()) => {}
+                }
-                Err(e) => warn!("Failed to send report: {:?}", e),
+            } else {
+                let report = MouseReport {
+                    buttons: 0,
+                    x,
+                    y,
+                    wheel: 0,
+                    pan: 0,
+                };
+                // Send the report.
+                match writer.write_serialize(&report).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send report: {:?}", e),
+                }
            }
        }
    };
@@ -120,6 +142,18 @@ impl RequestHandler for MyRequestHandler {
        OutResponse::Accepted
    }
+    fn get_protocol(&self) -> HidProtocolMode {
+        let protocol = HidProtocolMode::from(HID_PROTOCOL_MODE.load(Ordering::Relaxed));
+        info!("The current HID protocol mode is: {}", protocol);
+        protocol
+    }
+    fn set_protocol(&mut self, protocol: HidProtocolMode) -> OutResponse {
+        info!("Switching to HID protocol mode: {}", protocol);
+        HID_PROTOCOL_MODE.store(protocol as u8, Ordering::Relaxed);
+        OutResponse::Accepted
+    }
    fn set_idle_ms(&mut self, id: Option<ReportId>, dur: u32) {
        info!("Set idle rate for {:?} to {:?}", id, dur);
    }
diff --git a/examples/rp235x/src/bin/usb_hid_keyboard.rs b/examples/rp235x/src/bin/usb_hid_keyboard.rs
index 6f496e23a..d8f64c470 100644
--- a/examples/rp235x/src/bin/usb_hid_keyboard.rs
+++ b/examples/rp235x/src/bin/usb_hid_keyboard.rs
@@ -1,7 +1,7 @@
 #![no_std]
 #![no_main]
-use core::sync::atomic::{AtomicBool, Ordering};
+use core::sync::atomic::{AtomicBool, AtomicU8, Ordering};
 use defmt::*;
 use embassy_executor::Spawner;
@@ -10,7 +10,9 @@ use embassy_rp::bind_interrupts;
 use embassy_rp::gpio::{Input, Pull};
 use embassy_rp::peripherals::USB;
 use embassy_rp::usb::{Driver as UsbDriver, InterruptHandler};
-use embassy_usb::class::hid::{HidReaderWriter, ReportId, RequestHandler, State as HidState};
+use embassy_usb::class::hid::{
+    HidBootProtocol, HidProtocolMode, HidReaderWriter, HidSubclass, ReportId, RequestHandler, State as HidState,
+};
 use embassy_usb::control::OutResponse;
 use embassy_usb::{Builder, Config, Handler};
 use usbd_hid::descriptor::{KeyboardReport, SerializedDescriptor};
@@ -20,6 +22,8 @@ bind_interrupts!(struct Irqs {
    USBCTRL_IRQ => InterruptHandler<USB>;
 });
+static HID_PROTOCOL_MODE: AtomicU8 = AtomicU8::new(HidProtocolMode::Boot as u8);
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
    let p = embassy_rp::init(Default::default());
@@ -33,6 +37,10 @@ async fn main(_spawner: Spawner) {
    config.serial_number = Some("12345678");
    config.max_power = 100;
    config.max_packet_size_0 = 64;
+    config.composite_with_iads = false;
+    config.device_class = 0;
+    config.device_sub_class = 0;
+    config.device_protocol = 0;
    // Create embassy-usb DeviceBuilder using the driver and config.
    // It needs some buffers for building the descriptors.
@@ -63,6 +71,8 @@ async fn main(_spawner: Spawner) {
        request_handler: None,
        poll_ms: 60,
        max_packet_size: 64,
+        hid_subclass: HidSubclass::Boot,
+        hid_boot_protocol: HidBootProtocol::Keyboard,
    };
    let hid = HidReaderWriter::<_, 1, 8>::new(&mut builder, &mut state, config);
@@ -86,30 +96,45 @@ async fn main(_spawner: Spawner) {
            info!("Waiting for HIGH on pin 16");
            signal_pin.wait_for_high().await;
            info!("HIGH DETECTED");
-            // Create a report with the A key pressed. (no shift modifier)
-            let report = KeyboardReport {
+            if HID_PROTOCOL_MODE.load(Ordering::Relaxed) == HidProtocolMode::Boot as u8 {
-                keycodes: [4, 0, 0, 0, 0, 0],
+                match writer.write(&[0, 0, 4, 0, 0, 0, 0, 0]).await {
-                leds: 0,
+                    Ok(()) => {}
-                modifier: 0,
+                    Err(e) => warn!("Failed to send boot report: {:?}", e),
-                reserved: 0,
+                };
-            };
+            } else {
-            // Send the report.
+                // Create a report with the A key pressed. (no shift modifier)
-            match writer.write_serialize(&report).await {
+                let report = KeyboardReport {
-                Ok(()) => {}
+                    keycodes: [4, 0, 0, 0, 0, 0],
-                Err(e) => warn!("Failed to send report: {:?}", e),
+                    leds: 0,
-            };
+                    modifier: 0,
+                    reserved: 0,
+                };
+                // Send the report.
+                match writer.write_serialize(&report).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send report: {:?}", e),
+                };
+            }
            signal_pin.wait_for_low().await;
            info!("LOW DETECTED");
-            let report = KeyboardReport {
+            if HID_PROTOCOL_MODE.load(Ordering::Relaxed) == HidProtocolMode::Boot as u8 {
-                keycodes: [0, 0, 0, 0, 0, 0],
+                match writer.write(&[0, 0, 0, 0, 0, 0, 0, 0]).await {
-                leds: 0,
+                    Ok(()) => {}
-                modifier: 0,
+                    Err(e) => warn!("Failed to send boot report: {:?}", e),
-                reserved: 0,
+                };
-            };
+            } else {
-            match writer.write_serialize(&report).await {
+                let report = KeyboardReport {
-                Ok(()) => {}
+                    keycodes: [0, 0, 0, 0, 0, 0],
-                Err(e) => warn!("Failed to send report: {:?}", e),
+                    leds: 0,
-            };
+                    modifier: 0,
+                    reserved: 0,
+                };
+                match writer.write_serialize(&report).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send report: {:?}", e),
+                };
+            }
        }
    };
@@ -135,6 +160,18 @@ impl RequestHandler for MyRequestHandler {
        OutResponse::Accepted
    }
+    fn get_protocol(&self) -> HidProtocolMode {
+        let protocol = HidProtocolMode::from(HID_PROTOCOL_MODE.load(Ordering::Relaxed));
+        info!("The current HID protocol mode is: {}", protocol);
+        protocol
+    }
+    fn set_protocol(&mut self, protocol: HidProtocolMode) -> OutResponse {
+        info!("Switching to HID protocol mode: {}", protocol);
+        HID_PROTOCOL_MODE.store(protocol as u8, Ordering::Relaxed);
+        OutResponse::Accepted
+    }
    fn set_idle_ms(&mut self, id: Option<ReportId>, dur: u32) {
        info!("Set idle rate for {:?} to {:?}", id, dur);
    }
diff --git a/examples/stm32c0/src/bin/adc.rs b/examples/stm32c0/src/bin/adc.rs
index 1f54b0b18..ad597b63c 100644
--- a/examples/stm32c0/src/bin/adc.rs
+++ b/examples/stm32c0/src/bin/adc.rs
@@ -3,7 +3,6 @@
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::adc::vals::Scandir;
 use embassy_stm32::adc::{Adc, AdcChannel, AnyAdcChannel, Resolution, SampleTime};
 use embassy_stm32::peripherals::ADC1;
 use embassy_time::Timer;
@@ -17,7 +16,7 @@ async fn main(_spawner: Spawner) {
    info!("ADC STM32C0 example.");
    // We need to set certain sample time to be able to read temp sensor.
-    let mut adc = Adc::new(p.ADC1, SampleTime::CYCLES12_5, Resolution::BITS12);
+    let mut adc = Adc::new(p.ADC1, Resolution::BITS12);
    let mut temp = adc.enable_temperature().degrade_adc();
    let mut vref = adc.enable_vrefint().degrade_adc();
    let mut pin0 = p.PA0.degrade_adc();
@@ -27,16 +26,20 @@ async fn main(_spawner: Spawner) {
    loop {
        info!("============================");
-        let blocking_temp = adc.blocking_read(&mut temp);
+        let blocking_temp = adc.blocking_read(&mut temp, SampleTime::CYCLES12_5);
-        let blocking_vref = adc.blocking_read(&mut vref);
+        let blocking_vref = adc.blocking_read(&mut vref, SampleTime::CYCLES12_5);
-        let blocing_pin0 = adc.blocking_read(&mut pin0);
+        let blocing_pin0 = adc.blocking_read(&mut pin0, SampleTime::CYCLES12_5);
        info!(
            "Blocking ADC read: vref = {}, temp = {}, pin0 = {}.",
            blocking_vref, blocking_temp, blocing_pin0
        );
-        let channels_seqence: [&mut AnyAdcChannel<ADC1>; 3] = [&mut vref, &mut temp, &mut pin0];
+        let channels_sequence: [(&mut AnyAdcChannel<ADC1>, SampleTime); 3] = [
-        adc.read(dma.reborrow(), channels_seqence.into_iter(), &mut read_buffer)
+            (&mut vref, SampleTime::CYCLES12_5),
+            (&mut temp, SampleTime::CYCLES12_5),
+            (&mut pin0, SampleTime::CYCLES12_5),
+        ];
+        adc.read(dma.reborrow(), channels_sequence.into_iter(), &mut read_buffer)
            .await;
        // Values are ordered according to hardware ADC channel number!
        info!(
@@ -44,15 +47,6 @@ async fn main(_spawner: Spawner) {
            read_buffer[0], read_buffer[1], read_buffer[2]
        );
-        let hw_channel_selection: u32 =
-            (1 << temp.get_hw_channel()) + (1 << vref.get_hw_channel()) + (1 << pin0.get_hw_channel());
-        adc.read_in_hw_order(dma.reborrow(), hw_channel_selection, Scandir::UP, &mut read_buffer)
-            .await;
-        info!(
-            "DMA ADC read in hardware order: vref = {}, temp = {}, pin0 = {}.",
-            read_buffer[2], read_buffer[1], read_buffer[0]
-        );
        Timer::after_millis(2000).await;
    }
 }
diff --git a/examples/stm32f0/Cargo.toml b/examples/stm32f0/Cargo.toml
index a78873d21..177dd0ac2 100644
--- a/examples/stm32f0/Cargo.toml
+++ b/examples/stm32f0/Cargo.toml
@@ -16,6 +16,7 @@ panic-probe = { version = "1.0.0", features = ["print-defmt"] }
 embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
+embedded-hal-1 = { package = "embedded-hal", version = "1.0" }
 static_cell = "2"
 portable-atomic = { version = "1.5", features = ["unsafe-assume-single-core"] }
diff --git a/examples/stm32f0/src/bin/adc-watchdog.rs b/examples/stm32f0/src/bin/adc-watchdog.rs
index ff98aac8e..6879dd10a 100644
--- a/examples/stm32f0/src/bin/adc-watchdog.rs
+++ b/examples/stm32f0/src/bin/adc-watchdog.rs
@@ -3,7 +3,7 @@
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::adc::{self, Adc, WatchdogChannels};
+use embassy_stm32::adc::{self, Adc, SampleTime, WatchdogChannels};
 use embassy_stm32::bind_interrupts;
 use embassy_stm32::peripherals::ADC1;
 use {defmt_rtt as _, panic_probe as _};
@@ -23,12 +23,12 @@ async fn main(_spawner: Spawner) {
    loop {
        // Wait for pin to go high
        adc.init_watchdog(WatchdogChannels::from_channel(&pin), 0, 0x07F);
-        let v_high = adc.monitor_watchdog().await;
+        let v_high = adc.monitor_watchdog(SampleTime::CYCLES13_5).await;
        info!("ADC sample is high {}", v_high);
        // Wait for pin to go low
        adc.init_watchdog(WatchdogChannels::from_channel(&pin), 0x01f, 0xFFF);
-        let v_low = adc.monitor_watchdog().await;
+        let v_low = adc.monitor_watchdog(SampleTime::CYCLES13_5).await;
        info!("ADC sample is low {}", v_low);
    }
 }
diff --git a/examples/stm32f0/src/bin/adc.rs b/examples/stm32f0/src/bin/adc.rs
index 8825e2687..fafeeffaf 100644
--- a/examples/stm32f0/src/bin/adc.rs
+++ b/examples/stm32f0/src/bin/adc.rs
@@ -19,11 +19,10 @@ async fn main(_spawner: Spawner) {
    info!("Hello World!");
    let mut adc = Adc::new(p.ADC1, Irqs);
-    adc.set_sample_time(SampleTime::CYCLES71_5);
    let mut pin = p.PA1;
    let mut vrefint = adc.enable_vref();
-    let vrefint_sample = adc.read(&mut vrefint).await;
+    let vrefint_sample = adc.read(&mut vrefint, SampleTime::CYCLES13_5).await;
    let convert_to_millivolts = |sample| {
        // From https://www.st.com/resource/en/datasheet/stm32f031c6.pdf
        // 6.3.4 Embedded reference voltage
@@ -33,7 +32,7 @@ async fn main(_spawner: Spawner) {
    };
    loop {
-        let v = adc.read(&mut pin).await;
+        let v = adc.read(&mut pin, SampleTime::CYCLES13_5).await;
        info!("--> {} - {} mV", v, convert_to_millivolts(v));
        Timer::after_millis(100).await;
    }
diff --git a/examples/stm32f0/src/bin/i2c_master.rs b/examples/stm32f0/src/bin/i2c_master.rs
new file mode 100644
index 000000000..2e61ecdf7
--- /dev/null
+++ b/examples/stm32f0/src/bin/i2c_master.rs
@@ -0,0 +1,609 @@
+#![no_std]
+#![no_main]
+// Hardware Setup for NUCLEO-F072RB:
+// - I2C1 pins: PB8 (SCL), PB9 (SDA) on CN5 connector
+// - Connect to I2C slave device (e.g., Digilent Analog Discovery I2C slave, or EEPROM)
+// - Default slave address: 0x50
+// - Pull-up resistors: 4.7kΩ on both SCL and SDA
+// - CN5 Pin 10 (PB8/SCL) and CN5 Pin 9 (PB9/SDA)
+//
+// Analog Discovery - Waveforms Setup:
+// - Increase buffer size: Settings -> Device Manager -> Option 4
+// - Run Protocol Analyzer
+// - Configure as I2C Slave at address 0x50
+// - Connect and configure DIO pins for SCL and SDA
+// - Frequency: 100kHz - [✓] Clock Stretching
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::i2c::{Config, I2c, Master};
+use embassy_stm32::mode::{Async, Blocking};
+use embassy_stm32::time::Hertz;
+use embassy_stm32::{bind_interrupts, i2c, peripherals};
+use embassy_time::Timer;
+use embedded_hal_1::i2c::Operation;
+use {defmt_rtt as _, panic_probe as _};
+bind_interrupts!(struct Irqs {
+    I2C1 => i2c::EventInterruptHandler<peripherals::I2C1>, i2c::ErrorInterruptHandler<peripherals::I2C1>;
+});
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = embassy_stm32::init(Default::default());
+    info!("Run stm32 I2C v2 Master Tests...");
+    let mut i2c_peri = p.I2C1;
+    let mut scl = p.PB8;
+    let mut sda = p.PB9;
+    let mut config = Config::default();
+    config.frequency = Hertz(100_000);
+    // I2C slave address for Analog Discovery or test EEPROM
+    let slave_addr = 0x50u8;
+    // Wait for slave device to be ready
+    Timer::after_millis(100).await;
+    // ========== BLOCKING DIRECT API TESTS ==========
+    info!("========== BLOCKING DIRECT API TESTS ==========");
+    {
+        let mut i2c = I2c::new_blocking(i2c_peri.reborrow(), scl.reborrow(), sda.reborrow(), config);
+        info!("=== Test 1: Direct blocking_write ===");
+        test_blocking_write(&mut i2c, slave_addr);
+        info!("=== Test 2: Direct blocking_read ===");
+        test_blocking_read(&mut i2c, slave_addr);
+        info!("=== Test 3: Direct blocking_write_read ===");
+        test_blocking_write_read(&mut i2c, slave_addr);
+        info!("=== Test 4: Direct blocking_write_vectored ===");
+        test_blocking_write_vectored(&mut i2c, slave_addr);
+        info!("=== Test 5: Large buffer (>255 bytes) ===");
+        test_blocking_large_buffer(&mut i2c, slave_addr);
+        info!("Blocking direct API tests OK");
+    }
+    Timer::after_millis(100).await;
+    // ========== BLOCKING TRANSACTION TESTS ==========
+    info!("========== BLOCKING TRANSACTION TESTS ==========");
+    {
+        let mut i2c = I2c::new_blocking(i2c_peri.reborrow(), scl.reborrow(), sda.reborrow(), config);
+        info!("=== Test 6: Consecutive Writes (Should Merge) ===");
+        test_consecutive_writes_blocking(&mut i2c, slave_addr);
+        info!("=== Test 7: Consecutive Reads (Should Merge) ===");
+        test_consecutive_reads_blocking(&mut i2c, slave_addr);
+        info!("=== Test 8: Write then Read (RESTART) ===");
+        test_write_then_read_blocking(&mut i2c, slave_addr);
+        info!("=== Test 9: Read then Write (RESTART) ===");
+        test_read_then_write_blocking(&mut i2c, slave_addr);
+        info!("=== Test 10: Complex Mixed Sequence ===");
+        test_mixed_sequence_blocking(&mut i2c, slave_addr);
+        info!("=== Test 11: Single Operations ===");
+        test_single_operations_blocking(&mut i2c, slave_addr);
+        info!("Blocking transaction tests OK");
+    }
+    Timer::after_millis(100).await;
+    // ========== ASYNC TESTS (DMA) ==========
+    info!("========== ASYNC TESTS (DMA) ==========");
+    {
+        let tx_dma = p.DMA1_CH2;
+        let rx_dma = p.DMA1_CH3;
+        let mut i2c = I2c::new(i2c_peri, scl, sda, Irqs, tx_dma, rx_dma, config);
+        // Direct API tests (reusing same I2C instance)
+        info!("=== Direct API Test 1: write() ===");
+        test_async_write(&mut i2c, slave_addr).await;
+        info!("=== Direct API Test 2: read() ===");
+        test_async_read(&mut i2c, slave_addr).await;
+        info!("=== Direct API Test 3: write_read() ===");
+        test_async_write_read(&mut i2c, slave_addr).await;
+        info!("=== Direct API Test 4: write_vectored() ===");
+        test_async_write_vectored(&mut i2c, slave_addr).await;
+        info!("=== Direct API Test 5: Large buffer (>255 bytes) ===");
+        test_async_large_buffer(&mut i2c, slave_addr).await;
+        info!("Async Direct API tests OK");
+        // Transaction tests
+        info!("=== Transaction Test 6: Consecutive Writes (Should Merge) ===");
+        test_consecutive_writes_async(&mut i2c, slave_addr).await;
+        info!("=== Transaction Test 7: Consecutive Reads (Should Merge) ===");
+        test_consecutive_reads_async(&mut i2c, slave_addr).await;
+        info!("=== Transaction Test 8: Write then Read (RESTART) ===");
+        test_write_then_read_async(&mut i2c, slave_addr).await;
+        info!("=== Transaction Test 9: Read then Write (RESTART) ===");
+        test_read_then_write_async(&mut i2c, slave_addr).await;
+        info!("=== Transaction Test 10: Complex Mixed Sequence ===");
+        test_mixed_sequence_async(&mut i2c, slave_addr).await;
+        info!("=== Transaction Test 11: Single Operations ===");
+        test_single_operations_async(&mut i2c, slave_addr).await;
+        info!("Async transaction tests OK");
+    }
+    info!("All tests OK");
+    cortex_m::asm::bkpt();
+}
+// ==================== BLOCKING DIRECT API TEST FUNCTIONS ====================
+fn test_blocking_write(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+    let write_data = [0x42, 0x43, 0x44, 0x45];
+    match i2c.blocking_write(addr, &write_data) {
+        Ok(_) => info!("✓ blocking_write succeeded: {:02x}", write_data),
+        Err(e) => {
+            error!("✗ blocking_write failed: {:?}", e);
+            defmt::panic!("Test failed: blocking_write");
+        }
+    }
+}
+fn test_blocking_read(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+    let mut read_buf = [0u8; 8];
+    match i2c.blocking_read(addr, &mut read_buf) {
+        Ok(_) => info!("✓ blocking_read succeeded: {:02x}", read_buf),
+        Err(e) => {
+            error!("✗ blocking_read failed: {:?}", e);
+            defmt::panic!("Test failed: blocking_read");
+        }
+    }
+}
+fn test_blocking_write_read(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+    let write_data = [0x50, 0x51];
+    let mut read_buf = [0u8; 6];
+    match i2c.blocking_write_read(addr, &write_data, &mut read_buf) {
+        Ok(_) => {
+            info!("✓ blocking_write_read succeeded");
+            info!("  Written: {:02x}", write_data);
+            info!("  Read: {:02x}", read_buf);
+        }
+        Err(e) => {
+            error!("✗ blocking_write_read failed: {:?}", e);
+            defmt::panic!("Test failed: blocking_write_read");
+        }
+    }
+}
+fn test_blocking_write_vectored(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+    let buf1 = [0x60, 0x61, 0x62];
+    let buf2 = [0x70, 0x71];
+    let buf3 = [0x80, 0x81, 0x82, 0x83];
+    let bufs = [&buf1[..], &buf2[..], &buf3[..]];
+    match i2c.blocking_write_vectored(addr, &bufs) {
+        Ok(_) => info!("✓ blocking_write_vectored succeeded (9 bytes total)"),
+        Err(e) => {
+            error!("✗ blocking_write_vectored failed: {:?}", e);
+            defmt::panic!("Test failed: blocking_write_vectored");
+        }
+    }
+}
+fn test_blocking_large_buffer(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+    // Test with 300 bytes to verify RELOAD mechanism works (needs chunking at 255 bytes)
+    let mut write_buf = [0u8; 300];
+    for (i, byte) in write_buf.iter_mut().enumerate() {
+        *byte = (i & 0xFF) as u8;
+    }
+    match i2c.blocking_write(addr, &write_buf) {
+        Ok(_) => info!("✓ Large buffer write succeeded (300 bytes, tests RELOAD)"),
+        Err(e) => {
+            error!("✗ Large buffer write failed: {:?}", e);
+            defmt::panic!("Test failed: large buffer write");
+        }
+    }
+    // Test large read
+    let mut read_buf = [0u8; 300];
+    match i2c.blocking_read(addr, &mut read_buf) {
+        Ok(_) => info!("✓ Large buffer read succeeded (300 bytes, tests RELOAD)"),
+        Err(e) => {
+            error!("✗ Large buffer read failed: {:?}", e);
+            defmt::panic!("Test failed: large buffer read");
+        }
+    }
+}
+// ==================== BLOCKING TRANSACTION TEST FUNCTIONS ====================
+fn test_consecutive_writes_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+    // Expected on bus: START, ADDR+W, data1, data2, data3, STOP
+    // NO intermediate RESTART/STOP between writes - they should be merged
+    let data1 = [0x10, 0x11, 0x12];
+    let data2 = [0x20, 0x21];
+    let data3 = [0x30, 0x31, 0x32, 0x33];
+    let mut ops = [
+        Operation::Write(&data1),
+        Operation::Write(&data2),
+        Operation::Write(&data3),
+    ];
+    match i2c.blocking_transaction(addr, &mut ops) {
+        Ok(_) => info!("✓ Consecutive writes succeeded (merged 9 bytes)"),
+        Err(e) => {
+            error!("✗ Consecutive writes failed: {:?}", e);
+            defmt::panic!("Test failed: consecutive writes");
+        }
+    }
+}
+fn test_consecutive_reads_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+    // Expected on bus: START, ADDR+R, data1, data2, data3, NACK, STOP
+    // NO intermediate RESTART/STOP between reads - they should be merged
+    let mut buf1 = [0u8; 4];
+    let mut buf2 = [0u8; 3];
+    let mut buf3 = [0u8; 2];
+    let mut ops = [
+        Operation::Read(&mut buf1),
+        Operation::Read(&mut buf2),
+        Operation::Read(&mut buf3),
+    ];
+    match i2c.blocking_transaction(addr, &mut ops) {
+        Ok(_) => {
+            info!("✓ Consecutive reads succeeded (merged 9 bytes)");
+            info!("  buf1: {:02x}", buf1);
+            info!("  buf2: {:02x}", buf2);
+            info!("  buf3: {:02x}", buf3);
+        }
+        Err(e) => {
+            error!("✗ Consecutive reads failed: {:?}", e);
+            defmt::panic!("Test failed: consecutive reads");
+        }
+    }
+}
+fn test_write_then_read_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+    // Expected: START, ADDR+W, data, RESTART, ADDR+R, data, NACK, STOP
+    let write_data = [0xAA, 0xBB];
+    let mut read_buf = [0u8; 4];
+    let mut ops = [Operation::Write(&write_data), Operation::Read(&mut read_buf)];
+    match i2c.blocking_transaction(addr, &mut ops) {
+        Ok(_) => {
+            info!("✓ Write-then-read succeeded with RESTART");
+            info!("  Written: {:02x}", write_data);
+            info!("  Read: {:02x}", read_buf);
+        }
+        Err(e) => {
+            error!("✗ Write-then-read failed: {:?}", e);
+            defmt::panic!("Test failed: write-then-read");
+        }
+    }
+}
+fn test_read_then_write_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+    // Expected: START, ADDR+R, data, NACK, RESTART, ADDR+W, data, STOP
+    let mut read_buf = [0u8; 3];
+    let write_data = [0xCC, 0xDD, 0xEE];
+    let mut ops = [Operation::Read(&mut read_buf), Operation::Write(&write_data)];
+    match i2c.blocking_transaction(addr, &mut ops) {
+        Ok(_) => {
+            info!("✓ Read-then-write succeeded with RESTART");
+            info!("  Read: {:02x}", read_buf);
+            info!("  Written: {:02x}", write_data);
+        }
+        Err(e) => {
+            error!("✗ Read-then-write failed: {:?}", e);
+            defmt::panic!("Test failed: read-then-write");
+        }
+    }
+}
+fn test_mixed_sequence_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+    // Complex: W, W, R, R, W, R
+    // Groups: [W,W] RESTART [R,R] RESTART [W] RESTART [R]
+    let w1 = [0x01, 0x02];
+    let w2 = [0x03, 0x04];
+    let mut r1 = [0u8; 2];
+    let mut r2 = [0u8; 2];
+    let w3 = [0x05];
+    let mut r3 = [0u8; 1];
+    let mut ops = [
+        Operation::Write(&w1),
+        Operation::Write(&w2),
+        Operation::Read(&mut r1),
+        Operation::Read(&mut r2),
+        Operation::Write(&w3),
+        Operation::Read(&mut r3),
+    ];
+    match i2c.blocking_transaction(addr, &mut ops) {
+        Ok(_) => {
+            info!("✓ Mixed sequence succeeded");
+            info!("  Groups: [W4] RESTART [R4] RESTART [W1] RESTART [R1]");
+        }
+        Err(e) => {
+            error!("✗ Mixed sequence failed: {:?}", e);
+            defmt::panic!("Test failed: mixed sequence");
+        }
+    }
+}
+fn test_single_operations_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+    // Test single write
+    let write_data = [0xFF];
+    let mut ops = [Operation::Write(&write_data)];
+    match i2c.blocking_transaction(addr, &mut ops) {
+        Ok(_) => info!("✓ Single write succeeded"),
+        Err(e) => {
+            error!("✗ Single write failed: {:?}", e);
+            defmt::panic!("Test failed: single write");
+        }
+    }
+    // Test single read
+    let mut read_buf = [0u8; 1];
+    let mut ops = [Operation::Read(&mut read_buf)];
+    match i2c.blocking_transaction(addr, &mut ops) {
+        Ok(_) => info!("✓ Single read succeeded, data: 0x{:02x}", read_buf[0]),
+        Err(e) => {
+            error!("✗ Single read failed: {:?}", e);
+            defmt::panic!("Test failed: single read");
+        }
+    }
+}
+// ==================== ASYNC DIRECT API TEST FUNCTIONS ====================
+async fn test_async_write(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let write_data = [0x42, 0x43, 0x44, 0x45];
+    match i2c.write(addr, &write_data).await {
+        Ok(_) => info!("✓ async write succeeded: {:02x}", write_data),
+        Err(e) => {
+            error!("✗ async write failed: {:?}", e);
+            defmt::panic!("Test failed: async write");
+        }
+    }
+}
+async fn test_async_read(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let mut read_buf = [0u8; 8];
+    match i2c.read(addr, &mut read_buf).await {
+        Ok(_) => info!("✓ async read succeeded: {:02x}", read_buf),
+        Err(e) => {
+            error!("✗ async read failed: {:?}", e);
+            defmt::panic!("Test failed: async read");
+        }
+    }
+}
+async fn test_async_write_read(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let write_data = [0x50, 0x51];
+    let mut read_buf = [0u8; 6];
+    match i2c.write_read(addr, &write_data, &mut read_buf).await {
+        Ok(_) => {
+            info!("✓ async write_read succeeded");
+            info!("  Written: {:02x}", write_data);
+            info!("  Read: {:02x}", read_buf);
+        }
+        Err(e) => {
+            error!("✗ async write_read failed: {:?}", e);
+            defmt::panic!("Test failed: async write_read");
+        }
+    }
+}
+async fn test_async_write_vectored(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let buf1 = [0x60, 0x61, 0x62];
+    let buf2 = [0x70, 0x71];
+    let buf3 = [0x80, 0x81, 0x82, 0x83];
+    let bufs = [&buf1[..], &buf2[..], &buf3[..]];
+    match i2c.write_vectored(addr.into(), &bufs).await {
+        Ok(_) => info!("✓ async write_vectored succeeded (9 bytes total)"),
+        Err(e) => {
+            error!("✗ async write_vectored failed: {:?}", e);
+            defmt::panic!("Test failed: async write_vectored");
+        }
+    }
+}
+async fn test_async_large_buffer(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    // Test with 300 bytes to verify RELOAD mechanism works with DMA (needs chunking at 255 bytes)
+    let mut write_buf = [0u8; 300];
+    for (i, byte) in write_buf.iter_mut().enumerate() {
+        *byte = (i & 0xFF) as u8;
+    }
+    match i2c.write(addr, &write_buf).await {
+        Ok(_) => info!("✓ Large buffer async write succeeded (300 bytes, tests RELOAD with DMA)"),
+        Err(e) => {
+            error!("✗ Large buffer async write failed: {:?}", e);
+            defmt::panic!("Test failed: large buffer async write");
+        }
+    }
+    // Test large read
+    let mut read_buf = [0u8; 300];
+    match i2c.read(addr, &mut read_buf).await {
+        Ok(_) => info!("✓ Large buffer async read succeeded (300 bytes, tests RELOAD with DMA)"),
+        Err(e) => {
+            error!("✗ Large buffer async read failed: {:?}", e);
+            defmt::panic!("Test failed: large buffer async read");
+        }
+    }
+}
+// ==================== ASYNC TRANSACTION TEST FUNCTIONS ====================
+async fn test_consecutive_writes_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let data1 = [0x10, 0x11, 0x12];
+    let data2 = [0x20, 0x21];
+    let data3 = [0x30, 0x31, 0x32, 0x33];
+    let mut ops = [
+        Operation::Write(&data1),
+        Operation::Write(&data2),
+        Operation::Write(&data3),
+    ];
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => info!("✓ Consecutive writes succeeded (merged 9 bytes)"),
+        Err(e) => {
+            error!("✗ Consecutive writes failed: {:?}", e);
+            defmt::panic!("Test failed: consecutive writes");
+        }
+    }
+}
+async fn test_consecutive_reads_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let mut buf1 = [0u8; 4];
+    let mut buf2 = [0u8; 3];
+    let mut buf3 = [0u8; 2];
+    let mut ops = [
+        Operation::Read(&mut buf1),
+        Operation::Read(&mut buf2),
+        Operation::Read(&mut buf3),
+    ];
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => {
+            info!("✓ Consecutive reads succeeded (merged 9 bytes)");
+            info!("  buf1: {:02x}", buf1);
+            info!("  buf2: {:02x}", buf2);
+            info!("  buf3: {:02x}", buf3);
+        }
+        Err(e) => {
+            error!("✗ Consecutive reads failed: {:?}", e);
+            defmt::panic!("Test failed: consecutive reads");
+        }
+    }
+}
+async fn test_write_then_read_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let write_data = [0xAA, 0xBB];
+    let mut read_buf = [0u8; 4];
+    let mut ops = [Operation::Write(&write_data), Operation::Read(&mut read_buf)];
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => {
+            info!("✓ Write-then-read succeeded with RESTART");
+            info!("  Written: {:02x}", write_data);
+            info!("  Read: {:02x}", read_buf);
+        }
+        Err(e) => {
+            error!("✗ Write-then-read failed: {:?}", e);
+            defmt::panic!("Test failed: write-then-read");
+        }
+    }
+}
+async fn test_read_then_write_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let mut read_buf = [0u8; 3];
+    let write_data = [0xCC, 0xDD, 0xEE];
+    let mut ops = [Operation::Read(&mut read_buf), Operation::Write(&write_data)];
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => {
+            info!("✓ Read-then-write succeeded with RESTART");
+            info!("  Read: {:02x}", read_buf);
+            info!("  Written: {:02x}", write_data);
+        }
+        Err(e) => {
+            error!("✗ Read-then-write failed: {:?}", e);
+            defmt::panic!("Test failed: read-then-write");
+        }
+    }
+}
+async fn test_mixed_sequence_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let w1 = [0x01, 0x02];
+    let w2 = [0x03, 0x04];
+    let mut r1 = [0u8; 2];
+    let mut r2 = [0u8; 2];
+    let w3 = [0x05];
+    let mut r3 = [0u8; 1];
+    let mut ops = [
+        Operation::Write(&w1),
+        Operation::Write(&w2),
+        Operation::Read(&mut r1),
+        Operation::Read(&mut r2),
+        Operation::Write(&w3),
+        Operation::Read(&mut r3),
+    ];
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => {
+            info!("✓ Mixed sequence succeeded");
+            info!("  Groups: [W4] RESTART [R4] RESTART [W1] RESTART [R1]");
+        }
+        Err(e) => {
+            error!("✗ Mixed sequence failed: {:?}", e);
+            defmt::panic!("Test failed: mixed sequence");
+        }
+    }
+}
+async fn test_single_operations_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    // Test single write
+    let write_data = [0xFF];
+    let mut ops = [Operation::Write(&write_data)];
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => info!("✓ Single write succeeded"),
+        Err(e) => {
+            error!("✗ Single write failed: {:?}", e);
+            defmt::panic!("Test failed: single write");
+        }
+    }
+    // Test single read
+    let mut read_buf = [0u8; 1];
+    let mut ops = [Operation::Read(&mut read_buf)];
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => info!("✓ Single read succeeded, data: 0x{:02x}", read_buf[0]),
+        Err(e) => {
+            error!("✗ Single read failed: {:?}", e);
+            defmt::panic!("Test failed: single read");
+        }
+    }
+}
diff --git a/examples/stm32f1/src/bin/adc.rs b/examples/stm32f1/src/bin/adc.rs
index 541ff159e..2451aee3d 100644
--- a/examples/stm32f1/src/bin/adc.rs
+++ b/examples/stm32f1/src/bin/adc.rs
@@ -3,7 +3,7 @@
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::adc::Adc;
+use embassy_stm32::adc::{Adc, SampleTime};
 use embassy_stm32::peripherals::ADC1;
 use embassy_stm32::{adc, bind_interrupts};
 use embassy_time::Timer;
@@ -22,7 +22,7 @@ async fn main(_spawner: Spawner) {
    let mut pin = p.PB1;
    let mut vrefint = adc.enable_vref();
-    let vrefint_sample = adc.read(&mut vrefint).await;
+    let vrefint_sample = adc.read(&mut vrefint, SampleTime::CYCLES13_5).await;
    let convert_to_millivolts = |sample| {
        // From http://www.st.com/resource/en/datasheet/CD00161566.pdf
        // 5.3.4 Embedded reference voltage
@@ -32,7 +32,7 @@ async fn main(_spawner: Spawner) {
    };
    loop {
-        let v = adc.read(&mut pin).await;
+        let v = adc.read(&mut pin, SampleTime::CYCLES13_5).await;
        info!("--> {} - {} mV", v, convert_to_millivolts(v));
        Timer::after_millis(100).await;
    }
diff --git a/examples/stm32f334/src/bin/adc.rs b/examples/stm32f334/src/bin/adc.rs
index a993b00ca..486f160ec 100644
--- a/examples/stm32f334/src/bin/adc.rs
+++ b/examples/stm32f334/src/bin/adc.rs
@@ -40,24 +40,22 @@ async fn main(_spawner: Spawner) -> ! {
    let mut adc = Adc::new(p.ADC1, Irqs);
-    adc.set_sample_time(SampleTime::CYCLES601_5);
    info!("enable vrefint...");
    let mut vrefint = adc.enable_vref();
    let mut temperature = adc.enable_temperature();
    loop {
-        let vref = adc.read(&mut vrefint).await;
+        let vref = adc.read(&mut vrefint, SampleTime::CYCLES601_5).await;
-        info!("read vref: {} (should be {})", vref, vrefint.value());
+        info!("read vref: {} (should be {})", vref, vrefint.calibrated_value());
-        let temp = adc.read(&mut temperature).await;
+        let temp = adc.read(&mut temperature, SampleTime::CYCLES601_5).await;
        info!("read temperature: {}", temp);
-        let pin = adc.read(&mut p.PA0).await;
+        let pin = adc.read(&mut p.PA0, SampleTime::CYCLES601_5).await;
        info!("read pin: {}", pin);
-        let pin_mv = (pin as u32 * vrefint.value() as u32 / vref as u32) * 3300 / 4095;
+        let pin_mv = (pin as u32 * vrefint.calibrated_value() as u32 / vref as u32) * 3300 / 4095;
        info!("computed pin mv: {}", pin_mv);
        Timer::after_millis(500).await;
diff --git a/examples/stm32f334/src/bin/opamp.rs b/examples/stm32f334/src/bin/opamp.rs
index 3e621f2a1..9555fd35d 100644
--- a/examples/stm32f334/src/bin/opamp.rs
+++ b/examples/stm32f334/src/bin/opamp.rs
@@ -42,8 +42,6 @@ async fn main(_spawner: Spawner) -> ! {
    let mut adc = Adc::new(p.ADC2, Irqs);
    let mut opamp = OpAmp::new(p.OPAMP2);
-    adc.set_sample_time(SampleTime::CYCLES601_5);
    info!("enable vrefint...");
    let mut vrefint = adc.enable_vref();
@@ -51,16 +49,16 @@ async fn main(_spawner: Spawner) -> ! {
    let mut buffer = opamp.buffer_ext(p.PA7.reborrow(), p.PA6.reborrow());
    loop {
-        let vref = adc.read(&mut vrefint).await;
+        let vref = adc.read(&mut vrefint, SampleTime::CYCLES601_5).await;
-        info!("read vref: {} (should be {})", vref, vrefint.value());
+        info!("read vref: {} (should be {})", vref, vrefint.calibrated_value());
-        let temp = adc.read(&mut temperature).await;
+        let temp = adc.read(&mut temperature, SampleTime::CYCLES601_5).await;
        info!("read temperature: {}", temp);
-        let buffer = adc.read(&mut buffer).await;
+        let buffer = adc.read(&mut buffer, SampleTime::CYCLES601_5).await;
        info!("read buffer: {}", buffer);
-        let pin_mv = (buffer as u32 * vrefint.value() as u32 / vref as u32) * 3300 / 4095;
+        let pin_mv = (buffer as u32 * vrefint.calibrated_value() as u32 / vref as u32) * 3300 / 4095;
        info!("computed pin mv: {}", pin_mv);
        Timer::after_millis(500).await;
diff --git a/examples/stm32f4/src/bin/adc.rs b/examples/stm32f4/src/bin/adc.rs
index 423d29225..694e85657 100644
--- a/examples/stm32f4/src/bin/adc.rs
+++ b/examples/stm32f4/src/bin/adc.rs
@@ -4,7 +4,7 @@
 use cortex_m::prelude::_embedded_hal_blocking_delay_DelayUs;
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::adc::{Adc, Temperature, VrefInt};
+use embassy_stm32::adc::{Adc, SampleTime, Temperature, VrefInt};
 use embassy_time::{Delay, Timer};
 use {defmt_rtt as _, panic_probe as _};
@@ -14,7 +14,7 @@ async fn main(_spawner: Spawner) {
    info!("Hello World!");
    let mut delay = Delay;
-    let mut adc = Adc::new(p.ADC1);
+    let mut adc = Adc::new_with_config(p.ADC1, Default::default());
    let mut pin = p.PC1;
    let mut vrefint = adc.enable_vrefint();
@@ -23,7 +23,7 @@ async fn main(_spawner: Spawner) {
    // Startup delay can be combined to the maximum of either
    delay.delay_us(Temperature::start_time_us().max(VrefInt::start_time_us()));
-    let vrefint_sample = adc.blocking_read(&mut vrefint);
+    let vrefint_sample = adc.blocking_read(&mut vrefint, SampleTime::CYCLES112);
    let convert_to_millivolts = |sample| {
        // From http://www.st.com/resource/en/datasheet/DM00071990.pdf
@@ -50,16 +50,16 @@ async fn main(_spawner: Spawner) {
    loop {
        // Read pin
-        let v = adc.blocking_read(&mut pin);
+        let v = adc.blocking_read(&mut pin, SampleTime::CYCLES112);
        info!("PC1: {} ({} mV)", v, convert_to_millivolts(v));
        // Read internal temperature
-        let v = adc.blocking_read(&mut temp);
+        let v = adc.blocking_read(&mut temp, SampleTime::CYCLES112);
        let celcius = convert_to_celcius(v);
        info!("Internal temp: {} ({} C)", v, celcius);
        // Read internal voltage reference
-        let v = adc.blocking_read(&mut vrefint);
+        let v = adc.blocking_read(&mut vrefint, SampleTime::CYCLES112);
        info!("VrefInt: {}", v);
        Timer::after_millis(100).await;
diff --git a/examples/stm32f4/src/bin/adc_dma.rs b/examples/stm32f4/src/bin/adc_dma.rs
index f8da91336..d61b1b2eb 100644
--- a/examples/stm32f4/src/bin/adc_dma.rs
+++ b/examples/stm32f4/src/bin/adc_dma.rs
@@ -4,7 +4,7 @@ use cortex_m::singleton;
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_stm32::Peripherals;
-use embassy_stm32::adc::{Adc, AdcChannel, RingBufferedAdc, SampleTime};
+use embassy_stm32::adc::{Adc, AdcChannel, RegularConversionMode, RingBufferedAdc, SampleTime};
 use embassy_time::Instant;
 use {defmt_rtt as _, panic_probe as _};
@@ -20,26 +20,28 @@ async fn adc_task(p: Peripherals) {
    let adc_data: &mut [u16; ADC_BUF_SIZE] = singleton!(ADCDAT : [u16; ADC_BUF_SIZE] = [0u16; ADC_BUF_SIZE]).unwrap();
    let adc_data2: &mut [u16; ADC_BUF_SIZE] = singleton!(ADCDAT2 : [u16; ADC_BUF_SIZE] = [0u16; ADC_BUF_SIZE]).unwrap();
-    let adc = Adc::new(p.ADC1);
+    let adc = Adc::new_with_config(p.ADC1, Default::default());
-    let adc2 = Adc::new(p.ADC2);
+    let adc2 = Adc::new_with_config(p.ADC2, Default::default());
    let mut adc: RingBufferedAdc<embassy_stm32::peripherals::ADC1> = adc.into_ring_buffered(
        p.DMA2_CH0,
        adc_data,
        [
-            (&mut p.PA0.degrade_adc(), SampleTime::CYCLES112),
+            (p.PA0.degrade_adc(), SampleTime::CYCLES112),
-            (&mut p.PA2.degrade_adc(), SampleTime::CYCLES112),
+            (p.PA2.degrade_adc(), SampleTime::CYCLES112),
        ]
        .into_iter(),
+        RegularConversionMode::Continuous,
    );
    let mut adc2: RingBufferedAdc<embassy_stm32::peripherals::ADC2> = adc2.into_ring_buffered(
        p.DMA2_CH2,
        adc_data2,
        [
-            (&mut p.PA1.degrade_adc(), SampleTime::CYCLES112),
+            (p.PA1.degrade_adc(), SampleTime::CYCLES112),
-            (&mut p.PA3.degrade_adc(), SampleTime::CYCLES112),
+            (p.PA3.degrade_adc(), SampleTime::CYCLES112),
        ]
        .into_iter(),
+        RegularConversionMode::Continuous,
    );
    // Note that overrun is a big consideration in this implementation. Whatever task is running the adc.read() calls absolutely must circle back around
diff --git a/examples/stm32f4/src/bin/usb_hid_keyboard.rs b/examples/stm32f4/src/bin/usb_hid_keyboard.rs
index a3afb887c..9971e43f5 100644
--- a/examples/stm32f4/src/bin/usb_hid_keyboard.rs
+++ b/examples/stm32f4/src/bin/usb_hid_keyboard.rs
@@ -1,7 +1,7 @@
 #![no_std]
 #![no_main]
-use core::sync::atomic::{AtomicBool, Ordering};
+use core::sync::atomic::{AtomicBool, AtomicU8, Ordering};
 use defmt::*;
 use embassy_executor::Spawner;
@@ -11,7 +11,9 @@ use embassy_stm32::gpio::Pull;
 use embassy_stm32::time::Hertz;
 use embassy_stm32::usb::Driver;
 use embassy_stm32::{Config, bind_interrupts, peripherals, usb};
-use embassy_usb::class::hid::{HidReaderWriter, ReportId, RequestHandler, State};
+use embassy_usb::class::hid::{
+    HidBootProtocol, HidProtocolMode, HidReaderWriter, HidSubclass, ReportId, RequestHandler, State,
+};
 use embassy_usb::control::OutResponse;
 use embassy_usb::{Builder, Handler};
 use usbd_hid::descriptor::{KeyboardReport, SerializedDescriptor};
@@ -21,6 +23,8 @@ bind_interrupts!(struct Irqs {
    OTG_FS => usb::InterruptHandler<peripherals::USB_OTG_FS>;
 });
+static HID_PROTOCOL_MODE: AtomicU8 = AtomicU8::new(HidProtocolMode::Boot as u8);
 // If you are trying this and your USB device doesn't connect, the most
 // common issues are the RCC config and vbus_detection
 //
@@ -70,6 +74,10 @@ async fn main(_spawner: Spawner) {
    config.serial_number = Some("12345678");
    config.max_power = 100;
    config.max_packet_size_0 = 64;
+    config.composite_with_iads = false;
+    config.device_class = 0;
+    config.device_sub_class = 0;
+    config.device_protocol = 0;
    // Create embassy-usb DeviceBuilder using the driver and config.
    // It needs some buffers for building the descriptors.
@@ -101,6 +109,8 @@ async fn main(_spawner: Spawner) {
        request_handler: None,
        poll_ms: 60,
        max_packet_size: 8,
+        hid_subclass: HidSubclass::Boot,
+        hid_boot_protocol: HidBootProtocol::Keyboard,
    };
    let hid = HidReaderWriter::<_, 1, 8>::new(&mut builder, &mut state, config);
@@ -121,32 +131,46 @@ async fn main(_spawner: Spawner) {
            button.wait_for_rising_edge().await;
            // signal_pin.wait_for_high().await;
            info!("Button pressed!");
-            // Create a report with the A key pressed. (no shift modifier)
+            if HID_PROTOCOL_MODE.load(Ordering::Relaxed) == HidProtocolMode::Boot as u8 {
-            let report = KeyboardReport {
+                match writer.write(&[0, 0, 4, 0, 0, 0, 0, 0]).await {
-                keycodes: [4, 0, 0, 0, 0, 0],
+                    Ok(()) => {}
-                leds: 0,
+                    Err(e) => warn!("Failed to send boot report: {:?}", e),
-                modifier: 0,
+                };
-                reserved: 0,
+            } else {
-            };
+                // Create a report with the A key pressed. (no shift modifier)
-            // Send the report.
+                let report = KeyboardReport {
-            match writer.write_serialize(&report).await {
+                    keycodes: [4, 0, 0, 0, 0, 0],
-                Ok(()) => {}
+                    leds: 0,
-                Err(e) => warn!("Failed to send report: {:?}", e),
+                    modifier: 0,
-            };
+                    reserved: 0,
+                };
+                // Send the report.
+                match writer.write_serialize(&report).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send report: {:?}", e),
+                };
+            }
            button.wait_for_falling_edge().await;
            // signal_pin.wait_for_low().await;
            info!("Button released!");
-            let report = KeyboardReport {
+            if HID_PROTOCOL_MODE.load(Ordering::Relaxed) == HidProtocolMode::Boot as u8 {
-                keycodes: [0, 0, 0, 0, 0, 0],
+                match writer.write(&[0, 0, 0, 0, 0, 0, 0, 0]).await {
-                leds: 0,
+                    Ok(()) => {}
-                modifier: 0,
+                    Err(e) => warn!("Failed to send boot report: {:?}", e),
-                reserved: 0,
+                };
-            };
+            } else {
-            match writer.write_serialize(&report).await {
+                let report = KeyboardReport {
-                Ok(()) => {}
+                    keycodes: [0, 0, 0, 0, 0, 0],
-                Err(e) => warn!("Failed to send report: {:?}", e),
+                    leds: 0,
-            };
+                    modifier: 0,
+                    reserved: 0,
+                };
+                match writer.write_serialize(&report).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send report: {:?}", e),
+                };
+            }
        }
    };
@@ -172,6 +196,18 @@ impl RequestHandler for MyRequestHandler {
        OutResponse::Accepted
    }
+    fn get_protocol(&self) -> HidProtocolMode {
+        let protocol = HidProtocolMode::from(HID_PROTOCOL_MODE.load(Ordering::Relaxed));
+        info!("The current HID protocol mode is: {}", protocol);
+        protocol
+    }
+    fn set_protocol(&mut self, protocol: HidProtocolMode) -> OutResponse {
+        info!("Switching to HID protocol mode: {}", protocol);
+        HID_PROTOCOL_MODE.store(protocol as u8, Ordering::Relaxed);
+        OutResponse::Accepted
+    }
    fn set_idle_ms(&mut self, id: Option<ReportId>, dur: u32) {
        info!("Set idle rate for {:?} to {:?}", id, dur);
    }
diff --git a/examples/stm32f4/src/bin/usb_hid_mouse.rs b/examples/stm32f4/src/bin/usb_hid_mouse.rs
index 162a035f2..e83d01f88 100644
--- a/examples/stm32f4/src/bin/usb_hid_mouse.rs
+++ b/examples/stm32f4/src/bin/usb_hid_mouse.rs
@@ -1,6 +1,8 @@
 #![no_std]
 #![no_main]
+use core::sync::atomic::{AtomicU8, Ordering};
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_futures::join::join;
@@ -9,7 +11,9 @@ use embassy_stm32::usb::Driver;
 use embassy_stm32::{Config, bind_interrupts, peripherals, usb};
 use embassy_time::Timer;
 use embassy_usb::Builder;
-use embassy_usb::class::hid::{HidWriter, ReportId, RequestHandler, State};
+use embassy_usb::class::hid::{
+    HidBootProtocol, HidProtocolMode, HidSubclass, HidWriter, ReportId, RequestHandler, State,
+};
 use embassy_usb::control::OutResponse;
 use usbd_hid::descriptor::{MouseReport, SerializedDescriptor};
 use {defmt_rtt as _, panic_probe as _};
@@ -18,6 +22,8 @@ bind_interrupts!(struct Irqs {
    OTG_FS => usb::InterruptHandler<peripherals::USB_OTG_FS>;
 });
+static HID_PROTOCOL_MODE: AtomicU8 = AtomicU8::new(HidProtocolMode::Boot as u8);
 // If you are trying this and your USB device doesn't connect, the most
 // common issues are the RCC config and vbus_detection
 //
@@ -65,6 +71,10 @@ async fn main(_spawner: Spawner) {
    config.manufacturer = Some("Embassy");
    config.product = Some("HID mouse example");
    config.serial_number = Some("12345678");
+    config.composite_with_iads = false;
+    config.device_class = 0;
+    config.device_sub_class = 0;
+    config.device_protocol = 0;
    // Create embassy-usb DeviceBuilder using the driver and config.
    // It needs some buffers for building the descriptors.
@@ -91,6 +101,8 @@ async fn main(_spawner: Spawner) {
        request_handler: Some(&mut request_handler),
        poll_ms: 60,
        max_packet_size: 8,
+        hid_subclass: HidSubclass::Boot,
+        hid_boot_protocol: HidBootProtocol::Mouse,
    };
    let mut writer = HidWriter::<_, 5>::new(&mut builder, &mut state, config);
@@ -108,16 +120,26 @@ async fn main(_spawner: Spawner) {
            Timer::after_millis(500).await;
            y = -y;
-            let report = MouseReport {
-                buttons: 0,
+            if HID_PROTOCOL_MODE.load(Ordering::Relaxed) == HidProtocolMode::Boot as u8 {
-                x: 0,
+                let buttons = 0u8;
-                y,
+                let x = 0i8;
-                wheel: 0,
+                match writer.write(&[buttons, x as u8, y as u8]).await {
-                pan: 0,
+                    Ok(()) => {}
-            };
+                    Err(e) => warn!("Failed to send boot report: {:?}", e),
-            match writer.write_serialize(&report).await {
+                }
-                Ok(()) => {}
+            } else {
-                Err(e) => warn!("Failed to send report: {:?}", e),
+                let report = MouseReport {
+                    buttons: 0,
+                    x: 0,
+                    y,
+                    wheel: 0,
+                    pan: 0,
+                };
+                match writer.write_serialize(&report).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send report: {:?}", e),
+                }
            }
        }
    };
@@ -140,6 +162,18 @@ impl RequestHandler for MyRequestHandler {
        OutResponse::Accepted
    }
+    fn get_protocol(&self) -> HidProtocolMode {
+        let protocol = HidProtocolMode::from(HID_PROTOCOL_MODE.load(Ordering::Relaxed));
+        info!("The current HID protocol mode is: {}", protocol);
+        protocol
+    }
+    fn set_protocol(&mut self, protocol: HidProtocolMode) -> OutResponse {
+        info!("Switching to HID protocol mode: {}", protocol);
+        HID_PROTOCOL_MODE.store(protocol as u8, Ordering::Relaxed);
+        OutResponse::Accepted
+    }
    fn set_idle_ms(&mut self, id: Option<ReportId>, dur: u32) {
        info!("Set idle rate for {:?} to {:?}", id, dur);
    }
diff --git a/examples/stm32f469/src/bin/dsi_bsp.rs b/examples/stm32f469/src/bin/dsi_bsp.rs
index d659291ff..7ba4da72b 100644
--- a/examples/stm32f469/src/bin/dsi_bsp.rs
+++ b/examples/stm32f469/src/bin/dsi_bsp.rs
@@ -3,7 +3,7 @@
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::dsihost::{DsiHost, PacketType, blocking_delay_ms};
+use embassy_stm32::dsihost::{DsiHost, PacketType};
 use embassy_stm32::gpio::{Level, Output, Speed};
 use embassy_stm32::ltdc::Ltdc;
 use embassy_stm32::pac::dsihost::regs::{Ier0, Ier1};
@@ -13,7 +13,7 @@ use embassy_stm32::rcc::{
    AHBPrescaler, APBPrescaler, Hse, HseMode, Pll, PllMul, PllPDiv, PllPreDiv, PllQDiv, PllRDiv, PllSource, Sysclk,
 };
 use embassy_stm32::time::mhz;
-use embassy_time::Timer;
+use embassy_time::{Duration, Timer, block_for};
 use {defmt_rtt as _, panic_probe as _};
 enum _Orientation {
@@ -444,7 +444,7 @@ async fn main(_spawner: Spawner) {
    dsi.enable_wrapper_dsi();
    // First, delay 120 ms (reason unknown, STM32 Cube Example does it)
-    blocking_delay_ms(120);
+    block_for(Duration::from_millis(120));
    // 1 to 26
    dsi.write_cmd(0, NT35510_WRITES_0[0], &NT35510_WRITES_0[1..]).unwrap();
@@ -480,7 +480,7 @@ async fn main(_spawner: Spawner) {
    dsi.write_cmd(0, NT35510_WRITES_37[0], &NT35510_WRITES_37[1..]).unwrap();
    // Add a delay, otherwise MADCTL not taken
-    blocking_delay_ms(200);
+    block_for(Duration::from_millis(200));
    // Configure orientation as landscape
    dsi.write_cmd(0, NT35510_MADCTL_LANDSCAPE[0], &NT35510_MADCTL_LANDSCAPE[1..])
@@ -494,7 +494,7 @@ async fn main(_spawner: Spawner) {
    dsi.write_cmd(0, NT35510_WRITES_27[0], &NT35510_WRITES_27[1..]).unwrap();
    // Wait for sleep out exit
-    blocking_delay_ms(120);
+    block_for(Duration::from_millis(120));
    // Configure COLOR_CODING
    dsi.write_cmd(0, NT35510_WRITES_37[0], &NT35510_WRITES_37[1..]).unwrap();
@@ -590,7 +590,7 @@ async fn main(_spawner: Spawner) {
    //LTDC->SRCR = LTDC_SRCR_IMR;
    LTDC.srcr().modify(|w| w.set_imr(Imr::RELOAD));
-    blocking_delay_ms(5000);
+    block_for(Duration::from_millis(5000));
    const READ_SIZE: u16 = 1;
    let mut data = [1u8; READ_SIZE as usize];
@@ -606,7 +606,7 @@ async fn main(_spawner: Spawner) {
        .unwrap();
    info!("Display ID3: {:#04x}", data);
-    blocking_delay_ms(500);
+    block_for(Duration::from_millis(500));
    info!("Config done, start blinking LED");
    loop {
diff --git a/examples/stm32f7/src/bin/adc.rs b/examples/stm32f7/src/bin/adc.rs
index 6689e3b5d..0f226d34e 100644
--- a/examples/stm32f7/src/bin/adc.rs
+++ b/examples/stm32f7/src/bin/adc.rs
@@ -3,7 +3,7 @@
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::adc::Adc;
+use embassy_stm32::adc::{Adc, SampleTime};
 use embassy_time::Timer;
 use {defmt_rtt as _, panic_probe as _};
@@ -16,7 +16,7 @@ async fn main(_spawner: Spawner) {
    let mut pin = p.PA3;
    let mut vrefint = adc.enable_vrefint();
-    let vrefint_sample = adc.blocking_read(&mut vrefint);
+    let vrefint_sample = adc.blocking_read(&mut vrefint, SampleTime::CYCLES112);
    let convert_to_millivolts = |sample| {
        // From http://www.st.com/resource/en/datasheet/DM00273119.pdf
        // 6.3.27 Reference voltage
@@ -26,7 +26,7 @@ async fn main(_spawner: Spawner) {
    };
    loop {
-        let v = adc.blocking_read(&mut pin);
+        let v = adc.blocking_read(&mut pin, SampleTime::CYCLES112);
        info!("--> {} - {} mV", v, convert_to_millivolts(v));
        Timer::after_millis(100).await;
    }
diff --git a/examples/stm32g0/src/bin/adc.rs b/examples/stm32g0/src/bin/adc.rs
index 7d8653ef2..972e43b55 100644
--- a/examples/stm32g0/src/bin/adc.rs
+++ b/examples/stm32g0/src/bin/adc.rs
@@ -13,11 +13,10 @@ async fn main(_spawner: Spawner) {
    info!("Hello World!");
    let mut adc = Adc::new_with_clock(p.ADC1, Clock::Async { div: Presc::DIV1 });
-    adc.set_sample_time(SampleTime::CYCLES79_5);
    let mut pin = p.PA1;
    let mut vrefint = adc.enable_vrefint();
-    let vrefint_sample = adc.blocking_read(&mut vrefint);
+    let vrefint_sample = adc.blocking_read(&mut vrefint, SampleTime::CYCLES79_5);
    let convert_to_millivolts = |sample| {
        // From https://www.st.com/resource/en/datasheet/stm32g031g8.pdf
        // 6.3.3 Embedded internal reference voltage
@@ -27,7 +26,7 @@ async fn main(_spawner: Spawner) {
    };
    loop {
-        let v = adc.blocking_read(&mut pin);
+        let v = adc.blocking_read(&mut pin, SampleTime::CYCLES79_5);
        info!("--> {} - {} mV", v, convert_to_millivolts(v));
        Timer::after_millis(100).await;
    }
diff --git a/examples/stm32g0/src/bin/adc_oversampling.rs b/examples/stm32g0/src/bin/adc_oversampling.rs
index 834d1cd4a..aa8b1771b 100644
--- a/examples/stm32g0/src/bin/adc_oversampling.rs
+++ b/examples/stm32g0/src/bin/adc_oversampling.rs
@@ -7,7 +7,7 @@
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::adc::{Adc, Clock, Ovsr, Ovss, Presc, SampleTime};
+use embassy_stm32::adc::{Adc, AdcConfig, Clock, Ovsr, Ovss, Presc, SampleTime};
 use embassy_time::Timer;
 use {defmt_rtt as _, panic_probe as _};
@@ -16,16 +16,17 @@ async fn main(_spawner: Spawner) {
    let p = embassy_stm32::init(Default::default());
    info!("Adc oversample test");
-    let mut adc = Adc::new_with_clock(p.ADC1, Clock::Async { div: Presc::DIV1 });
+    let mut config = AdcConfig::default();
-    adc.set_sample_time(SampleTime::CYCLES1_5);
+    config.clock = Some(Clock::Async { div: Presc::DIV1 });
-    let mut pin = p.PA1;
+    config.oversampling_ratio = Some(Ovsr::MUL16);
+    config.oversampling_shift = Some(Ovss::NO_SHIFT);
+    config.oversampling_enable = Some(true);
-    adc.set_oversampling_ratio(Ovsr::MUL16);
+    let mut adc = Adc::new_with_config(p.ADC1, config);
-    adc.set_oversampling_shift(Ovss::NO_SHIFT);
+    let mut pin = p.PA1;
-    adc.oversampling_enable(true);
    loop {
-        let v = adc.blocking_read(&mut pin);
+        let v = adc.blocking_read(&mut pin, SampleTime::CYCLES1_5);
        info!("--> {} ", v); //max 65520 = 0xFFF0
        Timer::after_millis(100).await;
    }
diff --git a/examples/stm32g4/src/bin/adc.rs b/examples/stm32g4/src/bin/adc.rs
index 920142a18..2149e0748 100644
--- a/examples/stm32g4/src/bin/adc.rs
+++ b/examples/stm32g4/src/bin/adc.rs
@@ -28,12 +28,16 @@ async fn main(_spawner: Spawner) {
    let mut p = embassy_stm32::init(config);
    info!("Hello World!");
-    let mut adc = Adc::new(p.ADC2);
+    let mut adc = Adc::new(p.ADC2, Default::default());
-    adc.set_sample_time(SampleTime::CYCLES24_5);
+    let mut adc_temp = Adc::new(p.ADC1, Default::default());
+    let mut temperature = adc_temp.enable_temperature();
    loop {
-        let measured = adc.blocking_read(&mut p.PA7);
+        let measured = adc.blocking_read(&mut p.PA7, SampleTime::CYCLES24_5);
+        let temperature = adc_temp.blocking_read(&mut temperature, SampleTime::CYCLES24_5);
        info!("measured: {}", measured);
+        info!("temperature: {}", temperature);
        Timer::after_millis(500).await;
    }
 }
diff --git a/examples/stm32g4/src/bin/adc_differential.rs b/examples/stm32g4/src/bin/adc_differential.rs
index 301f0da84..6dedf88d6 100644
--- a/examples/stm32g4/src/bin/adc_differential.rs
+++ b/examples/stm32g4/src/bin/adc_differential.rs
@@ -30,17 +30,16 @@ async fn main(_spawner: Spawner) {
        config.rcc.mux.adc12sel = mux::Adcsel::SYS;
        config.rcc.sys = Sysclk::PLL1_R;
    }
-    let mut p = embassy_stm32::init(config);
+    let p = embassy_stm32::init(config);
-    let mut adc = Adc::new(p.ADC1);
+    let mut adc = Adc::new(p.ADC1, Default::default());
-    adc.set_sample_time(SampleTime::CYCLES247_5);
+    let mut differential_channel = (p.PA0, p.PA1);
-    adc.set_differential(&mut p.PA0, true); //p:pa0,n:pa1
    // can also use
    // adc.set_differential_channel(1, true);
    info!("adc initialized");
    loop {
-        let measured = adc.blocking_read(&mut p.PA0);
+        let measured = adc.blocking_read(&mut differential_channel, SampleTime::CYCLES247_5);
        info!("data: {}", measured);
        Timer::after_millis(500).await;
    }
diff --git a/examples/stm32g4/src/bin/adc_dma.rs b/examples/stm32g4/src/bin/adc_dma.rs
index ef8b0c3c2..478b6b2ca 100644
--- a/examples/stm32g4/src/bin/adc_dma.rs
+++ b/examples/stm32g4/src/bin/adc_dma.rs
@@ -33,7 +33,7 @@ async fn main(_spawner: Spawner) {
    info!("Hello World!");
-    let mut adc = Adc::new(p.ADC1);
+    let mut adc = Adc::new(p.ADC1, Default::default());
    let mut dma = p.DMA1_CH1;
    let mut vrefint_channel = adc.enable_vrefint().degrade_adc();
diff --git a/examples/stm32g4/src/bin/adc_injected_and_regular.rs b/examples/stm32g4/src/bin/adc_injected_and_regular.rs
index 3ae2ff064..1e97fa925 100644
--- a/examples/stm32g4/src/bin/adc_injected_and_regular.rs
+++ b/examples/stm32g4/src/bin/adc_injected_and_regular.rs
@@ -77,7 +77,7 @@ async fn main(_spawner: embassy_executor::Spawner) {
    pwm.set_mms2(Mms2::UPDATE);
    // Configure regular conversions with DMA
-    let adc1 = Adc::new(p.ADC1);
+    let adc1 = Adc::new(p.ADC1, Default::default());
    let vrefint_channel = adc1.enable_vrefint().degrade_adc();
    let pa0 = p.PC1.degrade_adc();
diff --git a/examples/stm32g4/src/bin/adc_oversampling.rs b/examples/stm32g4/src/bin/adc_oversampling.rs
index 1e464183a..87ffea4be 100644
--- a/examples/stm32g4/src/bin/adc_oversampling.rs
+++ b/examples/stm32g4/src/bin/adc_oversampling.rs
@@ -9,7 +9,7 @@ use defmt::*;
 use embassy_executor::Spawner;
 use embassy_stm32::Config;
 use embassy_stm32::adc::vals::{Rovsm, Trovs};
-use embassy_stm32::adc::{Adc, SampleTime};
+use embassy_stm32::adc::{Adc, AdcConfig, SampleTime};
 use embassy_time::Timer;
 use {defmt_rtt as _, panic_probe as _};
@@ -32,8 +32,8 @@ async fn main(_spawner: Spawner) {
    }
    let mut p = embassy_stm32::init(config);
-    let mut adc = Adc::new(p.ADC1);
+    let mut config = AdcConfig::default();
-    adc.set_sample_time(SampleTime::CYCLES6_5);
    // From https://www.st.com/resource/en/reference_manual/rm0440-stm32g4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
    // page652 Oversampler
    // Table 172. Maximum output results vs N and M. Grayed values indicates truncation
@@ -45,12 +45,14 @@ async fn main(_spawner: Spawner) {
    // 0x05 oversampling ratio X64
    // 0x06 oversampling ratio X128
    // 0x07 oversampling ratio X256
-    adc.set_oversampling_ratio(0x03); // ratio X3
+    config.oversampling_ratio = Some(0x03); // ratio X3
-    adc.set_oversampling_shift(0b0000); // no shift
+    config.oversampling_shift = Some(0b0000); // no shift
-    adc.enable_regular_oversampling_mode(Rovsm::RESUMED, Trovs::AUTOMATIC, true);
+    config.oversampling_mode = Some((Rovsm::RESUMED, Trovs::AUTOMATIC, true));
+    let mut adc = Adc::new(p.ADC1, config);
    loop {
-        let measured = adc.blocking_read(&mut p.PA0);
+        let measured = adc.blocking_read(&mut p.PA0, SampleTime::CYCLES6_5);
        info!("data: 0x{:X}", measured); //max 0xFFF0 -> 65520
        Timer::after_millis(500).await;
    }
diff --git a/examples/stm32h5/src/bin/adc.rs b/examples/stm32h5/src/bin/adc.rs
index 0566320d4..c919b1a95 100644
--- a/examples/stm32h5/src/bin/adc.rs
+++ b/examples/stm32h5/src/bin/adc.rs
@@ -45,14 +45,12 @@ async fn main(_spawner: Spawner) {
    let mut adc = Adc::new(p.ADC1);
-    adc.set_sample_time(SampleTime::CYCLES24_5);
    let mut vrefint_channel = adc.enable_vrefint();
    loop {
-        let vrefint = adc.blocking_read(&mut vrefint_channel);
+        let vrefint = adc.blocking_read(&mut vrefint_channel, SampleTime::CYCLES24_5);
        info!("vrefint: {}", vrefint);
-        let measured = adc.blocking_read(&mut p.PA0);
+        let measured = adc.blocking_read(&mut p.PA0, SampleTime::CYCLES24_5);
        info!("measured: {}", measured);
        Timer::after_millis(500).await;
    }
diff --git a/examples/stm32h5/src/bin/adc_dma.rs b/examples/stm32h5/src/bin/adc_dma.rs
index fb9fcbc5c..2138257f7 100644
--- a/examples/stm32h5/src/bin/adc_dma.rs
+++ b/examples/stm32h5/src/bin/adc_dma.rs
@@ -6,7 +6,7 @@ use embassy_executor::Spawner;
 use embassy_stm32::adc::{self, Adc, AdcChannel, RxDma, SampleTime};
 use embassy_stm32::peripherals::{ADC1, ADC2, GPDMA1_CH0, GPDMA1_CH1, PA0, PA1, PA2, PA3};
 use embassy_stm32::{Config, Peri};
-use embassy_time::Instant;
+use embassy_time::{Duration, Instant, Ticker};
 use {defmt_rtt as _, panic_probe as _};
 #[embassy_executor::main]
@@ -76,6 +76,9 @@ async fn adc_task<'a, T: adc::Instance>(
    let mut pin1 = pin1.degrade_adc();
    let mut pin2 = pin2.degrade_adc();
+    info!("adc init");
+    let mut ticker = Ticker::every(Duration::from_millis(500));
    let mut tic = Instant::now();
    let mut buffer = [0u16; 512];
    loop {
@@ -84,11 +87,13 @@ async fn adc_task<'a, T: adc::Instance>(
        adc.read(
            dma.reborrow(),
            [(&mut pin1, SampleTime::CYCLES2_5), (&mut pin2, SampleTime::CYCLES2_5)].into_iter(),
-            &mut buffer,
+            &mut buffer[0..2],
        )
        .await;
        let toc = Instant::now();
        info!("\n adc1: {} dt = {}", buffer[0..16], (toc - tic).as_micros());
        tic = toc;
+        ticker.next().await;
    }
 }
diff --git a/examples/stm32h7/src/bin/adc.rs b/examples/stm32h7/src/bin/adc.rs
index a53c9d8d5..fc45541bf 100644
--- a/examples/stm32h7/src/bin/adc.rs
+++ b/examples/stm32h7/src/bin/adc.rs
@@ -46,14 +46,12 @@ async fn main(_spawner: Spawner) {
    let mut adc = Adc::new(p.ADC3);
-    adc.set_sample_time(SampleTime::CYCLES32_5);
    let mut vrefint_channel = adc.enable_vrefint();
    loop {
-        let vrefint = adc.blocking_read(&mut vrefint_channel);
+        let vrefint = adc.blocking_read(&mut vrefint_channel, SampleTime::CYCLES32_5);
        info!("vrefint: {}", vrefint);
-        let measured = adc.blocking_read(&mut p.PC0);
+        let measured = adc.blocking_read(&mut p.PC0, SampleTime::CYCLES32_5);
        info!("measured: {}", measured);
        Timer::after_millis(500).await;
    }
diff --git a/examples/stm32l0/src/bin/adc.rs b/examples/stm32l0/src/bin/adc.rs
index 9dd09bc45..83be74ed9 100644
--- a/examples/stm32l0/src/bin/adc.rs
+++ b/examples/stm32l0/src/bin/adc.rs
@@ -19,11 +19,10 @@ async fn main(_spawner: Spawner) {
    info!("Hello World!");
    let mut adc = Adc::new(p.ADC1, Irqs);
-    adc.set_sample_time(SampleTime::CYCLES79_5);
    let mut pin = p.PA1;
    let mut vrefint = adc.enable_vref();
-    let vrefint_sample = adc.read(&mut vrefint).await;
+    let vrefint_sample = adc.read(&mut vrefint, SampleTime::CYCLES79_5).await;
    let convert_to_millivolts = |sample| {
        // From https://www.st.com/resource/en/datasheet/stm32l051c6.pdf
        // 6.3.3 Embedded internal reference voltage
@@ -33,7 +32,7 @@ async fn main(_spawner: Spawner) {
    };
    loop {
-        let v = adc.read(&mut pin).await;
+        let v = adc.read(&mut pin, SampleTime::CYCLES79_5).await;
        info!("--> {} - {} mV", v, convert_to_millivolts(v));
        Timer::after_millis(100).await;
    }
diff --git a/examples/stm32l4/src/bin/adc.rs b/examples/stm32l4/src/bin/adc.rs
index 40e907940..42766a5e3 100644
--- a/examples/stm32l4/src/bin/adc.rs
+++ b/examples/stm32l4/src/bin/adc.rs
@@ -3,7 +3,7 @@
 use defmt::*;
 use embassy_stm32::Config;
-use embassy_stm32::adc::{Adc, Resolution};
+use embassy_stm32::adc::{Adc, AdcConfig, Resolution, SampleTime};
 use {defmt_rtt as _, panic_probe as _};
 #[cortex_m_rt::entry]
@@ -17,13 +17,16 @@ fn main() -> ! {
    }
    let p = embassy_stm32::init(config);
-    let mut adc = Adc::new(p.ADC1);
+    let mut config = AdcConfig::default();
+    config.resolution = Some(Resolution::BITS8);
+    let mut adc = Adc::new_with_config(p.ADC1, config);
    //adc.enable_vref();
-    adc.set_resolution(Resolution::BITS8);
    let mut channel = p.PC0;
    loop {
-        let v = adc.blocking_read(&mut channel);
+        let v = adc.blocking_read(&mut channel, SampleTime::from_bits(0));
        info!("--> {}", v);
    }
 }
diff --git a/examples/stm32l4/src/bin/adc_dma.rs b/examples/stm32l4/src/bin/adc_dma.rs
index 7a9200edd..550da95a4 100644
--- a/examples/stm32l4/src/bin/adc_dma.rs
+++ b/examples/stm32l4/src/bin/adc_dma.rs
@@ -4,7 +4,7 @@
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_stm32::Config;
-use embassy_stm32::adc::{Adc, AdcChannel, SampleTime};
+use embassy_stm32::adc::{Adc, AdcChannel, RegularConversionMode, SampleTime};
 use {defmt_rtt as _, panic_probe as _};
 const DMA_BUF_LEN: usize = 512;
@@ -20,19 +20,16 @@ async fn main(_spawner: Spawner) {
    }
    let p = embassy_stm32::init(config);
-    let mut adc = Adc::new(p.ADC1);
+    let adc = Adc::new(p.ADC1);
-    let mut adc_pin0 = p.PA0.degrade_adc();
+    let adc_pin0 = p.PA0.degrade_adc();
-    let mut adc_pin1 = p.PA1.degrade_adc();
+    let adc_pin1 = p.PA1.degrade_adc();
    let mut adc_dma_buf = [0u16; DMA_BUF_LEN];
    let mut measurements = [0u16; DMA_BUF_LEN / 2];
    let mut ring_buffered_adc = adc.into_ring_buffered(
        p.DMA1_CH1,
        &mut adc_dma_buf,
-        [
+        [(adc_pin0, SampleTime::CYCLES640_5), (adc_pin1, SampleTime::CYCLES640_5)].into_iter(),
-            (&mut adc_pin0, SampleTime::CYCLES640_5),
+        RegularConversionMode::Continuous,
-            (&mut adc_pin1, SampleTime::CYCLES640_5),
-        ]
-        .into_iter(),
    );
    info!("starting measurement loop");
diff --git a/examples/stm32l5/src/bin/usb_hid_mouse.rs b/examples/stm32l5/src/bin/usb_hid_mouse.rs
index b721f5b2e..d8f2de941 100644
--- a/examples/stm32l5/src/bin/usb_hid_mouse.rs
+++ b/examples/stm32l5/src/bin/usb_hid_mouse.rs
@@ -1,6 +1,8 @@
 #![no_std]
 #![no_main]
+use core::sync::atomic::{AtomicU8, Ordering};
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_futures::join::join;
@@ -8,7 +10,9 @@ use embassy_stm32::usb::Driver;
 use embassy_stm32::{Config, bind_interrupts, peripherals, usb};
 use embassy_time::Timer;
 use embassy_usb::Builder;
-use embassy_usb::class::hid::{HidWriter, ReportId, RequestHandler, State};
+use embassy_usb::class::hid::{
+    HidBootProtocol, HidProtocolMode, HidSubclass, HidWriter, ReportId, RequestHandler, State,
+};
 use embassy_usb::control::OutResponse;
 use usbd_hid::descriptor::{MouseReport, SerializedDescriptor};
 use {defmt_rtt as _, panic_probe as _};
@@ -17,6 +21,8 @@ bind_interrupts!(struct Irqs {
    USB_FS => usb::InterruptHandler<peripherals::USB>;
 });
+static HID_PROTOCOL_MODE: AtomicU8 = AtomicU8::new(HidProtocolMode::Boot as u8);
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
    let mut config = Config::default();
@@ -48,6 +54,10 @@ async fn main(_spawner: Spawner) {
    config.serial_number = Some("12345678");
    config.max_power = 100;
    config.max_packet_size_0 = 64;
+    config.composite_with_iads = false;
+    config.device_class = 0;
+    config.device_sub_class = 0;
+    config.device_protocol = 0;
    // Create embassy-usb DeviceBuilder using the driver and config.
    // It needs some buffers for building the descriptors.
@@ -73,6 +83,8 @@ async fn main(_spawner: Spawner) {
        request_handler: Some(&mut request_handler),
        poll_ms: 60,
        max_packet_size: 8,
+        hid_subclass: HidSubclass::Boot,
+        hid_boot_protocol: HidBootProtocol::Mouse,
    };
    let mut writer = HidWriter::<_, 5>::new(&mut builder, &mut state, config);
@@ -90,16 +102,26 @@ async fn main(_spawner: Spawner) {
            Timer::after_millis(500).await;
            y = -y;
-            let report = MouseReport {
-                buttons: 0,
+            if HID_PROTOCOL_MODE.load(Ordering::Relaxed) == HidProtocolMode::Boot as u8 {
-                x: 0,
+                let buttons = 0u8;
-                y,
+                let x = 0i8;
-                wheel: 0,
+                match writer.write(&[buttons, x as u8, y as u8]).await {
-                pan: 0,
+                    Ok(()) => {}
-            };
+                    Err(e) => warn!("Failed to send boot report: {:?}", e),
-            match writer.write_serialize(&report).await {
+                }
-                Ok(()) => {}
+            } else {
-                Err(e) => warn!("Failed to send report: {:?}", e),
+                let report = MouseReport {
+                    buttons: 0,
+                    x: 0,
+                    y,
+                    wheel: 0,
+                    pan: 0,
+                };
+                match writer.write_serialize(&report).await {
+                    Ok(()) => {}
+                    Err(e) => warn!("Failed to send report: {:?}", e),
+                }
            }
        }
    };
@@ -122,6 +144,18 @@ impl RequestHandler for MyRequestHandler {
        OutResponse::Accepted
    }
+    fn get_protocol(&self) -> HidProtocolMode {
+        let protocol = HidProtocolMode::from(HID_PROTOCOL_MODE.load(Ordering::Relaxed));
+        info!("The current HID protocol mode is: {}", protocol);
+        protocol
+    }
+    fn set_protocol(&mut self, protocol: HidProtocolMode) -> OutResponse {
+        info!("Switching to HID protocol mode: {}", protocol);
+        HID_PROTOCOL_MODE.store(protocol as u8, Ordering::Relaxed);
+        OutResponse::Accepted
+    }
    fn set_idle_ms(&mut self, id: Option<ReportId>, dur: u32) {
        info!("Set idle rate for {:?} to {:?}", id, dur);
    }
diff --git a/examples/stm32n6/.cargo/config.toml b/examples/stm32n6/.cargo/config.toml
new file mode 100644
index 000000000..2fdd70649
--- /dev/null
+++ b/examples/stm32n6/.cargo/config.toml
@@ -0,0 +1,8 @@
+[target.thumbv8m.main-none-eabihf]
+runner = 'probe-rs run --chip STM32N657'
+[build]
+target = "thumbv8m.main-none-eabihf"
+[env]
+DEFMT_LOG = "trace"
diff --git a/examples/stm32n6/Cargo.toml b/examples/stm32n6/Cargo.toml
new file mode 100644
index 000000000..5ed28eed1
--- /dev/null
+++ b/examples/stm32n6/Cargo.toml
@@ -0,0 +1,78 @@
+[package]
+edition = "2021"
+name = "embassy-stm32n6-examples"
+version = "0.1.0"
+license = "MIT OR Apache-2.0"
+publish = false
+[dependencies]
+# Change stm32h563zi to your chip name, if necessary.
+embassy-stm32 = { version = "0.4.0", path = "../../embassy-stm32", features = ["defmt", "stm32n657x0", "time-driver-any", "exti", "unstable-pac"] }
+embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt"] }
+embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
+embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
+embassy-net = { version = "0.7.1", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet", "proto-ipv6"] }
+embassy-usb = { version = "0.5.1", path = "../../embassy-usb", features = ["defmt"] }
+embassy-futures = { version = "0.1.2", path = "../../embassy-futures" }
+defmt = "1.0.1"
+defmt-rtt = "1.0.0"
+cortex-m = { version = "0.7.6", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = "0.7.0"
+embedded-hal = "0.2.6"
+embedded-hal-1 = { package = "embedded-hal", version = "1.0" }
+embedded-hal-async = { version = "1.0" }
+embedded-io-async = { version = "0.6.1" }
+embedded-nal-async = "0.8.0"
+panic-probe = { version = "1.0.0", features = ["print-defmt"] }
+heapless = { version = "0.8", default-features = false }
+critical-section = "1.1"
+micromath = "2.0.0"
+stm32-fmc = "0.3.0"
+embedded-storage = "0.3.1"
+static_cell = "2"
+# cargo build/run
+[profile.dev]
+codegen-units = 1
+debug = 2
+debug-assertions = true # <-
+incremental = false
+opt-level = 3 # <-
+overflow-checks = true # <-
+# cargo test
+[profile.test]
+codegen-units = 1
+debug = 2
+debug-assertions = true # <-
+incremental = false
+opt-level = 3 # <-
+overflow-checks = true # <-
+# cargo build/run --release
+[profile.release]
+codegen-units = 1
+debug = 2
+debug-assertions = false # <-
+incremental = false
+lto = 'fat'
+opt-level = 3 # <-
+overflow-checks = false # <-
+# cargo test --release
+[profile.bench]
+codegen-units = 1
+debug = 2
+debug-assertions = false # <-
+incremental = false
+lto = 'fat'
+opt-level = 3 # <-
+overflow-checks = false # <-
+[package.metadata.embassy]
+build = [
+  { target = "thumbv8m.main-none-eabihf", artifact-dir = "out/examples/stm32n6" }
+]
diff --git a/examples/stm32n6/build.rs b/examples/stm32n6/build.rs
new file mode 100644
index 000000000..8cd32d7ed
--- /dev/null
+++ b/examples/stm32n6/build.rs
@@ -0,0 +1,5 @@
+fn main() {
+    println!("cargo:rustc-link-arg-bins=--nmagic");
+    println!("cargo:rustc-link-arg-bins=-Tlink.x");
+    println!("cargo:rustc-link-arg-bins=-Tdefmt.x");
+}
diff --git a/examples/stm32n6/memory.x b/examples/stm32n6/memory.x
new file mode 100644
index 000000000..59f127adc
--- /dev/null
+++ b/examples/stm32n6/memory.x
@@ -0,0 +1,5 @@
+MEMORY
+{
+  FLASH       : ORIGIN = 0x34180400,   LENGTH = 255K
+  RAM         : ORIGIN = 0x341C0000,   LENGTH = 256K
+}
diff --git a/examples/stm32n6/src/bin/blinky.rs b/examples/stm32n6/src/bin/blinky.rs
new file mode 100644
index 000000000..018967f08
--- /dev/null
+++ b/examples/stm32n6/src/bin/blinky.rs
@@ -0,0 +1,36 @@
+#![no_std]
+#![no_main]
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::gpio::{Level, Output, Pull, Speed};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+#[embassy_executor::task]
+async fn button_task(mut p: ExtiInput<'static>) {
+    loop {
+        p.wait_for_any_edge().await;
+        info!("button pressed!");
+    }
+}
+#[embassy_executor::main]
+async fn main(spawner: Spawner) {
+    let p = embassy_stm32::init(Default::default());
+    info!("Hello World!");
+    let mut led = Output::new(p.PG10, Level::High, Speed::Low);
+    let button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up);
+    spawner.spawn(button_task(button).unwrap());
+    loop {
+        led.set_high();
+        Timer::after_millis(500).await;
+        led.set_low();
+        Timer::after_millis(500).await;
+    }
+}
diff --git a/examples/stm32u0/src/bin/adc.rs b/examples/stm32u0/src/bin/adc.rs
index 32a54299d..53bd37303 100644
--- a/examples/stm32u0/src/bin/adc.rs
+++ b/examples/stm32u0/src/bin/adc.rs
@@ -3,7 +3,7 @@
 use defmt::*;
 use embassy_stm32::Config;
-use embassy_stm32::adc::{Adc, Resolution};
+use embassy_stm32::adc::{Adc, AdcConfig, Resolution, SampleTime};
 use embassy_time::Duration;
 use {defmt_rtt as _, panic_probe as _};
@@ -18,12 +18,13 @@ fn main() -> ! {
    }
    let p = embassy_stm32::init(config);
-    let mut adc = Adc::new(p.ADC1);
+    let mut config = AdcConfig::default();
-    adc.set_resolution(Resolution::BITS8);
+    config.resolution = Some(Resolution::BITS8);
+    let mut adc = Adc::new_with_config(p.ADC1, config);
    let mut channel = p.PC0;
    loop {
-        let v = adc.blocking_read(&mut channel);
+        let v = adc.blocking_read(&mut channel, SampleTime::CYCLES12_5);
        info!("--> {}", v);
        embassy_time::block_for(Duration::from_millis(200));
    }
diff --git a/examples/stm32u5/src/bin/adc.rs b/examples/stm32u5/src/bin/adc.rs
index 91e33053e..ad59c0bea 100644
--- a/examples/stm32u5/src/bin/adc.rs
+++ b/examples/stm32u5/src/bin/adc.rs
@@ -2,8 +2,7 @@
 #![no_main]
 use defmt::*;
-use embassy_stm32::adc;
+use embassy_stm32::adc::{self, Adc, AdcChannel, AdcConfig, SampleTime, adc4};
-use embassy_stm32::adc::{AdcChannel, adc4};
 use {defmt_rtt as _, panic_probe as _};
 #[embassy_executor::main]
@@ -13,56 +12,55 @@ async fn main(_spawner: embassy_executor::Spawner) {
    let mut p = embassy_stm32::init(config);
    // **** ADC1 init ****
-    let mut adc1 = adc::Adc::new(p.ADC1);
+    let mut config = AdcConfig::default();
+    config.averaging = Some(adc::Averaging::Samples1024);
+    config.resolution = Some(adc::Resolution::BITS14);
+    let mut adc1 = Adc::new_with_config(p.ADC1, config);
    let mut adc1_pin1 = p.PA3; // A0 on nucleo u5a5
    let mut adc1_pin2 = p.PA2; // A1
-    adc1.set_resolution(adc::Resolution::BITS14);
-    adc1.set_averaging(adc::Averaging::Samples1024);
-    adc1.set_sample_time(adc::SampleTime::CYCLES160_5);
    let max1 = adc::resolution_to_max_count(adc::Resolution::BITS14);
    // **** ADC2 init ****
-    let mut adc2 = adc::Adc::new(p.ADC2);
+    let mut config = AdcConfig::default();
+    config.averaging = Some(adc::Averaging::Samples1024);
+    config.resolution = Some(adc::Resolution::BITS14);
+    let mut adc2 = Adc::new_with_config(p.ADC2, config);
    let mut adc2_pin1 = p.PC3; // A2
    let mut adc2_pin2 = p.PB0; // A3
-    adc2.set_resolution(adc::Resolution::BITS14);
-    adc2.set_averaging(adc::Averaging::Samples1024);
-    adc2.set_sample_time(adc::SampleTime::CYCLES160_5);
    let max2 = adc::resolution_to_max_count(adc::Resolution::BITS14);
    // **** ADC4 init ****
-    let mut adc4 = adc4::Adc4::new(p.ADC4);
+    let mut adc4 = Adc::new_adc4(p.ADC4);
    let mut adc4_pin1 = p.PC1; // A4
    let mut adc4_pin2 = p.PC0; // A5
-    adc4.set_resolution(adc4::Resolution::BITS12);
+    adc4.set_resolution_adc4(adc4::Resolution::BITS12);
-    adc4.set_averaging(adc4::Averaging::Samples256);
+    adc4.set_averaging_adc4(adc4::Averaging::Samples256);
-    adc4.set_sample_time(adc4::SampleTime::CYCLES1_5);
    let max4 = adc4::resolution_to_max_count(adc4::Resolution::BITS12);
    // **** ADC1 blocking read ****
-    let raw: u16 = adc1.blocking_read(&mut adc1_pin1);
+    let raw: u16 = adc1.blocking_read(&mut adc1_pin1, SampleTime::CYCLES160_5);
    let volt: f32 = 3.3 * raw as f32 / max1 as f32;
    info!("Read adc1 pin 1 {}", volt);
-    let raw: u16 = adc1.blocking_read(&mut adc1_pin2);
+    let raw: u16 = adc1.blocking_read(&mut adc1_pin2, SampleTime::CYCLES160_5);
    let volt: f32 = 3.3 * raw as f32 / max1 as f32;
    info!("Read adc1 pin 2 {}", volt);
    // **** ADC2 blocking read ****
-    let raw: u16 = adc2.blocking_read(&mut adc2_pin1);
+    let raw: u16 = adc2.blocking_read(&mut adc2_pin1, SampleTime::CYCLES160_5);
    let volt: f32 = 3.3 * raw as f32 / max2 as f32;
    info!("Read adc2 pin 1 {}", volt);
-    let raw: u16 = adc2.blocking_read(&mut adc2_pin2);
+    let raw: u16 = adc2.blocking_read(&mut adc2_pin2, SampleTime::CYCLES160_5);
    let volt: f32 = 3.3 * raw as f32 / max2 as f32;
    info!("Read adc2 pin 2 {}", volt);
    // **** ADC4 blocking read ****
-    let raw: u16 = adc4.blocking_read(&mut adc4_pin1);
+    let raw: u16 = adc4.blocking_read(&mut adc4_pin1, adc4::SampleTime::CYCLES1_5);
    let volt: f32 = 3.3 * raw as f32 / max4 as f32;
    info!("Read adc4 pin 1 {}", volt);
-    let raw: u16 = adc4.blocking_read(&mut adc4_pin2);
+    let raw: u16 = adc4.blocking_read(&mut adc4_pin2, adc4::SampleTime::CYCLES1_5);
    let volt: f32 = 3.3 * raw as f32 / max4 as f32;
    info!("Read adc4 pin 2 {}", volt);
@@ -97,11 +95,14 @@ async fn main(_spawner: embassy_executor::Spawner) {
    // The channels must be in ascending order and can't repeat for ADC4
    adc4.read(
        p.GPDMA1_CH1.reborrow(),
-        [&mut degraded42, &mut degraded41].into_iter(),
+        [
+            (&mut degraded42, adc4::SampleTime::CYCLES1_5),
+            (&mut degraded41, adc4::SampleTime::CYCLES1_5),
+        ]
+        .into_iter(),
        &mut measurements,
    )
-    .await
+    .await;
-    .unwrap();
    let volt2: f32 = 3.3 * measurements[0] as f32 / max4 as f32;
    let volt1: f32 = 3.3 * measurements[1] as f32 / max4 as f32;
    info!("Async read 4 pin 1 {}", volt1);
diff --git a/examples/stm32wba/src/bin/adc.rs b/examples/stm32wba/src/bin/adc.rs
index 8c80470b8..ade3f5d6a 100644
--- a/examples/stm32wba/src/bin/adc.rs
+++ b/examples/stm32wba/src/bin/adc.rs
@@ -2,7 +2,7 @@
 #![no_main]
 use defmt::*;
-use embassy_stm32::adc::{AdcChannel, adc4};
+use embassy_stm32::adc::{Adc, AdcChannel, SampleTime, adc4};
 use {defmt_rtt as _, panic_probe as _};
 #[embassy_executor::main]
@@ -12,20 +12,20 @@ async fn main(_spawner: embassy_executor::Spawner) {
    let mut p = embassy_stm32::init(config);
    // **** ADC4 init ****
-    let mut adc4 = adc4::Adc4::new(p.ADC4);
+    let mut adc4 = Adc::new_adc4(p.ADC4);
    let mut adc4_pin1 = p.PA0; // A4
    let mut adc4_pin2 = p.PA1; // A5
-    adc4.set_resolution(adc4::Resolution::BITS12);
+    adc4.set_resolution_adc4(adc4::Resolution::BITS12);
-    adc4.set_averaging(adc4::Averaging::Samples256);
+    adc4.set_averaging_adc4(adc4::Averaging::Samples256);
-    adc4.set_sample_time(adc4::SampleTime::CYCLES1_5);
    let max4 = adc4::resolution_to_max_count(adc4::Resolution::BITS12);
    // **** ADC4 blocking read ****
-    let raw: u16 = adc4.blocking_read(&mut adc4_pin1);
+    let raw: u16 = adc4.blocking_read(&mut adc4_pin1, adc4::SampleTime::CYCLES1_5);
    let volt: f32 = 3.0 * raw as f32 / max4 as f32;
    info!("Read adc4 pin 1 {}", volt);
-    let raw: u16 = adc4.blocking_read(&mut adc4_pin2);
+    let raw: u16 = adc4.blocking_read(&mut adc4_pin2, adc4::SampleTime::CYCLES1_5);
    let volt: f32 = 3.3 * raw as f32 / max4 as f32;
    info!("Read adc4 pin 2 {}", volt);
@@ -37,11 +37,14 @@ async fn main(_spawner: embassy_executor::Spawner) {
    // The channels must be in ascending order and can't repeat for ADC4
    adc4.read(
        p.GPDMA1_CH1.reborrow(),
-        [&mut degraded42, &mut degraded41].into_iter(),
+        [
+            (&mut degraded42, SampleTime::CYCLES12_5),
+            (&mut degraded41, SampleTime::CYCLES12_5),
+        ]
+        .into_iter(),
        &mut measurements,
    )
-    .await
+    .await;
-    .unwrap();
    let volt2: f32 = 3.3 * measurements[0] as f32 / max4 as f32;
    let volt1: f32 = 3.0 * measurements[1] as f32 / max4 as f32;
    info!("Async read 4 pin 1 {}", volt1);
diff --git a/examples/stm32wba6/src/bin/adc.rs b/examples/stm32wba6/src/bin/adc.rs
index 8c80470b8..9d1f39419 100644
--- a/examples/stm32wba6/src/bin/adc.rs
+++ b/examples/stm32wba6/src/bin/adc.rs
@@ -2,7 +2,7 @@
 #![no_main]
 use defmt::*;
-use embassy_stm32::adc::{AdcChannel, adc4};
+use embassy_stm32::adc::{Adc, AdcChannel, SampleTime, adc4};
 use {defmt_rtt as _, panic_probe as _};
 #[embassy_executor::main]
@@ -12,20 +12,19 @@ async fn main(_spawner: embassy_executor::Spawner) {
    let mut p = embassy_stm32::init(config);
    // **** ADC4 init ****
-    let mut adc4 = adc4::Adc4::new(p.ADC4);
+    let mut adc4 = Adc::new_adc4(p.ADC4);
    let mut adc4_pin1 = p.PA0; // A4
    let mut adc4_pin2 = p.PA1; // A5
-    adc4.set_resolution(adc4::Resolution::BITS12);
+    adc4.set_resolution_adc4(adc4::Resolution::BITS12);
-    adc4.set_averaging(adc4::Averaging::Samples256);
+    adc4.set_averaging_adc4(adc4::Averaging::Samples256);
-    adc4.set_sample_time(adc4::SampleTime::CYCLES1_5);
    let max4 = adc4::resolution_to_max_count(adc4::Resolution::BITS12);
    // **** ADC4 blocking read ****
-    let raw: u16 = adc4.blocking_read(&mut adc4_pin1);
+    let raw: u16 = adc4.blocking_read(&mut adc4_pin1, adc4::SampleTime::CYCLES1_5);
    let volt: f32 = 3.0 * raw as f32 / max4 as f32;
    info!("Read adc4 pin 1 {}", volt);
-    let raw: u16 = adc4.blocking_read(&mut adc4_pin2);
+    let raw: u16 = adc4.blocking_read(&mut adc4_pin2, adc4::SampleTime::CYCLES1_5);
    let volt: f32 = 3.3 * raw as f32 / max4 as f32;
    info!("Read adc4 pin 2 {}", volt);
@@ -37,11 +36,14 @@ async fn main(_spawner: embassy_executor::Spawner) {
    // The channels must be in ascending order and can't repeat for ADC4
    adc4.read(
        p.GPDMA1_CH1.reborrow(),
-        [&mut degraded42, &mut degraded41].into_iter(),
+        [
+            (&mut degraded42, SampleTime::CYCLES12_5),
+            (&mut degraded41, SampleTime::CYCLES12_5),
+        ]
+        .into_iter(),
        &mut measurements,
    )
-    .await
+    .await;
-    .unwrap();
    let volt2: f32 = 3.3 * measurements[0] as f32 / max4 as f32;
    let volt1: f32 = 3.0 * measurements[1] as f32 / max4 as f32;
    info!("Async read 4 pin 1 {}", volt1);
diff --git a/examples/stm32wl/src/bin/adc.rs b/examples/stm32wl/src/bin/adc.rs
index 6b21b086b..adabe0df8 100644
--- a/examples/stm32wl/src/bin/adc.rs
+++ b/examples/stm32wl/src/bin/adc.rs
@@ -18,11 +18,11 @@ async fn main(_spawner: Spawner) {
    info!("Hello World!");
    let mut adc = Adc::new_with_clock(p.ADC1, Clock::Sync { div: CkModePclk::DIV1 });
-    adc.set_sample_time(SampleTime::CYCLES79_5);
    let mut pin = p.PB2;
    let mut vrefint = adc.enable_vrefint();
-    let vrefint_sample = adc.blocking_read(&mut vrefint);
+    let vrefint_sample = adc.blocking_read(&mut vrefint, SampleTime::CYCLES79_5);
    let convert_to_millivolts = |sample| {
        // From https://www.st.com/resource/en/datasheet/stm32g031g8.pdf
        // 6.3.3 Embedded internal reference voltage
@@ -32,7 +32,7 @@ async fn main(_spawner: Spawner) {
    };
    loop {
-        let v = adc.blocking_read(&mut pin);
+        let v = adc.blocking_read(&mut pin, SampleTime::CYCLES79_5);
        info!("--> {} - {} mV", v, convert_to_millivolts(v));
        Timer::after_millis(100).await;
    }
diff --git a/examples/stm32wle5/src/bin/adc.rs b/examples/stm32wle5/src/bin/adc.rs
index 8b830a1e6..4e0574d97 100644
--- a/examples/stm32wle5/src/bin/adc.rs
+++ b/examples/stm32wle5/src/bin/adc.rs
@@ -73,11 +73,10 @@ async fn async_main(_spawner: Spawner) {
    info!("Hello World!");
    let mut adc = Adc::new(p.ADC1);
-    adc.set_sample_time(SampleTime::CYCLES79_5);
    let mut pin = p.PA10;
    let mut vrefint = adc.enable_vrefint();
-    let vrefint_sample = adc.blocking_read(&mut vrefint);
+    let vrefint_sample = adc.blocking_read(&mut vrefint, SampleTime::CYCLES79_5);
    let convert_to_millivolts = |sample| {
        // From https://www.st.com/resource/en/datasheet/stm32g031g8.pdf
        // 6.3.3 Embedded internal reference voltage
@@ -87,7 +86,7 @@ async fn async_main(_spawner: Spawner) {
    };
    loop {
-        let v = adc.blocking_read(&mut pin);
+        let v = adc.blocking_read(&mut pin, SampleTime::CYCLES79_5);
        info!("--> {} - {} mV", v, convert_to_millivolts(v));
        Timer::after_secs(1).await;
    }
diff --git a/tests/stm32/src/bin/dac.rs b/tests/stm32/src/bin/dac.rs
index d34bbb255..747b11e7f 100644
--- a/tests/stm32/src/bin/dac.rs
+++ b/tests/stm32/src/bin/dac.rs
@@ -10,7 +10,7 @@ use core::f32::consts::PI;
 use common::*;
 use defmt::assert;
 use embassy_executor::Spawner;
-use embassy_stm32::adc::Adc;
+use embassy_stm32::adc::{Adc, SampleTime};
 use embassy_stm32::dac::{DacCh1, Value};
 use embassy_time::Timer;
 use micromath::F32Ext;
@@ -37,7 +37,7 @@ async fn main(_spawner: Spawner) {
    dac.set(Value::Bit8(0));
    // Now wait a little to obtain a stable value
    Timer::after_millis(30).await;
-    let offset = adc.blocking_read(&mut adc_pin);
+    let offset = adc.blocking_read(&mut adc_pin, SampleTime::from_bits(0));
    for v in 0..=255 {
        // First set the DAC output value
@@ -48,7 +48,10 @@ async fn main(_spawner: Spawner) {
        Timer::after_millis(30).await;
        // Need to steal the peripherals here because PA4 is obviously in use already
-        let measured = adc.blocking_read(&mut unsafe { embassy_stm32::Peripherals::steal() }.PA4);
+        let measured = adc.blocking_read(
+            &mut unsafe { embassy_stm32::Peripherals::steal() }.PA4,
+            SampleTime::from_bits(0),
+        );
        // Calibrate and normalize the measurement to get close to the dac_output_val
        let measured_normalized = ((measured as i32 - offset as i32) / normalization_factor) as i16;
diff --git a/tests/stm32/src/bin/dac_l1.rs b/tests/stm32/src/bin/dac_l1.rs
index e6400f28e..2fe0cf1f1 100644
--- a/tests/stm32/src/bin/dac_l1.rs
+++ b/tests/stm32/src/bin/dac_l1.rs
@@ -10,7 +10,7 @@ use core::f32::consts::PI;
 use common::*;
 use defmt::assert;
 use embassy_executor::Spawner;
-use embassy_stm32::adc::Adc;
+use embassy_stm32::adc::{Adc, SampleTime};
 use embassy_stm32::dac::{DacCh1, Value};
 use embassy_stm32::{bind_interrupts, peripherals};
 use embassy_time::Timer;
@@ -47,7 +47,7 @@ async fn main(_spawner: Spawner) {
    dac.set(Value::Bit8(0));
    // Now wait a little to obtain a stable value
    Timer::after_millis(30).await;
-    let offset = adc.read(&mut adc_pin).await;
+    let offset = adc.read(&mut adc_pin, SampleTime::from_bits(0)).await;
    for v in 0..=255 {
        // First set the DAC output value
@@ -58,7 +58,12 @@ async fn main(_spawner: Spawner) {
        Timer::after_millis(30).await;
        // Need to steal the peripherals here because PA4 is obviously in use already
-        let measured = adc.read(&mut unsafe { embassy_stm32::Peripherals::steal() }.PA4).await;
+        let measured = adc
+            .read(
+                &mut unsafe { embassy_stm32::Peripherals::steal() }.PA4,
+                SampleTime::from_bits(0),
+            )
+            .await;
        // Calibrate and normalize the measurement to get close to the dac_output_val
        let measured_normalized = ((measured as i32 - offset as i32) / normalization_factor) as i16;