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-rw-r--r--embassy-stm32/src/xspi/enums.rs8
-rw-r--r--embassy-stm32/src/xspi/mod.rs29
2 files changed, 25 insertions, 12 deletions
diff --git a/embassy-stm32/src/xspi/enums.rs b/embassy-stm32/src/xspi/enums.rs
index e02ec797e..c96641180 100644
--- a/embassy-stm32/src/xspi/enums.rs
+++ b/embassy-stm32/src/xspi/enums.rs
@@ -160,9 +160,9 @@ impl Into<u8> for MemorySize {
160#[derive(Copy, Clone)] 160#[derive(Copy, Clone)]
161pub enum AddressSize { 161pub enum AddressSize {
162 /// 8-bit address 162 /// 8-bit address
163 _8Bit, 163 _8bit,
164 /// 16-bit address 164 /// 16-bit address
165 _16Bit, 165 _16bit,
166 /// 24-bit address 166 /// 24-bit address
167 _24bit, 167 _24bit,
168 /// 32-bit address 168 /// 32-bit address
@@ -172,8 +172,8 @@ pub enum AddressSize {
172impl Into<u8> for AddressSize { 172impl Into<u8> for AddressSize {
173 fn into(self) -> u8 { 173 fn into(self) -> u8 {
174 match self { 174 match self {
175 AddressSize::_8Bit => 0b00, 175 AddressSize::_8bit => 0b00,
176 AddressSize::_16Bit => 0b01, 176 AddressSize::_16bit => 0b01,
177 AddressSize::_24bit => 0b10, 177 AddressSize::_24bit => 0b10,
178 AddressSize::_32bit => 0b11, 178 AddressSize::_32bit => 0b11,
179 } 179 }
diff --git a/embassy-stm32/src/xspi/mod.rs b/embassy-stm32/src/xspi/mod.rs
index bc3007fe8..44c10b961 100644
--- a/embassy-stm32/src/xspi/mod.rs
+++ b/embassy-stm32/src/xspi/mod.rs
@@ -122,17 +122,17 @@ impl Default for TransferConfig {
122 Self { 122 Self {
123 iwidth: XspiWidth::NONE, 123 iwidth: XspiWidth::NONE,
124 instruction: None, 124 instruction: None,
125 isize: AddressSize::_8Bit, 125 isize: AddressSize::_8bit,
126 idtr: false, 126 idtr: false,
127 127
128 adwidth: XspiWidth::NONE, 128 adwidth: XspiWidth::NONE,
129 address: None, 129 address: None,
130 adsize: AddressSize::_8Bit, 130 adsize: AddressSize::_8bit,
131 addtr: false, 131 addtr: false,
132 132
133 abwidth: XspiWidth::NONE, 133 abwidth: XspiWidth::NONE,
134 alternate_bytes: None, 134 alternate_bytes: None,
135 absize: AddressSize::_8Bit, 135 absize: AddressSize::_8bit,
136 abdtr: false, 136 abdtr: false,
137 137
138 dwidth: XspiWidth::NONE, 138 dwidth: XspiWidth::NONE,
@@ -214,11 +214,11 @@ impl<'d, T: Instance, M: PeriMode> Xspi<'d, T, M> {
214 w.set_isize(WccrIsize::from_bits(write_config.isize.into())); 214 w.set_isize(WccrIsize::from_bits(write_config.isize.into()));
215 215
216 w.set_admode(WccrAdmode::from_bits(write_config.adwidth.into())); 216 w.set_admode(WccrAdmode::from_bits(write_config.adwidth.into()));
217 w.set_addtr(write_config.idtr); 217 w.set_addtr(write_config.addtr);
218 w.set_adsize(WccrAdsize::from_bits(write_config.adsize.into())); 218 w.set_adsize(WccrAdsize::from_bits(write_config.adsize.into()));
219 219
220 w.set_dmode(WccrDmode::from_bits(write_config.dwidth.into())); 220 w.set_dmode(WccrDmode::from_bits(write_config.dwidth.into()));
221 w.set_ddtr(write_config.idtr); 221 w.set_ddtr(write_config.ddtr);
222 222
223 w.set_abmode(WccrAbmode::from_bits(write_config.abwidth.into())); 223 w.set_abmode(WccrAbmode::from_bits(write_config.abwidth.into()));
224 w.set_dqse(true); 224 w.set_dqse(true);
@@ -283,6 +283,13 @@ impl<'d, T: Instance, M: PeriMode> Xspi<'d, T, M> {
283 width: XspiWidth, 283 width: XspiWidth,
284 dual_quad: bool, 284 dual_quad: bool,
285 ) -> Self { 285 ) -> Self {
286 // Enable the interface
287 match T::SPI_IDX {
288 1 => crate::pac::PWR.csr2().modify(|r| r.set_en_xspim1(true)),
289 2 => crate::pac::PWR.csr2().modify(|r| r.set_en_xspim2(true)),
290 _ => unreachable!(),
291 };
292
286 #[cfg(xspim_v1)] 293 #[cfg(xspim_v1)]
287 { 294 {
288 // RCC for xspim should be enabled before writing register 295 // RCC for xspim should be enabled before writing register
@@ -447,7 +454,7 @@ impl<'d, T: Instance, M: PeriMode> Xspi<'d, T, M> {
447 w.set_isize(CcrIsize::from_bits(command.isize.into())); 454 w.set_isize(CcrIsize::from_bits(command.isize.into()));
448 455
449 w.set_admode(CcrAdmode::from_bits(command.adwidth.into())); 456 w.set_admode(CcrAdmode::from_bits(command.adwidth.into()));
450 w.set_addtr(command.idtr); 457 w.set_addtr(command.addtr);
451 w.set_adsize(CcrAdsize::from_bits(command.adsize.into())); 458 w.set_adsize(CcrAdsize::from_bits(command.adsize.into()));
452 459
453 w.set_dmode(CcrDmode::from_bits(command.dwidth.into())); 460 w.set_dmode(CcrDmode::from_bits(command.dwidth.into()));
@@ -686,7 +693,10 @@ impl<'d, T: Instance> Xspi<'d, T, Blocking> {
686 None, 693 None,
687 new_pin!(clk, AfType::output(OutputType::PushPull, Speed::VeryHigh)), 694 new_pin!(clk, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
688 ncs.sel(), 695 ncs.sel(),
689 new_pin!(ncs, AfType::output(OutputType::OpenDrain, Speed::VeryHigh)), 696 new_pin!(
697 ncs,
698 AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
699 ),
690 None, 700 None,
691 None, 701 None,
692 None, 702 None,
@@ -915,7 +925,10 @@ impl<'d, T: Instance> Xspi<'d, T, Async> {
915 None, 925 None,
916 new_pin!(clk, AfType::output(OutputType::PushPull, Speed::VeryHigh)), 926 new_pin!(clk, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
917 ncs.sel(), 927 ncs.sel(),
918 new_pin!(ncs, AfType::output(OutputType::PushPull, Speed::VeryHigh)), 928 new_pin!(
929 ncs,
930 AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
931 ),
919 None, 932 None,
920 None, 933 None,
921 None, 934 None,