aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--embassy-stm32/src/eth/v1/mod.rs100
-rw-r--r--embassy-stm32/src/eth/v2/mod.rs40
2 files changed, 48 insertions, 92 deletions
diff --git a/embassy-stm32/src/eth/v1/mod.rs b/embassy-stm32/src/eth/v1/mod.rs
index 45cd33d9a..8b04b74c4 100644
--- a/embassy-stm32/src/eth/v1/mod.rs
+++ b/embassy-stm32/src/eth/v1/mod.rs
@@ -110,37 +110,6 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
110 phy: P, 110 phy: P,
111 mac_addr: [u8; 6], 111 mac_addr: [u8; 6],
112 ) -> Self { 112 ) -> Self {
113 // Enable the necessary Clocks
114 #[cfg(eth_v1a)]
115 critical_section::with(|_| {
116 RCC.apb2enr().modify(|w| w.set_afioen(true));
117
118 // Select RMII (Reduced Media Independent Interface)
119 // Must be done prior to enabling peripheral clock
120 AFIO.mapr().modify(|w| {
121 w.set_mii_rmii_sel(true);
122 w.set_swj_cfg(crate::pac::afio::vals::SwjCfg::NO_OP);
123 });
124
125 RCC.ahbenr().modify(|w| {
126 w.set_ethen(true);
127 w.set_ethtxen(true);
128 w.set_ethrxen(true);
129 });
130 });
131
132 #[cfg(any(eth_v1b, eth_v1c))]
133 critical_section::with(|_| {
134 RCC.ahb1enr().modify(|w| {
135 w.set_ethen(true);
136 w.set_ethtxen(true);
137 w.set_ethrxen(true);
138 });
139
140 // RMII (Reduced Media Independent Interface)
141 SYSCFG.pmc().modify(|w| w.set_mii_rmii_sel(true));
142 });
143
144 #[cfg(eth_v1a)] 113 #[cfg(eth_v1a)]
145 { 114 {
146 config_in_pins!(ref_clk, rx_d0, rx_d1); 115 config_in_pins!(ref_clk, rx_d0, rx_d1);
@@ -160,7 +129,7 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
160 tx_en.into(), 129 tx_en.into(),
161 ]); 130 ]);
162 131
163 Self::new_inner(queue, peri, irq, pins, phy, mac_addr) 132 Self::new_inner(queue, peri, irq, pins, phy, mac_addr, true)
164 } 133 }
165 134
166 fn new_inner<const TX: usize, const RX: usize>( 135 fn new_inner<const TX: usize, const RX: usize>(
@@ -170,7 +139,39 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
170 pins: Pins<'d>, 139 pins: Pins<'d>,
171 phy: P, 140 phy: P,
172 mac_addr: [u8; 6], 141 mac_addr: [u8; 6],
142 rmii_mii_sel: bool,
173 ) -> Self { 143 ) -> Self {
144 // Enable the necessary Clocks
145 #[cfg(eth_v1a)]
146 critical_section::with(|_| {
147 RCC.apb2enr().modify(|w| w.set_afioen(true));
148
149 // Select (R)MII (Reduced Media Independent Interface)
150 // Must be done prior to enabling peripheral clock
151 AFIO.mapr().modify(|w| {
152 w.set_mii_rmii_sel(rmii_mii_sel);
153 w.set_swj_cfg(crate::pac::afio::vals::SwjCfg::NO_OP);
154 });
155
156 RCC.ahbenr().modify(|w| {
157 w.set_ethen(true);
158 w.set_ethtxen(true);
159 w.set_ethrxen(true);
160 });
161 });
162
163 #[cfg(any(eth_v1b, eth_v1c))]
164 critical_section::with(|_| {
165 RCC.ahb1enr().modify(|w| {
166 w.set_ethen(true);
167 w.set_ethtxen(true);
168 w.set_ethrxen(true);
169 });
170
171 // (R)MII ((Reduced) Media Independent Interface)
172 SYSCFG.pmc().modify(|w| w.set_mii_rmii_sel(rmii_mii_sel));
173 });
174
174 let dma = T::regs().ethernet_dma(); 175 let dma = T::regs().ethernet_dma();
175 let mac = T::regs().ethernet_mac(); 176 let mac = T::regs().ethernet_mac();
176 177
@@ -281,39 +282,6 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
281 phy: P, 282 phy: P,
282 mac_addr: [u8; 6], 283 mac_addr: [u8; 6],
283 ) -> Self { 284 ) -> Self {
284 // TODO: Handle optional signals like CRS, MII_COL, RX_ER?
285
286 // Enable the necessary Clocks
287 #[cfg(eth_v1a)]
288 critical_section::with(|_| {
289 RCC.apb2enr().modify(|w| w.set_afioen(true));
290
291 // Select MII (Media Independent Interface)
292 // Must be done prior to enabling peripheral clock
293 AFIO.mapr().modify(|w| {
294 w.set_mii_rmii_sel(false);
295 w.set_swj_cfg(crate::pac::afio::vals::SwjCfg::NO_OP);
296 });
297
298 RCC.ahbenr().modify(|w| {
299 w.set_ethen(true);
300 w.set_ethtxen(true);
301 w.set_ethrxen(true);
302 });
303 });
304
305 #[cfg(any(eth_v1b, eth_v1c))]
306 critical_section::with(|_| {
307 RCC.ahb1enr().modify(|w| {
308 w.set_ethen(true);
309 w.set_ethtxen(true);
310 w.set_ethrxen(true);
311 });
312
313 // MII (Media Independent Interface)
314 SYSCFG.pmc().modify(|w| w.set_mii_rmii_sel(false));
315 });
316
317 #[cfg(eth_v1a)] 285 #[cfg(eth_v1a)]
318 { 286 {
319 config_in_pins!(rx_clk, tx_clk, rx_d0, rx_d1, rx_d2, rx_d3, rxdv); 287 config_in_pins!(rx_clk, tx_clk, rx_d0, rx_d1, rx_d2, rx_d3, rxdv);
@@ -340,7 +308,7 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
340 tx_en.into(), 308 tx_en.into(),
341 ]); 309 ]);
342 310
343 Self::new_inner(queue, peri, irq, pins, phy, mac_addr) 311 Self::new_inner(queue, peri, irq, pins, phy, mac_addr, false)
344 } 312 }
345} 313}
346 314
diff --git a/embassy-stm32/src/eth/v2/mod.rs b/embassy-stm32/src/eth/v2/mod.rs
index faed7d8e2..05ecee5ba 100644
--- a/embassy-stm32/src/eth/v2/mod.rs
+++ b/embassy-stm32/src/eth/v2/mod.rs
@@ -76,17 +76,6 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
76 phy: P, 76 phy: P,
77 mac_addr: [u8; 6], 77 mac_addr: [u8; 6],
78 ) -> Self { 78 ) -> Self {
79 // Enable the necessary clocks
80 critical_section::with(|_| {
81 crate::pac::RCC.ahb1enr().modify(|w| {
82 w.set_ethen(true);
83 w.set_ethtxen(true);
84 w.set_ethrxen(true);
85 });
86
87 crate::pac::SYSCFG.pmcr().modify(|w| w.set_eth_sel_phy(EthSelPhy::RMII));
88 });
89
90 config_pins!(ref_clk, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en); 79 config_pins!(ref_clk, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
91 80
92 let pins = Pins::Rmii([ 81 let pins = Pins::Rmii([
@@ -99,7 +88,7 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
99 tx_en.into(), 88 tx_en.into(),
100 ]); 89 ]);
101 90
102 Self::new_inner(queue, peri, irq, pins, phy, mac_addr) 91 Self::new_inner(queue, peri, irq, pins, phy, mac_addr, EthSelPhy::RMII)
103 } 92 }
104 93
105 /// Create a new MII ethernet driver using 12 pins. 94 /// Create a new MII ethernet driver using 12 pins.
@@ -122,19 +111,6 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
122 phy: P, 111 phy: P,
123 mac_addr: [u8; 6], 112 mac_addr: [u8; 6],
124 ) -> Self { 113 ) -> Self {
125 // Enable the necessary clocks
126 critical_section::with(|_| {
127 crate::pac::RCC.ahb1enr().modify(|w| {
128 w.set_ethen(true);
129 w.set_ethtxen(true);
130 w.set_ethrxen(true);
131 });
132
133 crate::pac::SYSCFG
134 .pmcr()
135 .modify(|w| w.set_eth_sel_phy(EthSelPhy::MII_GMII));
136 });
137
138 config_pins!( 114 config_pins!(
139 rx_clk, tx_clk, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en 115 rx_clk, tx_clk, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en
140 ); 116 );
@@ -154,7 +130,7 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
154 tx_en.into(), 130 tx_en.into(),
155 ]); 131 ]);
156 132
157 Self::new_inner(queue, peri, irq, pins, phy, mac_addr) 133 Self::new_inner(queue, peri, irq, pins, phy, mac_addr, EthSelPhy::MII_GMII)
158 } 134 }
159 135
160 fn new_inner<const TX: usize, const RX: usize>( 136 fn new_inner<const TX: usize, const RX: usize>(
@@ -164,7 +140,19 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
164 pins: Pins<'d>, 140 pins: Pins<'d>,
165 phy: P, 141 phy: P,
166 mac_addr: [u8; 6], 142 mac_addr: [u8; 6],
143 eth_sel_phy: EthSelPhy,
167 ) -> Self { 144 ) -> Self {
145 // Enable the necessary clocks
146 critical_section::with(|_| {
147 crate::pac::RCC.ahb1enr().modify(|w| {
148 w.set_ethen(true);
149 w.set_ethtxen(true);
150 w.set_ethrxen(true);
151 });
152
153 crate::pac::SYSCFG.pmcr().modify(|w| w.set_eth_sel_phy(eth_sel_phy));
154 });
155
168 let dma = T::regs().ethernet_dma(); 156 let dma = T::regs().ethernet_dma();
169 let mac = T::regs().ethernet_mac(); 157 let mac = T::regs().ethernet_mac();
170 let mtl = T::regs().ethernet_mtl(); 158 let mtl = T::regs().ethernet_mtl();
generated by cgit (git 2.34.1) at 2026-04-05 22:53:29 +0000