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-rw-r--r--embassy-stm32/src/hsem/mod.rs6
1 files changed, 4 insertions, 2 deletions
diff --git a/embassy-stm32/src/hsem/mod.rs b/embassy-stm32/src/hsem/mod.rs
index 31527bcdb..573a1851d 100644
--- a/embassy-stm32/src/hsem/mod.rs
+++ b/embassy-stm32/src/hsem/mod.rs
@@ -3,7 +3,7 @@
3use embassy_hal_internal::PeripheralType; 3use embassy_hal_internal::PeripheralType;
4 4
5use crate::pac; 5use crate::pac;
6use crate::rcc::RccPeripheral; 6use crate::rcc::{self, RccPeripheral};
7// TODO: This code works for all HSEM implemenations except for the STM32WBA52/4/5xx MCUs. 7// TODO: This code works for all HSEM implemenations except for the STM32WBA52/4/5xx MCUs.
8// Those MCUs have a different HSEM implementation (Secure semaphore lock support, 8// Those MCUs have a different HSEM implementation (Secure semaphore lock support,
9// Privileged / unprivileged semaphore lock support, Semaphore lock protection via semaphore attribute), 9// Privileged / unprivileged semaphore lock support, Semaphore lock protection via semaphore attribute),
@@ -46,7 +46,7 @@ pub enum CoreId {
46#[inline(always)] 46#[inline(always)]
47pub fn get_current_coreid() -> CoreId { 47pub fn get_current_coreid() -> CoreId {
48 let cpuid = unsafe { cortex_m::peripheral::CPUID::PTR.read_volatile().base.read() }; 48 let cpuid = unsafe { cortex_m::peripheral::CPUID::PTR.read_volatile().base.read() };
49 match cpuid & 0x000000F0 { 49 match (cpuid & 0x000000F0) >> 4 {
50 #[cfg(any(stm32wb, stm32wl))] 50 #[cfg(any(stm32wb, stm32wl))]
51 0x0 => CoreId::Core1, 51 0x0 => CoreId::Core1,
52 52
@@ -80,6 +80,8 @@ pub struct HardwareSemaphore<'d, T: Instance> {
80impl<'d, T: Instance> HardwareSemaphore<'d, T> { 80impl<'d, T: Instance> HardwareSemaphore<'d, T> {
81 /// Creates a new HardwareSemaphore instance. 81 /// Creates a new HardwareSemaphore instance.
82 pub fn new(peripheral: Peri<'d, T>) -> Self { 82 pub fn new(peripheral: Peri<'d, T>) -> Self {
83 rcc::enable_and_reset::<T>();
84
83 HardwareSemaphore { _peri: peripheral } 85 HardwareSemaphore { _peri: peripheral }
84 } 86 }
85 87