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-rw-r--r--embassy-stm32/src/i2c/v2.rs156
1 files changed, 13 insertions, 143 deletions
diff --git a/embassy-stm32/src/i2c/v2.rs b/embassy-stm32/src/i2c/v2.rs
index 7049affe8..54d2fe6ec 100644
--- a/embassy-stm32/src/i2c/v2.rs
+++ b/embassy-stm32/src/i2c/v2.rs
@@ -162,7 +162,6 @@ pub struct I2c<'d, T: Instance, TXDMA = NoDma, RXDMA = NoDma> {
162 tx_dma: PeripheralRef<'d, TXDMA>, 162 tx_dma: PeripheralRef<'d, TXDMA>,
163 #[allow(dead_code)] 163 #[allow(dead_code)]
164 rx_dma: PeripheralRef<'d, RXDMA>, 164 rx_dma: PeripheralRef<'d, RXDMA>,
165 #[cfg(feature = "time")]
166 timeout: Duration, 165 timeout: Duration,
167} 166}
168 167
@@ -226,6 +225,8 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
226 rx_dma, 225 rx_dma,
227 #[cfg(feature = "time")] 226 #[cfg(feature = "time")]
228 timeout: config.transaction_timeout, 227 timeout: config.transaction_timeout,
228 #[cfg(not(feature = "time"))]
229 timeout: Duration::dummy_duration(),
229 } 230 }
230 } 231 }
231 232
@@ -339,21 +340,12 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
339 } 340 }
340 341
341 fn flush_txdr(&self) { 342 fn flush_txdr(&self) {
342 //if $i2c.isr.read().txis().bit_is_set() {
343 //$i2c.txdr.write(|w| w.txdata().bits(0));
344 //}
345
346 if T::regs().isr().read().txis() { 343 if T::regs().isr().read().txis() {
347 T::regs().txdr().write(|w| w.set_txdata(0)); 344 T::regs().txdr().write(|w| w.set_txdata(0));
348 } 345 }
349 if !T::regs().isr().read().txe() { 346 if !T::regs().isr().read().txe() {
350 T::regs().isr().modify(|w| w.set_txe(true)) 347 T::regs().isr().modify(|w| w.set_txe(true))
351 } 348 }
352
353 // If TXDR is not flagged as empty, write 1 to flush it
354 //if $i2c.isr.read().txe().is_not_empty() {
355 //$i2c.isr.write(|w| w.txe().set_bit());
356 //}
357 } 349 }
358 350
359 fn wait_txe(&self, check_timeout: impl Fn() -> Result<(), Error>) -> Result<(), Error> { 351 fn wait_txe(&self, check_timeout: impl Fn() -> Result<(), Error>) -> Result<(), Error> {
@@ -687,82 +679,26 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
687 679
688 // ========================= 680 // =========================
689 // Async public API 681 // Async public API
690
691 #[cfg(feature = "time")]
692 pub async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Error>
693 where
694 TXDMA: crate::i2c::TxDma<T>,
695 {
696 self.write_timeout_internal(address, write, self.timeout).await
697 }
698
699 #[cfg(not(feature = "time"))]
700 pub async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Error> 682 pub async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Error>
701 where 683 where
702 TXDMA: crate::i2c::TxDma<T>, 684 TXDMA: crate::i2c::TxDma<T>,
703 { 685 {
704 self.write_timeout_internal(address, write, Duration::dummy_duration())
705 .await
706 }
707
708 #[cfg(feature = "time")]
709 pub async fn write_timeout(&mut self, address: u8, write: &[u8], timeout: Duration) -> Result<(), Error>
710 where
711 TXDMA: crate::i2c::TxDma<T>,
712 {
713 self.write_timeout_internal(address, write, timeout).await
714 }
715
716 async fn write_timeout_internal(&mut self, address: u8, write: &[u8], timeout: Duration) -> Result<(), Error>
717 where
718 TXDMA: crate::i2c::TxDma<T>,
719 {
720 if write.is_empty() { 686 if write.is_empty() {
721 self.write_internal(address, write, true, timeout_fn(timeout)) 687 self.write_internal(address, write, true, timeout_fn(self.timeout))
722 } else { 688 } else {
723 with_timeout( 689 with_timeout(
724 timeout, 690 self.timeout,
725 self.write_dma_internal(address, write, true, true, timeout_fn(timeout)), 691 self.write_dma_internal(address, write, true, true, timeout_fn(self.timeout)),
726 ) 692 )
727 .await 693 .await
728 .unwrap_or(Err(Error::Timeout)) 694 .unwrap_or(Err(Error::Timeout))
729 } 695 }
730 } 696 }
731 697
732 #[cfg(feature = "time")]
733 pub async fn write_vectored(&mut self, address: u8, write: &[&[u8]]) -> Result<(), Error> 698 pub async fn write_vectored(&mut self, address: u8, write: &[&[u8]]) -> Result<(), Error>
734 where 699 where
735 TXDMA: crate::i2c::TxDma<T>, 700 TXDMA: crate::i2c::TxDma<T>,
736 { 701 {
737 self.write_vectored_timeout_internal(address, write, self.timeout).await
738 }
739
740 #[cfg(not(feature = "time"))]
741 pub async fn write_vectored(&mut self, address: u8, write: &[&[u8]]) -> Result<(), Error>
742 where
743 TXDMA: crate::i2c::TxDma<T>,
744 {
745 self.write_vectored_timeout_internal(address, write, Duration::dummy_duration())
746 .await
747 }
748
749 #[cfg(feature = "time")]
750 pub async fn write_vectored_timeout(&mut self, address: u8, write: &[&[u8]], timeout: Duration) -> Result<(), Error>
751 where
752 TXDMA: crate::i2c::TxDma<T>,
753 {
754 self.write_vectored_timeout_internal(address, write, timeout).await
755 }
756
757 async fn write_vectored_timeout_internal(
758 &mut self,
759 address: u8,
760 write: &[&[u8]],
761 timeout: Duration,
762 ) -> Result<(), Error>
763 where
764 TXDMA: crate::i2c::TxDma<T>,
765 {
766 if write.is_empty() { 702 if write.is_empty() {
767 return Err(Error::ZeroLengthTransfer); 703 return Err(Error::ZeroLengthTransfer);
768 } 704 }
@@ -775,8 +711,8 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
775 let is_last = next.is_none(); 711 let is_last = next.is_none();
776 712
777 with_timeout( 713 with_timeout(
778 timeout, 714 self.timeout,
779 self.write_dma_internal(address, c, first, is_last, timeout_fn(timeout)), 715 self.write_dma_internal(address, c, first, is_last, timeout_fn(self.timeout)),
780 ) 716 )
781 .await 717 .await
782 .unwrap_or(Err(Error::Timeout))?; 718 .unwrap_or(Err(Error::Timeout))?;
@@ -786,107 +722,41 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
786 Ok(()) 722 Ok(())
787 } 723 }
788 724
789 #[cfg(feature = "time")]
790 pub async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error>
791 where
792 RXDMA: crate::i2c::RxDma<T>,
793 {
794 self.read_timeout_internal(address, buffer, self.timeout).await
795 }
796
797 #[cfg(not(feature = "time"))]
798 pub async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error> 725 pub async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error>
799 where 726 where
800 RXDMA: crate::i2c::RxDma<T>, 727 RXDMA: crate::i2c::RxDma<T>,
801 { 728 {
802 self.read_timeout_internal(address, buffer, Duration::dummy_duration())
803 .await
804 }
805
806 #[cfg(feature = "time")]
807 pub async fn read_timeout(&mut self, address: u8, buffer: &mut [u8], timeout: Duration) -> Result<(), Error>
808 where
809 RXDMA: crate::i2c::RxDma<T>,
810 {
811 self.read_timeout_internal(address, buffer, timeout).await
812 }
813
814 async fn read_timeout_internal(&mut self, address: u8, buffer: &mut [u8], timeout: Duration) -> Result<(), Error>
815 where
816 RXDMA: crate::i2c::RxDma<T>,
817 {
818 if buffer.is_empty() { 729 if buffer.is_empty() {
819 self.read_internal(address, buffer, false, timeout_fn(timeout)) 730 self.read_internal(address, buffer, false, timeout_fn(self.timeout))
820 } else { 731 } else {
821 with_timeout( 732 with_timeout(
822 timeout, 733 self.timeout,
823 self.read_dma_internal(address, buffer, false, timeout_fn(timeout)), 734 self.read_dma_internal(address, buffer, false, timeout_fn(self.timeout)),
824 ) 735 )
825 .await 736 .await
826 .unwrap_or(Err(Error::Timeout)) 737 .unwrap_or(Err(Error::Timeout))
827 } 738 }
828 } 739 }
829 740
830 #[cfg(feature = "time")]
831 pub async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> 741 pub async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error>
832 where 742 where
833 TXDMA: super::TxDma<T>, 743 TXDMA: super::TxDma<T>,
834 RXDMA: super::RxDma<T>, 744 RXDMA: super::RxDma<T>,
835 { 745 {
836 self.write_read_timeout_internal(address, write, read, self.timeout)
837 .await
838 }
839
840 #[cfg(not(feature = "time"))]
841 pub async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error>
842 where
843 TXDMA: super::TxDma<T>,
844 RXDMA: super::RxDma<T>,
845 {
846 self.write_read_timeout_internal(address, write, read, Duration::dummy_duration())
847 .await
848 }
849
850 #[cfg(feature = "time")]
851 pub async fn write_read_timeout(
852 &mut self,
853 address: u8,
854 write: &[u8],
855 read: &mut [u8],
856 timeout: Duration,
857 ) -> Result<(), Error>
858 where
859 TXDMA: super::TxDma<T>,
860 RXDMA: super::RxDma<T>,
861 {
862 self.write_read_timeout_internal(address, write, read, timeout).await
863 }
864
865 async fn write_read_timeout_internal(
866 &mut self,
867 address: u8,
868 write: &[u8],
869 read: &mut [u8],
870 timeout: Duration,
871 ) -> Result<(), Error>
872 where
873 TXDMA: super::TxDma<T>,
874 RXDMA: super::RxDma<T>,
875 {
876 let start_instant = Instant::now(); 746 let start_instant = Instant::now();
877 let check_timeout = timeout_fn(timeout); 747 let check_timeout = timeout_fn(self.timeout);
878 if write.is_empty() { 748 if write.is_empty() {
879 self.write_internal(address, write, false, &check_timeout)?; 749 self.write_internal(address, write, false, &check_timeout)?;
880 } else { 750 } else {
881 with_timeout( 751 with_timeout(
882 timeout, 752 self.timeout,
883 self.write_dma_internal(address, write, true, true, &check_timeout), 753 self.write_dma_internal(address, write, true, true, &check_timeout),
884 ) 754 )
885 .await 755 .await
886 .unwrap_or(Err(Error::Timeout))?; 756 .unwrap_or(Err(Error::Timeout))?;
887 } 757 }
888 758
889 let time_left_until_timeout = timeout - Instant::now().duration_since(start_instant); 759 let time_left_until_timeout = self.timeout - Instant::now().duration_since(start_instant);
890 760
891 if read.is_empty() { 761 if read.is_empty() {
892 self.read_internal(address, read, true, &check_timeout)?; 762 self.read_internal(address, read, true, &check_timeout)?;