diff options
| -rw-r--r-- | embassy-stm32/src/qspi/mod.rs | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/embassy-stm32/src/qspi/mod.rs b/embassy-stm32/src/qspi/mod.rs index 92219e018..900dfa832 100644 --- a/embassy-stm32/src/qspi/mod.rs +++ b/embassy-stm32/src/qspi/mod.rs | |||
| @@ -183,14 +183,17 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> { | |||
| 183 | 183 | ||
| 184 | while T::REGS.sr().read().busy() {} | 184 | while T::REGS.sr().read().busy() {} |
| 185 | 185 | ||
| 186 | // Apply precautionary steps according to the errata... | 186 | #[cfg(stm32h7)] |
| 187 | T::REGS.cr().write_value(Cr(0)); | 187 | { |
| 188 | while T::REGS.sr().read().busy() {} | 188 | // Apply precautionary steps according to the errata... |
| 189 | T::REGS.cr().write_value(Cr(0xFF000001)); | 189 | T::REGS.cr().write_value(Cr(0)); |
| 190 | T::REGS.ccr().write(|w| w.set_frcm(true)); | 190 | while T::REGS.sr().read().busy() {} |
| 191 | T::REGS.ccr().write(|w| w.set_frcm(true)); | 191 | T::REGS.cr().write_value(Cr(0xFF000001)); |
| 192 | T::REGS.cr().write_value(Cr(0)); | 192 | T::REGS.ccr().write(|w| w.set_frcm(true)); |
| 193 | while T::REGS.sr().read().busy() {} | 193 | T::REGS.ccr().write(|w| w.set_frcm(true)); |
| 194 | T::REGS.cr().write_value(Cr(0)); | ||
| 195 | while T::REGS.sr().read().busy() {} | ||
| 196 | } | ||
| 194 | 197 | ||
| 195 | T::REGS.cr().modify(|w| { | 198 | T::REGS.cr().modify(|w| { |
| 196 | w.set_en(true); | 199 | w.set_en(true); |