5 files changed, 90 insertions, 84 deletions

diff --git a/embassy-stm32/src/rcc/wb.rs b/embassy-stm32/src/rcc/wb.rs
index e9b7296d5..ae708b37f 100644
--- a/embassy-stm32/src/rcc/wb.rs
+++ b/embassy-stm32/src/rcc/wb.rs
@@ -1,6 +1,6 @@
 pub use super::common::{AHBPrescaler, APBPrescaler};
 use crate::rcc::Clocks;
-use crate::rtc::{enable as enable_rtc, RtcClockSource};
+use crate::rtc::{Rtc, RtcClockSource};
 use crate::time::{khz, mhz, Hertz};
 
 /// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC,
@@ -375,5 +375,5 @@ pub(crate) fn configure_clocks(config: &Config) {
         w.set_shdhpre(config.ahb3_pre.into());
     });
 
-    config.rtc.map(|clock_source| enable_rtc(clock_source));
+    config.rtc.map(|clock_source| Rtc::set_clock_source(clock_source));
 }
diff --git a/embassy-stm32/src/rtc/mod.rs b/embassy-stm32/src/rtc/mod.rs
index 2d54c926d..945bfafd6 100644
--- a/embassy-stm32/src/rtc/mod.rs
+++ b/embassy-stm32/src/rtc/mod.rs
@@ -1,5 +1,4 @@
 //! RTC peripheral abstraction
-use core::marker::PhantomData;
 mod datetime;
 
 pub use self::datetime::{DateTime, DayOfWeek, Error as DateTimeError};
@@ -17,6 +16,9 @@ mod _version;
 pub use _version::*;
 use embassy_hal_internal::Peripheral;
 
+use crate::peripherals::RTC;
+use crate::rtc::sealed::Instance;
+
 /// Errors that can occur on methods on [RtcClock]
 #[derive(Clone, Debug, PartialEq, Eq)]
 pub enum RtcError {
@@ -28,22 +30,10 @@ pub enum RtcError {
 }
 
 /// RTC Abstraction
-pub struct Rtc<'d, T: Instance> {
-    phantom: PhantomData<&'d mut T>,
+pub struct Rtc {
     rtc_config: RtcConfig,
 }
 
-#[allow(dead_code)]
-pub(crate) fn enable(clock_source: RtcClockSource) {
-    Rtc::<crate::peripherals::RTC>::enable(clock_source);
-}
-
-#[cfg(feature = "time")]
-#[allow(dead_code)]
-pub(crate) fn set_wakeup_timer(_duration: embassy_time::Duration) {
-    todo!()
-}
-
 #[derive(Copy, Clone, Debug, PartialEq)]
 #[repr(u8)]
 pub enum RtcClockSource {
@@ -59,8 +49,6 @@ pub enum RtcClockSource {
 
 #[derive(Copy, Clone, PartialEq)]
 pub struct RtcConfig {
-    /// RTC clock source
-    clock_source: RtcClockSource,
     /// Asynchronous prescaler factor
     /// This is the asynchronous division factor:
     /// ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)
@@ -78,7 +66,6 @@ impl Default for RtcConfig {
     /// Raw sub-seconds in 1/256.
     fn default() -> Self {
         RtcConfig {
-            clock_source: RtcClockSource::LSI,
             async_prescaler: 127,
             sync_prescaler: 255,
         }
@@ -86,12 +73,6 @@ impl Default for RtcConfig {
 }
 
 impl RtcConfig {
-    /// Sets the clock source of RTC config
-    pub fn clock_source(mut self, clock_source: RtcClockSource) -> Self {
-        self.clock_source = clock_source;
-        self
-    }
-
     /// Set the asynchronous prescaler of RTC config
     pub fn async_prescaler(mut self, prescaler: u8) -> Self {
         self.async_prescaler = prescaler;
@@ -122,16 +103,13 @@ impl Default for RtcCalibrationCyclePeriod {
     }
 }
 
-impl<'d, T: Instance> Rtc<'d, T> {
-    pub fn new(_rtc: impl Peripheral<P = T> + 'd, rtc_config: RtcConfig) -> Self {
-        T::enable_peripheral_clk();
+impl Rtc {
+    pub fn new(_rtc: impl Peripheral<P = RTC>, rtc_config: RtcConfig) -> Self {
+        RTC::enable_peripheral_clk();
 
-        let mut rtc_struct = Self {
-            phantom: PhantomData,
-            rtc_config,
-        };
+        let mut rtc_struct = Self { rtc_config };
 
-        Self::enable(rtc_config.clock_source);
+        Self::enable();
 
         rtc_struct.configure(rtc_config);
         rtc_struct.rtc_config = rtc_config;
@@ -157,7 +135,7 @@ impl<'d, T: Instance> Rtc<'d, T> {
     ///
     /// Will return an `RtcError::InvalidDateTime` if the stored value in the system is not a valid [`DayOfWeek`].
     pub fn now(&self) -> Result<DateTime, RtcError> {
-        let r = T::regs();
+        let r = RTC::regs();
         let tr = r.tr().read();
         let second = bcd2_to_byte((tr.st(), tr.su()));
         let minute = bcd2_to_byte((tr.mnt(), tr.mnu()));
@@ -176,7 +154,7 @@ impl<'d, T: Instance> Rtc<'d, T> {
 
     /// Check if daylight savings time is active.
     pub fn get_daylight_savings(&self) -> bool {
-        let cr = T::regs().cr().read();
+        let cr = RTC::regs().cr().read();
         cr.bkp()
     }
 
@@ -191,14 +169,14 @@ impl<'d, T: Instance> Rtc<'d, T> {
         self.rtc_config
     }
 
-    pub const BACKUP_REGISTER_COUNT: usize = T::BACKUP_REGISTER_COUNT;
+    pub const BACKUP_REGISTER_COUNT: usize = RTC::BACKUP_REGISTER_COUNT;
 
     /// Read content of the backup register.
     ///
     /// The registers retain their values during wakes from standby mode or system resets. They also
     /// retain their value when Vdd is switched off as long as V_BAT is powered.
     pub fn read_backup_register(&self, register: usize) -> Option<u32> {
-        T::read_backup_register(&T::regs(), register)
+        RTC::read_backup_register(&RTC::regs(), register)
     }
 
     /// Set content of the backup register.
@@ -206,7 +184,7 @@ impl<'d, T: Instance> Rtc<'d, T> {
     /// The registers retain their values during wakes from standby mode or system resets. They also
     /// retain their value when Vdd is switched off as long as V_BAT is powered.
     pub fn write_backup_register(&self, register: usize, value: u32) {
-        T::write_backup_register(&T::regs(), register, value)
+        RTC::write_backup_register(&RTC::regs(), register, value)
     }
 }
 
@@ -257,5 +235,3 @@ pub(crate) mod sealed {
         // fn apply_config(&mut self, rtc_config: RtcConfig);
     }
 }
-
-pub trait Instance: sealed::Instance + 'static {}
diff --git a/embassy-stm32/src/rtc/v2.rs b/embassy-stm32/src/rtc/v2.rs
index 743a04d62..5b8960696 100644
--- a/embassy-stm32/src/rtc/v2.rs
+++ b/embassy-stm32/src/rtc/v2.rs
@@ -1,13 +1,12 @@
 use stm32_metapac::rtc::vals::{Init, Osel, Pol};
 
-use super::{sealed, Instance, RtcClockSource, RtcConfig};
+use super::{sealed, RtcClockSource, RtcConfig};
 use crate::pac::rtc::Rtc;
+use crate::peripherals::RTC;
+use crate::rtc::sealed::Instance;
 
-impl<'d, T: Instance> super::Rtc<'d, T> {
-    pub(super) fn enable(clock_source: RtcClockSource) {
-        #[cfg(not(rtc_v2wb))]
-        use stm32_metapac::rcc::vals::Rtcsel;
-
+impl super::Rtc {
+    fn unlock_registers() {
         #[cfg(any(rtc_v2f2, rtc_v2f3, rtc_v2l1))]
         let cr = crate::pac::PWR.cr();
         #[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb))]
@@ -16,10 +15,35 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
         // TODO: Missing from PAC for l0 and f0?
         #[cfg(not(any(rtc_v2f0, rtc_v2l0)))]
         {
-            cr.modify(|w| w.set_dbp(true));
-            while !cr.read().dbp() {}
+            if !cr.read().dbp() {
+                cr.modify(|w| w.set_dbp(true));
+                while !cr.read().dbp() {}
+            }
         }
+    }
+
+    #[allow(dead_code)]
+    pub(crate) fn set_clock_source(clock_source: RtcClockSource) {
+        #[cfg(not(rtc_v2wb))]
+        use stm32_metapac::rcc::vals::Rtcsel;
+
+        #[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
+        let cr = crate::pac::RCC.bdcr();
+        #[cfg(any(rtc_v2l0, rtc_v2l1))]
+        let cr = crate::pac::RCC.csr();
+
+        Self::unlock_registers();
+
+        cr.modify(|w| {
+            // Select RTC source
+            #[cfg(not(rtc_v2wb))]
+            w.set_rtcsel(Rtcsel::from_bits(clock_source as u8));
+            #[cfg(rtc_v2wb)]
+            w.set_rtcsel(clock_source as u8);
+        });
+    }
 
+    pub(super) fn enable() {
         #[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
         let reg = crate::pac::RCC.bdcr().read();
         #[cfg(any(rtc_v2l0, rtc_v2l1))]
@@ -28,12 +52,9 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
         #[cfg(any(rtc_v2h7, rtc_v2l4, rtc_v2wb))]
         assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
 
-        #[cfg(rtc_v2wb)]
-        let rtcsel = reg.rtcsel();
-        #[cfg(not(rtc_v2wb))]
-        let rtcsel = reg.rtcsel().to_bits();
+        if !reg.rtcen() {
+            Self::unlock_registers();
 
-        if !reg.rtcen() || rtcsel != clock_source as u8 {
             #[cfg(not(any(rtc_v2l0, rtc_v2l1, rtc_v2f2)))]
             crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true));
             #[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
@@ -46,12 +67,8 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
                 #[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
                 w.set_bdrst(false);
 
-                // Select RTC source
-                #[cfg(not(rtc_v2wb))]
-                w.set_rtcsel(Rtcsel::from_bits(clock_source as u8));
-                #[cfg(rtc_v2wb)]
-                w.set_rtcsel(clock_source as u8);
                 w.set_rtcen(true);
+                w.set_rtcsel(reg.rtcsel());
 
                 // Restore bcdr
                 #[cfg(any(rtc_v2l4, rtc_v2wb))]
@@ -157,7 +174,7 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
     where
         F: FnOnce(&crate::pac::rtc::Rtc) -> R,
     {
-        let r = T::regs();
+        let r = RTC::regs();
         // Disable write protection.
         // This is safe, as we're only writin the correct and expected values.
         r.wpr().write(|w| w.set_key(0xca));
@@ -218,5 +235,3 @@ impl sealed::Instance for crate::peripherals::RTC {
         }
     }
 }
-
-impl Instance for crate::peripherals::RTC {}
diff --git a/embassy-stm32/src/rtc/v3.rs b/embassy-stm32/src/rtc/v3.rs
index 9f04c9b69..3297303ee 100644
--- a/embassy-stm32/src/rtc/v3.rs
+++ b/embassy-stm32/src/rtc/v3.rs
@@ -1,42 +1,62 @@
 use stm32_metapac::rtc::vals::{Calp, Calw16, Calw8, Fmt, Init, Key, Osel, Pol, TampalrmPu, TampalrmType};
 
-use super::{sealed, Instance, RtcCalibrationCyclePeriod, RtcClockSource, RtcConfig};
+use super::{sealed, RtcCalibrationCyclePeriod, RtcClockSource, RtcConfig};
 use crate::pac::rtc::Rtc;
+use crate::peripherals::RTC;
+use crate::rtc::sealed::Instance;
 
-impl<'d, T: Instance> super::Rtc<'d, T> {
-    pub(super) fn enable(clock_source: RtcClockSource) {
+impl super::Rtc {
+    fn unlock_registers() {
         // Unlock the backup domain
         #[cfg(not(any(rtc_v3u5, rcc_wl5, rcc_wle)))]
         {
-            crate::pac::PWR.cr1().modify(|w| w.set_dbp(true));
-            while !crate::pac::PWR.cr1().read().dbp() {}
+            if !crate::pac::PWR.cr1().read().dbp() {
+                crate::pac::PWR.cr1().modify(|w| w.set_dbp(true));
+                while !crate::pac::PWR.cr1().read().dbp() {}
+            }
         }
         #[cfg(any(rcc_wl5, rcc_wle))]
         {
             use crate::pac::pwr::vals::Dbp;
 
-            crate::pac::PWR.cr1().modify(|w| w.set_dbp(Dbp::ENABLED));
-            while crate::pac::PWR.cr1().read().dbp() != Dbp::ENABLED {}
+            if crate::pac::PWR.cr1().read().dbp() != Dbp::ENABLED {
+                crate::pac::PWR.cr1().modify(|w| w.set_dbp(Dbp::ENABLED));
+                while crate::pac::PWR.cr1().read().dbp() != Dbp::ENABLED {}
+            }
         }
+    }
 
-        let reg = crate::pac::RCC.bdcr().read();
-        assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
-
+    #[allow(dead_code)]
+    pub(crate) fn set_clock_source(clock_source: RtcClockSource) {
         let clock_source = clock_source as u8;
         #[cfg(not(any(rcc_wl5, rcc_wle)))]
         let clock_source = crate::pac::rcc::vals::Rtcsel::from_bits(clock_source);
 
-        if !reg.rtcen() || reg.rtcsel() != clock_source {
-            crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true));
+        Self::unlock_registers();
+
+        crate::pac::RCC.bdcr().modify(|w| {
+            // Select RTC source
+            w.set_rtcsel(clock_source);
+        });
+    }
+
+    pub(super) fn enable() {
+        let bdcr = crate::pac::RCC.bdcr();
 
-            crate::pac::RCC.bdcr().modify(|w| {
+        let reg = bdcr.read();
+        assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
+
+        if !reg.rtcen() {
+            Self::unlock_registers();
+
+            bdcr.modify(|w| w.set_bdrst(true));
+
+            bdcr.modify(|w| {
                 // Reset
                 w.set_bdrst(false);
 
-                // Select RTC source
-                w.set_rtcsel(clock_source);
-
                 w.set_rtcen(true);
+                w.set_rtcsel(reg.rtcsel());
 
                 // Restore bcdr
                 w.set_lscosel(reg.lscosel());
@@ -141,7 +161,7 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
     where
         F: FnOnce(&crate::pac::rtc::Rtc) -> R,
     {
-        let r = T::regs();
+        let r = RTC::regs();
         // Disable write protection.
         // This is safe, as we're only writin the correct and expected values.
         r.wpr().write(|w| w.set_key(Key::DEACTIVATE1));
@@ -188,5 +208,3 @@ impl sealed::Instance for crate::peripherals::RTC {
         }
     }
 }
-
-impl Instance for crate::peripherals::RTC {}
diff --git a/examples/stm32wl/src/bin/rtc.rs b/examples/stm32wl/src/bin/rtc.rs
index 0d7906bde..fb1bc6e3d 100644
--- a/examples/stm32wl/src/bin/rtc.rs
+++ b/examples/stm32wl/src/bin/rtc.rs
@@ -27,10 +27,7 @@ async fn main(_spawner: Spawner) {
         .and_hms_opt(10, 30, 15)
         .unwrap();
 
-    let mut rtc = Rtc::new(
-        p.RTC,
-        RtcConfig::default().clock_source(embassy_stm32::rtc::RtcClockSource::LSE),
-    );
+    let mut rtc = Rtc::new(p.RTC, RtcConfig::default());
     info!("Got RTC! {:?}", now.timestamp());
 
     rtc.set_datetime(now.into()).expect("datetime not set");