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-rw-r--r--embassy-stm32/src/rcc/f013.rs10
1 files changed, 5 insertions, 5 deletions
diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 1a0e34614..8ceae6a8a 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -495,7 +495,7 @@ pub(crate) unsafe fn init(config: Config) {
495 TimClockSource::PClk2 => {} 495 TimClockSource::PClk2 => {}
496 TimClockSource::PllClk => { 496 TimClockSource::PllClk => {
497 RCC.cfgr3() 497 RCC.cfgr3()
498 .modify(|w| w.set_tim2sw(crate::pac::rcc::vals::Timsw::PLL1_P)); 498 .modify(|w| w.set_tim2sw(crate::pac::rcc::vals::Tim2sw::PLL1_P));
499 } 499 }
500 }; 500 };
501 501
@@ -533,7 +533,7 @@ pub(crate) unsafe fn init(config: Config) {
533 stm32f398 533 stm32f398
534 ))] 534 ))]
535 match config.tim.tim15 { 535 match config.tim.tim15 {
536 TimClockSource::PClk2 => None, 536 TimClockSource::PClk2 => {},
537 TimClockSource::PllClk => { 537 TimClockSource::PllClk => {
538 RCC.cfgr3() 538 RCC.cfgr3()
539 .modify(|w| w.set_tim15sw(crate::pac::rcc::vals::Timsw::PLL1_P)); 539 .modify(|w| w.set_tim15sw(crate::pac::rcc::vals::Timsw::PLL1_P));
@@ -548,7 +548,7 @@ pub(crate) unsafe fn init(config: Config) {
548 stm32f398 548 stm32f398
549 ))] 549 ))]
550 match config.tim.tim16 { 550 match config.tim.tim16 {
551 TimClockSource::PClk2 => None, 551 TimClockSource::PClk2 => {},
552 TimClockSource::PllClk => { 552 TimClockSource::PllClk => {
553 RCC.cfgr3() 553 RCC.cfgr3()
554 .modify(|w| w.set_tim16sw(crate::pac::rcc::vals::Timsw::PLL1_P)); 554 .modify(|w| w.set_tim16sw(crate::pac::rcc::vals::Timsw::PLL1_P));
@@ -563,7 +563,7 @@ pub(crate) unsafe fn init(config: Config) {
563 stm32f398 563 stm32f398
564 ))] 564 ))]
565 match config.tim.tim17 { 565 match config.tim.tim17 {
566 TimClockSource::PClk2 => None, 566 TimClockSource::PClk2 => {},
567 TimClockSource::PllClk => { 567 TimClockSource::PllClk => {
568 RCC.cfgr3() 568 RCC.cfgr3()
569 .modify(|w| w.set_tim17sw(crate::pac::rcc::vals::Timsw::PLL1_P)); 569 .modify(|w| w.set_tim17sw(crate::pac::rcc::vals::Timsw::PLL1_P));
@@ -572,7 +572,7 @@ pub(crate) unsafe fn init(config: Config) {
572 572
573 #[cfg(any(all(stm32f303, any(package_D, package_E))))] 573 #[cfg(any(all(stm32f303, any(package_D, package_E))))]
574 match config.tim.tim20 { 574 match config.tim.tim20 {
575 TimClockSource::PClk2 => None, 575 TimClockSource::PClk2 => {},
576 TimClockSource::PllClk => { 576 TimClockSource::PllClk => {
577 RCC.cfgr3() 577 RCC.cfgr3()
578 .modify(|w| w.set_tim20sw(crate::pac::rcc::vals::Timsw::PLL1_P)); 578 .modify(|w| w.set_tim20sw(crate::pac::rcc::vals::Timsw::PLL1_P));