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-rw-r--r--embassy-nrf/src/chips/nrf5340_app.rs318
-rw-r--r--embassy-nrf/src/chips/nrf5340_net.rs5
-rw-r--r--embassy-nrf/src/chips/nrf9160.rs244
3 files changed, 298 insertions, 269 deletions
diff --git a/embassy-nrf/src/chips/nrf5340_app.rs b/embassy-nrf/src/chips/nrf5340_app.rs
index afc2c4a7e..5e9a8ed05 100644
--- a/embassy-nrf/src/chips/nrf5340_app.rs
+++ b/embassy-nrf/src/chips/nrf5340_app.rs
@@ -6,10 +6,13 @@ pub mod pac {
6 // To avoid cfg spam, we remove _ns or _s suffixes here. 6 // To avoid cfg spam, we remove _ns or _s suffixes here.
7 7
8 pub use nrf5340_app_pac::NVIC_PRIO_BITS; 8 pub use nrf5340_app_pac::NVIC_PRIO_BITS;
9 9
10 #[cfg(feature="rt")]
11 #[doc(no_inline)]
12 pub use nrf5340_app_pac::interrupt;
13
10 #[doc(no_inline)] 14 #[doc(no_inline)]
11 pub use nrf5340_app_pac::{ 15 pub use nrf5340_app_pac::{
12 interrupt,
13 Interrupt, 16 Interrupt,
14 Peripherals, 17 Peripherals,
15 18
@@ -60,156 +63,167 @@ pub mod pac {
60 wdt0_ns as wdt0, 63 wdt0_ns as wdt0,
61 }; 64 };
62 65
63 #[cfg(feature = "nrf5340-app-ns")] 66 /// Non-Secure mode (NS) peripherals
64 #[doc(no_inline)] 67 pub mod ns {
65 pub use nrf5340_app_pac::{ 68 #[cfg(feature = "nrf5340-app-ns")]
66 CLOCK_NS as CLOCK, 69 #[doc(no_inline)]
67 COMP_NS as COMP, 70 pub use nrf5340_app_pac::{
68 CTRLAP_NS as CTRLAP, 71 CLOCK_NS as CLOCK,
69 DCNF_NS as DCNF, 72 COMP_NS as COMP,
70 DPPIC_NS as DPPIC, 73 CTRLAP_NS as CTRLAP,
71 EGU0_NS as EGU0, 74 DCNF_NS as DCNF,
72 EGU1_NS as EGU1, 75 DPPIC_NS as DPPIC,
73 EGU2_NS as EGU2, 76 EGU0_NS as EGU0,
74 EGU3_NS as EGU3, 77 EGU1_NS as EGU1,
75 EGU4_NS as EGU4, 78 EGU2_NS as EGU2,
76 EGU5_NS as EGU5, 79 EGU3_NS as EGU3,
77 FPU_NS as FPU, 80 EGU4_NS as EGU4,
78 GPIOTE1_NS as GPIOTE1, 81 EGU5_NS as EGU5,
79 I2S0_NS as I2S0, 82 FPU_NS as FPU,
80 IPC_NS as IPC, 83 GPIOTE1_NS as GPIOTE1,
81 KMU_NS as KMU, 84 I2S0_NS as I2S0,
82 LPCOMP_NS as LPCOMP, 85 IPC_NS as IPC,
83 MUTEX_NS as MUTEX, 86 KMU_NS as KMU,
84 NFCT_NS as NFCT, 87 LPCOMP_NS as LPCOMP,
85 NVMC_NS as NVMC, 88 MUTEX_NS as MUTEX,
86 OSCILLATORS_NS as OSCILLATORS, 89 NFCT_NS as NFCT,
87 P0_NS as P0, 90 NVMC_NS as NVMC,
88 P1_NS as P1, 91 OSCILLATORS_NS as OSCILLATORS,
89 PDM0_NS as PDM0, 92 P0_NS as P0,
90 POWER_NS as POWER, 93 P1_NS as P1,
91 PWM0_NS as PWM0, 94 PDM0_NS as PDM0,
92 PWM1_NS as PWM1, 95 POWER_NS as POWER,
93 PWM2_NS as PWM2, 96 PWM0_NS as PWM0,
94 PWM3_NS as PWM3, 97 PWM1_NS as PWM1,
95 QDEC0_NS as QDEC0, 98 PWM2_NS as PWM2,
96 QDEC1_NS as QDEC1, 99 PWM3_NS as PWM3,
97 QSPI_NS as QSPI, 100 QDEC0_NS as QDEC0,
98 REGULATORS_NS as REGULATORS, 101 QDEC1_NS as QDEC1,
99 RESET_NS as RESET, 102 QSPI_NS as QSPI,
100 RTC0_NS as RTC0, 103 REGULATORS_NS as REGULATORS,
101 RTC1_NS as RTC1, 104 RESET_NS as RESET,
102 SAADC_NS as SAADC, 105 RTC0_NS as RTC0,
103 SPIM0_NS as SPIM0, 106 RTC1_NS as RTC1,
104 SPIM1_NS as SPIM1, 107 SAADC_NS as SAADC,
105 SPIM2_NS as SPIM2, 108 SPIM0_NS as SPIM0,
106 SPIM3_NS as SPIM3, 109 SPIM1_NS as SPIM1,
107 SPIM4_NS as SPIM4, 110 SPIM2_NS as SPIM2,
108 SPIS0_NS as SPIS0, 111 SPIM3_NS as SPIM3,
109 SPIS1_NS as SPIS1, 112 SPIM4_NS as SPIM4,
110 SPIS2_NS as SPIS2, 113 SPIS0_NS as SPIS0,
111 SPIS3_NS as SPIS3, 114 SPIS1_NS as SPIS1,
112 TIMER0_NS as TIMER0, 115 SPIS2_NS as SPIS2,
113 TIMER1_NS as TIMER1, 116 SPIS3_NS as SPIS3,
114 TIMER2_NS as TIMER2, 117 TIMER0_NS as TIMER0,
115 TWIM0_NS as TWIM0, 118 TIMER1_NS as TIMER1,
116 TWIM1_NS as TWIM1, 119 TIMER2_NS as TIMER2,
117 TWIM2_NS as TWIM2, 120 TWIM0_NS as TWIM0,
118 TWIM3_NS as TWIM3, 121 TWIM1_NS as TWIM1,
119 TWIS0_NS as TWIS0, 122 TWIM2_NS as TWIM2,
120 TWIS1_NS as TWIS1, 123 TWIM3_NS as TWIM3,
121 TWIS2_NS as TWIS2, 124 TWIS0_NS as TWIS0,
122 TWIS3_NS as TWIS3, 125 TWIS1_NS as TWIS1,
123 UARTE0_NS as UARTE0, 126 TWIS2_NS as TWIS2,
124 UARTE1_NS as UARTE1, 127 TWIS3_NS as TWIS3,
125 UARTE2_NS as UARTE2, 128 UARTE0_NS as UARTE0,
126 UARTE3_NS as UARTE3, 129 UARTE1_NS as UARTE1,
127 USBD_NS as USBD, 130 UARTE2_NS as UARTE2,
128 USBREGULATOR_NS as USBREGULATOR, 131 UARTE3_NS as UARTE3,
129 VMC_NS as VMC, 132 USBD_NS as USBD,
130 WDT0_NS as WDT0, 133 USBREGULATOR_NS as USBREGULATOR,
131 WDT1_NS as WDT1, 134 VMC_NS as VMC,
132 }; 135 WDT0_NS as WDT0,
133 136 WDT1_NS as WDT1,
134 #[cfg(feature = "nrf5340-app-s")] 137 };
135 #[doc(no_inline)] 138 }
136 pub use nrf5340_app_pac::{ 139
137 CACHEDATA_S as CACHEDATA, 140 /// Secure mode (S) peripherals
138 CACHEINFO_S as CACHEINFO, 141 pub mod s {
139 CACHE_S as CACHE, 142 #[cfg(feature = "nrf5340-app-s")]
140 CLOCK_S as CLOCK, 143 #[doc(no_inline)]
141 COMP_S as COMP, 144 pub use nrf5340_app_pac::{
142 CRYPTOCELL_S as CRYPTOCELL, 145 CACHEDATA_S as CACHEDATA,
143 CTI_S as CTI, 146 CACHEINFO_S as CACHEINFO,
144 CTRLAP_S as CTRLAP, 147 CACHE_S as CACHE,
145 DCNF_S as DCNF, 148 CLOCK_S as CLOCK,
146 DPPIC_S as DPPIC, 149 COMP_S as COMP,
147 EGU0_S as EGU0, 150 CRYPTOCELL_S as CRYPTOCELL,
148 EGU1_S as EGU1, 151 CTI_S as CTI,
149 EGU2_S as EGU2, 152 CTRLAP_S as CTRLAP,
150 EGU3_S as EGU3, 153 DCNF_S as DCNF,
151 EGU4_S as EGU4, 154 DPPIC_S as DPPIC,
152 EGU5_S as EGU5, 155 EGU0_S as EGU0,
153 FICR_S as FICR, 156 EGU1_S as EGU1,
154 FPU_S as FPU, 157 EGU2_S as EGU2,
155 GPIOTE0_S as GPIOTE0, 158 EGU3_S as EGU3,
156 I2S0_S as I2S0, 159 EGU4_S as EGU4,
157 IPC_S as IPC, 160 EGU5_S as EGU5,
158 KMU_S as KMU, 161 FICR_S as FICR,
159 LPCOMP_S as LPCOMP, 162 FPU_S as FPU,
160 MUTEX_S as MUTEX, 163 GPIOTE0_S as GPIOTE0,
161 NFCT_S as NFCT, 164 I2S0_S as I2S0,
162 NVMC_S as NVMC, 165 IPC_S as IPC,
163 OSCILLATORS_S as OSCILLATORS, 166 KMU_S as KMU,
164 P0_S as P0, 167 LPCOMP_S as LPCOMP,
165 P1_S as P1, 168 MUTEX_S as MUTEX,
166 PDM0_S as PDM0, 169 NFCT_S as NFCT,
167 POWER_S as POWER, 170 NVMC_S as NVMC,
168 PWM0_S as PWM0, 171 OSCILLATORS_S as OSCILLATORS,
169 PWM1_S as PWM1, 172 P0_S as P0,
170 PWM2_S as PWM2, 173 P1_S as P1,
171 PWM3_S as PWM3, 174 PDM0_S as PDM0,
172 QDEC0_S as QDEC0, 175 POWER_S as POWER,
173 QDEC1_S as QDEC1, 176 PWM0_S as PWM0,
174 QSPI_S as QSPI, 177 PWM1_S as PWM1,
175 REGULATORS_S as REGULATORS, 178 PWM2_S as PWM2,
176 RESET_S as RESET, 179 PWM3_S as PWM3,
177 RTC0_S as RTC0, 180 QDEC0_S as QDEC0,
178 RTC1_S as RTC1, 181 QDEC1_S as QDEC1,
179 SAADC_S as SAADC, 182 QSPI_S as QSPI,
180 SPIM0_S as SPIM0, 183 REGULATORS_S as REGULATORS,
181 SPIM1_S as SPIM1, 184 RESET_S as RESET,
182 SPIM2_S as SPIM2, 185 RTC0_S as RTC0,
183 SPIM3_S as SPIM3, 186 RTC1_S as RTC1,
184 SPIM4_S as SPIM4, 187 SAADC_S as SAADC,
185 SPIS0_S as SPIS0, 188 SPIM0_S as SPIM0,
186 SPIS1_S as SPIS1, 189 SPIM1_S as SPIM1,
187 SPIS2_S as SPIS2, 190 SPIM2_S as SPIM2,
188 SPIS3_S as SPIS3, 191 SPIM3_S as SPIM3,
189 SPU_S as SPU, 192 SPIM4_S as SPIM4,
190 TAD_S as TAD, 193 SPIS0_S as SPIS0,
191 TIMER0_S as TIMER0, 194 SPIS1_S as SPIS1,
192 TIMER1_S as TIMER1, 195 SPIS2_S as SPIS2,
193 TIMER2_S as TIMER2, 196 SPIS3_S as SPIS3,
194 TWIM0_S as TWIM0, 197 SPU_S as SPU,
195 TWIM1_S as TWIM1, 198 TAD_S as TAD,
196 TWIM2_S as TWIM2, 199 TIMER0_S as TIMER0,
197 TWIM3_S as TWIM3, 200 TIMER1_S as TIMER1,
198 TWIS0_S as TWIS0, 201 TIMER2_S as TIMER2,
199 TWIS1_S as TWIS1, 202 TWIM0_S as TWIM0,
200 TWIS2_S as TWIS2, 203 TWIM1_S as TWIM1,
201 TWIS3_S as TWIS3, 204 TWIM2_S as TWIM2,
202 UARTE0_S as UARTE0, 205 TWIM3_S as TWIM3,
203 UARTE1_S as UARTE1, 206 TWIS0_S as TWIS0,
204 UARTE2_S as UARTE2, 207 TWIS1_S as TWIS1,
205 UARTE3_S as UARTE3, 208 TWIS2_S as TWIS2,
206 UICR_S as UICR, 209 TWIS3_S as TWIS3,
207 USBD_S as USBD, 210 UARTE0_S as UARTE0,
208 USBREGULATOR_S as USBREGULATOR, 211 UARTE1_S as UARTE1,
209 VMC_S as VMC, 212 UARTE2_S as UARTE2,
210 WDT0_S as WDT0, 213 UARTE3_S as UARTE3,
211 WDT1_S as WDT1, 214 UICR_S as UICR,
212 }; 215 USBD_S as USBD,
216 USBREGULATOR_S as USBREGULATOR,
217 VMC_S as VMC,
218 WDT0_S as WDT0,
219 WDT1_S as WDT1,
220 };
221 }
222
223 #[cfg(feature = "_ns")]
224 pub use ns::*;
225 #[cfg(feature = "_s")]
226 pub use s::*;
213} 227}
214 228
215/// The maximum buffer size that the EasyDMA can send/recv in one operation. 229/// The maximum buffer size that the EasyDMA can send/recv in one operation.
diff --git a/embassy-nrf/src/chips/nrf5340_net.rs b/embassy-nrf/src/chips/nrf5340_net.rs
index dee666a61..a7cf82872 100644
--- a/embassy-nrf/src/chips/nrf5340_net.rs
+++ b/embassy-nrf/src/chips/nrf5340_net.rs
@@ -7,9 +7,12 @@ pub mod pac {
7 7
8 pub use nrf5340_net_pac::NVIC_PRIO_BITS; 8 pub use nrf5340_net_pac::NVIC_PRIO_BITS;
9 9
10 #[cfg(feature="rt")]
11 #[doc(no_inline)]
12 pub use nrf5340_net_pac::interrupt;
13
10 #[doc(no_inline)] 14 #[doc(no_inline)]
11 pub use nrf5340_net_pac::{ 15 pub use nrf5340_net_pac::{
12 interrupt,
13 Interrupt, 16 Interrupt,
14 Peripherals, 17 Peripherals,
15 18
diff --git a/embassy-nrf/src/chips/nrf9160.rs b/embassy-nrf/src/chips/nrf9160.rs
index 495285ba3..8b1356ef8 100644
--- a/embassy-nrf/src/chips/nrf9160.rs
+++ b/embassy-nrf/src/chips/nrf9160.rs
@@ -7,9 +7,12 @@ pub mod pac {
7 7
8 pub use nrf9160_pac::NVIC_PRIO_BITS; 8 pub use nrf9160_pac::NVIC_PRIO_BITS;
9 9
10 #[cfg(feature="rt")]
11 #[doc(no_inline)]
12 pub use nrf9160_pac::interrupt;
13
10 #[doc(no_inline)] 14 #[doc(no_inline)]
11 pub use nrf9160_pac::{ 15 pub use nrf9160_pac::{
12 interrupt,
13 Interrupt, 16 Interrupt,
14 17
15 cc_host_rgf_s as cc_host_rgf, 18 cc_host_rgf_s as cc_host_rgf,
@@ -45,122 +48,131 @@ pub mod pac {
45 wdt_ns as wdt, 48 wdt_ns as wdt,
46 }; 49 };
47 50
48 #[cfg(feature = "nrf9160-ns")] 51 /// Non-Secure mode (NS) peripherals
49 #[doc(no_inline)] 52 pub mod ns {
50 pub use nrf9160_pac::{ 53 #[doc(no_inline)]
51 CLOCK_NS as CLOCK, 54 pub use nrf9160_pac::{
52 DPPIC_NS as DPPIC, 55 CLOCK_NS as CLOCK,
53 EGU0_NS as EGU0, 56 DPPIC_NS as DPPIC,
54 EGU1_NS as EGU1, 57 EGU0_NS as EGU0,
55 EGU2_NS as EGU2, 58 EGU1_NS as EGU1,
56 EGU3_NS as EGU3, 59 EGU2_NS as EGU2,
57 EGU4_NS as EGU4, 60 EGU3_NS as EGU3,
58 EGU5_NS as EGU5, 61 EGU4_NS as EGU4,
59 FPU_NS as FPU, 62 EGU5_NS as EGU5,
60 GPIOTE1_NS as GPIOTE1, 63 FPU_NS as FPU,
61 I2S_NS as I2S, 64 GPIOTE1_NS as GPIOTE1,
62 IPC_NS as IPC, 65 I2S_NS as I2S,
63 KMU_NS as KMU, 66 IPC_NS as IPC,
64 NVMC_NS as NVMC, 67 KMU_NS as KMU,
65 P0_NS as P0, 68 NVMC_NS as NVMC,
66 PDM_NS as PDM, 69 P0_NS as P0,
67 POWER_NS as POWER, 70 PDM_NS as PDM,
68 PWM0_NS as PWM0, 71 POWER_NS as POWER,
69 PWM1_NS as PWM1, 72 PWM0_NS as PWM0,
70 PWM2_NS as PWM2, 73 PWM1_NS as PWM1,
71 PWM3_NS as PWM3, 74 PWM2_NS as PWM2,
72 REGULATORS_NS as REGULATORS, 75 PWM3_NS as PWM3,
73 RTC0_NS as RTC0, 76 REGULATORS_NS as REGULATORS,
74 RTC1_NS as RTC1, 77 RTC0_NS as RTC0,
75 SAADC_NS as SAADC, 78 RTC1_NS as RTC1,
76 SPIM0_NS as SPIM0, 79 SAADC_NS as SAADC,
77 SPIM1_NS as SPIM1, 80 SPIM0_NS as SPIM0,
78 SPIM2_NS as SPIM2, 81 SPIM1_NS as SPIM1,
79 SPIM3_NS as SPIM3, 82 SPIM2_NS as SPIM2,
80 SPIS0_NS as SPIS0, 83 SPIM3_NS as SPIM3,
81 SPIS1_NS as SPIS1, 84 SPIS0_NS as SPIS0,
82 SPIS2_NS as SPIS2, 85 SPIS1_NS as SPIS1,
83 SPIS3_NS as SPIS3, 86 SPIS2_NS as SPIS2,
84 TIMER0_NS as TIMER0, 87 SPIS3_NS as SPIS3,
85 TIMER1_NS as TIMER1, 88 TIMER0_NS as TIMER0,
86 TIMER2_NS as TIMER2, 89 TIMER1_NS as TIMER1,
87 TWIM0_NS as TWIM0, 90 TIMER2_NS as TIMER2,
88 TWIM1_NS as TWIM1, 91 TWIM0_NS as TWIM0,
89 TWIM2_NS as TWIM2, 92 TWIM1_NS as TWIM1,
90 TWIM3_NS as TWIM3, 93 TWIM2_NS as TWIM2,
91 TWIS0_NS as TWIS0, 94 TWIM3_NS as TWIM3,
92 TWIS1_NS as TWIS1, 95 TWIS0_NS as TWIS0,
93 TWIS2_NS as TWIS2, 96 TWIS1_NS as TWIS1,
94 TWIS3_NS as TWIS3, 97 TWIS2_NS as TWIS2,
95 UARTE0_NS as UARTE0, 98 TWIS3_NS as TWIS3,
96 UARTE1_NS as UARTE1, 99 UARTE0_NS as UARTE0,
97 UARTE2_NS as UARTE2, 100 UARTE1_NS as UARTE1,
98 UARTE3_NS as UARTE3, 101 UARTE2_NS as UARTE2,
99 VMC_NS as VMC, 102 UARTE3_NS as UARTE3,
100 WDT_NS as WDT, 103 VMC_NS as VMC,
101 }; 104 WDT_NS as WDT,
105 };
106 }
102 107
103 #[cfg(feature = "nrf9160-s")] 108 /// Secure mode (S) peripherals
104 #[doc(no_inline)] 109 pub mod s {
105 pub use nrf9160_pac::{ 110 #[doc(no_inline)]
106 CC_HOST_RGF_S as CC_HOST_RGF, 111 pub use nrf9160_pac::{
107 CLOCK_S as CLOCK, 112 CC_HOST_RGF_S as CC_HOST_RGF,
108 CRYPTOCELL_S as CRYPTOCELL, 113 CLOCK_S as CLOCK,
109 CTRL_AP_PERI_S as CTRL_AP_PERI, 114 CRYPTOCELL_S as CRYPTOCELL,
110 DPPIC_S as DPPIC, 115 CTRL_AP_PERI_S as CTRL_AP_PERI,
111 EGU0_S as EGU0, 116 DPPIC_S as DPPIC,
112 EGU1_S as EGU1, 117 EGU0_S as EGU0,
113 EGU2_S as EGU2, 118 EGU1_S as EGU1,
114 EGU3_S as EGU3, 119 EGU2_S as EGU2,
115 EGU4_S as EGU4, 120 EGU3_S as EGU3,
116 EGU5_S as EGU5, 121 EGU4_S as EGU4,
117 FICR_S as FICR, 122 EGU5_S as EGU5,
118 FPU_S as FPU, 123 FICR_S as FICR,
119 GPIOTE0_S as GPIOTE0, 124 FPU_S as FPU,
120 I2S_S as I2S, 125 GPIOTE0_S as GPIOTE0,
121 IPC_S as IPC, 126 I2S_S as I2S,
122 KMU_S as KMU, 127 IPC_S as IPC,
123 NVMC_S as NVMC, 128 KMU_S as KMU,
124 P0_S as P0, 129 NVMC_S as NVMC,
125 PDM_S as PDM, 130 P0_S as P0,
126 POWER_S as POWER, 131 PDM_S as PDM,
127 PWM0_S as PWM0, 132 POWER_S as POWER,
128 PWM1_S as PWM1, 133 PWM0_S as PWM0,
129 PWM2_S as PWM2, 134 PWM1_S as PWM1,
130 PWM3_S as PWM3, 135 PWM2_S as PWM2,
131 REGULATORS_S as REGULATORS, 136 PWM3_S as PWM3,
132 RTC0_S as RTC0, 137 REGULATORS_S as REGULATORS,
133 RTC1_S as RTC1, 138 RTC0_S as RTC0,
134 SAADC_S as SAADC, 139 RTC1_S as RTC1,
135 SPIM0_S as SPIM0, 140 SAADC_S as SAADC,
136 SPIM1_S as SPIM1, 141 SPIM0_S as SPIM0,
137 SPIM2_S as SPIM2, 142 SPIM1_S as SPIM1,
138 SPIM3_S as SPIM3, 143 SPIM2_S as SPIM2,
139 SPIS0_S as SPIS0, 144 SPIM3_S as SPIM3,
140 SPIS1_S as SPIS1, 145 SPIS0_S as SPIS0,
141 SPIS2_S as SPIS2, 146 SPIS1_S as SPIS1,
142 SPIS3_S as SPIS3, 147 SPIS2_S as SPIS2,
143 SPU_S as SPU, 148 SPIS3_S as SPIS3,
144 TAD_S as TAD, 149 SPU_S as SPU,
145 TIMER0_S as TIMER0, 150 TAD_S as TAD,
146 TIMER1_S as TIMER1, 151 TIMER0_S as TIMER0,
147 TIMER2_S as TIMER2, 152 TIMER1_S as TIMER1,
148 TWIM0_S as TWIM0, 153 TIMER2_S as TIMER2,
149 TWIM1_S as TWIM1, 154 TWIM0_S as TWIM0,
150 TWIM2_S as TWIM2, 155 TWIM1_S as TWIM1,
151 TWIM3_S as TWIM3, 156 TWIM2_S as TWIM2,
152 TWIS0_S as TWIS0, 157 TWIM3_S as TWIM3,
153 TWIS1_S as TWIS1, 158 TWIS0_S as TWIS0,
154 TWIS2_S as TWIS2, 159 TWIS1_S as TWIS1,
155 TWIS3_S as TWIS3, 160 TWIS2_S as TWIS2,
156 UARTE0_S as UARTE0, 161 TWIS3_S as TWIS3,
157 UARTE1_S as UARTE1, 162 UARTE0_S as UARTE0,
158 UARTE2_S as UARTE2, 163 UARTE1_S as UARTE1,
159 UARTE3_S as UARTE3, 164 UARTE2_S as UARTE2,
160 UICR_S as UICR, 165 UARTE3_S as UARTE3,
161 VMC_S as VMC, 166 UICR_S as UICR,
162 WDT_S as WDT, 167 VMC_S as VMC,
163 }; 168 WDT_S as WDT,
169 };
170 }
171
172 #[cfg(feature = "_ns")]
173 pub use ns::*;
174 #[cfg(feature = "_s")]
175 pub use s::*;
164} 176}
165 177
166/// The maximum buffer size that the EasyDMA can send/recv in one operation. 178/// The maximum buffer size that the EasyDMA can send/recv in one operation.
generated by cgit (git 2.34.1) at 2026-04-05 21:50:43 +0000