aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--embassy-stm32/Cargo.toml4
-rw-r--r--embassy-stm32/build.rs69
-rw-r--r--embassy-stm32/src/adc/f1.rs3
-rw-r--r--embassy-stm32/src/adc/f3.rs2
-rw-r--r--embassy-stm32/src/adc/mod.rs7
-rw-r--r--embassy-stm32/src/eth/mod.rs3
-rw-r--r--embassy-stm32/src/eth/v1/mod.rs4
-rw-r--r--embassy-stm32/src/eth/v2/mod.rs4
-rw-r--r--embassy-stm32/src/hrtim/mod.rs4
-rw-r--r--embassy-stm32/src/hrtim/traits.rs16
-rw-r--r--embassy-stm32/src/i2s.rs9
-rw-r--r--embassy-stm32/src/rcc/c0.rs15
-rw-r--r--embassy-stm32/src/rcc/f.rs59
-rw-r--r--embassy-stm32/src/rcc/f0.rs21
-rw-r--r--embassy-stm32/src/rcc/f1.rs19
-rw-r--r--embassy-stm32/src/rcc/f3.rs22
-rw-r--r--embassy-stm32/src/rcc/g0.rs15
-rw-r--r--embassy-stm32/src/rcc/g4.rs23
-rw-r--r--embassy-stm32/src/rcc/h.rs61
-rw-r--r--embassy-stm32/src/rcc/l.rs75
-rw-r--r--embassy-stm32/src/rcc/mod.rs159
-rw-r--r--embassy-stm32/src/rcc/u5.rs46
-rw-r--r--embassy-stm32/src/rcc/wba.rs32
-rw-r--r--embassy-stm32/src/sdmmc/mod.rs64
-rw-r--r--embassy-stm32/src/usb/usb.rs2
25 files changed, 286 insertions, 452 deletions
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index aed9f7a46..c412e13d5 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -68,7 +68,7 @@ rand_core = "0.6.3"
68sdio-host = "0.5.0" 68sdio-host = "0.5.0"
69critical-section = "1.1" 69critical-section = "1.1"
70#stm32-metapac = { version = "15" } 70#stm32-metapac = { version = "15" }
71stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-768b3e8e3199e03de0acd0d4590d06f51eebb7dd" } 71stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-3e3b53df78b4c90ae9c44a58b4f9f93c93a415b7" }
72vcell = "0.1.3" 72vcell = "0.1.3"
73bxcan = "0.7.0" 73bxcan = "0.7.0"
74nb = "1.0.0" 74nb = "1.0.0"
@@ -89,7 +89,7 @@ critical-section = { version = "1.1", features = ["std"] }
89proc-macro2 = "1.0.36" 89proc-macro2 = "1.0.36"
90quote = "1.0.15" 90quote = "1.0.15"
91#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]} 91#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
92stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-768b3e8e3199e03de0acd0d4590d06f51eebb7dd", default-features = false, features = ["metadata"]} 92stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-3e3b53df78b4c90ae9c44a58b4f9f93c93a415b7", default-features = false, features = ["metadata"]}
93 93
94 94
95[features] 95[features]
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 74cc3f8b9..3885c5d18 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -461,6 +461,8 @@ fn main() {
461 let force_refcount = HashSet::from(["usart"]); 461 let force_refcount = HashSet::from(["usart"]);
462 let mut refcount_statics = BTreeSet::new(); 462 let mut refcount_statics = BTreeSet::new();
463 463
464 let mut clock_names = BTreeSet::new();
465
464 for p in METADATA.peripherals { 466 for p in METADATA.peripherals {
465 if !singletons.contains(&p.name.to_string()) { 467 if !singletons.contains(&p.name.to_string()) {
466 continue; 468 continue;
@@ -492,7 +494,6 @@ fn main() {
492 494
493 let ptype = if let Some(reg) = &p.registers { reg.kind } else { "" }; 495 let ptype = if let Some(reg) = &p.registers { reg.kind } else { "" };
494 let pname = format_ident!("{}", p.name); 496 let pname = format_ident!("{}", p.name);
495 let clk = format_ident!("{}", rcc.clock);
496 let en_reg = format_ident!("{}", en.register); 497 let en_reg = format_ident!("{}", en.register);
497 let set_en_field = format_ident!("set_{}", en.field); 498 let set_en_field = format_ident!("set_{}", en.field);
498 499
@@ -522,14 +523,7 @@ fn main() {
522 (TokenStream::new(), TokenStream::new()) 523 (TokenStream::new(), TokenStream::new())
523 }; 524 };
524 525
525 let mux_supported = HashSet::from(["c0", "h5", "h50", "h7", "h7ab", "h7rm0433", "g0", "g4", "l4"])
526 .contains(rcc_registers.version);
527 let mux_for = |mux: Option<&'static PeripheralRccRegister>| { 526 let mux_for = |mux: Option<&'static PeripheralRccRegister>| {
528 // restrict mux implementation to supported versions
529 if !mux_supported {
530 return None;
531 }
532
533 let mux = mux?; 527 let mux = mux?;
534 let fieldset = rcc_enum_map.get(mux.register)?; 528 let fieldset = rcc_enum_map.get(mux.register)?;
535 let enumm = fieldset.get(mux.field)?; 529 let enumm = fieldset.get(mux.field)?;
@@ -550,15 +544,9 @@ fn main() {
550 .map(|v| { 544 .map(|v| {
551 let variant_name = format_ident!("{}", v.name); 545 let variant_name = format_ident!("{}", v.name);
552 let clock_name = format_ident!("{}", v.name.to_ascii_lowercase()); 546 let clock_name = format_ident!("{}", v.name.to_ascii_lowercase());
553 547 clock_names.insert(v.name.to_ascii_lowercase());
554 if v.name.starts_with("HCLK") || v.name.starts_with("PCLK") || v.name == "SYS" { 548 quote! {
555 quote! { 549 #enum_name::#variant_name => unsafe { crate::rcc::get_freqs().#clock_name.unwrap() },
556 #enum_name::#variant_name => unsafe { crate::rcc::get_freqs().#clock_name },
557 }
558 } else {
559 quote! {
560 #enum_name::#variant_name => unsafe { crate::rcc::get_freqs().#clock_name.unwrap() },
561 }
562 } 550 }
563 }) 551 })
564 .collect(); 552 .collect();
@@ -569,19 +557,21 @@ fn main() {
569 #[allow(unreachable_patterns)] 557 #[allow(unreachable_patterns)]
570 match crate::pac::RCC.#fieldset_name().read().#field_name() { 558 match crate::pac::RCC.#fieldset_name().read().#field_name() {
571 #match_arms 559 #match_arms
572
573 _ => unreachable!(), 560 _ => unreachable!(),
574 } 561 }
575 } 562 }
576 } 563 }
577 None => quote! { 564 None => {
578 unsafe { crate::rcc::get_freqs().#clk } 565 let clock_name = format_ident!("{}", rcc.clock);
579 }, 566 clock_names.insert(rcc.clock.to_string());
567 quote! {
568 unsafe { crate::rcc::get_freqs().#clock_name.unwrap() }
569 }
570 }
580 }; 571 };
581 572
582 /* 573 /*
583 A refcount leak can result if the same field is shared by peripherals with different stop modes 574 A refcount leak can result if the same field is shared by peripherals with different stop modes
584
585 This condition should be checked in stm32-data 575 This condition should be checked in stm32-data
586 */ 576 */
587 let stop_refcount = match rcc.stop_mode { 577 let stop_refcount = match rcc.stop_mode {
@@ -628,6 +618,39 @@ fn main() {
628 } 618 }
629 } 619 }
630 620
621 // Generate RCC
622 clock_names.insert("sys".to_string());
623 clock_names.insert("rtc".to_string());
624 let clock_idents: Vec<_> = clock_names.iter().map(|n| format_ident!("{}", n)).collect();
625 g.extend(quote! {
626 #[derive(Clone, Copy, Debug)]
627 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
628 pub struct Clocks {
629 #(
630 pub #clock_idents: Option<crate::time::Hertz>,
631 )*
632 }
633 });
634
635 let clocks_macro = quote!(
636 macro_rules! set_clocks {
637 ($($(#[$m:meta])* $k:ident: $v:expr,)*) => {
638 {
639 #[allow(unused)]
640 struct Temp {
641 $($(#[$m])* $k: Option<crate::time::Hertz>,)*
642 }
643 let all = Temp {
644 $($(#[$m])* $k: $v,)*
645 };
646 crate::rcc::set_freqs(crate::rcc::Clocks {
647 #( #clock_idents: all.#clock_idents, )*
648 });
649 }
650 };
651 }
652 );
653
631 let refcount_mod: TokenStream = refcount_statics 654 let refcount_mod: TokenStream = refcount_statics
632 .iter() 655 .iter()
633 .map(|refcount_static| { 656 .map(|refcount_static| {
@@ -1349,7 +1372,7 @@ fn main() {
1349 } 1372 }
1350 } 1373 }
1351 1374
1352 let mut m = String::new(); 1375 let mut m = clocks_macro.to_string();
1353 1376
1354 // DO NOT ADD more macros like these. 1377 // DO NOT ADD more macros like these.
1355 // These turned to be a bad idea! 1378 // These turned to be a bad idea!
diff --git a/embassy-stm32/src/adc/f1.rs b/embassy-stm32/src/adc/f1.rs
index fb27bb87b..c896d8e3a 100644
--- a/embassy-stm32/src/adc/f1.rs
+++ b/embassy-stm32/src/adc/f1.rs
@@ -6,7 +6,6 @@ use embassy_hal_internal::into_ref;
6use embedded_hal_02::blocking::delay::DelayUs; 6use embedded_hal_02::blocking::delay::DelayUs;
7 7
8use crate::adc::{Adc, AdcPin, Instance, SampleTime}; 8use crate::adc::{Adc, AdcPin, Instance, SampleTime};
9use crate::rcc::get_freqs;
10use crate::time::Hertz; 9use crate::time::Hertz;
11use crate::{interrupt, Peripheral}; 10use crate::{interrupt, Peripheral};
12 11
@@ -80,7 +79,7 @@ impl<'d, T: Instance> Adc<'d, T> {
80 } 79 }
81 80
82 fn freq() -> Hertz { 81 fn freq() -> Hertz {
83 unsafe { get_freqs() }.adc.unwrap() 82 T::frequency()
84 } 83 }
85 84
86 pub fn sample_time_for_us(&self, us: u32) -> SampleTime { 85 pub fn sample_time_for_us(&self, us: u32) -> SampleTime {
diff --git a/embassy-stm32/src/adc/f3.rs b/embassy-stm32/src/adc/f3.rs
index 6f59c230f..6606a2b9c 100644
--- a/embassy-stm32/src/adc/f3.rs
+++ b/embassy-stm32/src/adc/f3.rs
@@ -102,7 +102,7 @@ impl<'d, T: Instance> Adc<'d, T> {
102 } 102 }
103 103
104 fn freq() -> Hertz { 104 fn freq() -> Hertz {
105 <T as crate::adc::sealed::Instance>::frequency() 105 <T as crate::rcc::sealed::RccPeripheral>::frequency()
106 } 106 }
107 107
108 pub fn sample_time_for_us(&self, us: u32) -> SampleTime { 108 pub fn sample_time_for_us(&self, us: u32) -> SampleTime {
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index e4dd35c34..d21c3053f 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -61,8 +61,6 @@ pub(crate) mod sealed {
61 fn regs() -> crate::pac::adc::Adc; 61 fn regs() -> crate::pac::adc::Adc;
62 #[cfg(not(any(adc_f1, adc_v1, adc_f3_v2, adc_f3_v1_1, adc_g0)))] 62 #[cfg(not(any(adc_f1, adc_v1, adc_f3_v2, adc_f3_v1_1, adc_g0)))]
63 fn common_regs() -> crate::pac::adccommon::AdcCommon; 63 fn common_regs() -> crate::pac::adccommon::AdcCommon;
64 #[cfg(adc_f3)]
65 fn frequency() -> crate::time::Hertz;
66 #[cfg(any(adc_f1, adc_f3, adc_v1, adc_f3_v1_1))] 64 #[cfg(any(adc_f1, adc_f3, adc_v1, adc_f3_v1_1))]
67 fn state() -> &'static State; 65 fn state() -> &'static State;
68 } 66 }
@@ -103,11 +101,6 @@ foreach_adc!(
103 return crate::pac::$common_inst 101 return crate::pac::$common_inst
104 } 102 }
105 103
106 #[cfg(adc_f3)]
107 fn frequency() -> crate::time::Hertz {
108 unsafe { crate::rcc::get_freqs() }.$clock.unwrap()
109 }
110
111 #[cfg(any(adc_f1, adc_f3, adc_v1, adc_f3_v1_1))] 104 #[cfg(any(adc_f1, adc_f3, adc_v1, adc_f3_v1_1))]
112 fn state() -> &'static sealed::State { 105 fn state() -> &'static sealed::State {
113 static STATE: sealed::State = sealed::State::new(); 106 static STATE: sealed::State = sealed::State::new();
diff --git a/embassy-stm32/src/eth/mod.rs b/embassy-stm32/src/eth/mod.rs
index fbcdd7fae..71fe09c3f 100644
--- a/embassy-stm32/src/eth/mod.rs
+++ b/embassy-stm32/src/eth/mod.rs
@@ -13,6 +13,7 @@ use embassy_net_driver::{Capabilities, HardwareAddress, LinkState};
13use embassy_sync::waitqueue::AtomicWaker; 13use embassy_sync::waitqueue::AtomicWaker;
14 14
15pub use self::_version::{InterruptHandler, *}; 15pub use self::_version::{InterruptHandler, *};
16use crate::rcc::RccPeripheral;
16 17
17#[allow(unused)] 18#[allow(unused)]
18const MTU: usize = 1514; 19const MTU: usize = 1514;
@@ -183,7 +184,7 @@ pub(crate) mod sealed {
183} 184}
184 185
185/// Ethernet instance. 186/// Ethernet instance.
186pub trait Instance: sealed::Instance + Send + 'static {} 187pub trait Instance: sealed::Instance + RccPeripheral + Send + 'static {}
187 188
188impl sealed::Instance for crate::peripherals::ETH { 189impl sealed::Instance for crate::peripherals::ETH {
189 fn regs() -> crate::pac::eth::Eth { 190 fn regs() -> crate::pac::eth::Eth {
diff --git a/embassy-stm32/src/eth/v1/mod.rs b/embassy-stm32/src/eth/v1/mod.rs
index 2ce5b3927..e5b7b0452 100644
--- a/embassy-stm32/src/eth/v1/mod.rs
+++ b/embassy-stm32/src/eth/v1/mod.rs
@@ -20,6 +20,7 @@ use crate::pac::AFIO;
20#[cfg(any(eth_v1b, eth_v1c))] 20#[cfg(any(eth_v1b, eth_v1c))]
21use crate::pac::SYSCFG; 21use crate::pac::SYSCFG;
22use crate::pac::{ETH, RCC}; 22use crate::pac::{ETH, RCC};
23use crate::rcc::sealed::RccPeripheral;
23use crate::{interrupt, Peripheral}; 24use crate::{interrupt, Peripheral};
24 25
25/// Interrupt handler. 26/// Interrupt handler.
@@ -191,8 +192,7 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
191 192
192 // TODO MTU size setting not found for v1 ethernet, check if correct 193 // TODO MTU size setting not found for v1 ethernet, check if correct
193 194
194 // NOTE(unsafe) We got the peripheral singleton, which means that `rcc::init` was called 195 let hclk = <T as RccPeripheral>::frequency();
195 let hclk = unsafe { crate::rcc::get_freqs() }.hclk1;
196 let hclk_mhz = hclk.0 / 1_000_000; 196 let hclk_mhz = hclk.0 / 1_000_000;
197 197
198 // Set the MDC clock frequency in the range 1MHz - 2.5MHz 198 // Set the MDC clock frequency in the range 1MHz - 2.5MHz
diff --git a/embassy-stm32/src/eth/v2/mod.rs b/embassy-stm32/src/eth/v2/mod.rs
index 4b22d1d21..8d69561d4 100644
--- a/embassy-stm32/src/eth/v2/mod.rs
+++ b/embassy-stm32/src/eth/v2/mod.rs
@@ -11,6 +11,7 @@ use crate::gpio::sealed::{AFType, Pin as _};
11use crate::gpio::{AnyPin, Speed}; 11use crate::gpio::{AnyPin, Speed};
12use crate::interrupt::InterruptExt; 12use crate::interrupt::InterruptExt;
13use crate::pac::ETH; 13use crate::pac::ETH;
14use crate::rcc::sealed::RccPeripheral;
14use crate::{interrupt, Peripheral}; 15use crate::{interrupt, Peripheral};
15 16
16/// Interrupt handler. 17/// Interrupt handler.
@@ -264,8 +265,7 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
264 w.set_rbsz(RX_BUFFER_SIZE as u16); 265 w.set_rbsz(RX_BUFFER_SIZE as u16);
265 }); 266 });
266 267
267 // NOTE(unsafe) We got the peripheral singleton, which means that `rcc::init` was called 268 let hclk = <T as RccPeripheral>::frequency();
268 let hclk = unsafe { crate::rcc::get_freqs() }.hclk1;
269 let hclk_mhz = hclk.0 / 1_000_000; 269 let hclk_mhz = hclk.0 / 1_000_000;
270 270
271 // Set the MDC clock frequency in the range 1MHz - 2.5MHz 271 // Set the MDC clock frequency in the range 1MHz - 2.5MHz
diff --git a/embassy-stm32/src/hrtim/mod.rs b/embassy-stm32/src/hrtim/mod.rs
index faefaabbc..3ec646fc3 100644
--- a/embassy-stm32/src/hrtim/mod.rs
+++ b/embassy-stm32/src/hrtim/mod.rs
@@ -10,8 +10,6 @@ pub use traits::Instance;
10#[allow(unused_imports)] 10#[allow(unused_imports)]
11use crate::gpio::sealed::{AFType, Pin}; 11use crate::gpio::sealed::{AFType, Pin};
12use crate::gpio::AnyPin; 12use crate::gpio::AnyPin;
13#[cfg(stm32f334)]
14use crate::rcc::get_freqs;
15use crate::time::Hertz; 13use crate::time::Hertz;
16use crate::Peripheral; 14use crate::Peripheral;
17 15
@@ -182,7 +180,7 @@ impl<'d, T: Instance> AdvancedPwm<'d, T> {
182 T::enable_and_reset(); 180 T::enable_and_reset();
183 181
184 #[cfg(stm32f334)] 182 #[cfg(stm32f334)]
185 if unsafe { get_freqs() }.hrtim.is_some() { 183 if crate::pac::RCC.cfgr3().read().hrtim1sw() == crate::pac::rcc::vals::Timsw::PLL1_P {
186 // Enable and and stabilize the DLL 184 // Enable and and stabilize the DLL
187 T::regs().dllcr().modify(|w| { 185 T::regs().dllcr().modify(|w| {
188 w.set_cal(true); 186 w.set_cal(true);
diff --git a/embassy-stm32/src/hrtim/traits.rs b/embassy-stm32/src/hrtim/traits.rs
index cfd31c47c..dcc2b9ef4 100644
--- a/embassy-stm32/src/hrtim/traits.rs
+++ b/embassy-stm32/src/hrtim/traits.rs
@@ -80,10 +80,12 @@ pub(crate) mod sealed {
80 80
81 fn set_master_frequency(frequency: Hertz) { 81 fn set_master_frequency(frequency: Hertz) {
82 let f = frequency.0; 82 let f = frequency.0;
83 #[cfg(not(stm32f334))] 83
84 // TODO: wire up HRTIM to the RCC mux infra.
85 //#[cfg(stm32f334)]
86 //let timer_f = unsafe { crate::rcc::get_freqs() }.hrtim.unwrap_or(Self::frequency()).0;
87 //#[cfg(not(stm32f334))]
84 let timer_f = Self::frequency().0; 88 let timer_f = Self::frequency().0;
85 #[cfg(stm32f334)]
86 let timer_f = unsafe { crate::rcc::get_freqs() }.hrtim.unwrap_or(Self::frequency()).0;
87 89
88 let psc_min = (timer_f / f) / (u16::MAX as u32 / 32); 90 let psc_min = (timer_f / f) / (u16::MAX as u32 / 32);
89 let psc = if Self::regs().isr().read().dllrdy() { 91 let psc = if Self::regs().isr().read().dllrdy() {
@@ -103,10 +105,12 @@ pub(crate) mod sealed {
103 105
104 fn set_channel_frequency(channel: usize, frequency: Hertz) { 106 fn set_channel_frequency(channel: usize, frequency: Hertz) {
105 let f = frequency.0; 107 let f = frequency.0;
106 #[cfg(not(stm32f334))] 108
109 // TODO: wire up HRTIM to the RCC mux infra.
110 //#[cfg(stm32f334)]
111 //let timer_f = unsafe { crate::rcc::get_freqs() }.hrtim.unwrap_or(Self::frequency()).0;
112 //#[cfg(not(stm32f334))]
107 let timer_f = Self::frequency().0; 113 let timer_f = Self::frequency().0;
108 #[cfg(stm32f334)]
109 let timer_f = unsafe { crate::rcc::get_freqs() }.hrtim.unwrap_or(Self::frequency()).0;
110 114
111 let psc_min = (timer_f / f) / (u16::MAX as u32 / 32); 115 let psc_min = (timer_f / f) / (u16::MAX as u32 / 32);
112 let psc = if Self::regs().isr().read().dllrdy() { 116 let psc = if Self::regs().isr().read().dllrdy() {
diff --git a/embassy-stm32/src/i2s.rs b/embassy-stm32/src/i2s.rs
index 1f85c0bc5..e9065dce6 100644
--- a/embassy-stm32/src/i2s.rs
+++ b/embassy-stm32/src/i2s.rs
@@ -4,7 +4,6 @@ use embassy_hal_internal::into_ref;
4use crate::gpio::sealed::{AFType, Pin as _}; 4use crate::gpio::sealed::{AFType, Pin as _};
5use crate::gpio::AnyPin; 5use crate::gpio::AnyPin;
6use crate::pac::spi::vals; 6use crate::pac::spi::vals;
7use crate::rcc::get_freqs;
8use crate::spi::{Config as SpiConfig, *}; 7use crate::spi::{Config as SpiConfig, *};
9use crate::time::Hertz; 8use crate::time::Hertz;
10use crate::{Peripheral, PeripheralRef}; 9use crate::{Peripheral, PeripheralRef};
@@ -193,10 +192,10 @@ impl<'d, T: Instance, Tx, Rx> I2S<'d, T, Tx, Rx> {
193 spi_cfg.frequency = freq; 192 spi_cfg.frequency = freq;
194 let spi = Spi::new_internal(peri, txdma, rxdma, spi_cfg); 193 let spi = Spi::new_internal(peri, txdma, rxdma, spi_cfg);
195 194
196 #[cfg(all(rcc_f4, not(stm32f410)))] 195 // TODO move i2s to the new mux infra.
197 let pclk = unsafe { get_freqs() }.plli2s1_q.unwrap(); 196 //#[cfg(all(rcc_f4, not(stm32f410)))]
198 197 //let pclk = unsafe { get_freqs() }.plli2s1_q.unwrap();
199 #[cfg(stm32f410)] 198 //#[cfg(stm32f410)]
200 let pclk = T::frequency(); 199 let pclk = T::frequency();
201 200
202 let (odd, div) = compute_baud_rate(pclk, freq, config.master_clock, config.format); 201 let (odd, div) = compute_baud_rate(pclk, freq, config.master_clock, config.format);
diff --git a/embassy-stm32/src/rcc/c0.rs b/embassy-stm32/src/rcc/c0.rs
index 68f029ca0..ca1222185 100644
--- a/embassy-stm32/src/rcc/c0.rs
+++ b/embassy-stm32/src/rcc/c0.rs
@@ -2,7 +2,6 @@ use crate::pac::flash::vals::Latency;
2use crate::pac::rcc::vals::Sw; 2use crate::pac::rcc::vals::Sw;
3pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Hsidiv as HSIPrescaler, Ppre as APBPrescaler}; 3pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Hsidiv as HSIPrescaler, Ppre as APBPrescaler};
4use crate::pac::{FLASH, RCC}; 4use crate::pac::{FLASH, RCC};
5use crate::rcc::{set_freqs, Clocks};
6use crate::time::Hertz; 5use crate::time::Hertz;
7 6
8/// HSI speed 7/// HSI speed
@@ -133,13 +132,13 @@ pub(crate) unsafe fn init(config: Config) {
133 } 132 }
134 }; 133 };
135 134
136 set_freqs(Clocks { 135 set_clocks!(
137 hsi: None, 136 hsi: None,
138 lse: None, 137 lse: None,
139 sys: sys_clk, 138 sys: Some(sys_clk),
140 hclk1: ahb_freq, 139 hclk1: Some(ahb_freq),
141 pclk1: apb_freq, 140 pclk1: Some(apb_freq),
142 pclk1_tim: apb_tim_freq, 141 pclk1_tim: Some(apb_tim_freq),
143 rtc, 142 rtc: rtc,
144 }); 143 );
145} 144}
diff --git a/embassy-stm32/src/rcc/f.rs b/embassy-stm32/src/rcc/f.rs
index 36d9f178f..e306d478d 100644
--- a/embassy-stm32/src/rcc/f.rs
+++ b/embassy-stm32/src/rcc/f.rs
@@ -7,7 +7,6 @@ pub use crate::pac::rcc::vals::{
7#[cfg(any(stm32f4, stm32f7))] 7#[cfg(any(stm32f4, stm32f7))]
8use crate::pac::PWR; 8use crate::pac::PWR;
9use crate::pac::{FLASH, RCC}; 9use crate::pac::{FLASH, RCC};
10use crate::rcc::{set_freqs, Clocks};
11use crate::time::Hertz; 10use crate::time::Hertz;
12 11
13// TODO: on some F4s, PLLM is shared between all PLLs. Enforce that. 12// TODO: on some F4s, PLLM is shared between all PLLs. Enforce that.
@@ -183,9 +182,9 @@ pub(crate) unsafe fn init(config: Config) {
183 }; 182 };
184 let pll = init_pll(PllInstance::Pll, config.pll, &pll_input); 183 let pll = init_pll(PllInstance::Pll, config.pll, &pll_input);
185 #[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))] 184 #[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))]
186 let _plli2s = init_pll(PllInstance::Plli2s, config.plli2s, &pll_input); 185 let plli2s = init_pll(PllInstance::Plli2s, config.plli2s, &pll_input);
187 #[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))] 186 #[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
188 let _pllsai = init_pll(PllInstance::Pllsai, config.pllsai, &pll_input); 187 let pllsai = init_pll(PllInstance::Pllsai, config.pllsai, &pll_input);
189 188
190 // Configure sysclk 189 // Configure sysclk
191 let sys = match config.sys { 190 let sys = match config.sys {
@@ -257,27 +256,41 @@ pub(crate) unsafe fn init(config: Config) {
257 }); 256 });
258 while RCC.cfgr().read().sws() != config.sys {} 257 while RCC.cfgr().read().sws() != config.sys {}
259 258
260 set_freqs(Clocks { 259 set_clocks!(
261 sys, 260 hsi: hsi,
262 hclk1: hclk, 261 hse: hse,
263 hclk2: hclk, 262 lse: None, // TODO
264 hclk3: hclk, 263 lsi: None, // TODO
265 pclk1, 264 sys: Some(sys),
266 pclk2, 265 hclk1: Some(hclk),
267 pclk1_tim, 266 hclk2: Some(hclk),
268 pclk2_tim, 267 hclk3: Some(hclk),
269 rtc, 268 pclk1: Some(pclk1),
269 pclk2: Some(pclk2),
270 pclk1_tim: Some(pclk1_tim),
271 pclk2_tim: Some(pclk2_tim),
272 rtc: rtc,
270 pll1_q: pll.q, 273 pll1_q: pll.q,
271 #[cfg(all(rcc_f4, not(stm32f410)))] 274
272 plli2s1_q: _plli2s.q, 275 #[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))]
273 #[cfg(all(rcc_f4, not(stm32f410)))] 276 plli2s1_p: plli2s.p,
274 plli2s1_r: _plli2s.r, 277 #[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))]
275 278 plli2s1_q: plli2s.q,
276 #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))] 279 #[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))]
277 pllsai1_q: _pllsai.q, 280 plli2s1_r: plli2s.r,
278 #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))] 281
279 pllsai1_r: _pllsai.r, 282 #[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
280 }); 283 pllsai1_p: pllsai.p,
284 #[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
285 pllsai1_q: pllsai.q,
286 #[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
287 pllsai1_r: pllsai.r,
288
289 clk48: pll.q,
290
291 hsi_hse: None,
292 afif: None,
293 );
281} 294}
282 295
283struct PllInput { 296struct PllInput {
diff --git a/embassy-stm32/src/rcc/f0.rs b/embassy-stm32/src/rcc/f0.rs
index feaa2f4c0..a6b627887 100644
--- a/embassy-stm32/src/rcc/f0.rs
+++ b/embassy-stm32/src/rcc/f0.rs
@@ -1,6 +1,5 @@
1use stm32_metapac::flash::vals::Latency; 1use stm32_metapac::flash::vals::Latency;
2 2
3use super::{set_freqs, Clocks};
4use crate::pac::rcc::vals::{Hpre, Pllmul, Pllsrc, Ppre, Sw, Usbsw}; 3use crate::pac::rcc::vals::{Hpre, Pllmul, Pllsrc, Ppre, Sw, Usbsw};
5use crate::pac::{FLASH, RCC}; 4use crate::pac::{FLASH, RCC};
6use crate::time::Hertz; 5use crate::time::Hertz;
@@ -160,13 +159,15 @@ pub(crate) unsafe fn init(config: Config) {
160 159
161 let rtc = config.ls.init(); 160 let rtc = config.ls.init();
162 161
163 set_freqs(Clocks { 162 set_clocks!(
164 sys: Hertz(real_sysclk), 163 hsi: None,
165 pclk1: Hertz(pclk), 164 lse: None,
166 pclk2: Hertz(pclk), 165 sys: Some(Hertz(real_sysclk)),
167 pclk1_tim: Hertz(pclk * timer_mul), 166 pclk1: Some(Hertz(pclk)),
168 pclk2_tim: Hertz(pclk * timer_mul), 167 pclk2: Some(Hertz(pclk)),
169 hclk1: Hertz(hclk), 168 pclk1_tim: Some(Hertz(pclk * timer_mul)),
170 rtc, 169 pclk2_tim: Some(Hertz(pclk * timer_mul)),
171 }); 170 hclk1: Some(Hertz(hclk)),
171 rtc: rtc,
172 );
172} 173}
diff --git a/embassy-stm32/src/rcc/f1.rs b/embassy-stm32/src/rcc/f1.rs
index 169551e45..7f0adab27 100644
--- a/embassy-stm32/src/rcc/f1.rs
+++ b/embassy-stm32/src/rcc/f1.rs
@@ -1,6 +1,5 @@
1use core::convert::TryFrom; 1use core::convert::TryFrom;
2 2
3use super::{set_freqs, Clocks};
4use crate::pac::flash::vals::Latency; 3use crate::pac::flash::vals::Latency;
5use crate::pac::rcc::vals::*; 4use crate::pac::rcc::vals::*;
6use crate::pac::{FLASH, RCC}; 5use crate::pac::{FLASH, RCC};
@@ -179,14 +178,14 @@ pub(crate) unsafe fn init(config: Config) {
179 178
180 let rtc = config.ls.init(); 179 let rtc = config.ls.init();
181 180
182 set_freqs(Clocks { 181 set_clocks!(
183 sys: Hertz(real_sysclk), 182 sys: Some(Hertz(real_sysclk)),
184 pclk1: Hertz(pclk1), 183 pclk1: Some(Hertz(pclk1)),
185 pclk2: Hertz(pclk2), 184 pclk2: Some(Hertz(pclk2)),
186 pclk1_tim: Hertz(pclk1 * timer_mul1), 185 pclk1_tim: Some(Hertz(pclk1 * timer_mul1)),
187 pclk2_tim: Hertz(pclk2 * timer_mul2), 186 pclk2_tim: Some(Hertz(pclk2 * timer_mul2)),
188 hclk1: Hertz(hclk), 187 hclk1: Some(Hertz(hclk)),
189 adc: Some(Hertz(adcclk)), 188 adc: Some(Hertz(adcclk)),
190 rtc, 189 rtc: rtc,
191 }); 190 );
192} 191}
diff --git a/embassy-stm32/src/rcc/f3.rs b/embassy-stm32/src/rcc/f3.rs
index bf035fd25..25866e446 100644
--- a/embassy-stm32/src/rcc/f3.rs
+++ b/embassy-stm32/src/rcc/f3.rs
@@ -4,7 +4,6 @@ use crate::pac::flash::vals::Latency;
4pub use crate::pac::rcc::vals::Adcpres; 4pub use crate::pac::rcc::vals::Adcpres;
5use crate::pac::rcc::vals::{Hpre, Pllmul, Pllsrc, Ppre, Prediv, Sw, Usbpre}; 5use crate::pac::rcc::vals::{Hpre, Pllmul, Pllsrc, Ppre, Prediv, Sw, Usbpre};
6use crate::pac::{FLASH, RCC}; 6use crate::pac::{FLASH, RCC};
7use crate::rcc::{set_freqs, Clocks};
8use crate::time::Hertz; 7use crate::time::Hertz;
9 8
10/// HSI speed 9/// HSI speed
@@ -279,13 +278,16 @@ pub(crate) unsafe fn init(config: Config) {
279 278
280 let rtc = config.ls.init(); 279 let rtc = config.ls.init();
281 280
282 set_freqs(Clocks { 281 set_clocks!(
283 sys: sysclk, 282 hsi: None,
284 pclk1: pclk1, 283 lse: None,
285 pclk2: pclk2, 284 pll1_p: None,
286 pclk1_tim: pclk1 * timer_mul1, 285 sys: Some(sysclk),
287 pclk2_tim: pclk2 * timer_mul2, 286 pclk1: Some(pclk1),
288 hclk1: hclk, 287 pclk2: Some(pclk2),
288 pclk1_tim: Some(pclk1 * timer_mul1),
289 pclk2_tim: Some(pclk2 * timer_mul2),
290 hclk1: Some(hclk),
289 #[cfg(rcc_f3)] 291 #[cfg(rcc_f3)]
290 adc: adc, 292 adc: adc,
291 #[cfg(all(rcc_f3, adc3_common))] 293 #[cfg(all(rcc_f3, adc3_common))]
@@ -294,8 +296,8 @@ pub(crate) unsafe fn init(config: Config) {
294 adc34: None, 296 adc34: None,
295 #[cfg(stm32f334)] 297 #[cfg(stm32f334)]
296 hrtim: hrtim, 298 hrtim: hrtim,
297 rtc, 299 rtc: rtc,
298 }); 300 );
299} 301}
300 302
301#[inline] 303#[inline]
diff --git a/embassy-stm32/src/rcc/g0.rs b/embassy-stm32/src/rcc/g0.rs
index b38fe1dcc..e3cd46fb9 100644
--- a/embassy-stm32/src/rcc/g0.rs
+++ b/embassy-stm32/src/rcc/g0.rs
@@ -4,7 +4,6 @@ pub use crate::pac::rcc::vals::{
4 Hpre as AHBPrescaler, Hsidiv as HSIPrescaler, Pllm, Plln, Pllp, Pllq, Pllr, Ppre as APBPrescaler, 4 Hpre as AHBPrescaler, Hsidiv as HSIPrescaler, Pllm, Plln, Pllp, Pllq, Pllr, Ppre as APBPrescaler,
5}; 5};
6use crate::pac::{FLASH, PWR, RCC}; 6use crate::pac::{FLASH, PWR, RCC};
7use crate::rcc::{set_freqs, Clocks};
8use crate::time::Hertz; 7use crate::time::Hertz;
9 8
10/// HSI speed 9/// HSI speed
@@ -352,11 +351,11 @@ pub(crate) unsafe fn init(config: Config) {
352 #[cfg(not(any(stm32g0b1, stm32g0c1, stm32g0b0)))] 351 #[cfg(not(any(stm32g0b1, stm32g0c1, stm32g0b0)))]
353 let hsi48_freq: Option<Hertz> = None; 352 let hsi48_freq: Option<Hertz> = None;
354 353
355 set_freqs(Clocks { 354 set_clocks!(
356 sys: sys_clk, 355 sys: Some(sys_clk),
357 hclk1: ahb_freq, 356 hclk1: Some(ahb_freq),
358 pclk1: apb_freq, 357 pclk1: Some(apb_freq),
359 pclk1_tim: apb_tim_freq, 358 pclk1_tim: Some(apb_tim_freq),
360 hsi: hsi_freq, 359 hsi: hsi_freq,
361 hsi48: hsi48_freq, 360 hsi48: hsi48_freq,
362 hsi_div_8: hsi_div_8_freq, 361 hsi_div_8: hsi_div_8_freq,
@@ -365,6 +364,6 @@ pub(crate) unsafe fn init(config: Config) {
365 lsi: lsi_freq, 364 lsi: lsi_freq,
366 pll1_q: pll1_q_freq, 365 pll1_q: pll1_q_freq,
367 pll1_p: pll1_p_freq, 366 pll1_p: pll1_p_freq,
368 rtc, 367 rtc: rtc,
369 }); 368 );
370} 369}
diff --git a/embassy-stm32/src/rcc/g4.rs b/embassy-stm32/src/rcc/g4.rs
index 891f0490b..3e20bf6af 100644
--- a/embassy-stm32/src/rcc/g4.rs
+++ b/embassy-stm32/src/rcc/g4.rs
@@ -7,7 +7,6 @@ pub use crate::pac::rcc::vals::{
7 Pllp as PllP, Pllq as PllQ, Pllr as PllR, Ppre as APBPrescaler, 7 Pllp as PllP, Pllq as PllQ, Pllr as PllR, Ppre as APBPrescaler,
8}; 8};
9use crate::pac::{PWR, RCC}; 9use crate::pac::{PWR, RCC};
10use crate::rcc::{set_freqs, Clocks};
11use crate::time::Hertz; 10use crate::time::Hertz;
12 11
13/// HSI speed 12/// HSI speed
@@ -307,20 +306,20 @@ pub(crate) unsafe fn init(config: Config) {
307 306
308 let rtc = config.ls.init(); 307 let rtc = config.ls.init();
309 308
310 set_freqs(Clocks { 309 set_clocks!(
311 sys: sys_clk, 310 sys: Some(sys_clk),
312 hclk1: ahb_freq, 311 hclk1: Some(ahb_freq),
313 hclk2: ahb_freq, 312 hclk2: Some(ahb_freq),
314 hclk3: ahb_freq, 313 hclk3: Some(ahb_freq),
315 pclk1: apb1_freq, 314 pclk1: Some(apb1_freq),
316 pclk1_tim: apb1_tim_freq, 315 pclk1_tim: Some(apb1_tim_freq),
317 pclk2: apb2_freq, 316 pclk2: Some(apb2_freq),
318 pclk2_tim: apb2_tim_freq, 317 pclk2_tim: Some(apb2_tim_freq),
319 adc: adc12_ck, 318 adc: adc12_ck,
320 adc34: adc345_ck, 319 adc34: adc345_ck,
321 pll1_p: None, 320 pll1_p: None,
322 pll1_q: None, // TODO 321 pll1_q: None, // TODO
323 hse: None, // TODO 322 hse: None, // TODO
324 rtc, 323 rtc: rtc,
325 }); 324 );
326} 325}
diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs
index dcaf2dced..9ac2115f0 100644
--- a/embassy-stm32/src/rcc/h.rs
+++ b/embassy-stm32/src/rcc/h.rs
@@ -12,7 +12,6 @@ pub use crate::pac::rcc::vals::{
12}; 12};
13use crate::pac::rcc::vals::{Ckpersel, Pllrge, Pllvcosel, Timpre}; 13use crate::pac::rcc::vals::{Ckpersel, Pllrge, Pllvcosel, Timpre};
14use crate::pac::{FLASH, PWR, RCC}; 14use crate::pac::{FLASH, PWR, RCC};
15use crate::rcc::{set_freqs, Clocks};
16use crate::time::Hertz; 15use crate::time::Hertz;
17 16
18/// HSI speed 17/// HSI speed
@@ -430,7 +429,7 @@ pub(crate) unsafe fn init(config: Config) {
430 }; 429 };
431 430
432 // Configure HSI48. 431 // Configure HSI48.
433 let _hsi48 = config.hsi48.map(super::init_hsi48); 432 let hsi48 = config.hsi48.map(super::init_hsi48);
434 433
435 // Configure CSI. 434 // Configure CSI.
436 RCC.cr().modify(|w| w.set_csion(config.csi)); 435 RCC.cr().modify(|w| w.set_csion(config.csi));
@@ -614,45 +613,33 @@ pub(crate) unsafe fn init(config: Config) {
614 while !pac::SYSCFG.cccsr().read().ready() {} 613 while !pac::SYSCFG.cccsr().read().ready() {}
615 } 614 }
616 615
617 set_freqs(Clocks { 616 set_clocks!(
618 sys, 617 sys: Some(sys),
619 hclk1: hclk, 618 hclk1: Some(hclk),
620 hclk2: hclk, 619 hclk2: Some(hclk),
621 hclk3: hclk, 620 hclk3: Some(hclk),
622 hclk4: hclk, 621 hclk4: Some(hclk),
623 pclk1: apb1, 622 pclk1: Some(apb1),
624 pclk2: apb2, 623 pclk2: Some(apb2),
625 pclk3: apb3, 624 pclk3: Some(apb3),
626 #[cfg(stm32h7)] 625 #[cfg(stm32h7)]
627 pclk4: apb4, 626 pclk4: Some(apb4),
628 #[cfg(stm32h5)] 627 pclk1_tim: Some(apb1_tim),
629 pclk4: Hertz(1), 628 pclk2_tim: Some(apb2_tim),
630 pclk1_tim: apb1_tim, 629 adc: adc,
631 pclk2_tim: apb2_tim, 630 rtc: rtc,
632 adc, 631
633 rtc, 632 hsi: hsi,
634 633 hsi48: hsi48,
635 #[cfg(any(stm32h5, stm32h7))] 634 csi: csi,
636 hsi: None, 635 hse: hse,
637 #[cfg(stm32h5)]
638 hsi48: None,
639 #[cfg(stm32h5)]
640 lsi: None,
641 #[cfg(any(stm32h5, stm32h7))]
642 csi: None,
643 636
644 #[cfg(any(stm32h5, stm32h7))]
645 lse: None, 637 lse: None,
646 #[cfg(any(stm32h5, stm32h7))] 638 lsi: None,
647 hse: None,
648 639
649 #[cfg(any(stm32h5, stm32h7))]
650 pll1_q: pll1.q, 640 pll1_q: pll1.q,
651 #[cfg(any(stm32h5, stm32h7))]
652 pll2_p: pll2.p, 641 pll2_p: pll2.p,
653 #[cfg(any(stm32h5, stm32h7))]
654 pll2_q: pll2.q, 642 pll2_q: pll2.q,
655 #[cfg(any(stm32h5, stm32h7))]
656 pll2_r: pll2.r, 643 pll2_r: pll2.r,
657 #[cfg(any(rcc_h5, stm32h7))] 644 #[cfg(any(rcc_h5, stm32h7))]
658 pll3_p: pll3.p, 645 pll3_p: pll3.p,
@@ -670,12 +657,8 @@ pub(crate) unsafe fn init(config: Config) {
670 657
671 #[cfg(stm32h5)] 658 #[cfg(stm32h5)]
672 audioclk: None, 659 audioclk: None,
673 #[cfg(any(stm32h5, stm32h7))]
674 per: None, 660 per: None,
675 661 );
676 #[cfg(stm32h7)]
677 rcc_pclk_d3: None,
678 });
679} 662}
680 663
681struct PllInput { 664struct PllInput {
diff --git a/embassy-stm32/src/rcc/l.rs b/embassy-stm32/src/rcc/l.rs
index 257fd83fe..ab1681dd4 100644
--- a/embassy-stm32/src/rcc/l.rs
+++ b/embassy-stm32/src/rcc/l.rs
@@ -9,7 +9,6 @@ pub use crate::pac::rcc::vals::Clk48sel as Clk48Src;
9pub use crate::pac::rcc::vals::Hsepre as HsePrescaler; 9pub use crate::pac::rcc::vals::Hsepre as HsePrescaler;
10pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Msirange as MSIRange, Ppre as APBPrescaler, Sw as ClockSrc}; 10pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Msirange as MSIRange, Ppre as APBPrescaler, Sw as ClockSrc};
11use crate::pac::{FLASH, RCC}; 11use crate::pac::{FLASH, RCC};
12use crate::rcc::{set_freqs, Clocks};
13use crate::time::Hertz; 12use crate::time::Hertz;
14 13
15/// HSI speed 14/// HSI speed
@@ -262,7 +261,7 @@ pub(crate) unsafe fn init(config: Config) {
262 #[cfg(any(stm32l4, stm32l5, stm32wb))] 261 #[cfg(any(stm32l4, stm32l5, stm32wb))]
263 let pllsai1 = init_pll(PllInstance::Pllsai1, config.pllsai1, &pll_input); 262 let pllsai1 = init_pll(PllInstance::Pllsai1, config.pllsai1, &pll_input);
264 #[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))] 263 #[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
265 let _pllsai2 = init_pll(PllInstance::Pllsai2, config.pllsai2, &pll_input); 264 let pllsai2 = init_pll(PllInstance::Pllsai2, config.pllsai2, &pll_input);
266 265
267 let sys_clk = match config.mux { 266 let sys_clk = match config.mux {
268 ClockSrc::HSE => hse.unwrap(), 267 ClockSrc::HSE => hse.unwrap(),
@@ -274,12 +273,12 @@ pub(crate) unsafe fn init(config: Config) {
274 #[cfg(any(rcc_l0_v2, stm32l4, stm32l5, stm32wb))] 273 #[cfg(any(rcc_l0_v2, stm32l4, stm32l5, stm32wb))]
275 RCC.ccipr().modify(|w| w.set_clk48sel(config.clk48_src)); 274 RCC.ccipr().modify(|w| w.set_clk48sel(config.clk48_src));
276 #[cfg(any(rcc_l0_v2))] 275 #[cfg(any(rcc_l0_v2))]
277 let _clk48 = match config.clk48_src { 276 let clk48 = match config.clk48_src {
278 Clk48Src::HSI48 => _hsi48, 277 Clk48Src::HSI48 => _hsi48,
279 Clk48Src::PLL1_VCO_DIV_2 => pll.clk48, 278 Clk48Src::PLL1_VCO_DIV_2 => pll.clk48,
280 }; 279 };
281 #[cfg(any(stm32l4, stm32l5, stm32wb))] 280 #[cfg(any(stm32l4, stm32l5, stm32wb))]
282 let _clk48 = match config.clk48_src { 281 let clk48 = match config.clk48_src {
283 Clk48Src::HSI48 => _hsi48, 282 Clk48Src::HSI48 => _hsi48,
284 Clk48Src::MSI => msi, 283 Clk48Src::MSI => msi,
285 Clk48Src::PLLSAI1_Q => pllsai1.q, 284 Clk48Src::PLLSAI1_Q => pllsai1.q,
@@ -376,37 +375,53 @@ pub(crate) unsafe fn init(config: Config) {
376 while !RCC.extcfgr().read().c2hpref() {} 375 while !RCC.extcfgr().read().c2hpref() {}
377 } 376 }
378 377
379 set_freqs(Clocks { 378 set_clocks!(
380 sys: sys_clk, 379 sys: Some(sys_clk),
381 hclk1, 380 hclk1: Some(hclk1),
382 #[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))] 381 #[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
383 hclk2, 382 hclk2: Some(hclk2),
384 #[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))] 383 #[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
385 hclk3, 384 hclk3: Some(hclk3),
386 pclk1, 385 pclk1: Some(pclk1),
387 pclk2, 386 pclk2: Some(pclk2),
388 pclk1_tim, 387 pclk1_tim: Some(pclk1_tim),
389 pclk2_tim, 388 pclk2_tim: Some(pclk2_tim),
390 #[cfg(stm32wl)] 389 #[cfg(stm32wl)]
391 pclk3: hclk3, 390 pclk3: Some(hclk3),
392 #[cfg(rcc_l4)] 391 hsi: hsi,
393 hsi: None, 392 hse: hse,
394 #[cfg(rcc_l4)] 393 msi: msi,
395 lse: None, 394 #[cfg(any(rcc_l0_v2, stm32l4, stm32l5, stm32wb))]
396 #[cfg(rcc_l4)] 395 clk48: clk48,
397 pllsai1_p: None, 396
398 #[cfg(rcc_l4)] 397 #[cfg(not(any(stm32l0, stm32l1)))]
399 pllsai2_p: None, 398 pll1_p: pll.p,
400 #[cfg(rcc_l4)] 399 #[cfg(not(any(stm32l0, stm32l1)))]
401 pll1_p: None, 400 pll1_q: pll.q,
402 #[cfg(rcc_l4)] 401 pll1_r: pll.r,
403 pll1_q: None, 402
404 #[cfg(rcc_l4)] 403 #[cfg(any(stm32l4, stm32l5, stm32wb))]
404 pllsai1_p: pllsai1.p,
405 #[cfg(any(stm32l4, stm32l5, stm32wb))]
406 pllsai1_q: pllsai1.q,
407 #[cfg(any(stm32l4, stm32l5, stm32wb))]
408 pllsai1_r: pllsai1.r,
409
410 #[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
411 pllsai2_p: pllsai2.p,
412 #[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
413 pllsai2_q: pllsai2.q,
414 #[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
415 pllsai2_r: pllsai2.r,
416
417 rtc: rtc,
418
419 // TODO
405 sai1_extclk: None, 420 sai1_extclk: None,
406 #[cfg(rcc_l4)]
407 sai2_extclk: None, 421 sai2_extclk: None,
408 rtc, 422 lsi: None,
409 }); 423 lse: None,
424 );
410} 425}
411 426
412#[cfg(any(stm32l0, stm32l1))] 427#[cfg(any(stm32l0, stm32l1))]
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index 240ffc6d2..280da7ae3 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -5,8 +5,6 @@
5 5
6use core::mem::MaybeUninit; 6use core::mem::MaybeUninit;
7 7
8use crate::time::Hertz;
9
10mod bd; 8mod bd;
11mod mco; 9mod mco;
12pub use bd::*; 10pub use bd::*;
@@ -32,162 +30,7 @@ mod _version;
32 30
33pub use _version::*; 31pub use _version::*;
34 32
35// Model Clock Configuration 33pub use crate::_generated::Clocks;
36//
37// pub struct Clocks {
38// hse: Option<Hertz>,
39// hsi: bool,
40// lse: Option<Hertz>,
41// lsi: bool,
42// rtc: RtcSource,
43// }
44
45#[derive(Clone, Copy, Debug)]
46#[cfg_attr(feature = "defmt", derive(defmt::Format))]
47pub struct Clocks {
48 pub sys: Hertz,
49
50 // APB
51 pub pclk1: Hertz,
52 pub pclk1_tim: Hertz,
53 #[cfg(not(any(rcc_c0, rcc_g0)))]
54 pub pclk2: Hertz,
55 #[cfg(not(any(rcc_c0, rcc_g0)))]
56 pub pclk2_tim: Hertz,
57 #[cfg(any(rcc_wl5, rcc_wle, rcc_h5, rcc_h50, rcc_h7, rcc_h7rm0433, rcc_h7ab, rcc_u5))]
58 pub pclk3: Hertz,
59 #[cfg(any(rcc_h7, rcc_h7rm0433, rcc_h7ab, stm32h5))]
60 pub pclk4: Hertz,
61 #[cfg(any(rcc_wba))]
62 pub pclk7: Hertz,
63
64 // AHB
65 pub hclk1: Hertz,
66 #[cfg(any(
67 rcc_l4,
68 rcc_l4plus,
69 rcc_l5,
70 rcc_f2,
71 rcc_f4,
72 rcc_f410,
73 rcc_f7,
74 rcc_h5,
75 rcc_h50,
76 rcc_h7,
77 rcc_h7rm0433,
78 rcc_h7ab,
79 rcc_g4,
80 rcc_u5,
81 rcc_wb,
82 rcc_wba,
83 rcc_wl5,
84 rcc_wle
85 ))]
86 pub hclk2: Hertz,
87 #[cfg(any(
88 rcc_l4,
89 rcc_l4plus,
90 rcc_l5,
91 rcc_f2,
92 rcc_f4,
93 rcc_f410,
94 rcc_f7,
95 rcc_h5,
96 rcc_h50,
97 rcc_h7,
98 rcc_h7rm0433,
99 rcc_h7ab,
100 rcc_u5,
101 rcc_g4,
102 rcc_wb,
103 rcc_wl5,
104 rcc_wle
105 ))]
106 pub hclk3: Hertz,
107 #[cfg(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7rm0433, rcc_h7ab, rcc_wba))]
108 pub hclk4: Hertz,
109
110 #[cfg(all(rcc_f4, not(stm32f410)))]
111 pub plli2s1_q: Option<Hertz>,
112 #[cfg(all(rcc_f4, not(stm32f410)))]
113 pub plli2s1_r: Option<Hertz>,
114
115 #[cfg(rcc_l4)]
116 pub pllsai1_p: Option<Hertz>,
117 #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
118 pub pllsai1_q: Option<Hertz>,
119 #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
120 pub pllsai1_r: Option<Hertz>,
121 #[cfg(rcc_l4)]
122 pub pllsai2_p: Option<Hertz>,
123
124 #[cfg(any(stm32g0, stm32g4, rcc_l4))]
125 pub pll1_p: Option<Hertz>,
126 #[cfg(any(stm32h5, stm32h7, stm32f2, stm32f4, stm32f7, rcc_l4, stm32g0, stm32g4))]
127 pub pll1_q: Option<Hertz>,
128 #[cfg(any(stm32h5, stm32h7))]
129 pub pll2_p: Option<Hertz>,
130 #[cfg(any(stm32h5, stm32h7))]
131 pub pll2_q: Option<Hertz>,
132 #[cfg(any(stm32h5, stm32h7))]
133 pub pll2_r: Option<Hertz>,
134 #[cfg(any(stm32h5, stm32h7))]
135 pub pll3_p: Option<Hertz>,
136 #[cfg(any(stm32h5, stm32h7))]
137 pub pll3_q: Option<Hertz>,
138 #[cfg(any(stm32h5, stm32h7))]
139 pub pll3_r: Option<Hertz>,
140
141 #[cfg(any(
142 rcc_f1,
143 rcc_f100,
144 rcc_f1cl,
145 rcc_h5,
146 rcc_h50,
147 rcc_h7,
148 rcc_h7rm0433,
149 rcc_h7ab,
150 rcc_f3,
151 rcc_g4
152 ))]
153 pub adc: Option<Hertz>,
154
155 #[cfg(any(rcc_f3, rcc_g4))]
156 pub adc34: Option<Hertz>,
157
158 #[cfg(stm32f334)]
159 pub hrtim: Option<Hertz>,
160
161 pub rtc: Option<Hertz>,
162
163 #[cfg(any(stm32h5, stm32h7, rcc_l4, rcc_c0, stm32g0))]
164 pub hsi: Option<Hertz>,
165 #[cfg(any(stm32h5, stm32g0))]
166 pub hsi48: Option<Hertz>,
167 #[cfg(stm32g0)]
168 pub hsi_div_8: Option<Hertz>,
169 #[cfg(any(stm32g0, stm32h5))]
170 pub lsi: Option<Hertz>,
171 #[cfg(any(stm32h5, stm32h7))]
172 pub csi: Option<Hertz>,
173
174 #[cfg(any(stm32h5, stm32h7, rcc_l4, rcc_c0, stm32g0))]
175 pub lse: Option<Hertz>,
176 #[cfg(any(stm32h5, stm32h7, stm32g0, stm32g4))]
177 pub hse: Option<Hertz>,
178
179 #[cfg(stm32h5)]
180 pub audioclk: Option<Hertz>,
181 #[cfg(any(stm32h5, stm32h7))]
182 pub per: Option<Hertz>,
183
184 #[cfg(stm32h7)]
185 pub rcc_pclk_d3: Option<Hertz>,
186 #[cfg(rcc_l4)]
187 pub sai1_extclk: Option<Hertz>,
188 #[cfg(rcc_l4)]
189 pub sai2_extclk: Option<Hertz>,
190}
191 34
192#[cfg(feature = "low-power")] 35#[cfg(feature = "low-power")]
193/// Must be written within a critical section 36/// Must be written within a critical section
diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs
index dff08dc9b..9cec6c96c 100644
--- a/embassy-stm32/src/rcc/u5.rs
+++ b/embassy-stm32/src/rcc/u5.rs
@@ -1,7 +1,6 @@
1pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Msirange, Plldiv, Pllm, Plln, Ppre as APBPrescaler}; 1pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Msirange, Plldiv, Pllm, Plln, Ppre as APBPrescaler};
2use crate::pac::rcc::vals::{Msirgsel, Pllmboost, Pllrge, Pllsrc, Sw}; 2use crate::pac::rcc::vals::{Msirgsel, Pllmboost, Pllrge, Pllsrc, Sw};
3use crate::pac::{FLASH, PWR, RCC}; 3use crate::pac::{FLASH, PWR, RCC};
4use crate::rcc::{set_freqs, Clocks};
5use crate::time::Hertz; 4use crate::time::Hertz;
6 5
7/// HSI speed 6/// HSI speed
@@ -338,7 +337,7 @@ pub(crate) unsafe fn init(config: Config) {
338 } 337 }
339 }; 338 };
340 339
341 let _hsi48 = config.hsi48.map(super::init_hsi48); 340 let hsi48 = config.hsi48.map(super::init_hsi48);
342 341
343 // The clock source is ready 342 // The clock source is ready
344 // Calculate and set the flash wait states 343 // Calculate and set the flash wait states
@@ -448,18 +447,37 @@ pub(crate) unsafe fn init(config: Config) {
448 447
449 let rtc = config.ls.init(); 448 let rtc = config.ls.init();
450 449
451 set_freqs(Clocks { 450 set_clocks!(
452 sys: sys_clk, 451 sys: Some(sys_clk),
453 hclk1: ahb_freq, 452 hclk1: Some(ahb_freq),
454 hclk2: ahb_freq, 453 hclk2: Some(ahb_freq),
455 hclk3: ahb_freq, 454 hclk3: Some(ahb_freq),
456 pclk1: apb1_freq, 455 pclk1: Some(apb1_freq),
457 pclk2: apb2_freq, 456 pclk2: Some(apb2_freq),
458 pclk3: apb3_freq, 457 pclk3: Some(apb3_freq),
459 pclk1_tim: apb1_tim_freq, 458 pclk1_tim: Some(apb1_tim_freq),
460 pclk2_tim: apb2_tim_freq, 459 pclk2_tim: Some(apb2_tim_freq),
461 rtc, 460 hsi48: hsi48,
462 }); 461 rtc: rtc,
462
463 // TODO
464 hse: None,
465 hsi: None,
466 audioclk: None,
467 hsi48_div_2: None,
468 lse: None,
469 lsi: None,
470 msik: None,
471 pll1_p: None,
472 pll1_q: None,
473 pll1_r: None,
474 pll2_p: None,
475 pll2_q: None,
476 pll2_r: None,
477 pll3_p: None,
478 pll3_q: None,
479 pll3_r: None,
480 );
463} 481}
464 482
465fn msirange_to_hertz(range: Msirange) -> Hertz { 483fn msirange_to_hertz(range: Msirange) -> Hertz {
diff --git a/embassy-stm32/src/rcc/wba.rs b/embassy-stm32/src/rcc/wba.rs
index dfa236484..47ce4783c 100644
--- a/embassy-stm32/src/rcc/wba.rs
+++ b/embassy-stm32/src/rcc/wba.rs
@@ -4,7 +4,6 @@ pub use crate::pac::rcc::vals::{
4 Adcsel as AdcClockSource, Hpre as AHBPrescaler, Hsepre as HsePrescaler, Ppre as APBPrescaler, Sw as ClockSrc, 4 Adcsel as AdcClockSource, Hpre as AHBPrescaler, Hsepre as HsePrescaler, Ppre as APBPrescaler, Sw as ClockSrc,
5}; 5};
6use crate::pac::{FLASH, RCC}; 6use crate::pac::{FLASH, RCC};
7use crate::rcc::{set_freqs, Clocks};
8use crate::time::Hertz; 7use crate::time::Hertz;
9 8
10/// HSI speed 9/// HSI speed
@@ -155,16 +154,23 @@ pub(crate) unsafe fn init(config: Config) {
155 154
156 RCC.ccipr3().modify(|w| w.set_adcsel(config.adc_clock_source)); 155 RCC.ccipr3().modify(|w| w.set_adcsel(config.adc_clock_source));
157 156
158 set_freqs(Clocks { 157 set_clocks!(
159 sys: sys_clk, 158 sys: Some(sys_clk),
160 hclk1, 159 hclk1: Some(hclk1),
161 hclk2, 160 hclk2: Some(hclk2),
162 hclk4, 161 hclk4: Some(hclk4),
163 pclk1, 162 pclk1: Some(pclk1),
164 pclk2, 163 pclk2: Some(pclk2),
165 pclk7, 164 pclk7: Some(pclk7),
166 pclk1_tim, 165 pclk1_tim: Some(pclk1_tim),
167 pclk2_tim, 166 pclk2_tim: Some(pclk2_tim),
168 rtc, 167 rtc: rtc,
169 }); 168 hse: hse,
169 hsi: hsi,
170
171 // TODO
172 lse: None,
173 lsi: None,
174 pll1_q: None,
175 );
170} 176}
diff --git a/embassy-stm32/src/sdmmc/mod.rs b/embassy-stm32/src/sdmmc/mod.rs
index debe26c88..61589a215 100644
--- a/embassy-stm32/src/sdmmc/mod.rs
+++ b/embassy-stm32/src/sdmmc/mod.rs
@@ -670,7 +670,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
670 _ => panic!("Invalid Bus Width"), 670 _ => panic!("Invalid Bus Width"),
671 }; 671 };
672 672
673 let ker_ck = T::kernel_clk(); 673 let ker_ck = T::frequency();
674 let (_bypass, clkdiv, new_clock) = clk_div(ker_ck, freq)?; 674 let (_bypass, clkdiv, new_clock) = clk_div(ker_ck, freq)?;
675 675
676 // Enforce AHB and SDMMC_CK clock relation. See RM0433 Rev 7 676 // Enforce AHB and SDMMC_CK clock relation. See RM0433 Rev 7
@@ -1023,7 +1023,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
1023 /// specified frequency. 1023 /// specified frequency.
1024 pub async fn init_card(&mut self, freq: Hertz) -> Result<(), Error> { 1024 pub async fn init_card(&mut self, freq: Hertz) -> Result<(), Error> {
1025 let regs = T::regs(); 1025 let regs = T::regs();
1026 let ker_ck = T::kernel_clk(); 1026 let ker_ck = T::frequency();
1027 1027
1028 let bus_width = match self.d3.is_some() { 1028 let bus_width = match self.d3.is_some() {
1029 true => BusWidth::Four, 1029 true => BusWidth::Four,
@@ -1429,7 +1429,6 @@ pub(crate) mod sealed {
1429 1429
1430 fn regs() -> RegBlock; 1430 fn regs() -> RegBlock;
1431 fn state() -> &'static AtomicWaker; 1431 fn state() -> &'static AtomicWaker;
1432 fn kernel_clk() -> Hertz;
1433 } 1432 }
1434 1433
1435 pub trait Pins<T: Instance> {} 1434 pub trait Pins<T: Instance> {}
@@ -1461,61 +1460,6 @@ pub trait SdmmcDma<T: Instance> {}
1461#[cfg(sdmmc_v2)] 1460#[cfg(sdmmc_v2)]
1462impl<T: Instance> SdmmcDma<T> for NoDma {} 1461impl<T: Instance> SdmmcDma<T> for NoDma {}
1463 1462
1464cfg_if::cfg_if! {
1465 // TODO, these could not be implemented, because required clocks are not exposed in RCC:
1466 // - H7 uses pll1_q_ck or pll2_r_ck depending on SDMMCSEL
1467 // - L1 uses pll48
1468 // - L4 uses clk48(pll48)
1469 // - L4+, L5, U5 uses clk48(pll48) or PLLSAI3CLK(PLLP) depending on SDMMCSEL
1470 if #[cfg(stm32f1)] {
1471 // F1 uses AHB1(HCLK), which is correct in PAC
1472 macro_rules! kernel_clk {
1473 ($inst:ident) => {
1474 <peripherals::$inst as crate::rcc::sealed::RccPeripheral>::frequency()
1475 }
1476 }
1477 } else if #[cfg(any(stm32f2, stm32f4))] {
1478 // F2, F4 always use pll48
1479 macro_rules! kernel_clk {
1480 ($inst:ident) => {
1481 critical_section::with(|_| unsafe {
1482 unwrap!(crate::rcc::get_freqs().pll1_q)
1483 })
1484 }
1485 }
1486 } else if #[cfg(stm32f7)] {
1487 macro_rules! kernel_clk {
1488 (SDMMC1) => {
1489 critical_section::with(|_| unsafe {
1490 let sdmmcsel = crate::pac::RCC.dckcfgr2().read().sdmmc1sel();
1491 if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYS {
1492 crate::rcc::get_freqs().sys
1493 } else {
1494 unwrap!(crate::rcc::get_freqs().pll1_q)
1495 }
1496 })
1497 };
1498 (SDMMC2) => {
1499 critical_section::with(|_| unsafe {
1500 let sdmmcsel = crate::pac::RCC.dckcfgr2().read().sdmmc2sel();
1501 if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYS {
1502 crate::rcc::get_freqs().sys
1503 } else {
1504 unwrap!(crate::rcc::get_freqs().pll1_q)
1505 }
1506 })
1507 };
1508 }
1509 } else {
1510 // Use default peripheral clock and hope it works
1511 macro_rules! kernel_clk {
1512 ($inst:ident) => {
1513 <peripherals::$inst as crate::rcc::sealed::RccPeripheral>::frequency()
1514 }
1515 }
1516 }
1517}
1518
1519foreach_peripheral!( 1463foreach_peripheral!(
1520 (sdmmc, $inst:ident) => { 1464 (sdmmc, $inst:ident) => {
1521 impl sealed::Instance for peripherals::$inst { 1465 impl sealed::Instance for peripherals::$inst {
@@ -1529,10 +1473,6 @@ foreach_peripheral!(
1529 static WAKER: ::embassy_sync::waitqueue::AtomicWaker = ::embassy_sync::waitqueue::AtomicWaker::new(); 1473 static WAKER: ::embassy_sync::waitqueue::AtomicWaker = ::embassy_sync::waitqueue::AtomicWaker::new();
1530 &WAKER 1474 &WAKER
1531 } 1475 }
1532
1533 fn kernel_clk() -> Hertz {
1534 kernel_clk!($inst)
1535 }
1536 } 1476 }
1537 1477
1538 impl Instance for peripherals::$inst {} 1478 impl Instance for peripherals::$inst {}
diff --git a/embassy-stm32/src/usb/usb.rs b/embassy-stm32/src/usb/usb.rs
index f39915906..34d6b52fd 100644
--- a/embassy-stm32/src/usb/usb.rs
+++ b/embassy-stm32/src/usb/usb.rs
@@ -280,7 +280,7 @@ impl<'d, T: Instance> Driver<'d, T> {
280 #[cfg(time)] 280 #[cfg(time)]
281 embassy_time::block_for(embassy_time::Duration::from_millis(100)); 281 embassy_time::block_for(embassy_time::Duration::from_millis(100));
282 #[cfg(not(time))] 282 #[cfg(not(time))]
283 cortex_m::asm::delay(unsafe { crate::rcc::get_freqs() }.sys.0 / 10); 283 cortex_m::asm::delay(unsafe { crate::rcc::get_freqs() }.sys.unwrap().0 / 10);
284 284
285 #[cfg(not(usb_v4))] 285 #[cfg(not(usb_v4))]
286 regs.btable().write(|w| w.set_btable(0)); 286 regs.btable().write(|w| w.set_btable(0));
generated by cgit (git 2.34.1) at 2026-04-05 22:10:38 +0000