3 files changed, 131 insertions, 28 deletions

diff --git a/embassy-stm32/src/adc/g4.rs b/embassy-stm32/src/adc/g4.rs
index 613fe921b..f60a14a72 100644
--- a/embassy-stm32/src/adc/g4.rs
+++ b/embassy-stm32/src/adc/g4.rs
@@ -17,6 +17,9 @@ use crate::{Peri, pac, rcc};
 mod ringbuffered;
 pub use ringbuffered::RingBufferedAdc;
 
+mod injected;
+pub use injected::InjectedAdc;
+
 /// Default VREF voltage used for sample conversion to millivolts.
 pub const VREF_DEFAULT_MV: u32 = 3300;
 /// VREF voltage used for factory calibration of VREFINTCAL register.
@@ -126,6 +129,22 @@ impl Prescaler {
     }
 }
 
+// Trigger source for ADC conversions
+pub struct ConversionTrigger {
+    // See Table 166 and 167 in RM0440 Rev 9 for ADC1/2 External triggers
+    // Note that Injected and Regular channels uses different mappings
+    pub channel: u8,
+    pub edge: Exten,
+}
+
+// Conversion mode for regular ADC channels
+pub enum RegularConversionMode {
+    // Samples as fast as possible
+    Continuous,
+    // Sample at rate determined by external trigger
+    Triggered(ConversionTrigger),
+}
+
 impl<'d, T: Instance> Adc<'d, T> {
     /// Create a new ADC driver.
     pub fn new(adc: Peri<'d, T>) -> Self {
@@ -508,11 +527,10 @@ impl<'d, T: Instance> Adc<'d, T> {
     }
 
     /// Set external trigger for regular conversion sequence
-    /// Possible trigger values are seen in Table 166 in RM0440 Rev 9
-    pub fn set_regular_conversion_trigger(&mut self, trigger: u8, edge: Exten) {
+    pub fn set_regular_conversion_trigger(&mut self, trigger: ConversionTrigger) {
         T::regs().cfgr().modify(|r| {
-            r.set_extsel(trigger);
-            r.set_exten(edge);
+            r.set_extsel(trigger.channel);
+            r.set_exten(trigger.edge);
         });
         // Regular conversions uses DMA so no need to generate interrupt
         T::regs().ier().modify(|r| r.set_eosie(false));
@@ -542,6 +560,7 @@ impl<'d, T: Instance> Adc<'d, T> {
         dma: Peri<'a, impl RxDma<T>>,
         dma_buf: &'a mut [u16],
         sequence: impl ExactSizeIterator<Item = (&'a mut AnyAdcChannel<T>, SampleTime)>,
+        mode: RegularConversionMode,
     ) -> RingBufferedAdc<'a, T> {
         assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
         assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
@@ -596,11 +615,24 @@ impl<'d, T: Instance> Adc<'d, T> {
 
         T::regs().cfgr().modify(|reg| {
             reg.set_discen(false); // Convert all channels for each trigger
-            reg.set_cont(false); // New trigger is neede for each sample to be read
             reg.set_dmacfg(Dmacfg::CIRCULAR);
             reg.set_dmaen(Dmaen::ENABLE);
         });
 
+        match mode {
+            RegularConversionMode::Continuous => {
+                T::regs().cfgr().modify(|reg| {
+                    reg.set_cont(true);
+                });
+            },
+            RegularConversionMode::Triggered(trigger) => {
+                T::regs().cfgr().modify(|r| {
+                    r.set_cont(false); // New trigger is neede for each sample to be read
+                });
+                self.set_regular_conversion_trigger(trigger);
+            }
+        }
+
         RingBufferedAdc::new(dma, dma_buf)
     }
 
@@ -608,7 +640,8 @@ impl<'d, T: Instance> Adc<'d, T> {
     pub fn configure_injected_sequence<'a>(
         &mut self,
         sequence: impl ExactSizeIterator<Item = (&'a mut AnyAdcChannel<T>, SampleTime)>,
-    ) {
+        trigger: ConversionTrigger,
+    ) -> InjectedAdc<T> {
         assert!(sequence.len() != 0, "Read sequence cannot be empty");
         assert!(
             sequence.len() <= NR_INJECTED_RANKS,
@@ -656,6 +689,35 @@ impl<'d, T: Instance> Adc<'d, T> {
         T::regs().cfgr().modify(|reg| {
             reg.set_jdiscen(false); // Will convert all channels for each trigger
         });
+
+        self.set_injected_conversion_trigger(trigger);
+        self.enable_injected_eos_interrupt(true);
+
+        self.start_injected_conversion();
+        InjectedAdc::new()
+    }
+
+    pub fn into_regular_ringbuffered_and_injected_interrupts<'a>(
+        &mut self,
+        dma: Peri<'a, impl RxDma<T>>,
+        dma_buf: &'a mut [u16],
+        regular_sequence: impl ExactSizeIterator<Item = (&'a mut AnyAdcChannel<T>, SampleTime)>,
+        regular_conversion_mode: RegularConversionMode,
+        injected_sequence: impl ExactSizeIterator<Item = (&'a mut AnyAdcChannel<T>, SampleTime)>,
+        injected_trigger: ConversionTrigger,
+    ) -> (RingBufferedAdc<'a, T>, InjectedAdc<T>) {
+        (
+            self.into_ring_buffered(
+                dma,
+                dma_buf,
+                regular_sequence,
+                regular_conversion_mode,
+            ),
+            self.configure_injected_sequence(
+                injected_sequence,
+                injected_trigger,
+            ),
+        )
     }
 
     /// Start injected ADC conversion
@@ -667,10 +729,10 @@ impl<'d, T: Instance> Adc<'d, T> {
 
     /// Set external trigger for injected conversion sequence
     /// Possible trigger values are seen in Table 167 in RM0440 Rev 9
-    pub fn set_injected_conversion_trigger(&mut self, trigger: u8, edge: Exten) {
+    pub fn set_injected_conversion_trigger(&mut self, trigger: ConversionTrigger) {
         T::regs().jsqr().modify(|r| {
-            r.set_jextsel(trigger);
-            r.set_jexten(edge);
+            r.set_jextsel(trigger.channel);
+            r.set_jexten(trigger.edge);
         });
     }
 
@@ -681,7 +743,7 @@ impl<'d, T: Instance> Adc<'d, T> {
 
     /// Read sampled data from all injected ADC injected ranks
     /// Clear the JEOS flag to allow a new injected sequence
-    pub fn clear_injected_eos(&mut self) -> [u16; NR_INJECTED_RANKS] {
+    pub(super) fn read_injected_samples() -> [u16; NR_INJECTED_RANKS] {
         let mut data = [0u16; NR_INJECTED_RANKS];
         for i in 0..NR_INJECTED_RANKS {
             data[i] = T::regs().jdr(i).read().jdata();
@@ -732,6 +794,9 @@ impl<'d, T: Instance> Adc<'d, T> {
             });
             while T::regs().cr().read().adstart() {}
         }
+    }
+
+    pub(super) fn stop_injected_conversions() {
         // Cancel injected conversions
         if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
             T::regs().cr().modify(|reg| {
diff --git a/embassy-stm32/src/adc/injected.rs b/embassy-stm32/src/adc/injected.rs
new file mode 100644
index 000000000..0efc47759
--- /dev/null
+++ b/embassy-stm32/src/adc/injected.rs
@@ -0,0 +1,36 @@
+use core::marker::PhantomData;
+use core::sync::atomic::{Ordering, compiler_fence};
+
+#[allow(unused_imports)]
+use embassy_hal_internal::Peri;
+
+use crate::adc::Adc;
+#[allow(unused_imports)]
+use crate::adc::Instance;
+
+const NR_INJECTED_RANKS: usize = 4;
+
+pub struct InjectedAdc<T: Instance> {
+    _phantom: PhantomData<T>,
+}
+
+impl<T: Instance> InjectedAdc<T> {
+    pub(crate) fn new() -> Self {
+        Self {
+            _phantom: PhantomData,
+        }
+    }
+
+    pub fn read_injected_samples(&mut self) -> [u16; NR_INJECTED_RANKS] {
+        Adc::<T>::read_injected_samples()
+    }
+}
+
+
+impl<T: Instance> Drop for InjectedAdc<T> {
+    fn drop(&mut self) {
+        Adc::<T>::teardown_adc();
+
+        compiler_fence(Ordering::SeqCst);
+    }
+}
diff --git a/examples/stm32g4/src/bin/adc_injected_and_regular.rs b/examples/stm32g4/src/bin/adc_injected_and_regular.rs
index c2985e1d6..85e01dbf3 100644
--- a/examples/stm32g4/src/bin/adc_injected_and_regular.rs
+++ b/examples/stm32g4/src/bin/adc_injected_and_regular.rs
@@ -9,7 +9,7 @@
 use core::cell::RefCell;
 
 use defmt::info;
-use embassy_stm32::adc::{Adc, AdcChannel as _, Exten, SampleTime};
+use embassy_stm32::adc::{Adc, AdcChannel as _, Exten, SampleTime, ConversionTrigger, RegularConversionMode};
 use embassy_stm32::interrupt::typelevel::{ADC1_2, Interrupt};
 use embassy_stm32::peripherals::ADC1;
 use embassy_stm32::time::Hertz;
@@ -17,9 +17,10 @@ use embassy_stm32::timer::complementary_pwm::{ComplementaryPwm, Mms2};
 use embassy_stm32::timer::low_level::CountingMode;
 use embassy_stm32::{Config, interrupt};
 use embassy_sync::blocking_mutex::CriticalSectionMutex;
+use embassy_stm32::adc::InjectedAdc;
 use {critical_section, defmt_rtt as _, panic_probe as _};
 
-static ADC1_HANDLE: CriticalSectionMutex<RefCell<Option<Adc<'static, ADC1>>>> =
+static ADC1_HANDLE: CriticalSectionMutex<RefCell<Option<InjectedAdc<ADC1>>>> =
     CriticalSectionMutex::new(RefCell::new(None));
 
 /// This example showcases how to use both regular ADC conversions with DMA and injected ADC
@@ -85,29 +86,30 @@ async fn main(_spawner: embassy_executor::Spawner) {
     ]
     .into_iter();
 
+    // Configurations of Injected ADC measurements
+    let mut pa2 = p.PA2.degrade_adc();
+    let injected_sequence = [(&mut pa2, SampleTime::CYCLES247_5)].into_iter();
+
     // Configure DMA for retrieving regular ADC measurements
     let dma1_ch1 = p.DMA1_CH1;
     // Using buffer of double size means the half-full interrupts will generate at the expected rate
     let mut readings = [0u16; 4];
-    let mut ring_buffered_adc = adc1.into_ring_buffered(dma1_ch1, &mut readings, regular_sequence);
-
-    // Configurations of Injected ADC measurements
-    let mut pa2 = p.PA2.degrade_adc();
-    let injected_seq = [(&mut pa2, SampleTime::CYCLES247_5)].into_iter();
-    adc1.configure_injected_sequence(injected_seq);
 
-    adc1.set_regular_conversion_trigger(ADC1_REGULAR_TRIGGER_TIM1_TRGO2, Exten::RISING_EDGE);
-    adc1.set_injected_conversion_trigger(ADC1_INJECTED_TRIGGER_TIM1_TRGO2, Exten::RISING_EDGE);
+    let injected_trigger = ConversionTrigger { channel: ADC1_INJECTED_TRIGGER_TIM1_TRGO2, edge: Exten::RISING_EDGE };
+    let regular_trigger = ConversionTrigger { channel: ADC1_REGULAR_TRIGGER_TIM1_TRGO2, edge: Exten::RISING_EDGE };
 
-    // ADC must be started after all configurations are completed
-    adc1.start_injected_conversion();
-
-    // Enable interrupt at end of injected ADC conversion
-    adc1.enable_injected_eos_interrupt(true);
+    let (mut ring_buffered_adc, injected_adc) = adc1.into_regular_ringbuffered_and_injected_interrupts(
+        dma1_ch1,
+        &mut readings,
+        regular_sequence,
+        RegularConversionMode::Triggered(regular_trigger),
+        injected_sequence,
+        injected_trigger,
+    );
 
     // Store ADC globally to allow access from ADC interrupt
     critical_section::with(|cs| {
-        ADC1_HANDLE.borrow(cs).replace(Some(adc1));
+        ADC1_HANDLE.borrow(cs).replace(Some(injected_adc));
     });
     // Enable interrupt for ADC1_2
     unsafe { ADC1_2::enable() };
@@ -136,8 +138,8 @@ async fn main(_spawner: embassy_executor::Spawner) {
 #[interrupt]
 unsafe fn ADC1_2() {
     critical_section::with(|cs| {
-        if let Some(adc) = ADC1_HANDLE.borrow(cs).borrow_mut().as_mut() {
-            let injected_data = adc.clear_injected_eos();
+        if let Some(injected_adc) = ADC1_HANDLE.borrow(cs).borrow_mut().as_mut() {
+            let injected_data = injected_adc.read_injected_samples();
             info!("Injected reading of PA2: {}", injected_data[0]);
         }
     });