1 files changed, 2 insertions, 1 deletions

diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs
index 439b7f020..f0105ece8 100644
--- a/embassy-stm32/src/timer/low_level.rs
+++ b/embassy-stm32/src/timer/low_level.rs
@@ -275,7 +275,8 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
     /// Generate timer update event from software.
     ///
     /// Set URS to avoid generating interrupt or DMA request. This update event is only
-    /// used to load value from pre-load registers.
+    /// used to load value from pre-load registers. If called when the timer is running,
+    /// it may disrupt the output waveform.
     pub fn generate_update_event(&self) {
         self.regs_core().cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
         self.regs_core().egr().write(|r| r.set_ug(true));