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-rw-r--r--embassy-stm32/src/dac/mod.rs21
1 files changed, 11 insertions, 10 deletions
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index b53083524..6686a387a 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -5,7 +5,6 @@ use core::marker::PhantomData;
5 5
6use embassy_hal_common::{into_ref, PeripheralRef}; 6use embassy_hal_common::{into_ref, PeripheralRef};
7 7
8use crate::dma::{Transfer, TransferOptions};
9use crate::pac::dac; 8use crate::pac::dac;
10use crate::rcc::RccPeripheral; 9use crate::rcc::RccPeripheral;
11use crate::{peripherals, Peripheral}; 10use crate::{peripherals, Peripheral};
@@ -195,6 +194,7 @@ pub struct Dac<'d, T: Instance, TxCh1, TxCh2> {
195pub struct DacCh1<'d, T: Instance, Tx> { 194pub struct DacCh1<'d, T: Instance, Tx> {
196 /// To consume T 195 /// To consume T
197 _peri: PeripheralRef<'d, T>, 196 _peri: PeripheralRef<'d, T>,
197 #[allow(unused)] // For chips whose DMA is not (yet) supported
198 dma: PeripheralRef<'d, Tx>, 198 dma: PeripheralRef<'d, Tx>,
199} 199}
200 200
@@ -204,6 +204,7 @@ pub struct DacCh1<'d, T: Instance, Tx> {
204pub struct DacCh2<'d, T: Instance, Tx> { 204pub struct DacCh2<'d, T: Instance, Tx> {
205 /// Instead of PeripheralRef to consume T 205 /// Instead of PeripheralRef to consume T
206 phantom: PhantomData<&'d mut T>, 206 phantom: PhantomData<&'d mut T>,
207 #[allow(unused)] // For chips whose DMA is not (yet) supported
207 dma: PeripheralRef<'d, Tx>, 208 dma: PeripheralRef<'d, Tx>,
208} 209}
209 210
@@ -265,7 +266,7 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
265 let tx_request = self.dma.request(); 266 let tx_request = self.dma.request();
266 let dma_channel = &self.dma; 267 let dma_channel = &self.dma;
267 268
268 let tx_options = TransferOptions { 269 let tx_options = crate::dma::TransferOptions {
269 circular, 270 circular,
270 half_transfer_ir: false, 271 half_transfer_ir: false,
271 complete_transfer_ir: !circular, 272 complete_transfer_ir: !circular,
@@ -275,7 +276,7 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
275 // Initiate the correct type of DMA transfer depending on what data is passed 276 // Initiate the correct type of DMA transfer depending on what data is passed
276 let tx_f = match data { 277 let tx_f = match data {
277 ValueArray::Bit8(buf) => unsafe { 278 ValueArray::Bit8(buf) => unsafe {
278 Transfer::new_write( 279 crate::dma::Transfer::new_write(
279 dma_channel, 280 dma_channel,
280 tx_request, 281 tx_request,
281 buf, 282 buf,
@@ -284,7 +285,7 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
284 ) 285 )
285 }, 286 },
286 ValueArray::Bit12Left(buf) => unsafe { 287 ValueArray::Bit12Left(buf) => unsafe {
287 Transfer::new_write( 288 crate::dma::Transfer::new_write(
288 dma_channel, 289 dma_channel,
289 tx_request, 290 tx_request,
290 buf, 291 buf,
@@ -293,7 +294,7 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
293 ) 294 )
294 }, 295 },
295 ValueArray::Bit12Right(buf) => unsafe { 296 ValueArray::Bit12Right(buf) => unsafe {
296 Transfer::new_write( 297 crate::dma::Transfer::new_write(
297 dma_channel, 298 dma_channel,
298 tx_request, 299 tx_request,
299 buf, 300 buf,
@@ -377,7 +378,7 @@ impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
377 let tx_request = self.dma.request(); 378 let tx_request = self.dma.request();
378 let dma_channel = &self.dma; 379 let dma_channel = &self.dma;
379 380
380 let tx_options = TransferOptions { 381 let tx_options = crate::dma::TransferOptions {
381 circular, 382 circular,
382 half_transfer_ir: false, 383 half_transfer_ir: false,
383 complete_transfer_ir: !circular, 384 complete_transfer_ir: !circular,
@@ -387,7 +388,7 @@ impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
387 // Initiate the correct type of DMA transfer depending on what data is passed 388 // Initiate the correct type of DMA transfer depending on what data is passed
388 let tx_f = match data { 389 let tx_f = match data {
389 ValueArray::Bit8(buf) => unsafe { 390 ValueArray::Bit8(buf) => unsafe {
390 Transfer::new_write( 391 crate::dma::Transfer::new_write(
391 dma_channel, 392 dma_channel,
392 tx_request, 393 tx_request,
393 buf, 394 buf,
@@ -396,7 +397,7 @@ impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
396 ) 397 )
397 }, 398 },
398 ValueArray::Bit12Left(buf) => unsafe { 399 ValueArray::Bit12Left(buf) => unsafe {
399 Transfer::new_write( 400 crate::dma::Transfer::new_write(
400 dma_channel, 401 dma_channel,
401 tx_request, 402 tx_request,
402 buf, 403 buf,
@@ -405,7 +406,7 @@ impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
405 ) 406 )
406 }, 407 },
407 ValueArray::Bit12Right(buf) => unsafe { 408 ValueArray::Bit12Right(buf) => unsafe {
408 Transfer::new_write( 409 crate::dma::Transfer::new_write(
409 dma_channel, 410 dma_channel,
410 tx_request, 411 tx_request,
411 buf, 412 buf,
@@ -526,7 +527,7 @@ foreach_peripheral!(
526 #[cfg(rcc_h7)] 527 #[cfg(rcc_h7)]
527 impl crate::rcc::sealed::RccPeripheral for peripherals::$inst { 528 impl crate::rcc::sealed::RccPeripheral for peripherals::$inst {
528 fn frequency() -> crate::time::Hertz { 529 fn frequency() -> crate::time::Hertz {
529 critical_section::with(|_| crate::rcc::get_freqs().apb1) 530 critical_section::with(|_| unsafe { crate::rcc::get_freqs().apb1 })
530 } 531 }
531 532
532 fn reset() { 533 fn reset() {