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-rw-r--r--embassy-stm32/src/spi/mod.rs23
-rw-r--r--embassy-stm32/src/spi/v1.rs18
-rw-r--r--embassy-stm32/src/spi/v2.rs18
-rw-r--r--embassy-stm32/src/spi/v3.rs24
4 files changed, 49 insertions, 34 deletions
diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs
index 70f40f0ea..5420ba365 100644
--- a/embassy-stm32/src/spi/mod.rs
+++ b/embassy-stm32/src/spi/mod.rs
@@ -290,6 +290,29 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
290 } 290 }
291} 291}
292 292
293trait RegsExt {
294 fn tx_ptr<W>(&self) -> *mut W;
295 fn rx_ptr<W>(&self) -> *mut W;
296}
297
298impl RegsExt for crate::pac::spi::Spi {
299 fn tx_ptr<W>(&self) -> *mut W {
300 #[cfg(not(spi_v3))]
301 let dr = self.dr();
302 #[cfg(spi_v3)]
303 let dr = self.txdr();
304 dr.ptr() as *mut W
305 }
306
307 fn rx_ptr<W>(&self) -> *mut W {
308 #[cfg(not(spi_v3))]
309 let dr = self.dr();
310 #[cfg(spi_v3)]
311 let dr = self.rxdr();
312 dr.ptr() as *mut W
313 }
314}
315
293pub(crate) mod sealed { 316pub(crate) mod sealed {
294 use super::*; 317 use super::*;
295 318
diff --git a/embassy-stm32/src/spi/v1.rs b/embassy-stm32/src/spi/v1.rs
index 8cdc3cd59..b98a78343 100644
--- a/embassy-stm32/src/spi/v1.rs
+++ b/embassy-stm32/src/spi/v1.rs
@@ -2,7 +2,7 @@
2 2
3use crate::dma::NoDma; 3use crate::dma::NoDma;
4use crate::gpio::sealed::Pin; 4use crate::gpio::sealed::Pin;
5use crate::spi::{Error, Instance, RxDmaChannel, TxDmaChannel, WordSize}; 5use crate::spi::{Error, Instance, RegsExt, RxDmaChannel, TxDmaChannel, WordSize};
6use core::future::Future; 6use core::future::Future;
7use core::ptr; 7use core::ptr;
8use embassy_traits::spi as traits; 8use embassy_traits::spi as traits;
@@ -42,7 +42,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
42 self.set_word_size(WordSize::EightBit); 42 self.set_word_size(WordSize::EightBit);
43 43
44 let request = self.txdma.request(); 44 let request = self.txdma.request();
45 let dst = T::regs().dr().ptr() as *mut u8; 45 let dst = T::regs().tx_ptr();
46 let f = self.txdma.write(request, write, dst); 46 let f = self.txdma.write(request, write, dst);
47 47
48 unsafe { 48 unsafe {
@@ -77,11 +77,11 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
77 let clock_byte_count = read.len(); 77 let clock_byte_count = read.len();
78 78
79 let rx_request = self.rxdma.request(); 79 let rx_request = self.rxdma.request();
80 let rx_src = T::regs().dr().ptr() as *mut u8; 80 let rx_src = T::regs().rx_ptr();
81 let rx_f = self.rxdma.read(rx_request, rx_src, read); 81 let rx_f = self.rxdma.read(rx_request, rx_src, read);
82 82
83 let tx_request = self.txdma.request(); 83 let tx_request = self.txdma.request();
84 let tx_dst = T::regs().dr().ptr() as *mut u8; 84 let tx_dst = T::regs().tx_ptr();
85 let clock_byte = 0x00; 85 let clock_byte = 0x00;
86 let tx_f = self 86 let tx_f = self
87 .txdma 87 .txdma
@@ -130,13 +130,13 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
130 self.set_word_size(WordSize::EightBit); 130 self.set_word_size(WordSize::EightBit);
131 131
132 let rx_request = self.rxdma.request(); 132 let rx_request = self.rxdma.request();
133 let rx_src = T::regs().dr().ptr() as *mut u8; 133 let rx_src = T::regs().rx_ptr();
134 let rx_f = self 134 let rx_f = self
135 .rxdma 135 .rxdma
136 .read(rx_request, rx_src, &mut read[0..write.len()]); 136 .read(rx_request, rx_src, &mut read[0..write.len()]);
137 137
138 let tx_request = self.txdma.request(); 138 let tx_request = self.txdma.request();
139 let tx_dst = T::regs().dr().ptr() as *mut u8; 139 let tx_dst = T::regs().tx_ptr();
140 let tx_f = self.txdma.write(tx_request, write, tx_dst); 140 let tx_f = self.txdma.write(tx_request, write, tx_dst);
141 141
142 unsafe { 142 unsafe {
@@ -308,8 +308,7 @@ fn write_word<W: Word>(regs: &'static crate::pac::spi::Spi, word: W) -> Result<(
308 } 308 }
309 if sr.txe() { 309 if sr.txe() {
310 unsafe { 310 unsafe {
311 let dr = regs.dr().ptr() as *mut W; 311 ptr::write_volatile(regs.tx_ptr(), word);
312 ptr::write_volatile(dr, word);
313 } 312 }
314 return Ok(()); 313 return Ok(());
315 } 314 }
@@ -335,8 +334,7 @@ fn read_word<W: Word>(regs: &'static crate::pac::spi::Spi) -> Result<W, Error> {
335 } 334 }
336 if sr.rxne() { 335 if sr.rxne() {
337 unsafe { 336 unsafe {
338 let dr = regs.dr().ptr() as *const W; 337 return Ok(ptr::read_volatile(regs.rx_ptr()));
339 return Ok(ptr::read_volatile(dr));
340 } 338 }
341 } 339 }
342 } 340 }
diff --git a/embassy-stm32/src/spi/v2.rs b/embassy-stm32/src/spi/v2.rs
index a34266992..5c62400eb 100644
--- a/embassy-stm32/src/spi/v2.rs
+++ b/embassy-stm32/src/spi/v2.rs
@@ -2,7 +2,7 @@
2 2
3use crate::dma::NoDma; 3use crate::dma::NoDma;
4use crate::gpio::sealed::Pin; 4use crate::gpio::sealed::Pin;
5use crate::spi::{Error, Instance, RxDmaChannel, TxDmaChannel, WordSize}; 5use crate::spi::{Error, Instance, RegsExt, RxDmaChannel, TxDmaChannel, WordSize};
6use core::future::Future; 6use core::future::Future;
7use core::ptr; 7use core::ptr;
8use embassy_traits::spi as traits; 8use embassy_traits::spi as traits;
@@ -44,7 +44,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
44 self.set_word_size(WordSize::EightBit); 44 self.set_word_size(WordSize::EightBit);
45 45
46 let request = self.txdma.request(); 46 let request = self.txdma.request();
47 let dst = T::regs().dr().ptr() as *mut u8; 47 let dst = T::regs().tx_ptr();
48 let f = self.txdma.write(request, write, dst); 48 let f = self.txdma.write(request, write, dst);
49 49
50 unsafe { 50 unsafe {
@@ -88,11 +88,11 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
88 let clock_byte_count = read.len(); 88 let clock_byte_count = read.len();
89 89
90 let rx_request = self.rxdma.request(); 90 let rx_request = self.rxdma.request();
91 let rx_src = T::regs().dr().ptr() as *mut u8; 91 let rx_src = T::regs().rx_ptr();
92 let rx_f = self.rxdma.read(rx_request, rx_src, read); 92 let rx_f = self.rxdma.read(rx_request, rx_src, read);
93 93
94 let tx_request = self.txdma.request(); 94 let tx_request = self.txdma.request();
95 let tx_dst = T::regs().dr().ptr() as *mut u8; 95 let tx_dst = T::regs().tx_ptr();
96 let clock_byte = 0x00; 96 let clock_byte = 0x00;
97 let tx_f = self 97 let tx_f = self
98 .txdma 98 .txdma
@@ -146,13 +146,13 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
146 self.set_word_size(WordSize::EightBit); 146 self.set_word_size(WordSize::EightBit);
147 147
148 let rx_request = self.rxdma.request(); 148 let rx_request = self.rxdma.request();
149 let rx_src = T::regs().dr().ptr() as *mut u8; 149 let rx_src = T::regs().rx_ptr();
150 let rx_f = self 150 let rx_f = self
151 .rxdma 151 .rxdma
152 .read(rx_request, rx_src, &mut read[0..write.len()]); 152 .read(rx_request, rx_src, &mut read[0..write.len()]);
153 153
154 let tx_request = self.txdma.request(); 154 let tx_request = self.txdma.request();
155 let tx_dst = T::regs().dr().ptr() as *mut u8; 155 let tx_dst = T::regs().tx_ptr();
156 let tx_f = self.txdma.write(tx_request, write, tx_dst); 156 let tx_f = self.txdma.write(tx_request, write, tx_dst);
157 157
158 unsafe { 158 unsafe {
@@ -223,8 +223,7 @@ fn write_word<W: Word>(regs: &'static crate::pac::spi::Spi, word: W) -> Result<(
223 return Err(Error::Crc); 223 return Err(Error::Crc);
224 } else if sr.txe() { 224 } else if sr.txe() {
225 unsafe { 225 unsafe {
226 let dr = regs.dr().ptr() as *mut W; 226 ptr::write_volatile(regs.tx_ptr(), word);
227 ptr::write_volatile(dr, word);
228 } 227 }
229 return Ok(()); 228 return Ok(());
230 } 229 }
@@ -245,8 +244,7 @@ fn read_word<W: Word>(regs: &'static crate::pac::spi::Spi) -> Result<W, Error> {
245 return Err(Error::Crc); 244 return Err(Error::Crc);
246 } else if sr.rxne() { 245 } else if sr.rxne() {
247 unsafe { 246 unsafe {
248 let dr = regs.dr().ptr() as *const W; 247 return Ok(ptr::read_volatile(regs.rx_ptr()));
249 return Ok(ptr::read_volatile(dr));
250 } 248 }
251 } 249 }
252 } 250 }
diff --git a/embassy-stm32/src/spi/v3.rs b/embassy-stm32/src/spi/v3.rs
index 59afa553b..a23a6dd02 100644
--- a/embassy-stm32/src/spi/v3.rs
+++ b/embassy-stm32/src/spi/v3.rs
@@ -2,7 +2,7 @@
2 2
3use crate::dma::NoDma; 3use crate::dma::NoDma;
4use crate::gpio::sealed::Pin; 4use crate::gpio::sealed::Pin;
5use crate::spi::{Error, Instance, RxDmaChannel, TxDmaChannel, WordSize}; 5use crate::spi::{Error, Instance, RegsExt, RxDmaChannel, TxDmaChannel, WordSize};
6use core::future::Future; 6use core::future::Future;
7use core::ptr; 7use core::ptr;
8use embassy_traits::spi as traits; 8use embassy_traits::spi as traits;
@@ -49,7 +49,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
49 } 49 }
50 50
51 let request = self.txdma.request(); 51 let request = self.txdma.request();
52 let dst = T::regs().txdr().ptr() as *mut u8; 52 let dst = T::regs().tx_ptr();
53 let f = self.txdma.write(request, write, dst); 53 let f = self.txdma.write(request, write, dst);
54 54
55 unsafe { 55 unsafe {
@@ -96,11 +96,11 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
96 let clock_byte_count = read.len(); 96 let clock_byte_count = read.len();
97 97
98 let rx_request = self.rxdma.request(); 98 let rx_request = self.rxdma.request();
99 let rx_src = T::regs().rxdr().ptr() as *mut u8; 99 let rx_src = T::regs().rx_ptr();
100 let rx_f = self.rxdma.read(rx_request, rx_src, read); 100 let rx_f = self.rxdma.read(rx_request, rx_src, read);
101 101
102 let tx_request = self.txdma.request(); 102 let tx_request = self.txdma.request();
103 let tx_dst = T::regs().txdr().ptr() as *mut u8; 103 let tx_dst = T::regs().tx_ptr();
104 let clock_byte = 0x00; 104 let clock_byte = 0x00;
105 let tx_f = self 105 let tx_f = self
106 .txdma 106 .txdma
@@ -155,13 +155,13 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
155 } 155 }
156 156
157 let rx_request = self.rxdma.request(); 157 let rx_request = self.rxdma.request();
158 let rx_src = T::regs().rxdr().ptr() as *mut u8; 158 let rx_src = T::regs().rx_ptr();
159 let rx_f = self 159 let rx_f = self
160 .rxdma 160 .rxdma
161 .read(rx_request, rx_src, &mut read[0..write.len()]); 161 .read(rx_request, rx_src, &mut read[0..write.len()]);
162 162
163 let tx_request = self.txdma.request(); 163 let tx_request = self.txdma.request();
164 let tx_dst = T::regs().txdr().ptr() as *mut u8; 164 let tx_dst = T::regs().tx_ptr();
165 let tx_f = self.txdma.write(tx_request, write, tx_dst); 165 let tx_f = self.txdma.write(tx_request, write, tx_dst);
166 166
167 unsafe { 167 unsafe {
@@ -223,8 +223,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T, NoDm
223 // spin 223 // spin
224 } 224 }
225 unsafe { 225 unsafe {
226 let txdr = regs.txdr().ptr() as *mut u8; 226 ptr::write_volatile(regs.tx_ptr(), *word);
227 ptr::write_volatile(txdr, *word);
228 regs.cr1().modify(|reg| reg.set_cstart(true)); 227 regs.cr1().modify(|reg| reg.set_cstart(true));
229 } 228 }
230 loop { 229 loop {
@@ -245,9 +244,8 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T, NoDm
245 break; 244 break;
246 } 245 }
247 unsafe { 246 unsafe {
248 let rxdr = regs.rxdr().ptr() as *const u8;
249 // discard read to prevent pverrun. 247 // discard read to prevent pverrun.
250 let _ = ptr::read_volatile(rxdr); 248 let _: u8 = ptr::read_volatile(T::regs().rx_ptr());
251 } 249 }
252 } 250 }
253 251
@@ -276,8 +274,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T, N
276 // spin 274 // spin
277 } 275 }
278 unsafe { 276 unsafe {
279 let txdr = regs.txdr().ptr() as *mut u8; 277 ptr::write_volatile(T::regs().tx_ptr(), *word);
280 ptr::write_volatile(txdr, *word);
281 regs.cr1().modify(|reg| reg.set_cstart(true)); 278 regs.cr1().modify(|reg| reg.set_cstart(true));
282 } 279 }
283 loop { 280 loop {
@@ -297,8 +294,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T, N
297 } 294 }
298 } 295 }
299 unsafe { 296 unsafe {
300 let rxdr = regs.rxdr().ptr() as *const u8; 297 *word = ptr::read_volatile(T::regs().rx_ptr());
301 *word = ptr::read_volatile(rxdr);
302 } 298 }
303 let sr = unsafe { regs.sr().read() }; 299 let sr = unsafe { regs.sr().read() };
304 if sr.tifre() { 300 if sr.tifre() {