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-rw-r--r--embassy-stm32/src/dac/mod.rs9
1 files changed, 4 insertions, 5 deletions
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index bf15eaac5..979748bb4 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -164,7 +164,7 @@ pub trait DacChannel<T: Instance, Tx> {
164 } 164 }
165 165
166 /// Set mode register of the given channel 166 /// Set mode register of the given channel
167 #[cfg(dac_v2)] 167 #[cfg(any(dac_v2, dac_v3))]
168 fn set_channel_mode(&mut self, val: u8) -> Result<(), Error> { 168 fn set_channel_mode(&mut self, val: u8) -> Result<(), Error> {
169 T::regs().mcr().modify(|reg| { 169 T::regs().mcr().modify(|reg| {
170 reg.set_mode(Self::CHANNEL.index(), val); 170 reg.set_mode(Self::CHANNEL.index(), val);
@@ -262,7 +262,7 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
262 262
263 // Configure each activated channel. All results can be `unwrap`ed since they 263 // Configure each activated channel. All results can be `unwrap`ed since they
264 // will only error if the channel is not configured (i.e. ch1, ch2 are false) 264 // will only error if the channel is not configured (i.e. ch1, ch2 are false)
265 #[cfg(dac_v2)] 265 #[cfg(any(dac_v2, dac_v3))]
266 dac.set_channel_mode(0).unwrap(); 266 dac.set_channel_mode(0).unwrap();
267 dac.enable_channel().unwrap(); 267 dac.enable_channel().unwrap();
268 dac.set_trigger_enable(true).unwrap(); 268 dac.set_trigger_enable(true).unwrap();
@@ -288,7 +288,6 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
288 /// Note that for performance reasons in circular mode the transfer complete interrupt is disabled. 288 /// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
289 /// 289 ///
290 /// **Important:** Channel 1 has to be configured for the DAC instance! 290 /// **Important:** Channel 1 has to be configured for the DAC instance!
291 #[cfg(all(bdma, not(dma)))] // It currently only works with BDMA-only chips (DMA should theoretically work though)
292 pub async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error> 291 pub async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
293 where 292 where
294 Tx: DmaCh1<T>, 293 Tx: DmaCh1<T>,
@@ -377,7 +376,7 @@ impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
377 376
378 // Configure each activated channel. All results can be `unwrap`ed since they 377 // Configure each activated channel. All results can be `unwrap`ed since they
379 // will only error if the channel is not configured (i.e. ch1, ch2 are false) 378 // will only error if the channel is not configured (i.e. ch1, ch2 are false)
380 #[cfg(dac_v2)] 379 #[cfg(any(dac_v2, dac_v3))]
381 dac.set_channel_mode(0).unwrap(); 380 dac.set_channel_mode(0).unwrap();
382 dac.enable_channel().unwrap(); 381 dac.enable_channel().unwrap();
383 dac.set_trigger_enable(true).unwrap(); 382 dac.set_trigger_enable(true).unwrap();
@@ -499,7 +498,7 @@ impl<'d, T: Instance, TxCh1, TxCh2> Dac<'d, T, TxCh1, TxCh2> {
499 498
500 // Configure each activated channel. All results can be `unwrap`ed since they 499 // Configure each activated channel. All results can be `unwrap`ed since they
501 // will only error if the channel is not configured (i.e. ch1, ch2 are false) 500 // will only error if the channel is not configured (i.e. ch1, ch2 are false)
502 #[cfg(dac_v2)] 501 #[cfg(any(dac_v2, dac_v3))]
503 dac_ch1.set_channel_mode(0).unwrap(); 502 dac_ch1.set_channel_mode(0).unwrap();
504 dac_ch1.enable_channel().unwrap(); 503 dac_ch1.enable_channel().unwrap();
505 dac_ch1.set_trigger_enable(true).unwrap(); 504 dac_ch1.set_trigger_enable(true).unwrap();