4 files changed, 21 insertions, 18 deletions

diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 38254ee40..b5b734910 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -81,7 +81,7 @@ futures-util = { version = "0.3.30", default-features = false }
 sdio-host = "0.9.0"
 critical-section = "1.1"
 #stm32-metapac = { version = "16" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-9fc86ca7b3a8bc05182bf1ce3045602df1f5dce3" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-dbdc1a4ea26229805def4738b777933803086f93" }
 
 vcell = "0.1.3"
 nb = "1.0.0"
@@ -110,7 +110,7 @@ proc-macro2 = "1.0.36"
 quote = "1.0.15"
 
 #stm32-metapac = { version = "16", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-9fc86ca7b3a8bc05182bf1ce3045602df1f5dce3", default-features = false, features = ["metadata"] }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-dbdc1a4ea26229805def4738b777933803086f93", default-features = false, features = ["metadata"] }
 
 [features]
 default = ["rt"]
diff --git a/embassy-stm32/src/rcc/wba.rs b/embassy-stm32/src/rcc/wba.rs
index 30076b60d..4ca622614 100644
--- a/embassy-stm32/src/rcc/wba.rs
+++ b/embassy-stm32/src/rcc/wba.rs
@@ -1,6 +1,9 @@
 pub use crate::pac::pwr::vals::Vos as VoltageScale;
 use crate::pac::rcc::regs::Cfgr1;
-pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Hsepre as HsePrescaler, Ppre as APBPrescaler, Sw as Sysclk, Pllsrc as PllSource };
+pub use crate::pac::rcc::vals::{
+    Hpre as AHBPrescaler, Hsepre as HsePrescaler, Ppre as APBPrescaler, Sw as Sysclk, Pllsrc as PllSource,
+    Plldiv as PllDiv, Pllm, Plln as PllMul,
+};
 use crate::pac::rcc::vals::Pllrge;
 use crate::pac::{FLASH, RCC};
 use crate::rcc::LSI_FREQ;
@@ -29,28 +32,28 @@ pub struct Pll {
     /// The PLL pre-divider.
     ///
     /// The clock speed of the `source` divided by `m` must be between 4 and 16 MHz.
-    pub pllm: u8,
+    pub pllm: Pllm,
     /// The PLL multiplier.
     ///
     /// The multiplied clock – `source` divided by `m` times `n` – must be between 128 and 544
     /// MHz. The upper limit may be lower depending on the `Config { voltage_range }`.
-    pub mul: u8,
+    pub mul: PllMul,
     /// The divider for the P output.
     ///
     /// The P output is one of several options
     /// that can be used to feed the SAI/MDF/ADF Clock mux's.
-    pub divp: Option<u8>,
+    pub divp: Option<PllDiv>,
     /// The divider for the Q output.
     ///
     /// The Q ouput is one of severals options that can be used to feed the 48MHz clocks
     /// and the OCTOSPI clock. It may also be used on the MDF/ADF clock mux's.
-    pub divq: Option<u8>,
+    pub divq: Option<PllDiv>,
     /// The divider for the R output.
     ///
     /// When used to drive the system clock, `source` divided by `m` times `n` divided by `r`
     /// must not exceed 160 MHz. System clocks above 55 MHz require a non-default
     /// `Config { voltage_range }`.
-    pub divr: Option<u8>,
+    pub divr: Option<PllDiv>,
 
     pub frac: Option<u16>,
 }
@@ -318,10 +321,10 @@ fn init_pll(config: Option<Pll>, input: &PllInput, voltage_range: VoltageScale)
 
     let divr = RCC.pll1divr();
     divr.write(|w| {
-        w.set_plln(pll.mul as u16);
-        w.set_pllp(pll.divp.unwrap_or(1));
-        w.set_pllq(pll.divq.unwrap_or(1));
-        w.set_pllr(pll.divr.unwrap_or(1));
+        w.set_plln(pll.mul);
+        w.set_pllp(pll.divp.unwrap_or(PllDiv::DIV1));
+        w.set_pllq(pll.divq.unwrap_or(PllDiv::DIV1));
+        w.set_pllr(pll.divr.unwrap_or(PllDiv::DIV1));
         // w.set_pllfracn(pll.frac.unwrap_or(1));
     });
     RCC.pll1fracr().write(|w| {w.set_pllfracn(pll.frac.unwrap_or(1));});
diff --git a/embassy-stm32/src/usb/otg.rs b/embassy-stm32/src/usb/otg.rs
index c8499bdc7..02b27ed48 100644
--- a/embassy-stm32/src/usb/otg.rs
+++ b/embassy-stm32/src/usb/otg.rs
@@ -336,7 +336,7 @@ impl<'d, T: Instance> Bus<'d, T> {
             critical_section::with(|_| {
                 crate::pac::RCC.ahb2enr().modify(|w| {
                     w.set_usb_otg_hsen(true);
-                    w.set_otghsphyen(true);
+                    w.set_usb_otg_hs_phyen(true);
                 });
             });
         }
diff --git a/examples/stm32wba/src/bin/usb_hs_serial.rs b/examples/stm32wba/src/bin/usb_hs_serial.rs
index d77a679fe..e30f33625 100644
--- a/examples/stm32wba/src/bin/usb_hs_serial.rs
+++ b/examples/stm32wba/src/bin/usb_hs_serial.rs
@@ -36,11 +36,11 @@ async fn main(_spawner: Spawner) {
     // Fine-tune PLL1 dividers/multipliers
     config.rcc.pll1 = Some(embassy_stm32::rcc::Pll {
         source: PllSource::HSE,
-        pllm: 2,          // PLLM = 2 → HSE / 2 = 16 MHz input
-        mul: 12,          // PLLN = 12 → 16 MHz * 12 = 192 MHz VCO
-        divp: Some(2),    // PLLP = 2 → 96 MHz
-        divq: Some(2),    // PLLQ = 2 → 96 MHz
-        divr: Some(2),    // PLLR = 2 → 96 MHz
+        pllm: 2.into(),          // PLLM = 2 → HSE / 2 = 16 MHz input
+        mul: 12.into(),          // PLLN = 12 → 16 MHz * 12 = 192 MHz VCO
+        divp: Some(2.into()),    // PLLP = 2 → 96 MHz
+        divq: Some(2.into()),    // PLLQ = 2 → 96 MHz
+        divr: Some(2.into()),    // PLLR = 2 → 96 MHz
         frac: Some(4096), // Fractional part (enabled)
     });