diff options
| -rw-r--r-- | stm32-metapac-gen/src/lib.rs | 21 |
1 files changed, 6 insertions, 15 deletions
diff --git a/stm32-metapac-gen/src/lib.rs b/stm32-metapac-gen/src/lib.rs index d9ab92ee6..983ced910 100644 --- a/stm32-metapac-gen/src/lib.rs +++ b/stm32-metapac-gen/src/lib.rs | |||
| @@ -118,7 +118,7 @@ impl BlockInfo { | |||
| 118 | 118 | ||
| 119 | fn find_reg_for_field<'c>( | 119 | fn find_reg_for_field<'c>( |
| 120 | rcc: &'c ir::IR, | 120 | rcc: &'c ir::IR, |
| 121 | reg_prefix: &str, | 121 | reg_regex: &str, |
| 122 | field_name: &str, | 122 | field_name: &str, |
| 123 | ) -> Option<(&'c str, &'c str)> { | 123 | ) -> Option<(&'c str, &'c str)> { |
| 124 | rcc.fieldsets.iter().find_map(|(name, fieldset)| { | 124 | rcc.fieldsets.iter().find_map(|(name, fieldset)| { |
| @@ -126,7 +126,7 @@ fn find_reg_for_field<'c>( | |||
| 126 | // not help matching for clock name. | 126 | // not help matching for clock name. |
| 127 | if name.starts_with("C1") || name.starts_with("C2") { | 127 | if name.starts_with("C1") || name.starts_with("C2") { |
| 128 | None | 128 | None |
| 129 | } else if name.starts_with(reg_prefix) { | 129 | } else if Regex::new(reg_regex).unwrap().is_match(name) { |
| 130 | fieldset | 130 | fieldset |
| 131 | .fields | 131 | .fields |
| 132 | .iter() | 132 | .iter() |
| @@ -441,31 +441,22 @@ pub fn gen(options: Options) { | |||
| 441 | }; | 441 | }; |
| 442 | 442 | ||
| 443 | if let Some(clock_prefix) = clock_prefix { | 443 | if let Some(clock_prefix) = clock_prefix { |
| 444 | // Ignore the numbers in clock name when searching for enable bits because clock | ||
| 445 | // names do not map cleanly to regsiter names. | ||
| 446 | // Example: | ||
| 447 | // stm32f0: RCC_APB2ENR - APB peripheral clock enable register 2 CLOCK: APB1 | ||
| 448 | // stm32f4: RCC_APB2ENR - RCC APB2 peripheral clock enable register CLOCK: APB2 | ||
| 449 | // | ||
| 450 | // Search for the enable bit in all available registers to support the stm32f0 case. | ||
| 451 | let search_clock_prefix = clock_prefix.trim_end_matches(char::is_numeric); | ||
| 452 | |||
| 453 | // Workaround for clock registers being split on some chip families. Assume fields are | 444 | // Workaround for clock registers being split on some chip families. Assume fields are |
| 454 | // named after peripheral and look for first field matching and use that register. | 445 | // named after peripheral and look for first field matching and use that register. |
| 455 | let mut en = | 446 | let mut en = |
| 456 | find_reg_for_field(&rcc, search_clock_prefix, &format!("{}EN", name)); | 447 | find_reg_for_field(&rcc, "^.+ENR\\d*$", &format!("{}EN", name)); |
| 457 | let mut rst = | 448 | let mut rst = |
| 458 | find_reg_for_field(&rcc, search_clock_prefix, &format!("{}RST", name)); | 449 | find_reg_for_field(&rcc, "^.+RSTR\\d*$", &format!("{}RST", name)); |
| 459 | 450 | ||
| 460 | if en.is_none() && name.ends_with("1") { | 451 | if en.is_none() && name.ends_with("1") { |
| 461 | en = find_reg_for_field( | 452 | en = find_reg_for_field( |
| 462 | &rcc, | 453 | &rcc, |
| 463 | search_clock_prefix, | 454 | "^.+ENR\\d*$", |
| 464 | &format!("{}EN", &name[..name.len() - 1]), | 455 | &format!("{}EN", &name[..name.len() - 1]), |
| 465 | ); | 456 | ); |
| 466 | rst = find_reg_for_field( | 457 | rst = find_reg_for_field( |
| 467 | &rcc, | 458 | &rcc, |
| 468 | search_clock_prefix, | 459 | "^.+RSTR\\d*$", |
| 469 | &format!("{}RST", &name[..name.len() - 1]), | 460 | &format!("{}RST", &name[..name.len() - 1]), |
| 470 | ); | 461 | ); |
| 471 | } | 462 | } |
