2 files changed, 13 insertions, 5 deletions

diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs
index de7b3c8df..568067360 100644
--- a/embassy-stm32/src/usart/mod.rs
+++ b/embassy-stm32/src/usart/mod.rs
@@ -85,6 +85,7 @@ unsafe fn on_interrupt(r: Regs, s: &'static State) {
 
     compiler_fence(Ordering::SeqCst);
     s.rx_waker.wake();
+    s.tx_waker.wake();
 }
 
 #[derive(Clone, Copy, PartialEq, Eq, Debug)]
@@ -592,7 +593,7 @@ async fn flush(info: &Info, state: &State) -> Result<(), Error> {
 
         // future which completes when Transmission complete is detected
         let abort = poll_fn(move |cx| {
-            state.rx_waker.register(cx.waker());
+            state.tx_waker.register(cx.waker());
 
             let sr = sr(r).read();
             if sr.tc() {
@@ -2019,6 +2020,7 @@ enum Kind {
 
 struct State {
     rx_waker: AtomicWaker,
+    tx_waker: AtomicWaker,
     tx_rx_refcount: AtomicU8,
 }
 
@@ -2026,6 +2028,7 @@ impl State {
     const fn new() -> Self {
         Self {
             rx_waker: AtomicWaker::new(),
+            tx_waker: AtomicWaker::new(),
             tx_rx_refcount: AtomicU8::new(0),
         }
     }
diff --git a/embassy-stm32/src/usart/ringbuffered.rs b/embassy-stm32/src/usart/ringbuffered.rs
index 560ce4e8f..3631888e4 100644
--- a/embassy-stm32/src/usart/ringbuffered.rs
+++ b/embassy-stm32/src/usart/ringbuffered.rs
@@ -8,12 +8,12 @@ use embassy_hal_internal::PeripheralRef;
 use embedded_io_async::ReadReady;
 use futures_util::future::{select, Either};
 
-use super::{
-    clear_interrupt_flags, rdr, reconfigure, set_baudrate, sr, Config, ConfigError, Error, Info, State, UartRx,
-};
+use super::{rdr, reconfigure, set_baudrate, sr, Config, ConfigError, Error, Info, State, UartRx};
 use crate::dma::ReadableRingBuffer;
 use crate::gpio::{AnyPin, SealedPin as _};
 use crate::mode::Async;
+#[cfg(any(usart_v3, usart_v4))]
+use crate::pac::usart::regs;
 use crate::time::Hertz;
 use crate::usart::{Regs, Sr};
 
@@ -254,7 +254,12 @@ fn clear_idle_flag(r: Regs) -> Sr {
 
     // This read also clears the error and idle interrupt flags on v1.
     unsafe { rdr(r).read_volatile() };
-    clear_interrupt_flags(r, sr);
+    #[cfg(any(usart_v3, usart_v4))]
+    {
+        let mut clear_idle = regs::Icr(0);
+        clear_idle.set_idle(true);
+        r.icr().write_value(clear_idle);
+    }
 
     r.cr1().modify(|w| w.set_idleie(true));