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-rw-r--r--src/clocks/mod.rs16
-rw-r--r--src/clocks/periph_helpers.rs4
2 files changed, 8 insertions, 12 deletions
diff --git a/src/clocks/mod.rs b/src/clocks/mod.rs
index a12e125c6..0b4535dc4 100644
--- a/src/clocks/mod.rs
+++ b/src/clocks/mod.rs
@@ -652,17 +652,15 @@ impl ClockOperator<'_> {
652 }); 652 });
653 } 653 }
654 654
655 // Halt and reset the div 655 // Halt and reset the div; then set our desired div.
656 self.syscon.frohfdiv().write(|w| { 656 self.syscon.frohfdiv().write(|w| {
657 w.halt().halt(); 657 w.halt().halt();
658 w.reset().asserted(); 658 w.reset().asserted();
659 unsafe { w.div().bits(d.into_bits()) };
659 w 660 w
660 }); 661 });
661 // Then change the div, unhalt it, and reset it 662 // Then unhalt it, and reset it
662 self.syscon.frohfdiv().write(|w| { 663 self.syscon.frohfdiv().write(|w| {
663 unsafe {
664 w.div().bits(d.into_bits());
665 }
666 w.halt().run(); 664 w.halt().run();
667 w.reset().released(); 665 w.reset().released();
668 w 666 w
@@ -743,17 +741,15 @@ impl ClockOperator<'_> {
743 }); 741 });
744 } 742 }
745 743
746 // Halt and reset the div 744 // Halt and reset the div; then set our desired div.
747 self.syscon.frolfdiv().write(|w| { 745 self.syscon.frolfdiv().write(|w| {
748 w.halt().halt(); 746 w.halt().halt();
749 w.reset().asserted(); 747 w.reset().asserted();
748 unsafe { w.div().bits(d.into_bits()) };
750 w 749 w
751 }); 750 });
752 // Then change the div, unhalt it, and reset it 751 // Then unhalt it, and reset it
753 self.syscon.frolfdiv().write(|w| { 752 self.syscon.frolfdiv().write(|w| {
754 unsafe {
755 w.div().bits(d.into_bits());
756 }
757 w.halt().run(); 753 w.halt().run();
758 w.reset().released(); 754 w.reset().released();
759 w 755 w
diff --git a/src/clocks/periph_helpers.rs b/src/clocks/periph_helpers.rs
index e5b234c5b..8914f6833 100644
--- a/src/clocks/periph_helpers.rs
+++ b/src/clocks/periph_helpers.rs
@@ -240,12 +240,12 @@ impl SPConfHelper for LpuartConfig {
240 clkdiv.modify(|_r, w| { 240 clkdiv.modify(|_r, w| {
241 w.halt().on(); 241 w.halt().on();
242 w.reset().on(); 242 w.reset().on();
243 unsafe { w.div().bits(self.div.into_bits()) };
243 w 244 w
244 }); 245 });
245 clkdiv.modify(|_r, w| { 246 clkdiv.modify(|_r, w| {
246 w.halt().off(); 247 w.halt().off();
247 w.reset().off(); 248 w.reset().off();
248 unsafe { w.div().bits(self.div.into_bits()) };
249 w 249 w
250 }); 250 });
251 251
@@ -377,12 +377,12 @@ impl SPConfHelper for AdcConfig {
377 mrcc0.mrcc_adc_clkdiv().modify(|_r, w| { 377 mrcc0.mrcc_adc_clkdiv().modify(|_r, w| {
378 w.halt().on(); 378 w.halt().on();
379 w.reset().on(); 379 w.reset().on();
380 unsafe { w.div().bits(self.div.into_bits()) };
380 w 381 w
381 }); 382 });
382 mrcc0.mrcc_adc_clkdiv().modify(|_r, w| { 383 mrcc0.mrcc_adc_clkdiv().modify(|_r, w| {
383 w.halt().off(); 384 w.halt().off();
384 w.reset().off(); 385 w.reset().off();
385 unsafe { w.div().bits(self.div.into_bits()) };
386 w 386 w
387 }); 387 });
388 388