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-rw-r--r--cyw43-pio/src/lib.rs6
-rw-r--r--src/bus.rs2
-rw-r--r--src/consts.rs3
3 files changed, 6 insertions, 5 deletions
diff --git a/cyw43-pio/src/lib.rs b/cyw43-pio/src/lib.rs
index 46ea0411e..9c425cbaa 100644
--- a/cyw43-pio/src/lib.rs
+++ b/cyw43-pio/src/lib.rs
@@ -43,6 +43,7 @@ where
43 "set pindirs, 0 side 0" 43 "set pindirs, 0 side 0"
44 // these nops seem to be necessary for fast clkdiv 44 // these nops seem to be necessary for fast clkdiv
45 "nop side 1" 45 "nop side 1"
46 "nop side 0"
46 "nop side 1" 47 "nop side 1"
47 // read in y-1 bits 48 // read in y-1 bits
48 "lp2:" 49 "lp2:"
@@ -70,11 +71,10 @@ where
70 sm.write_instr(relocated.origin() as usize, relocated.code()); 71 sm.write_instr(relocated.origin() as usize, relocated.code());
71 72
72 // theoretical maximum according to data sheet, 100Mhz Pio => 50Mhz SPI Freq 73 // theoretical maximum according to data sheet, 100Mhz Pio => 50Mhz SPI Freq
73 // does not work yet, 74 sm.set_clkdiv(0x0140);
74 // sm.set_clkdiv(0x0140);
75 75
76 // same speed as pico-sdk, 62.5Mhz 76 // same speed as pico-sdk, 62.5Mhz
77 sm.set_clkdiv(0x0200); 77 // sm.set_clkdiv(0x0200);
78 78
79 // 32 Mhz 79 // 32 Mhz
80 // sm.set_clkdiv(0x03E8); 80 // sm.set_clkdiv(0x03E8);
diff --git a/src/bus.rs b/src/bus.rs
index 65caea8ec..add346b2f 100644
--- a/src/bus.rs
+++ b/src/bus.rs
@@ -74,7 +74,7 @@ where
74 // 32-bit word length, little endian (which is the default endianess). 74 // 32-bit word length, little endian (which is the default endianess).
75 self.write32_swapped( 75 self.write32_swapped(
76 REG_BUS_CTRL, 76 REG_BUS_CTRL,
77 WORD_LENGTH_32 | HIGH_SPEED | INTERRUPT_HIGH | WAKE_UP | STATUS_ENABLE, 77 WORD_LENGTH_32 | HIGH_SPEED | INTERRUPT_HIGH | WAKE_UP | STATUS_ENABLE | INTERRUPT_WITH_STATUS,
78 ) 78 )
79 .await; 79 .await;
80 80
diff --git a/src/consts.rs b/src/consts.rs
index 6ed7feb92..fee2d01ab 100644
--- a/src/consts.rs
+++ b/src/consts.rs
@@ -16,7 +16,8 @@ pub(crate) const WORD_LENGTH_32: u32 = 0x1;
16pub(crate) const HIGH_SPEED: u32 = 0x10; 16pub(crate) const HIGH_SPEED: u32 = 0x10;
17pub(crate) const INTERRUPT_HIGH: u32 = 1 << 5; 17pub(crate) const INTERRUPT_HIGH: u32 = 1 << 5;
18pub(crate) const WAKE_UP: u32 = 1 << 7; 18pub(crate) const WAKE_UP: u32 = 1 << 7;
19pub(crate) const STATUS_ENABLE: u32 = 0x10000; 19pub(crate) const STATUS_ENABLE: u32 = 1 << 16;
20pub(crate) const INTERRUPT_WITH_STATUS: u32 = 1 << 17;
20 21
21// SPI_STATUS_REGISTER bits 22// SPI_STATUS_REGISTER bits
22pub(crate) const STATUS_DATA_NOT_AVAILABLE: u32 = 0x00000001; 23pub(crate) const STATUS_DATA_NOT_AVAILABLE: u32 = 0x00000001;