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-rw-r--r--embassy-nrf/src/qspi.rs18
-rw-r--r--embassy-nrf/src/spim.rs8
2 files changed, 13 insertions, 13 deletions
diff --git a/embassy-nrf/src/qspi.rs b/embassy-nrf/src/qspi.rs
index 39428c62c..39cefa0a3 100644
--- a/embassy-nrf/src/qspi.rs
+++ b/embassy-nrf/src/qspi.rs
@@ -44,7 +44,7 @@ pub struct Config {
44} 44}
45 45
46pub struct Qspi<'d, T: Instance> { 46pub struct Qspi<'d, T: Instance> {
47 qspi: T, 47 peri: T,
48 irq: T::Interrupt, 48 irq: T::Interrupt,
49 phantom: PhantomData<&'d mut T>, 49 phantom: PhantomData<&'d mut T>,
50} 50}
@@ -131,14 +131,14 @@ impl<'d, T: Instance> Qspi<'d, T> {
131 r.events_ready.reset(); 131 r.events_ready.reset();
132 132
133 Self { 133 Self {
134 qspi, 134 peri: qspi,
135 irq, 135 irq,
136 phantom: PhantomData, 136 phantom: PhantomData,
137 } 137 }
138 } 138 }
139 139
140 pub fn sleep(mut self: Pin<&mut Self>) { 140 pub fn sleep(mut self: Pin<&mut Self>) {
141 let r = unsafe { self.as_mut().get_unchecked_mut() }.qspi.regs(); 141 let r = unsafe { self.as_mut().get_unchecked_mut() }.peri.regs();
142 142
143 info!("flash: sleeping"); 143 info!("flash: sleeping");
144 info!("flash: state = {:?}", r.status.read().bits()); 144 info!("flash: state = {:?}", r.status.read().bits());
@@ -177,7 +177,7 @@ impl<'d, T: Instance> Qspi<'d, T> {
177 177
178 let len = core::cmp::max(req.len(), resp.len()) as u8; 178 let len = core::cmp::max(req.len(), resp.len()) as u8;
179 179
180 let r = unsafe { self.as_mut().get_unchecked_mut() }.qspi.regs(); 180 let r = unsafe { self.as_mut().get_unchecked_mut() }.peri.regs();
181 r.cinstrdat0.write(|w| unsafe { w.bits(dat0) }); 181 r.cinstrdat0.write(|w| unsafe { w.bits(dat0) });
182 r.cinstrdat1.write(|w| unsafe { w.bits(dat1) }); 182 r.cinstrdat1.write(|w| unsafe { w.bits(dat1) });
183 183
@@ -198,7 +198,7 @@ impl<'d, T: Instance> Qspi<'d, T> {
198 198
199 self.as_mut().wait_ready().await; 199 self.as_mut().wait_ready().await;
200 200
201 let r = unsafe { self.as_mut().get_unchecked_mut() }.qspi.regs(); 201 let r = unsafe { self.as_mut().get_unchecked_mut() }.peri.regs();
202 202
203 let dat0 = r.cinstrdat0.read().bits(); 203 let dat0 = r.cinstrdat0.read().bits();
204 let dat1 = r.cinstrdat1.read().bits(); 204 let dat1 = r.cinstrdat1.read().bits();
@@ -222,7 +222,7 @@ impl<'d, T: Instance> Qspi<'d, T> {
222 let this = unsafe { self.get_unchecked_mut() }; 222 let this = unsafe { self.get_unchecked_mut() };
223 223
224 poll_fn(move |cx| { 224 poll_fn(move |cx| {
225 let r = this.qspi.regs(); 225 let r = this.peri.regs();
226 226
227 if r.events_ready.read().bits() != 0 { 227 if r.events_ready.read().bits() != 0 {
228 r.events_ready.reset(); 228 r.events_ready.reset();
@@ -257,7 +257,7 @@ impl<'d, T: Instance> Flash for Qspi<'d, T> {
257 assert_eq!(data.len() as u32 % 4, 0); 257 assert_eq!(data.len() as u32 % 4, 0);
258 assert_eq!(address as u32 % 4, 0); 258 assert_eq!(address as u32 % 4, 0);
259 259
260 let r = unsafe { self.as_mut().get_unchecked_mut() }.qspi.regs(); 260 let r = unsafe { self.as_mut().get_unchecked_mut() }.peri.regs();
261 261
262 r.read 262 r.read
263 .src 263 .src
@@ -293,7 +293,7 @@ impl<'d, T: Instance> Flash for Qspi<'d, T> {
293 assert_eq!(data.len() as u32 % 4, 0); 293 assert_eq!(data.len() as u32 % 4, 0);
294 assert_eq!(address as u32 % 4, 0); 294 assert_eq!(address as u32 % 4, 0);
295 295
296 let r = unsafe { self.as_mut().get_unchecked_mut() }.qspi.regs(); 296 let r = unsafe { self.as_mut().get_unchecked_mut() }.peri.regs();
297 r.write 297 r.write
298 .src 298 .src
299 .write(|w| unsafe { w.src().bits(data.as_ptr() as u32) }); 299 .write(|w| unsafe { w.src().bits(data.as_ptr() as u32) });
@@ -322,7 +322,7 @@ impl<'d, T: Instance> Flash for Qspi<'d, T> {
322 322
323 assert_eq!(address as u32 % 4096, 0); 323 assert_eq!(address as u32 % 4096, 0);
324 324
325 let r = unsafe { self.as_mut().get_unchecked_mut() }.qspi.regs(); 325 let r = unsafe { self.as_mut().get_unchecked_mut() }.peri.regs();
326 r.erase 326 r.erase
327 .ptr 327 .ptr
328 .write(|w| unsafe { w.ptr().bits(address as u32) }); 328 .write(|w| unsafe { w.ptr().bits(address as u32) });
diff --git a/embassy-nrf/src/spim.rs b/embassy-nrf/src/spim.rs
index f0c6ebe19..214868b6f 100644
--- a/embassy-nrf/src/spim.rs
+++ b/embassy-nrf/src/spim.rs
@@ -26,7 +26,7 @@ pub enum Error {
26} 26}
27 27
28pub struct Spim<'d, T: Instance> { 28pub struct Spim<'d, T: Instance> {
29 spim: T, 29 peri: T,
30 irq: T::Interrupt, 30 irq: T::Interrupt,
31 phantom: PhantomData<&'d mut T>, 31 phantom: PhantomData<&'d mut T>,
32} 32}
@@ -116,7 +116,7 @@ impl<'d, T: Instance> Spim<'d, T> {
116 r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) }); 116 r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
117 117
118 Self { 118 Self {
119 spim, 119 peri: spim,
120 irq, 120 irq,
121 phantom: PhantomData, 121 phantom: PhantomData,
122 } 122 }
@@ -155,7 +155,7 @@ impl<'d, T: Instance> FullDuplex<u8> for Spim<'d, T> {
155 // before any DMA action has started. 155 // before any DMA action has started.
156 compiler_fence(Ordering::SeqCst); 156 compiler_fence(Ordering::SeqCst);
157 157
158 let r = this.spim.regs(); 158 let r = this.peri.regs();
159 159
160 // Set up the DMA write. 160 // Set up the DMA write.
161 r.txd 161 r.txd
@@ -187,7 +187,7 @@ impl<'d, T: Instance> FullDuplex<u8> for Spim<'d, T> {
187 187
188 // Wait for 'end' event. 188 // Wait for 'end' event.
189 poll_fn(|cx| { 189 poll_fn(|cx| {
190 let r = this.spim.regs(); 190 let r = this.peri.regs();
191 191
192 if r.events_end.read().bits() != 0 { 192 if r.events_end.read().bits() != 0 {
193 r.events_end.reset(); 193 r.events_end.reset();